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Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
|
module RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_31(); // @[RoundAnyRawFNToRecFN.scala:48:5]
wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19]
wire [26:0] adjustedSig = 27'h2000000; // @[RoundAnyRawFNToRecFN.scala:114:22]
wire [22:0] _common_fractOut_T = 23'h400000; // @[RoundAnyRawFNToRecFN.scala:139:28]
wire [8:0] _expOut_T_2 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:253:14, :257:14, :261:14, :265:14]
wire [8:0] _expOut_T_1 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:18, :257:18, :261:18, :265:18, :269:16, :273:16, :277:16, :278:16]
wire [8:0] _sAdjustedExp_T_1 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] common_expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _common_expOut_T_2 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_3 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_7 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_10 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_13 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_15 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_17 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] _expOut_T_19 = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [8:0] expOut = 9'h100; // @[RoundAnyRawFNToRecFN.scala:106:14, :122:31, :136:{38,55}, :252:24, :256:17, :260:17, :264:17, :268:18, :272:15, :276:15, :277:73]
wire [22:0] common_fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_1 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _common_fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_3 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [22:0] fractOut = 23'h0; // @[RoundAnyRawFNToRecFN.scala:123:31, :138:16, :140:28, :280:12, :281:16, :283:11, :284:13]
wire [9:0] _sAdjustedExp_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:104:25, :136:55, :286:23]
wire [9:0] sAdjustedExp = 10'h100; // @[RoundAnyRawFNToRecFN.scala:106:31, :136:55, :286:23]
wire [9:0] _common_expOut_T_1 = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [9:0] _io_out_T = 10'h100; // @[RoundAnyRawFNToRecFN.scala:136:55, :286:23]
wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23]
wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53]
wire [4:0] io_exceptionFlags = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [4:0] _io_exceptionFlags_T_3 = 5'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:66]
wire [32:0] io_out = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire [32:0] _io_out_T_1 = 33'h80000000; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :286:33]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _roundMagUp_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _commonCase_T_3 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire commonCase = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :90:53, :98:66, :237:{22,33,36,61,64}, :243:{32,60}]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41]
wire [1:0] io_in_sig = 2'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire [3:0] io_in_sExp = 4'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16]
wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_isZero = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire io_in_sign = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5]
wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53]
wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53]
wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53]
wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53]
wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53]
wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27]
wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63]
wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42]
wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37]
wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37]
wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37]
wire common_inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:127:37]
wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34]
wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49]
wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32]
wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32]
wire _inexact_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:43]
wire inexact = 1'h0; // @[RoundAnyRawFNToRecFN.scala:240:28]
wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20]
wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60]
wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45]
wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42]
wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39]
wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45]
wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32]
wire signOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:250:22]
wire _expOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:253:32]
wire _fractOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:22]
wire _fractOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:280:38]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_103( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [11:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [11:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [11:0] source_1; // @[Monitor.scala:541:22]
reg [2063:0] inflight; // @[Monitor.scala:614:27]
reg [8255:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [8255:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire [4095:0] _GEN = {4084'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [4095:0] _GEN_2 = {4084'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [2063:0] inflight_1; // @[Monitor.scala:726:35]
reg [8255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_26( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_39 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
|
module OptimizationBarrier_TLBEntryData_5( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
|
module IntSyncCrossingSource_n1x1_54( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
AsyncResetRegVec_w1_i0_54 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d (nodeIn_0), // @[MixedNode.scala:551:17]
.io_q (nodeOut_sync_0)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Switch.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel.{ChannelParams, IngressChannelParams, EgressChannelParams, Flit}
class SwitchBundle(val outParams: Seq[ChannelParams], val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle with HasRouterOutputParams{
val flit = new Flit(allOutParams(0).payloadBits)
val out_virt_channel = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
}
class Switch(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams {
val io = IO(new Bundle {
val in = MixedVec(allInParams.map { u => Vec(u.destSpeedup,
Input(Valid(new SwitchBundle(outParams, egressParams)))) })
val out = MixedVec(allOutParams.map { u => Vec(u.srcSpeedup,
Output(Valid(new Flit(u.payloadBits)))) })
val sel = MixedVec(allOutParams.map { o => Vec(o.srcSpeedup,
MixedVec(allInParams.map { i => Vec(i.destSpeedup, Input(Bool())) })) })
})
val in_flat = Wire(Vec(allInParams.map(_.destSpeedup).reduce(_+_),
Valid(new SwitchBundle(outParams, egressParams))))
var idx = 0
io.in.foreach(_.foreach { i =>
in_flat(idx) := i
idx += 1
})
for (i <- 0 until nAllOutputs) {
for (j <- 0 until allOutParams(i).srcSpeedup) {
val sel_flat = io.sel(i)(j).asUInt
assert(PopCount(sel_flat) <= 1.U)
io.out(i)(j).valid := Mux1H(sel_flat, in_flat.map(_.valid)) && sel_flat =/= 0.U
io.out(i)(j).bits := Mux1H(sel_flat, in_flat.map(_.bits.flit))
io.out(i)(j).bits.virt_channel_id := Mux1H(sel_flat, in_flat.map(_.bits.out_virt_channel))
}
}
}
|
module Switch_19( // @[Switch.scala:16:7]
input clock, // @[Switch.scala:16:7]
input reset, // @[Switch.scala:16:7]
input io_in_1_0_valid, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_tail, // @[Switch.scala:27:14]
input [36:0] io_in_1_0_bits_flit_payload, // @[Switch.scala:27:14]
input io_in_1_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_1_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_1_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_1_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
input io_in_1_0_bits_out_virt_channel, // @[Switch.scala:27:14]
input io_in_0_0_valid, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_head, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_tail, // @[Switch.scala:27:14]
input [36:0] io_in_0_0_bits_flit_payload, // @[Switch.scala:27:14]
input io_in_0_0_bits_flit_flow_vnet_id, // @[Switch.scala:27:14]
input [3:0] io_in_0_0_bits_flit_flow_ingress_node, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_flit_flow_ingress_node_id, // @[Switch.scala:27:14]
input [3:0] io_in_0_0_bits_flit_flow_egress_node, // @[Switch.scala:27:14]
input [1:0] io_in_0_0_bits_flit_flow_egress_node_id, // @[Switch.scala:27:14]
output io_out_1_0_valid, // @[Switch.scala:27:14]
output io_out_1_0_bits_head, // @[Switch.scala:27:14]
output io_out_1_0_bits_tail, // @[Switch.scala:27:14]
output [36:0] io_out_1_0_bits_payload, // @[Switch.scala:27:14]
output [3:0] io_out_1_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [1:0] io_out_1_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output io_out_0_0_valid, // @[Switch.scala:27:14]
output io_out_0_0_bits_head, // @[Switch.scala:27:14]
output io_out_0_0_bits_tail, // @[Switch.scala:27:14]
output [36:0] io_out_0_0_bits_payload, // @[Switch.scala:27:14]
output io_out_0_0_bits_flow_vnet_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_flow_ingress_node, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_flow_ingress_node_id, // @[Switch.scala:27:14]
output [3:0] io_out_0_0_bits_flow_egress_node, // @[Switch.scala:27:14]
output [1:0] io_out_0_0_bits_flow_egress_node_id, // @[Switch.scala:27:14]
output io_out_0_0_bits_virt_channel_id, // @[Switch.scala:27:14]
input io_sel_1_0_1_0, // @[Switch.scala:27:14]
input io_sel_1_0_0_0, // @[Switch.scala:27:14]
input io_sel_0_0_1_0, // @[Switch.scala:27:14]
input io_sel_0_0_0_0 // @[Switch.scala:27:14]
);
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
|
module OptimizationBarrier_TLBEntryData_15( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module PE_275( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_19 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
|
module InputUnit_39( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_4_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_4_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_4_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_4_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_4_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_4_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_4_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_4_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_7, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [7:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_7; // @[InputUnit.scala:266:32]
wire vcalloc_vals_6; // @[InputUnit.scala:266:32]
wire vcalloc_vals_5; // @[InputUnit.scala:266:32]
wire vcalloc_vals_4; // @[InputUnit.scala:266:32]
wire vcalloc_vals_3; // @[InputUnit.scala:266:32]
wire vcalloc_vals_2; // @[InputUnit.scala:266:32]
wire vcalloc_vals_1; // @[InputUnit.scala:266:32]
wire vcalloc_vals_0; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_4_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_4_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_4_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_4_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_4_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_4_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_4_7; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_4_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_4_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_4_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_4_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_4_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_4_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_4_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_3_g; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_4_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_4_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_4_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_4_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_4_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_4_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_4_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_4_g; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_4_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_4_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_4_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_4_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_4_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_4_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_4_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_5_g; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_4_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_4_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_4_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_4_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_4_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_4_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_4_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_6_g; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_4_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_4_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_4_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_4_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_4_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_4_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_4_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_7_g; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_4_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_4_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_4_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_4_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_4_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_4_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_4_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_3_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19]
reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19]
reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [7:0] mask; // @[InputUnit.scala:250:21]
wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71]
wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70]
wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59]
assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36]
wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36]
wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36]
wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36]
wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36]
wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
|
Generate the Verilog code corresponding to the following Chisel files.
File MulRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to
Chisel by Andrew Waterman).
Copyright 2019, 2020 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf)
val notNaN_isInfOut = io.a.isInf || io.b.isInf
val notNaN_isZeroOut = io.a.isZero || io.b.isZero
val notNaN_signOut = io.a.sign ^ io.b.sign
val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S
val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc
io.rawOut.isInf := notNaN_isInfOut
io.rawOut.isZero := notNaN_isZeroOut
io.rawOut.sExp := common_sExpOut
io.rawOut.isNaN := io.a.isNaN || io.b.isNaN
io.rawOut.sign := notNaN_signOut
io.rawOut.sig := common_sigOut
}
class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth))
mulFullRaw.io.a := io.a
mulFullRaw.io.b := io.b
io.invalidExc := mulFullRaw.io.invalidExc
io.rawOut := mulFullRaw.io.rawOut
io.rawOut.sig := {
val sig = mulFullRaw.io.rawOut.sig
Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR)
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulRawFN = Module(new MulRawFN(expWidth, sigWidth))
mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulRawFN.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
|
module MulRawFN_18( // @[MulRecFN.scala:75:7]
input io_a_isNaN, // @[MulRecFN.scala:77:16]
input io_a_isInf, // @[MulRecFN.scala:77:16]
input io_a_isZero, // @[MulRecFN.scala:77:16]
input io_a_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_a_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_a_sig, // @[MulRecFN.scala:77:16]
input io_b_isNaN, // @[MulRecFN.scala:77:16]
input io_b_isInf, // @[MulRecFN.scala:77:16]
input io_b_isZero, // @[MulRecFN.scala:77:16]
input io_b_sign, // @[MulRecFN.scala:77:16]
input [9:0] io_b_sExp, // @[MulRecFN.scala:77:16]
input [24:0] io_b_sig, // @[MulRecFN.scala:77:16]
output io_invalidExc, // @[MulRecFN.scala:77:16]
output io_rawOut_isNaN, // @[MulRecFN.scala:77:16]
output io_rawOut_isInf, // @[MulRecFN.scala:77:16]
output io_rawOut_isZero, // @[MulRecFN.scala:77:16]
output io_rawOut_sign, // @[MulRecFN.scala:77:16]
output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:77:16]
output [26:0] io_rawOut_sig // @[MulRecFN.scala:77:16]
);
wire [47:0] _mulFullRaw_io_rawOut_sig; // @[MulRecFN.scala:84:28]
wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:75:7]
wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:75:7]
wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:75:7]
wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:75:7]
wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:75:7]
wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:75:7]
wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:75:7]
wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:75:7]
wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:75:7]
wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:75:7]
wire [26:0] _io_rawOut_sig_T_3; // @[MulRecFN.scala:93:10]
wire io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
wire io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
wire [26:0] io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
wire io_invalidExc_0; // @[MulRecFN.scala:75:7]
wire [25:0] _io_rawOut_sig_T = _mulFullRaw_io_rawOut_sig[47:22]; // @[MulRecFN.scala:84:28, :93:15]
wire [21:0] _io_rawOut_sig_T_1 = _mulFullRaw_io_rawOut_sig[21:0]; // @[MulRecFN.scala:84:28, :93:37]
wire _io_rawOut_sig_T_2 = |_io_rawOut_sig_T_1; // @[MulRecFN.scala:93:{37,55}]
assign _io_rawOut_sig_T_3 = {_io_rawOut_sig_T, _io_rawOut_sig_T_2}; // @[MulRecFN.scala:93:{10,15,55}]
assign io_rawOut_sig_0 = _io_rawOut_sig_T_3; // @[MulRecFN.scala:75:7, :93:10]
MulFullRawFN_18 mulFullRaw ( // @[MulRecFN.scala:84:28]
.io_a_isNaN (io_a_isNaN_0), // @[MulRecFN.scala:75:7]
.io_a_isInf (io_a_isInf_0), // @[MulRecFN.scala:75:7]
.io_a_isZero (io_a_isZero_0), // @[MulRecFN.scala:75:7]
.io_a_sign (io_a_sign_0), // @[MulRecFN.scala:75:7]
.io_a_sExp (io_a_sExp_0), // @[MulRecFN.scala:75:7]
.io_a_sig (io_a_sig_0), // @[MulRecFN.scala:75:7]
.io_b_isNaN (io_b_isNaN_0), // @[MulRecFN.scala:75:7]
.io_b_isInf (io_b_isInf_0), // @[MulRecFN.scala:75:7]
.io_b_isZero (io_b_isZero_0), // @[MulRecFN.scala:75:7]
.io_b_sign (io_b_sign_0), // @[MulRecFN.scala:75:7]
.io_b_sExp (io_b_sExp_0), // @[MulRecFN.scala:75:7]
.io_b_sig (io_b_sig_0), // @[MulRecFN.scala:75:7]
.io_invalidExc (io_invalidExc_0),
.io_rawOut_isNaN (io_rawOut_isNaN_0),
.io_rawOut_isInf (io_rawOut_isInf_0),
.io_rawOut_isZero (io_rawOut_isZero_0),
.io_rawOut_sign (io_rawOut_sign_0),
.io_rawOut_sExp (io_rawOut_sExp_0),
.io_rawOut_sig (_mulFullRaw_io_rawOut_sig)
); // @[MulRecFN.scala:84:28]
assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:75:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:75:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Fragmenter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes}
import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1}
import scala.math.min
import freechips.rocketchip.util.DataToAugmentedData
object EarlyAck {
sealed trait T
case object AllPuts extends T
case object PutFulls extends T
case object None extends T
}
// minSize: minimum size of transfers supported by all outward managers
// maxSize: maximum size of transfers supported after the Fragmenter is applied
// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
// earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat
// holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst
// nameSuffix: appends a suffix to the module name
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize")
require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize")
require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize")
val fragmentBits = log2Ceil(maxSize / minSize)
val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
val toggleBits = 1
val addedBits = fragmentBits + toggleBits + fullBits
def expandTransfer(x: TransferSizes, op: String) = if (!x) x else {
// validate that we can apply the fragmenter correctly
require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})")
TransferSizes(x.min, maxSize)
}
private def noChangeRequired = minSize == maxSize
private def shrinkTransfer(x: TransferSizes) =
if (!alwaysMin) x
else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max))
else TransferSizes.none
private def mapManager(m: TLSlaveParameters) = m.v1copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet, "Get"),
supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"),
supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"),
supportsHint = expandTransfer(m.supportsHint, "Hint"))
val node = new TLAdapterNode(
// We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master
clientFn = { c => (if (noChangeRequired) c else c.v2copy(
masters = Seq(TLMasterParameters.v2(
name = "TLFragmenter",
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
))},
managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) }
) {
override def circuitIdentity = noChangeRequired
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
if (noChangeRequired) {
out <> in
} else {
// All managers must share a common FIFO domain (responses might end up interleaved)
val manager = edgeOut.manager
val managers = manager.managers
val beatBytes = manager.beatBytes
val fifoId = managers(0).fifoId
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe,
s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region")
require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
// We can't support devices which are cached on both sides of us
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
// We can't support denied because we reassemble fragments
require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true")
require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None)
/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
* max size -- the maximum transfer size possible
* orig size -- the original pre-fragmenter size
* frag size -- the modified post-fragmenter size
* min size -- the threshold below which frag=orig
* beat size -- the amount transfered on any given beat
*
* The relationships are as follows:
* max >= orig >= frag
* max > min >= beat
* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
*
* The fragment# (sent via TL.source) is measured in multiples of min size.
* Meanwhile, to track the progress, counters measure in multiples of beat size.
*
* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
*
* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
* get64 get16 6 ackD16 6 ackD64 12 15
* ackD16 6 ackD64 14
* ackD16 6 ackD64 13
* ackD16 6 ackD64 12
* get16 4 ackD16 4 ackD64 8 11
* ackD16 4 ackD64 10
* ackD16 4 ackD64 9
* ackD16 4 ackD64 8
* get16 2 ackD16 2 ackD64 4 7
* ackD16 2 ackD64 6
* ackD16 2 ackD64 5
* ackD16 2 ackD64 4
* get16 0 ackD16 0 ackD64 0 3
* ackD16 0 ackD64 2
* ackD16 0 ackD64 1
* ackD16 0 ackD64 0
*
* get8 get8 0 ackD8 0 ackD8 0 1
* ackD8 0 ackD8 0
*
* get4 get4 0 ackD4 0 ackD4 0 0
* get1 get1 0 ackD1 0 ackD1 0 0
*
* put64 put16 6 15
* put64 put16 6 14
* put64 put16 6 13
* put64 put16 6 ack16 6 12 12
* put64 put16 4 11
* put64 put16 4 10
* put64 put16 4 9
* put64 put16 4 ack16 4 8 8
* put64 put16 2 7
* put64 put16 2 6
* put64 put16 2 5
* put64 put16 2 ack16 2 4 4
* put64 put16 0 3
* put64 put16 0 2
* put64 put16 0 1
* put64 put16 0 ack16 0 ack64 0 0
*
* put8 put8 0 1
* put8 put8 0 ack8 0 ack8 0 0
*
* put4 put4 0 ack4 0 ack4 0 0
* put1 put1 0 ack1 0 ack1 0 0
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// Consider the following waveform for two 4-beat bursts:
// ---A----A------------
// -------D-----DDD-DDDD
// Under TL rules, the second A can use the same source as the first A,
// because the source is released for reuse on the first response beat.
//
// However, if we fragment the requests, it looks like this:
// ---3210-3210---------
// -------3-----210-3210
// ... now we've broken the rules because 210 are twice inflight.
//
// This phenomenon means we can have essentially 2*maxSize/minSize-1
// fragmented transactions in flight per original transaction source.
//
// To keep the source unique, we encode the beat counter in the low
// bits of the source. To solve the overlap, we use a toggle bit.
// Whatever toggle bit the D is reassembling, A will use the opposite.
// First, handle the return path
val acknum = RegInit(0.U(counterBits.W))
val dOrig = Reg(UInt())
val dToggle = RegInit(false.B)
val dFragnum = out.d.bits.source(fragmentBits-1, 0)
val dFirst = acknum === 0.U
val dLast = dFragnum === 0.U // only for AccessAck (!Data)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
val dHasData = edgeOut.hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)
val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U)
val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes))
// calculate the original size
val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
when (out.d.fire) {
acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
when (dFirst) {
dOrig := dFirst_size
dToggle := out.d.bits.source(fragmentBits)
}
}
// Swallow up non-data ack fragments
val doEarlyAck = earlyAck match {
case EarlyAck.AllPuts => true.B
case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
case EarlyAck.None => false.B
}
val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.source := out.d.bits.source >> addedBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
if (edgeOut.manager.mayDenyPut) {
val r_denied = Reg(Bool())
val d_denied = (!dFirst && r_denied) || out.d.bits.denied
when (out.d.fire) { r_denied := d_denied }
in.d.bits.denied := d_denied
}
if (edgeOut.manager.mayDenyGet) {
// Take denied only from the first beat and hold that value
val d_denied = out.d.bits.denied holdUnless dFirst
when (dHasData) {
in.d.bits.denied := d_denied
in.d.bits.corrupt := d_denied || out.d.bits.corrupt
}
}
// What maximum transfer sizes do downstream devices support?
val maxArithmetics = managers.map(_.supportsArithmetic.max)
val maxLogicals = managers.map(_.supportsLogical.max)
val maxGets = managers.map(_.supportsGet.max)
val maxPutFulls = managers.map(_.supportsPutFull.max)
val maxPutPartials = managers.map(_.supportsPutPartial.max)
val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
// We assume that the request is valid => size 0 is impossible
val lgMinSize = log2Ceil(minSize).U
val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
// Make the request repeatable
val repeater = Module(new Repeater(in.a.bits))
repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits))
val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
val maxLgLogical = Mux1H(find, maxLgLogicals)
val maxLgGet = Mux1H(find, maxLgGets)
val maxLgPutFull = Mux1H(find, maxLgPutFulls)
val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
val maxLgHint = Mux1H(find, maxLgHints)
val limit = if (alwaysMin) lgMinSize else
MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
TLMessages.PutFullData -> maxLgPutFull,
TLMessages.PutPartialData -> maxLgPutPartial,
TLMessages.ArithmeticData -> maxLgArithmetic,
TLMessages.LogicalData -> maxLgLogical,
TLMessages.Get -> maxLgGet,
TLMessages.Hint -> maxLgHint))
val aOrig = in_a.bits.size
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
val aHasData = edgeIn.hasData(in_a.bits)
val aMask = Mux(aHasData, 0.U, aFragOH1)
val gennum = RegInit(0.U(counterBits.W))
val aFirst = gennum === 0.U
val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U)
val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
val aLast = aFragnum === 0.U
val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
when (out.a.fire) { gennum := new_gennum }
repeater.io.repeat := !aHasData && aFragnum =/= 0.U
out.a <> in_a
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U)
out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = ((BigInt(1) << beatBytes) - 1).U
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFragmenter
{
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
if (minSize <= maxSize) {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix))
fragmenter.node
} else { TLEphemeralNode()(ValName("no_fragmenter")) }
}
def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix)
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
|
module TLInterconnectCoupler_cbus_to_bootrom( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
input auto_fragmenter_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_fragmenter_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_fragmenter_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_fragmenter_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [16:0] auto_fragmenter_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_fragmenter_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_fragmenter_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_fragmenter_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_fragmenter_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [13:0] auto_fragmenter_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_fragmenter_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [16:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_tl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_in_d_bits_data // @[LazyModuleImp.scala:107:25]
);
TLFragmenter_BootROM fragmenter ( // @[Fragmenter.scala:345:34]
.clock (clock),
.reset (reset),
.auto_anon_in_a_ready (auto_tl_in_a_ready),
.auto_anon_in_a_valid (auto_tl_in_a_valid),
.auto_anon_in_a_bits_opcode (auto_tl_in_a_bits_opcode),
.auto_anon_in_a_bits_param (auto_tl_in_a_bits_param),
.auto_anon_in_a_bits_size (auto_tl_in_a_bits_size),
.auto_anon_in_a_bits_source (auto_tl_in_a_bits_source),
.auto_anon_in_a_bits_address (auto_tl_in_a_bits_address),
.auto_anon_in_a_bits_mask (auto_tl_in_a_bits_mask),
.auto_anon_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt),
.auto_anon_in_d_ready (auto_tl_in_d_ready),
.auto_anon_in_d_valid (auto_tl_in_d_valid),
.auto_anon_in_d_bits_size (auto_tl_in_d_bits_size),
.auto_anon_in_d_bits_source (auto_tl_in_d_bits_source),
.auto_anon_in_d_bits_data (auto_tl_in_d_bits_data),
.auto_anon_out_a_ready (auto_fragmenter_anon_out_a_ready),
.auto_anon_out_a_valid (auto_fragmenter_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (auto_fragmenter_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (auto_fragmenter_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (auto_fragmenter_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (auto_fragmenter_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (auto_fragmenter_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (auto_fragmenter_anon_out_a_bits_mask),
.auto_anon_out_a_bits_corrupt (auto_fragmenter_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (auto_fragmenter_anon_out_d_ready),
.auto_anon_out_d_valid (auto_fragmenter_anon_out_d_valid),
.auto_anon_out_d_bits_size (auto_fragmenter_anon_out_d_bits_size),
.auto_anon_out_d_bits_source (auto_fragmenter_anon_out_d_bits_source),
.auto_anon_out_d_bits_data (auto_fragmenter_anon_out_d_bits_data)
); // @[Fragmenter.scala:345:34]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
|
module dataMems_313( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PMA.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile.{CoreModule, CoreBundle}
import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters}
class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) {
val io = IO(new Bundle {
val paddr = Input(UInt())
val resp = Output(new Bundle {
val cacheable = Bool()
val r = Bool()
val w = Bool()
val pp = Bool()
val al = Bool()
val aa = Bool()
val x = Bool()
val eff = Bool()
})
})
// PMA
// check exist a slave can consume this address.
val legal_address = manager.findSafe(io.paddr).reduce(_||_)
// check utility to help check SoC property.
def fastCheck(member: TLManagerParameters => Boolean) =
legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B)
io.resp.cacheable := fastCheck(_.supportsAcquireB)
io.resp.r := fastCheck(_.supportsGet)
io.resp.w := fastCheck(_.supportsPutFull)
io.resp.pp := fastCheck(_.supportsPutPartial)
io.resp.al := fastCheck(_.supportsLogical)
io.resp.aa := fastCheck(_.supportsArithmetic)
io.resp.x := fastCheck(_.executable)
io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType)
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
|
module PMAChecker_8( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46]
wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73]
wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19]
wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_49; // @[PMA.scala:39:19]
wire _io_resp_pp_T_49; // @[PMA.scala:39:19]
wire _io_resp_al_T_49; // @[PMA.scala:39:19]
wire _io_resp_aa_T_49; // @[PMA.scala:39:19]
wire _io_resp_x_T_67; // @[PMA.scala:39:19]
wire _io_resp_eff_T_61; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31]
assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31]
assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31]
assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31]
assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31]
assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31]
assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31]
assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31]
assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89]
wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46]
wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89]
wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46]
wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73]
assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73]
assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46]
wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89]
wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46]
wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73]
assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73]
assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73]
assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73]
wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73]
assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ListBuffer.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import freechips.rocketchip.util._
case class ListBufferParameters[T <: Data](gen: T, queues: Int, entries: Int, bypass: Boolean)
{
val queueBits = log2Up(queues)
val entryBits = log2Up(entries)
}
class ListBufferPush[T <: Data](params: ListBufferParameters[T]) extends Bundle
{
val index = UInt(params.queueBits.W)
val data = Output(params.gen)
}
class ListBuffer[T <: Data](params: ListBufferParameters[T]) extends Module
{
override def desiredName = s"ListBuffer_${params.gen.typeName}_q${params.queues}_e${params.entries}"
val io = IO(new Bundle {
// push is visible on the same cycle; flow queues
val push = Flipped(Decoupled(new ListBufferPush(params)))
val valid = UInt(params.queues.W)
val pop = Flipped(Valid(UInt(params.queueBits.W)))
val data = Output(params.gen)
})
val valid = RegInit(0.U(params.queues.W))
val head = Mem(params.queues, UInt(params.entryBits.W))
val tail = Mem(params.queues, UInt(params.entryBits.W))
val used = RegInit(0.U(params.entries.W))
val next = Mem(params.entries, UInt(params.entryBits.W))
val data = Mem(params.entries, params.gen)
val freeOH = ~(leftOR(~used) << 1) & ~used
val freeIdx = OHToUInt(freeOH)
val valid_set = WireDefault(0.U(params.queues.W))
val valid_clr = WireDefault(0.U(params.queues.W))
val used_set = WireDefault(0.U(params.entries.W))
val used_clr = WireDefault(0.U(params.entries.W))
val push_tail = tail.read(io.push.bits.index)
val push_valid = valid(io.push.bits.index)
io.push.ready := !used.andR
when (io.push.fire) {
valid_set := UIntToOH(io.push.bits.index, params.queues)
used_set := freeOH
data.write(freeIdx, io.push.bits.data)
when (push_valid) {
next.write(push_tail, freeIdx)
} .otherwise {
head.write(io.push.bits.index, freeIdx)
}
tail.write(io.push.bits.index, freeIdx)
}
val pop_head = head.read(io.pop.bits)
val pop_valid = valid(io.pop.bits)
// Bypass push data to the peek port
io.data := (if (!params.bypass) data.read(pop_head) else Mux(!pop_valid, io.push.bits.data, data.read(pop_head)))
io.valid := (if (!params.bypass) valid else (valid | valid_set))
// It is an error to pop something that is not valid
assert (!io.pop.fire || (io.valid)(io.pop.bits))
when (io.pop.fire) {
used_clr := UIntToOH(pop_head, params.entries)
when (pop_head === tail.read(io.pop.bits)) {
valid_clr := UIntToOH(io.pop.bits, params.queues)
}
head.write(io.pop.bits, Mux(io.push.fire && push_valid && push_tail === pop_head, freeIdx, next.read(pop_head)))
}
// Empty bypass changes no state
when ((!params.bypass).B || !io.pop.valid || pop_valid) {
used := (used & ~used_clr) | used_set
valid := (valid & ~valid_clr) | valid_set
}
}
|
module ListBuffer_QueuedRequest_q21_e33( // @[ListBuffer.scala:36:7]
input clock, // @[ListBuffer.scala:36:7]
input reset, // @[ListBuffer.scala:36:7]
output io_push_ready, // @[ListBuffer.scala:39:14]
input io_push_valid, // @[ListBuffer.scala:39:14]
input [4:0] io_push_bits_index, // @[ListBuffer.scala:39:14]
input io_push_bits_data_prio_0, // @[ListBuffer.scala:39:14]
input io_push_bits_data_prio_2, // @[ListBuffer.scala:39:14]
input io_push_bits_data_control, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_opcode, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_param, // @[ListBuffer.scala:39:14]
input [2:0] io_push_bits_data_size, // @[ListBuffer.scala:39:14]
input [7:0] io_push_bits_data_source, // @[ListBuffer.scala:39:14]
input [12:0] io_push_bits_data_tag, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_data_offset, // @[ListBuffer.scala:39:14]
input [5:0] io_push_bits_data_put, // @[ListBuffer.scala:39:14]
output [20:0] io_valid, // @[ListBuffer.scala:39:14]
input io_pop_valid, // @[ListBuffer.scala:39:14]
input [4:0] io_pop_bits, // @[ListBuffer.scala:39:14]
output io_data_prio_0, // @[ListBuffer.scala:39:14]
output io_data_prio_1, // @[ListBuffer.scala:39:14]
output io_data_prio_2, // @[ListBuffer.scala:39:14]
output io_data_control, // @[ListBuffer.scala:39:14]
output [2:0] io_data_opcode, // @[ListBuffer.scala:39:14]
output [2:0] io_data_param, // @[ListBuffer.scala:39:14]
output [2:0] io_data_size, // @[ListBuffer.scala:39:14]
output [7:0] io_data_source, // @[ListBuffer.scala:39:14]
output [12:0] io_data_tag, // @[ListBuffer.scala:39:14]
output [5:0] io_data_offset, // @[ListBuffer.scala:39:14]
output [5:0] io_data_put // @[ListBuffer.scala:39:14]
);
wire [45:0] _data_ext_R0_data; // @[ListBuffer.scala:52:18]
wire [5:0] _next_ext_R0_data; // @[ListBuffer.scala:51:18]
wire [5:0] _tail_ext_R0_data; // @[ListBuffer.scala:49:18]
wire [5:0] _tail_ext_R1_data; // @[ListBuffer.scala:49:18]
wire [5:0] _head_ext_R0_data; // @[ListBuffer.scala:48:18]
wire io_push_valid_0 = io_push_valid; // @[ListBuffer.scala:36:7]
wire [4:0] io_push_bits_index_0 = io_push_bits_index; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_0_0 = io_push_bits_data_prio_0; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_2_0 = io_push_bits_data_prio_2; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_control_0 = io_push_bits_data_control; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_opcode_0 = io_push_bits_data_opcode; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_param_0 = io_push_bits_data_param; // @[ListBuffer.scala:36:7]
wire [2:0] io_push_bits_data_size_0 = io_push_bits_data_size; // @[ListBuffer.scala:36:7]
wire [7:0] io_push_bits_data_source_0 = io_push_bits_data_source; // @[ListBuffer.scala:36:7]
wire [12:0] io_push_bits_data_tag_0 = io_push_bits_data_tag; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_data_offset_0 = io_push_bits_data_offset; // @[ListBuffer.scala:36:7]
wire [5:0] io_push_bits_data_put_0 = io_push_bits_data_put; // @[ListBuffer.scala:36:7]
wire io_pop_valid_0 = io_pop_valid; // @[ListBuffer.scala:36:7]
wire [4:0] io_pop_bits_0 = io_pop_bits; // @[ListBuffer.scala:36:7]
wire io_push_bits_data_prio_1 = 1'h0; // @[ListBuffer.scala:36:7]
wire _io_push_ready_T_1; // @[ListBuffer.scala:65:20]
wire [4:0] valid_set_shiftAmount = io_push_bits_index_0; // @[OneHot.scala:64:49]
wire [4:0] valid_clr_shiftAmount = io_pop_bits_0; // @[OneHot.scala:64:49]
wire io_push_ready_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_0_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_1_0; // @[ListBuffer.scala:36:7]
wire io_data_prio_2_0; // @[ListBuffer.scala:36:7]
wire io_data_control_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_opcode_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_param_0; // @[ListBuffer.scala:36:7]
wire [2:0] io_data_size_0; // @[ListBuffer.scala:36:7]
wire [7:0] io_data_source_0; // @[ListBuffer.scala:36:7]
wire [12:0] io_data_tag_0; // @[ListBuffer.scala:36:7]
wire [5:0] io_data_offset_0; // @[ListBuffer.scala:36:7]
wire [5:0] io_data_put_0; // @[ListBuffer.scala:36:7]
wire [20:0] io_valid_0; // @[ListBuffer.scala:36:7]
reg [20:0] valid; // @[ListBuffer.scala:47:22]
assign io_valid_0 = valid; // @[ListBuffer.scala:36:7, :47:22]
reg [32:0] used; // @[ListBuffer.scala:50:22]
assign io_data_prio_0_0 = _data_ext_R0_data[0]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_prio_1_0 = _data_ext_R0_data[1]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_prio_2_0 = _data_ext_R0_data[2]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_control_0 = _data_ext_R0_data[3]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_opcode_0 = _data_ext_R0_data[6:4]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_param_0 = _data_ext_R0_data[9:7]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_size_0 = _data_ext_R0_data[12:10]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_source_0 = _data_ext_R0_data[20:13]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_tag_0 = _data_ext_R0_data[33:21]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_offset_0 = _data_ext_R0_data[39:34]; // @[ListBuffer.scala:36:7, :52:18]
assign io_data_put_0 = _data_ext_R0_data[45:40]; // @[ListBuffer.scala:36:7, :52:18]
wire [32:0] _freeOH_T = ~used; // @[ListBuffer.scala:50:22, :54:25]
wire [33:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48]
wire [32:0] _freeOH_T_2 = _freeOH_T_1[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}]
wire [34:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_5 = _freeOH_T_4[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}]
wire [36:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_8 = _freeOH_T_7[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}]
wire [40:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_11 = _freeOH_T_10[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}]
wire [48:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_14 = _freeOH_T_13[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}]
wire [64:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}]
wire [32:0] _freeOH_T_17 = _freeOH_T_16[32:0]; // @[package.scala:253:{48,53}]
wire [32:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17; // @[package.scala:253:{43,53}]
wire [32:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17]
wire [33:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17]
wire [33:0] _freeOH_T_21 = ~_freeOH_T_20; // @[ListBuffer.scala:54:{16,32}]
wire [32:0] _freeOH_T_22 = ~used; // @[ListBuffer.scala:50:22, :54:{25,40}]
wire [33:0] freeOH = {1'h0, _freeOH_T_21[32:0] & _freeOH_T_22}; // @[ListBuffer.scala:54:{16,38,40}]
wire [1:0] freeIdx_hi = freeOH[33:32]; // @[OneHot.scala:30:18]
wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18]
wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _freeIdx_T_1 = {30'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28]
wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}]
wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}]
wire [20:0] valid_set; // @[ListBuffer.scala:57:30]
wire [20:0] valid_clr; // @[ListBuffer.scala:58:30]
wire [32:0] used_set; // @[ListBuffer.scala:59:30]
wire [32:0] used_clr; // @[ListBuffer.scala:60:30]
wire [20:0] _push_valid_T = valid >> io_push_bits_index_0; // @[ListBuffer.scala:36:7, :47:22, :63:25]
wire push_valid = _push_valid_T[0]; // @[ListBuffer.scala:63:25]
wire _io_push_ready_T = &used; // @[ListBuffer.scala:50:22, :65:26]
assign _io_push_ready_T_1 = ~_io_push_ready_T; // @[ListBuffer.scala:65:{20,26}]
assign io_push_ready_0 = _io_push_ready_T_1; // @[ListBuffer.scala:36:7, :65:20]
wire data_MPORT_en = io_push_ready_0 & io_push_valid_0; // @[Decoupled.scala:51:35]
wire [31:0] _valid_set_T = 32'h1 << valid_set_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [20:0] _valid_set_T_1 = _valid_set_T[20:0]; // @[OneHot.scala:65:{12,27}]
assign valid_set = data_MPORT_en ? _valid_set_T_1 : 21'h0; // @[OneHot.scala:65:27]
assign used_set = data_MPORT_en ? freeOH[32:0] : 33'h0; // @[Decoupled.scala:51:35]
wire [20:0] _GEN = {16'h0, io_pop_bits_0}; // @[ListBuffer.scala:36:7, :79:24]
wire [20:0] _pop_valid_T = valid >> _GEN; // @[ListBuffer.scala:47:22, :79:24]
wire pop_valid = _pop_valid_T[0]; // @[ListBuffer.scala:79:24]
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_6( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_18 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_25 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74]
wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [207:0] c_sizes_set = 208'h0; // @[Monitor.scala:741:34]
wire [103:0] c_opcodes_set = 104'h0; // @[Monitor.scala:740:34]
wire [25:0] c_set = 26'h0; // @[Monitor.scala:738:34]
wire [25:0] c_set_wo_ready = 26'h0; // @[Monitor.scala:739:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_7 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire _source_ok_T_6 = io_in_a_bits_source_0 == 5'h19; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = ~_source_ok_T_7; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = source_ok_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_12 = _source_ok_T_10 & _source_ok_T_11; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire _source_ok_T_13 = io_in_a_bits_source_0 == 5'h9; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_3 = _source_ok_T_13; // @[Parameters.scala:1138:31]
wire _source_ok_T_14 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_15 = _source_ok_T_14 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_15 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_18 = _uncommonBits_T_18[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_19 = _uncommonBits_T_19[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_20 = _uncommonBits_T_20[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_21 = _uncommonBits_T_21[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_16 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_23 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_19 = _source_ok_T_17; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_20 = source_ok_uncommonBits_2 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_21 = _source_ok_T_19 & _source_ok_T_20; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_21; // @[Parameters.scala:1138:31]
wire _source_ok_T_22 = io_in_d_bits_source_0 == 5'h19; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_1 = _source_ok_T_22; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_24 = ~_source_ok_T_23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_26 = _source_ok_T_24; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_27 = source_ok_uncommonBits_3 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_28 = _source_ok_T_26 & _source_ok_T_27; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_2 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_d_bits_source_0 == 5'h9; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_3 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_31 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _T_847 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_847; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_847; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [13:0] address; // @[Monitor.scala:391:22]
wire _T_920 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_920; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_920; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_920; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [25:0] inflight; // @[Monitor.scala:614:27]
reg [103:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [207:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [25:0] a_set; // @[Monitor.scala:626:34]
wire [25:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [103:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [207:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [103:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [103:0] _a_opcode_lookup_T_6 = {100'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [103:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [207:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [207:0] _a_size_lookup_T_6 = {200'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [207:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[207:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire _T_773 = _T_847 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_773 ? _a_set_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_773 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_773 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_773 ? _a_opcodes_set_T_1[103:0] : 104'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_773 ? _a_sizes_set_T_1[207:0] : 208'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [25:0] d_clr; // @[Monitor.scala:664:34]
wire [25:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [103:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [207:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_819 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_819 & ~d_release_ack ? _d_clr_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire _T_788 = _T_920 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_788 ? _d_clr_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_788 ? _d_opcodes_clr_T_5[103:0] : 104'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_788 ? _d_sizes_clr_T_5[207:0] : 208'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [25:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [25:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [25:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [103:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [103:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [103:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [207:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [207:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [207:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [25:0] inflight_1; // @[Monitor.scala:726:35]
wire [25:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [103:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [103:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [207:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [207:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [103:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [103:0] _c_opcode_lookup_T_6 = {100'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [103:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [207:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [207:0] _c_size_lookup_T_6 = {200'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [207:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[207:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [25:0] d_clr_1; // @[Monitor.scala:774:34]
wire [25:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [103:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [207:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_891 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_891 & d_release_ack_1 ? _d_clr_wo_ready_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire _T_873 = _T_920 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_873 ? _d_clr_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_873 ? _d_opcodes_clr_T_11[103:0] : 104'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_873 ? _d_sizes_clr_T_11[207:0] : 208'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [25:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [25:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [103:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [103:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [207:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [207:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
|
module IntSyncCrossingSource_n1x2_1( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset, // @[Crossing.scala:41:9]
input auto_in_0, // @[LazyModuleImp.scala:107:25]
input auto_in_1, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_sync_1 // @[LazyModuleImp.scala:107:25]
);
wire [1:0] _reg_io_q; // @[AsyncResetReg.scala:86:21]
wire auto_in_0_0 = auto_in_0; // @[Crossing.scala:41:9]
wire auto_in_1_0 = auto_in_1; // @[Crossing.scala:41:9]
wire nodeIn_0 = auto_in_0_0; // @[Crossing.scala:41:9]
wire nodeIn_1 = auto_in_1_0; // @[Crossing.scala:41:9]
wire nodeOut_sync_0; // @[MixedNode.scala:542:17]
wire nodeOut_sync_1; // @[MixedNode.scala:542:17]
wire auto_out_sync_0_0; // @[Crossing.scala:41:9]
wire auto_out_sync_1_0; // @[Crossing.scala:41:9]
assign auto_out_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1_0 = nodeOut_sync_1; // @[Crossing.scala:41:9]
assign nodeOut_sync_0 = _reg_io_q[0]; // @[AsyncResetReg.scala:86:21]
assign nodeOut_sync_1 = _reg_io_q[1]; // @[AsyncResetReg.scala:86:21]
AsyncResetRegVec_w2_i0_1 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset),
.io_d ({nodeIn_1, nodeIn_0}), // @[Crossing.scala:45:36]
.io_q (_reg_io_q)
); // @[AsyncResetReg.scala:86:21]
assign auto_out_sync_0 = auto_out_sync_0_0; // @[Crossing.scala:41:9]
assign auto_out_sync_1 = auto_out_sync_1_0; // @[Crossing.scala:41:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_93( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31]
wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [7:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_3 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_3; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_3; // @[Monitor.scala:673:46, :783:46]
wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [1:0] _GEN_4 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [1:0] _GEN_5 = 2'h1 << _GEN_4; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35]
wire _T_1153 = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35]
wire _T_1238 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
package constellation.channel
import chisel3._
import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.util._
import constellation.noc.{HasNoCParams}
class NoCMonitor(val cParam: ChannelParams)(implicit val p: Parameters) extends Module with HasNoCParams {
val io = IO(new Bundle {
val in = Input(new Channel(cParam))
})
val in_flight = RegInit(VecInit(Seq.fill(cParam.nVirtualChannels) { false.B }))
for (i <- 0 until cParam.srcSpeedup) {
val flit = io.in.flit(i)
when (flit.valid) {
when (flit.bits.head) {
in_flight(flit.bits.virt_channel_id) := true.B
assert (!in_flight(flit.bits.virt_channel_id), "Flit head/tail sequencing is broken")
}
when (flit.bits.tail) {
in_flight(flit.bits.virt_channel_id) := false.B
}
}
val possibleFlows = cParam.possibleFlows
when (flit.valid && flit.bits.head) {
cParam match {
case n: ChannelParams => n.virtualChannelParams.zipWithIndex.foreach { case (v,i) =>
assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
case _ => assert(cParam.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)
}
}
}
}
File Types.scala:
package constellation.routing
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Parameters}
import constellation.noc.{HasNoCParams}
import constellation.channel.{Flit}
/** A representation for 1 specific virtual channel in wormhole routing
*
* @param src the source node
* @param vc ID for the virtual channel
* @param dst the destination node
* @param n_vc the number of virtual channels
*/
// BEGIN: ChannelRoutingInfo
case class ChannelRoutingInfo(
src: Int,
dst: Int,
vc: Int,
n_vc: Int
) {
// END: ChannelRoutingInfo
require (src >= -1 && dst >= -1 && vc >= 0, s"Illegal $this")
require (!(src == -1 && dst == -1), s"Illegal $this")
require (vc < n_vc, s"Illegal $this")
val isIngress = src == -1
val isEgress = dst == -1
}
/** Represents the properties of a packet that are relevant for routing
* ingressId and egressId uniquely identify a flow, but vnet and dst are used here
* to simplify the implementation of routingrelations
*
* @param ingressId packet's source ingress point
* @param egressId packet's destination egress point
* @param vNet virtual subnetwork identifier
* @param dst packet's destination node ID
*/
// BEGIN: FlowRoutingInfo
case class FlowRoutingInfo(
ingressId: Int,
egressId: Int,
vNetId: Int,
ingressNode: Int,
ingressNodeId: Int,
egressNode: Int,
egressNodeId: Int,
fifo: Boolean
) {
// END: FlowRoutingInfo
def isFlow(f: FlowRoutingBundle): Bool = {
(f.ingress_node === ingressNode.U &&
f.egress_node === egressNode.U &&
f.ingress_node_id === ingressNodeId.U &&
f.egress_node_id === egressNodeId.U)
}
def asLiteral(b: FlowRoutingBundle): BigInt = {
Seq(
(vNetId , b.vnet_id),
(ingressNode , b.ingress_node),
(ingressNodeId , b.ingress_node_id),
(egressNode , b.egress_node),
(egressNodeId , b.egress_node_id)
).foldLeft(0)((l, t) => {
(l << t._2.getWidth) | t._1
})
}
}
class FlowRoutingBundle(implicit val p: Parameters) extends Bundle with HasNoCParams {
// Instead of tracking ingress/egress ID, track the physical destination id and the offset at the destination
// This simplifies the routing tables
val vnet_id = UInt(log2Ceil(nVirtualNetworks).W)
val ingress_node = UInt(log2Ceil(nNodes).W)
val ingress_node_id = UInt(log2Ceil(maxIngressesAtNode).W)
val egress_node = UInt(log2Ceil(nNodes).W)
val egress_node_id = UInt(log2Ceil(maxEgressesAtNode).W)
}
|
module NoCMonitor_84( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
|
Generate the Verilog code corresponding to the following Chisel files.
File FPU.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util._
import chisel3.{DontCare, WireInit, withClock, withReset}
import chisel3.experimental.SourceInfo
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property
case class FPUParams(
minFLen: Int = 32,
fLen: Int = 64,
divSqrt: Boolean = true,
sfmaLatency: Int = 3,
dfmaLatency: Int = 4,
fpmuLatency: Int = 2,
ifpuLatency: Int = 2
)
object FPConstants
{
val RM_SZ = 3
val FLAGS_SZ = 5
}
trait HasFPUCtrlSigs {
val ldst = Bool()
val wen = Bool()
val ren1 = Bool()
val ren2 = Bool()
val ren3 = Bool()
val swap12 = Bool()
val swap23 = Bool()
val typeTagIn = UInt(2.W)
val typeTagOut = UInt(2.W)
val fromint = Bool()
val toint = Bool()
val fastpipe = Bool()
val fma = Bool()
val div = Bool()
val sqrt = Bool()
val wflags = Bool()
val vec = Bool()
}
class FPUCtrlSigs extends Bundle with HasFPUCtrlSigs
class FPUDecoder(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new Bundle {
val inst = Input(Bits(32.W))
val sigs = Output(new FPUCtrlSigs())
})
private val X2 = BitPat.dontCare(2)
val default = List(X,X,X,X,X,X,X,X2,X2,X,X,X,X,X,X,X,N)
val h: Array[(BitPat, List[BitPat])] =
Array(FLH -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSH -> List(Y,N,N,Y,N,Y,X, I, H,N,Y,N,N,N,N,N,N),
FMV_H_X -> List(N,Y,N,N,N,X,X, H, I,Y,N,N,N,N,N,N,N),
FCVT_H_W -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_WU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_L -> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FCVT_H_LU-> List(N,Y,N,N,N,X,X, H, H,Y,N,N,N,N,N,Y,N),
FMV_X_H -> List(N,N,Y,N,N,N,X, I, H,N,Y,N,N,N,N,N,N),
FCLASS_H -> List(N,N,Y,N,N,N,X, H, H,N,Y,N,N,N,N,N,N),
FCVT_W_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_H -> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_H-> List(N,N,Y,N,N,N,X, H,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_H -> List(N,Y,Y,N,N,N,X, H, S,N,N,Y,N,N,N,Y,N),
FCVT_H_S -> List(N,Y,Y,N,N,N,X, S, H,N,N,Y,N,N,N,Y,N),
FEQ_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLT_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FLE_H -> List(N,N,Y,Y,N,N,N, H, H,N,Y,N,N,N,N,Y,N),
FSGNJ_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FSGNJX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,N,N),
FMIN_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FMAX_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,Y,N,N,N,Y,N),
FADD_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FSUB_H -> List(N,Y,Y,Y,N,N,Y, H, H,N,N,N,Y,N,N,Y,N),
FMUL_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMADD_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FNMSUB_H -> List(N,Y,Y,Y,Y,N,N, H, H,N,N,N,Y,N,N,Y,N),
FDIV_H -> List(N,Y,Y,Y,N,N,N, H, H,N,N,N,N,Y,N,Y,N),
FSQRT_H -> List(N,Y,Y,N,N,N,X, H, H,N,N,N,N,N,Y,Y,N))
val f: Array[(BitPat, List[BitPat])] =
Array(FLW -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSW -> List(Y,N,N,Y,N,Y,X, I, S,N,Y,N,N,N,N,N,N),
FMV_W_X -> List(N,Y,N,N,N,X,X, S, I,Y,N,N,N,N,N,N,N),
FCVT_S_W -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_WU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_L -> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FCVT_S_LU-> List(N,Y,N,N,N,X,X, S, S,Y,N,N,N,N,N,Y,N),
FMV_X_W -> List(N,N,Y,N,N,N,X, I, S,N,Y,N,N,N,N,N,N),
FCLASS_S -> List(N,N,Y,N,N,N,X, S, S,N,Y,N,N,N,N,N,N),
FCVT_W_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_S -> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_S-> List(N,N,Y,N,N,N,X, S,X2,N,Y,N,N,N,N,Y,N),
FEQ_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLT_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FLE_S -> List(N,N,Y,Y,N,N,N, S, S,N,Y,N,N,N,N,Y,N),
FSGNJ_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FSGNJX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,N,N),
FMIN_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FMAX_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,Y,N,N,N,Y,N),
FADD_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FSUB_S -> List(N,Y,Y,Y,N,N,Y, S, S,N,N,N,Y,N,N,Y,N),
FMUL_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMADD_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FNMSUB_S -> List(N,Y,Y,Y,Y,N,N, S, S,N,N,N,Y,N,N,Y,N),
FDIV_S -> List(N,Y,Y,Y,N,N,N, S, S,N,N,N,N,Y,N,Y,N),
FSQRT_S -> List(N,Y,Y,N,N,N,X, S, S,N,N,N,N,N,Y,Y,N))
val d: Array[(BitPat, List[BitPat])] =
Array(FLD -> List(Y,Y,N,N,N,X,X,X2,X2,N,N,N,N,N,N,N,N),
FSD -> List(Y,N,N,Y,N,Y,X, I, D,N,Y,N,N,N,N,N,N),
FMV_D_X -> List(N,Y,N,N,N,X,X, D, I,Y,N,N,N,N,N,N,N),
FCVT_D_W -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_WU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_L -> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FCVT_D_LU-> List(N,Y,N,N,N,X,X, D, D,Y,N,N,N,N,N,Y,N),
FMV_X_D -> List(N,N,Y,N,N,N,X, I, D,N,Y,N,N,N,N,N,N),
FCLASS_D -> List(N,N,Y,N,N,N,X, D, D,N,Y,N,N,N,N,N,N),
FCVT_W_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_WU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_L_D -> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_LU_D-> List(N,N,Y,N,N,N,X, D,X2,N,Y,N,N,N,N,Y,N),
FCVT_S_D -> List(N,Y,Y,N,N,N,X, D, S,N,N,Y,N,N,N,Y,N),
FCVT_D_S -> List(N,Y,Y,N,N,N,X, S, D,N,N,Y,N,N,N,Y,N),
FEQ_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLT_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FLE_D -> List(N,N,Y,Y,N,N,N, D, D,N,Y,N,N,N,N,Y,N),
FSGNJ_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FSGNJX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,N,N),
FMIN_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FMAX_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,Y,N,N,N,Y,N),
FADD_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FSUB_D -> List(N,Y,Y,Y,N,N,Y, D, D,N,N,N,Y,N,N,Y,N),
FMUL_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMADD_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FNMSUB_D -> List(N,Y,Y,Y,Y,N,N, D, D,N,N,N,Y,N,N,Y,N),
FDIV_D -> List(N,Y,Y,Y,N,N,N, D, D,N,N,N,N,Y,N,Y,N),
FSQRT_D -> List(N,Y,Y,N,N,N,X, D, D,N,N,N,N,N,Y,Y,N))
val fcvt_hd: Array[(BitPat, List[BitPat])] =
Array(FCVT_H_D -> List(N,Y,Y,N,N,N,X, D, H,N,N,Y,N,N,N,Y,N),
FCVT_D_H -> List(N,Y,Y,N,N,N,X, H, D,N,N,Y,N,N,N,Y,N))
val vfmv_f_s: Array[(BitPat, List[BitPat])] =
Array(VFMV_F_S -> List(N,Y,N,N,N,N,X,X2,X2,N,N,N,N,N,N,N,Y))
val insns = ((minFLen, fLen) match {
case (32, 32) => f
case (16, 32) => h ++ f
case (32, 64) => f ++ d
case (16, 64) => h ++ f ++ d ++ fcvt_hd
case other => throw new Exception(s"minFLen = ${minFLen} & fLen = ${fLen} is an unsupported configuration")
}) ++ (if (usingVector) vfmv_f_s else Array[(BitPat, List[BitPat])]())
val decoder = DecodeLogic(io.inst, default, insns)
val s = io.sigs
val sigs = Seq(s.ldst, s.wen, s.ren1, s.ren2, s.ren3, s.swap12,
s.swap23, s.typeTagIn, s.typeTagOut, s.fromint, s.toint,
s.fastpipe, s.fma, s.div, s.sqrt, s.wflags, s.vec)
sigs zip decoder map {case(s,d) => s := d}
}
class FPUCoreIO(implicit p: Parameters) extends CoreBundle()(p) {
val hartid = Input(UInt(hartIdLen.W))
val time = Input(UInt(xLen.W))
val inst = Input(Bits(32.W))
val fromint_data = Input(Bits(xLen.W))
val fcsr_rm = Input(Bits(FPConstants.RM_SZ.W))
val fcsr_flags = Valid(Bits(FPConstants.FLAGS_SZ.W))
val v_sew = Input(UInt(3.W))
val store_data = Output(Bits(fLen.W))
val toint_data = Output(Bits(xLen.W))
val ll_resp_val = Input(Bool())
val ll_resp_type = Input(Bits(3.W))
val ll_resp_tag = Input(UInt(5.W))
val ll_resp_data = Input(Bits(fLen.W))
val valid = Input(Bool())
val fcsr_rdy = Output(Bool())
val nack_mem = Output(Bool())
val illegal_rm = Output(Bool())
val killx = Input(Bool())
val killm = Input(Bool())
val dec = Output(new FPUCtrlSigs())
val sboard_set = Output(Bool())
val sboard_clr = Output(Bool())
val sboard_clra = Output(UInt(5.W))
val keep_clock_enabled = Input(Bool())
}
class FPUIO(implicit p: Parameters) extends FPUCoreIO ()(p) {
val cp_req = Flipped(Decoupled(new FPInput())) //cp doesn't pay attn to kill sigs
val cp_resp = Decoupled(new FPResult())
}
class FPResult(implicit p: Parameters) extends CoreBundle()(p) {
val data = Bits((fLen+1).W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
class IntToFPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val typ = Bits(2.W)
val in1 = Bits(xLen.W)
}
class FPInput(implicit p: Parameters) extends CoreBundle()(p) with HasFPUCtrlSigs {
val rm = Bits(FPConstants.RM_SZ.W)
val fmaCmd = Bits(2.W)
val typ = Bits(2.W)
val fmt = Bits(2.W)
val in1 = Bits((fLen+1).W)
val in2 = Bits((fLen+1).W)
val in3 = Bits((fLen+1).W)
}
case class FType(exp: Int, sig: Int) {
def ieeeWidth = exp + sig
def recodedWidth = ieeeWidth + 1
def ieeeQNaN = ((BigInt(1) << (ieeeWidth - 1)) - (BigInt(1) << (sig - 2))).U(ieeeWidth.W)
def qNaN = ((BigInt(7) << (exp + sig - 3)) + (BigInt(1) << (sig - 2))).U(recodedWidth.W)
def isNaN(x: UInt) = x(sig + exp - 1, sig + exp - 3).andR
def isSNaN(x: UInt) = isNaN(x) && !x(sig - 2)
def classify(x: UInt) = {
val sign = x(sig + exp)
val code = x(exp + sig - 1, exp + sig - 3)
val codeHi = code(2, 1)
val isSpecial = codeHi === 3.U
val isHighSubnormalIn = x(exp + sig - 3, sig - 1) < 2.U
val isSubnormal = code === 1.U || codeHi === 1.U && isHighSubnormalIn
val isNormal = codeHi === 1.U && !isHighSubnormalIn || codeHi === 2.U
val isZero = code === 0.U
val isInf = isSpecial && !code(0)
val isNaN = code.andR
val isSNaN = isNaN && !x(sig-2)
val isQNaN = isNaN && x(sig-2)
Cat(isQNaN, isSNaN, isInf && !sign, isNormal && !sign,
isSubnormal && !sign, isZero && !sign, isZero && sign,
isSubnormal && sign, isNormal && sign, isInf && sign)
}
// convert between formats, ignoring rounding, range, NaN
def unsafeConvert(x: UInt, to: FType) = if (this == to) x else {
val sign = x(sig + exp)
val fractIn = x(sig - 2, 0)
val expIn = x(sig + exp - 1, sig - 1)
val fractOut = fractIn << to.sig >> sig
val expOut = {
val expCode = expIn(exp, exp - 2)
val commonCase = (expIn + (1 << to.exp).U) - (1 << exp).U
Mux(expCode === 0.U || expCode >= 6.U, Cat(expCode, commonCase(to.exp - 3, 0)), commonCase(to.exp, 0))
}
Cat(sign, expOut, fractOut)
}
private def ieeeBundle = {
val expWidth = exp
class IEEEBundle extends Bundle {
val sign = Bool()
val exp = UInt(expWidth.W)
val sig = UInt((ieeeWidth-expWidth-1).W)
}
new IEEEBundle
}
def unpackIEEE(x: UInt) = x.asTypeOf(ieeeBundle)
def recode(x: UInt) = hardfloat.recFNFromFN(exp, sig, x)
def ieee(x: UInt) = hardfloat.fNFromRecFN(exp, sig, x)
}
object FType {
val H = new FType(5, 11)
val S = new FType(8, 24)
val D = new FType(11, 53)
val all = List(H, S, D)
}
trait HasFPUParameters {
require(fLen == 0 || FType.all.exists(_.ieeeWidth == fLen))
val minFLen: Int
val fLen: Int
def xLen: Int
val minXLen = 32
val nIntTypes = log2Ceil(xLen/minXLen) + 1
def floatTypes = FType.all.filter(t => minFLen <= t.ieeeWidth && t.ieeeWidth <= fLen)
def minType = floatTypes.head
def maxType = floatTypes.last
def prevType(t: FType) = floatTypes(typeTag(t) - 1)
def maxExpWidth = maxType.exp
def maxSigWidth = maxType.sig
def typeTag(t: FType) = floatTypes.indexOf(t)
def typeTagWbOffset = (FType.all.indexOf(minType) + 1).U
def typeTagGroup(t: FType) = (if (floatTypes.contains(t)) typeTag(t) else typeTag(maxType)).U
// typeTag
def H = typeTagGroup(FType.H)
def S = typeTagGroup(FType.S)
def D = typeTagGroup(FType.D)
def I = typeTag(maxType).U
private def isBox(x: UInt, t: FType): Bool = x(t.sig + t.exp, t.sig + t.exp - 4).andR
private def box(x: UInt, xt: FType, y: UInt, yt: FType): UInt = {
require(xt.ieeeWidth == 2 * yt.ieeeWidth)
val swizzledNaN = Cat(
x(xt.sig + xt.exp, xt.sig + xt.exp - 3),
x(xt.sig - 2, yt.recodedWidth - 1).andR,
x(xt.sig + xt.exp - 5, xt.sig),
y(yt.recodedWidth - 2),
x(xt.sig - 2, yt.recodedWidth - 1),
y(yt.recodedWidth - 1),
y(yt.recodedWidth - 3, 0))
Mux(xt.isNaN(x), swizzledNaN, x)
}
// implement NaN unboxing for FU inputs
def unbox(x: UInt, tag: UInt, exactType: Option[FType]): UInt = {
val outType = exactType.getOrElse(maxType)
def helper(x: UInt, t: FType): Seq[(Bool, UInt)] = {
val prev =
if (t == minType) {
Seq()
} else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prev = helper(unswizzled, prevT)
val isbox = isBox(x, t)
prev.map(p => (isbox && p._1, p._2))
}
prev :+ (true.B, t.unsafeConvert(x, outType))
}
val (oks, floats) = helper(x, maxType).unzip
if (exactType.isEmpty || floatTypes.size == 1) {
Mux(oks(tag), floats(tag), maxType.qNaN)
} else {
val t = exactType.get
floats(typeTag(t)) | Mux(oks(typeTag(t)), 0.U, t.qNaN)
}
}
// make sure that the redundant bits in the NaN-boxed encoding are consistent
def consistent(x: UInt): Bool = {
def helper(x: UInt, t: FType): Bool = if (typeTag(t) == 0) true.B else {
val prevT = prevType(t)
val unswizzled = Cat(
x(prevT.sig + prevT.exp - 1),
x(t.sig - 1),
x(prevT.sig + prevT.exp - 2, 0))
val prevOK = !isBox(x, t) || helper(unswizzled, prevT)
val curOK = !t.isNaN(x) || x(t.sig + t.exp - 4) === x(t.sig - 2, prevT.recodedWidth - 1).andR
prevOK && curOK
}
helper(x, maxType)
}
// generate a NaN box from an FU result
def box(x: UInt, t: FType): UInt = {
if (t == maxType) {
x
} else {
val nt = floatTypes(typeTag(t) + 1)
val bigger = box(((BigInt(1) << nt.recodedWidth)-1).U, nt, x, t)
bigger | ((BigInt(1) << maxType.recodedWidth) - (BigInt(1) << nt.recodedWidth)).U
}
}
// generate a NaN box from an FU result
def box(x: UInt, tag: UInt): UInt = {
val opts = floatTypes.map(t => box(x, t))
opts(tag)
}
// zap bits that hardfloat thinks are don't-cares, but we do care about
def sanitizeNaN(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
x
} else {
val maskedNaN = x & ~((BigInt(1) << (t.sig-1)) | (BigInt(1) << (t.sig+t.exp-4))).U(t.recodedWidth.W)
Mux(t.isNaN(x), maskedNaN, x)
}
}
// implement NaN boxing and recoding for FL*/fmv.*.x
def recode(x: UInt, tag: UInt): UInt = {
def helper(x: UInt, t: FType): UInt = {
if (typeTag(t) == 0) {
t.recode(x)
} else {
val prevT = prevType(t)
box(t.recode(x), t, helper(x, prevT), prevT)
}
}
// fill MSBs of subword loads to emulate a wider load of a NaN-boxed value
val boxes = floatTypes.map(t => ((BigInt(1) << maxType.ieeeWidth) - (BigInt(1) << t.ieeeWidth)).U)
helper(boxes(tag) | x, maxType)
}
// implement NaN unboxing and un-recoding for FS*/fmv.x.*
def ieee(x: UInt, t: FType = maxType): UInt = {
if (typeTag(t) == 0) {
t.ieee(x)
} else {
val unrecoded = t.ieee(x)
val prevT = prevType(t)
val prevRecoded = Cat(
x(prevT.recodedWidth-2),
x(t.sig-1),
x(prevT.recodedWidth-3, 0))
val prevUnrecoded = ieee(prevRecoded, prevT)
Cat(unrecoded >> prevT.ieeeWidth, Mux(t.isNaN(x), prevUnrecoded, unrecoded(prevT.ieeeWidth-1, 0)))
}
}
}
abstract class FPUModule(implicit val p: Parameters) extends Module with HasCoreParameters with HasFPUParameters
class FPToInt(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
class Output extends Bundle {
val in = new FPInput
val lt = Bool()
val store = Bits(fLen.W)
val toint = Bits(xLen.W)
val exc = Bits(FPConstants.FLAGS_SZ.W)
}
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new Output)
})
val in = RegEnable(io.in.bits, io.in.valid)
val valid = RegNext(io.in.valid)
val dcmp = Module(new hardfloat.CompareRecFN(maxExpWidth, maxSigWidth))
dcmp.io.a := in.in1
dcmp.io.b := in.in2
dcmp.io.signaling := !in.rm(1)
val tag = in.typeTagOut
val toint_ieee = (floatTypes.map(t => if (t == FType.H) Fill(maxType.ieeeWidth / minXLen, ieee(in.in1)(15, 0).sextTo(minXLen))
else Fill(maxType.ieeeWidth / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
val toint = WireDefault(toint_ieee)
val intType = WireDefault(in.fmt(0))
io.out.bits.store := (floatTypes.map(t => Fill(fLen / t.ieeeWidth, ieee(in.in1)(t.ieeeWidth - 1, 0))): Seq[UInt])(tag)
io.out.bits.toint := ((0 until nIntTypes).map(i => toint((minXLen << i) - 1, 0).sextTo(xLen)): Seq[UInt])(intType)
io.out.bits.exc := 0.U
when (in.rm(0)) {
val classify_out = (floatTypes.map(t => t.classify(maxType.unsafeConvert(in.in1, t))): Seq[UInt])(tag)
toint := classify_out | (toint_ieee >> minXLen << minXLen)
intType := false.B
}
when (in.wflags) { // feq/flt/fle, fcvt
toint := (~in.rm & Cat(dcmp.io.lt, dcmp.io.eq)).orR | (toint_ieee >> minXLen << minXLen)
io.out.bits.exc := dcmp.io.exceptionFlags
intType := false.B
when (!in.ren2) { // fcvt
val cvtType = in.typ.extract(log2Ceil(nIntTypes), 1)
intType := cvtType
val conv = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, xLen))
conv.io.in := in.in1
conv.io.roundingMode := in.rm
conv.io.signedOut := ~in.typ(0)
toint := conv.io.out
io.out.bits.exc := Cat(conv.io.intExceptionFlags(2, 1).orR, 0.U(3.W), conv.io.intExceptionFlags(0))
for (i <- 0 until nIntTypes-1) {
val w = minXLen << i
when (cvtType === i.U) {
val narrow = Module(new hardfloat.RecFNToIN(maxExpWidth, maxSigWidth, w))
narrow.io.in := in.in1
narrow.io.roundingMode := in.rm
narrow.io.signedOut := ~in.typ(0)
val excSign = in.in1(maxExpWidth + maxSigWidth) && !maxType.isNaN(in.in1)
val excOut = Cat(conv.io.signedOut === excSign, Fill(w-1, !excSign))
val invalid = conv.io.intExceptionFlags(2) || narrow.io.intExceptionFlags(1)
when (invalid) { toint := Cat(conv.io.out >> w, excOut) }
io.out.bits.exc := Cat(invalid, 0.U(3.W), !invalid && conv.io.intExceptionFlags(0))
}
}
}
}
io.out.valid := valid
io.out.bits.lt := dcmp.io.lt || (dcmp.io.a.asSInt < 0.S && dcmp.io.b.asSInt >= 0.S)
io.out.bits.in := in
}
class IntToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new IntToFPInput))
val out = Valid(new FPResult)
})
val in = Pipe(io.in)
val tag = in.bits.typeTagIn
val mux = Wire(new FPResult)
mux.exc := 0.U
mux.data := recode(in.bits.in1, tag)
val intValue = {
val res = WireDefault(in.bits.in1.asSInt)
for (i <- 0 until nIntTypes-1) {
val smallInt = in.bits.in1((minXLen << i) - 1, 0)
when (in.bits.typ.extract(log2Ceil(nIntTypes), 1) === i.U) {
res := Mux(in.bits.typ(0), smallInt.zext, smallInt.asSInt)
}
}
res.asUInt
}
when (in.bits.wflags) { // fcvt
// could be improved for RVD/RVQ with a single variable-position rounding
// unit, rather than N fixed-position ones
val i2fResults = for (t <- floatTypes) yield {
val i2f = Module(new hardfloat.INToRecFN(xLen, t.exp, t.sig))
i2f.io.signedIn := ~in.bits.typ(0)
i2f.io.in := intValue
i2f.io.roundingMode := in.bits.rm
i2f.io.detectTininess := hardfloat.consts.tininess_afterRounding
(sanitizeNaN(i2f.io.out, t), i2f.io.exceptionFlags)
}
val (data, exc) = i2fResults.unzip
val dataPadded = data.init.map(d => Cat(data.last >> d.getWidth, d)) :+ data.last
mux.data := dataPadded(tag)
mux.exc := exc(tag)
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class FPToFP(val latency: Int)(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
val lt = Input(Bool()) // from FPToInt
})
val in = Pipe(io.in)
val signNum = Mux(in.bits.rm(1), in.bits.in1 ^ in.bits.in2, Mux(in.bits.rm(0), ~in.bits.in2, in.bits.in2))
val fsgnj = Cat(signNum(fLen), in.bits.in1(fLen-1, 0))
val fsgnjMux = Wire(new FPResult)
fsgnjMux.exc := 0.U
fsgnjMux.data := fsgnj
when (in.bits.wflags) { // fmin/fmax
val isnan1 = maxType.isNaN(in.bits.in1)
val isnan2 = maxType.isNaN(in.bits.in2)
val isInvalid = maxType.isSNaN(in.bits.in1) || maxType.isSNaN(in.bits.in2)
val isNaNOut = isnan1 && isnan2
val isLHS = isnan2 || in.bits.rm(0) =/= io.lt && !isnan1
fsgnjMux.exc := isInvalid << 4
fsgnjMux.data := Mux(isNaNOut, maxType.qNaN, Mux(isLHS, in.bits.in1, in.bits.in2))
}
val inTag = in.bits.typeTagIn
val outTag = in.bits.typeTagOut
val mux = WireDefault(fsgnjMux)
for (t <- floatTypes.init) {
when (outTag === typeTag(t).U) {
mux.data := Cat(fsgnjMux.data >> t.recodedWidth, maxType.unsafeConvert(fsgnjMux.data, t))
}
}
when (in.bits.wflags && !in.bits.ren2) { // fcvt
if (floatTypes.size > 1) {
// widening conversions simply canonicalize NaN operands
val widened = Mux(maxType.isNaN(in.bits.in1), maxType.qNaN, in.bits.in1)
fsgnjMux.data := widened
fsgnjMux.exc := maxType.isSNaN(in.bits.in1) << 4
// narrowing conversions require rounding (for RVQ, this could be
// optimized to use a single variable-position rounding unit, rather
// than two fixed-position ones)
for (outType <- floatTypes.init) when (outTag === typeTag(outType).U && ((typeTag(outType) == 0).B || outTag < inTag)) {
val narrower = Module(new hardfloat.RecFNToRecFN(maxType.exp, maxType.sig, outType.exp, outType.sig))
narrower.io.in := in.bits.in1
narrower.io.roundingMode := in.bits.rm
narrower.io.detectTininess := hardfloat.consts.tininess_afterRounding
val narrowed = sanitizeNaN(narrower.io.out, outType)
mux.data := Cat(fsgnjMux.data >> narrowed.getWidth, narrowed)
mux.exc := narrower.io.exceptionFlags
}
}
}
io.out <> Pipe(in.valid, mux, latency-1)
}
class MulAddRecFNPipe(latency: Int, expWidth: Int, sigWidth: Int) extends Module
{
override def desiredName = s"MulAddRecFNPipe_l${latency}_e${expWidth}_s${sigWidth}"
require(latency<=2)
val io = IO(new Bundle {
val validin = Input(Bool())
val op = Input(Bits(2.W))
val a = Input(Bits((expWidth + sigWidth + 1).W))
val b = Input(Bits((expWidth + sigWidth + 1).W))
val c = Input(Bits((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
val validout = Output(Bool())
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulAddRecFNToRaw_preMul = Module(new hardfloat.MulAddRecFNToRaw_preMul(expWidth, sigWidth))
val mulAddRecFNToRaw_postMul = Module(new hardfloat.MulAddRecFNToRaw_postMul(expWidth, sigWidth))
mulAddRecFNToRaw_preMul.io.op := io.op
mulAddRecFNToRaw_preMul.io.a := io.a
mulAddRecFNToRaw_preMul.io.b := io.b
mulAddRecFNToRaw_preMul.io.c := io.c
val mulAddResult =
(mulAddRecFNToRaw_preMul.io.mulAddA *
mulAddRecFNToRaw_preMul.io.mulAddB) +&
mulAddRecFNToRaw_preMul.io.mulAddC
val valid_stage0 = Wire(Bool())
val roundingMode_stage0 = Wire(UInt(3.W))
val detectTininess_stage0 = Wire(UInt(1.W))
val postmul_regs = if(latency>0) 1 else 0
mulAddRecFNToRaw_postMul.io.fromPreMul := Pipe(io.validin, mulAddRecFNToRaw_preMul.io.toPostMul, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.mulAddResult := Pipe(io.validin, mulAddResult, postmul_regs).bits
mulAddRecFNToRaw_postMul.io.roundingMode := Pipe(io.validin, io.roundingMode, postmul_regs).bits
roundingMode_stage0 := Pipe(io.validin, io.roundingMode, postmul_regs).bits
detectTininess_stage0 := Pipe(io.validin, io.detectTininess, postmul_regs).bits
valid_stage0 := Pipe(io.validin, false.B, postmul_regs).valid
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN = Module(new hardfloat.RoundRawFNToRecFN(expWidth, sigWidth, 0))
val round_regs = if(latency==2) 1 else 0
roundRawFNToRecFN.io.invalidExc := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.invalidExc, round_regs).bits
roundRawFNToRecFN.io.in := Pipe(valid_stage0, mulAddRecFNToRaw_postMul.io.rawOut, round_regs).bits
roundRawFNToRecFN.io.roundingMode := Pipe(valid_stage0, roundingMode_stage0, round_regs).bits
roundRawFNToRecFN.io.detectTininess := Pipe(valid_stage0, detectTininess_stage0, round_regs).bits
io.validout := Pipe(valid_stage0, false.B, round_regs).valid
roundRawFNToRecFN.io.infiniteExc := false.B
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
class FPUFMAPipe(val latency: Int, val t: FType)
(implicit p: Parameters) extends FPUModule()(p) with ShouldBeRetimed {
override def desiredName = s"FPUFMAPipe_l${latency}_f${t.ieeeWidth}"
require(latency>0)
val io = IO(new Bundle {
val in = Flipped(Valid(new FPInput))
val out = Valid(new FPResult)
})
val valid = RegNext(io.in.valid)
val in = Reg(new FPInput)
when (io.in.valid) {
val one = 1.U << (t.sig + t.exp - 1)
val zero = (io.in.bits.in1 ^ io.in.bits.in2) & (1.U << (t.sig + t.exp))
val cmd_fma = io.in.bits.ren3
val cmd_addsub = io.in.bits.swap23
in := io.in.bits
when (cmd_addsub) { in.in2 := one }
when (!(cmd_fma || cmd_addsub)) { in.in3 := zero }
}
val fma = Module(new MulAddRecFNPipe((latency-1) min 2, t.exp, t.sig))
fma.io.validin := valid
fma.io.op := in.fmaCmd
fma.io.roundingMode := in.rm
fma.io.detectTininess := hardfloat.consts.tininess_afterRounding
fma.io.a := in.in1
fma.io.b := in.in2
fma.io.c := in.in3
val res = Wire(new FPResult)
res.data := sanitizeNaN(fma.io.out, t)
res.exc := fma.io.exceptionFlags
io.out := Pipe(fma.io.validout, res, (latency-3) max 0)
}
class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
val io = IO(new FPUIO)
val (useClockGating, useDebugROB) = coreParams match {
case r: RocketCoreParams =>
val sz = if (r.debugROB.isDefined) r.debugROB.get.size else 1
(r.clockGate, sz < 1)
case _ => (false, false)
}
val clock_en_reg = Reg(Bool())
val clock_en = clock_en_reg || io.cp_req.valid
val gated_clock =
if (!useClockGating) clock
else ClockGate(clock, clock_en, "fpu_clock_gate")
val fp_decoder = Module(new FPUDecoder)
fp_decoder.io.inst := io.inst
val id_ctrl = WireInit(fp_decoder.io.sigs)
coreParams match { case r: RocketCoreParams => r.vector.map(v => {
val v_decode = v.decoder(p) // Only need to get ren1
v_decode.io.inst := io.inst
v_decode.io.vconfig := DontCare // core deals with this
when (v_decode.io.legal && v_decode.io.read_frs1) {
id_ctrl.ren1 := true.B
id_ctrl.swap12 := false.B
id_ctrl.toint := true.B
id_ctrl.typeTagIn := I
id_ctrl.typeTagOut := Mux(io.v_sew === 3.U, D, S)
}
when (v_decode.io.write_frd) { id_ctrl.wen := true.B }
})}
val ex_reg_valid = RegNext(io.valid, false.B)
val ex_reg_inst = RegEnable(io.inst, io.valid)
val ex_reg_ctrl = RegEnable(id_ctrl, io.valid)
val ex_ra = List.fill(3)(Reg(UInt()))
// load/vector response
val load_wb = RegNext(io.ll_resp_val)
val load_wb_typeTag = RegEnable(io.ll_resp_type(1,0) - typeTagWbOffset, io.ll_resp_val)
val load_wb_data = RegEnable(io.ll_resp_data, io.ll_resp_val)
val load_wb_tag = RegEnable(io.ll_resp_tag, io.ll_resp_val)
class FPUImpl { // entering gated-clock domain
val req_valid = ex_reg_valid || io.cp_req.valid
val ex_cp_valid = io.cp_req.fire
val mem_cp_valid = RegNext(ex_cp_valid, false.B)
val wb_cp_valid = RegNext(mem_cp_valid, false.B)
val mem_reg_valid = RegInit(false.B)
val killm = (io.killm || io.nack_mem) && !mem_cp_valid
// Kill X-stage instruction if M-stage is killed. This prevents it from
// speculatively being sent to the div-sqrt unit, which can cause priority
// inversion for two back-to-back divides, the first of which is killed.
val killx = io.killx || mem_reg_valid && killm
mem_reg_valid := ex_reg_valid && !killx || ex_cp_valid
val mem_reg_inst = RegEnable(ex_reg_inst, ex_reg_valid)
val wb_reg_valid = RegNext(mem_reg_valid && (!killm || mem_cp_valid), false.B)
val cp_ctrl = Wire(new FPUCtrlSigs)
cp_ctrl :<>= io.cp_req.bits.viewAsSupertype(new FPUCtrlSigs)
io.cp_resp.valid := false.B
io.cp_resp.bits.data := 0.U
io.cp_resp.bits.exc := DontCare
val ex_ctrl = Mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl)
val mem_ctrl = RegEnable(ex_ctrl, req_valid)
val wb_ctrl = RegEnable(mem_ctrl, mem_reg_valid)
// CoreMonitorBundle to monitor fp register file writes
val frfWriteBundle = Seq.fill(2)(WireInit(new CoreMonitorBundle(xLen, fLen), DontCare))
frfWriteBundle.foreach { i =>
i.clock := clock
i.reset := reset
i.hartid := io.hartid
i.timer := io.time(31,0)
i.valid := false.B
i.wrenx := false.B
i.wrenf := false.B
i.excpt := false.B
}
// regfile
val regfile = Mem(32, Bits((fLen+1).W))
when (load_wb) {
val wdata = recode(load_wb_data, load_wb_typeTag)
regfile(load_wb_tag) := wdata
assert(consistent(wdata))
if (enableCommitLog)
printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32.U, ieee(wdata))
if (useDebugROB)
DebugROB.pushWb(clock, reset, io.hartid, load_wb, load_wb_tag + 32.U, ieee(wdata))
frfWriteBundle(0).wrdst := load_wb_tag
frfWriteBundle(0).wrenf := true.B
frfWriteBundle(0).wrdata := ieee(wdata)
}
val ex_rs = ex_ra.map(a => regfile(a))
when (io.valid) {
when (id_ctrl.ren1) {
when (!id_ctrl.swap12) { ex_ra(0) := io.inst(19,15) }
when (id_ctrl.swap12) { ex_ra(1) := io.inst(19,15) }
}
when (id_ctrl.ren2) {
when (id_ctrl.swap12) { ex_ra(0) := io.inst(24,20) }
when (id_ctrl.swap23) { ex_ra(2) := io.inst(24,20) }
when (!id_ctrl.swap12 && !id_ctrl.swap23) { ex_ra(1) := io.inst(24,20) }
}
when (id_ctrl.ren3) { ex_ra(2) := io.inst(31,27) }
}
val ex_rm = Mux(ex_reg_inst(14,12) === 7.U, io.fcsr_rm, ex_reg_inst(14,12))
def fuInput(minT: Option[FType]): FPInput = {
val req = Wire(new FPInput)
val tag = ex_ctrl.typeTagIn
req.viewAsSupertype(new Bundle with HasFPUCtrlSigs) :#= ex_ctrl.viewAsSupertype(new Bundle with HasFPUCtrlSigs)
req.rm := ex_rm
req.in1 := unbox(ex_rs(0), tag, minT)
req.in2 := unbox(ex_rs(1), tag, minT)
req.in3 := unbox(ex_rs(2), tag, minT)
req.typ := ex_reg_inst(21,20)
req.fmt := ex_reg_inst(26,25)
req.fmaCmd := ex_reg_inst(3,2) | (!ex_ctrl.ren3 && ex_reg_inst(27))
when (ex_cp_valid) {
req := io.cp_req.bits
when (io.cp_req.bits.swap12) {
req.in1 := io.cp_req.bits.in2
req.in2 := io.cp_req.bits.in1
}
when (io.cp_req.bits.swap23) {
req.in2 := io.cp_req.bits.in3
req.in3 := io.cp_req.bits.in2
}
}
req
}
val sfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.S))
sfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === S
sfma.io.in.bits := fuInput(Some(sfma.t))
val fpiu = Module(new FPToInt)
fpiu.io.in.valid := req_valid && (ex_ctrl.toint || ex_ctrl.div || ex_ctrl.sqrt || (ex_ctrl.fastpipe && ex_ctrl.wflags))
fpiu.io.in.bits := fuInput(None)
io.store_data := fpiu.io.out.bits.store
io.toint_data := fpiu.io.out.bits.toint
when(fpiu.io.out.valid && mem_cp_valid && mem_ctrl.toint){
io.cp_resp.bits.data := fpiu.io.out.bits.toint
io.cp_resp.valid := true.B
}
val ifpu = Module(new IntToFP(cfg.ifpuLatency))
ifpu.io.in.valid := req_valid && ex_ctrl.fromint
ifpu.io.in.bits := fpiu.io.in.bits
ifpu.io.in.bits.in1 := Mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data)
val fpmu = Module(new FPToFP(cfg.fpmuLatency))
fpmu.io.in.valid := req_valid && ex_ctrl.fastpipe
fpmu.io.in.bits := fpiu.io.in.bits
fpmu.io.lt := fpiu.io.out.bits.lt
val divSqrt_wen = WireDefault(false.B)
val divSqrt_inFlight = WireDefault(false.B)
val divSqrt_waddr = Reg(UInt(5.W))
val divSqrt_cp = Reg(Bool())
val divSqrt_typeTag = Wire(UInt(log2Up(floatTypes.size).W))
val divSqrt_wdata = Wire(UInt((fLen+1).W))
val divSqrt_flags = Wire(UInt(FPConstants.FLAGS_SZ.W))
divSqrt_typeTag := DontCare
divSqrt_wdata := DontCare
divSqrt_flags := DontCare
// writeback arbitration
case class Pipe(p: Module, lat: Int, cond: (FPUCtrlSigs) => Bool, res: FPResult)
val pipes = List(
Pipe(fpmu, fpmu.latency, (c: FPUCtrlSigs) => c.fastpipe, fpmu.io.out.bits),
Pipe(ifpu, ifpu.latency, (c: FPUCtrlSigs) => c.fromint, ifpu.io.out.bits),
Pipe(sfma, sfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === S, sfma.io.out.bits)) ++
(fLen > 32).option({
val dfma = Module(new FPUFMAPipe(cfg.dfmaLatency, FType.D))
dfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === D
dfma.io.in.bits := fuInput(Some(dfma.t))
Pipe(dfma, dfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === D, dfma.io.out.bits)
}) ++
(minFLen == 16).option({
val hfma = Module(new FPUFMAPipe(cfg.sfmaLatency, FType.H))
hfma.io.in.valid := req_valid && ex_ctrl.fma && ex_ctrl.typeTagOut === H
hfma.io.in.bits := fuInput(Some(hfma.t))
Pipe(hfma, hfma.latency, (c: FPUCtrlSigs) => c.fma && c.typeTagOut === H, hfma.io.out.bits)
})
def latencyMask(c: FPUCtrlSigs, offset: Int) = {
require(pipes.forall(_.lat >= offset))
pipes.map(p => Mux(p.cond(c), (1 << p.lat-offset).U, 0.U)).reduce(_|_)
}
def pipeid(c: FPUCtrlSigs) = pipes.zipWithIndex.map(p => Mux(p._1.cond(c), p._2.U, 0.U)).reduce(_|_)
val maxLatency = pipes.map(_.lat).max
val memLatencyMask = latencyMask(mem_ctrl, 2)
class WBInfo extends Bundle {
val rd = UInt(5.W)
val typeTag = UInt(log2Up(floatTypes.size).W)
val cp = Bool()
val pipeid = UInt(log2Ceil(pipes.size).W)
}
val wen = RegInit(0.U((maxLatency-1).W))
val wbInfo = Reg(Vec(maxLatency-1, new WBInfo))
val mem_wen = mem_reg_valid && (mem_ctrl.fma || mem_ctrl.fastpipe || mem_ctrl.fromint)
val write_port_busy = RegEnable(mem_wen && (memLatencyMask & latencyMask(ex_ctrl, 1)).orR || (wen & latencyMask(ex_ctrl, 0)).orR, req_valid)
ccover(mem_reg_valid && write_port_busy, "WB_STRUCTURAL", "structural hazard on writeback")
for (i <- 0 until maxLatency-2) {
when (wen(i+1)) { wbInfo(i) := wbInfo(i+1) }
}
wen := wen >> 1
when (mem_wen) {
when (!killm) {
wen := wen >> 1 | memLatencyMask
}
for (i <- 0 until maxLatency-1) {
when (!write_port_busy && memLatencyMask(i)) {
wbInfo(i).cp := mem_cp_valid
wbInfo(i).typeTag := mem_ctrl.typeTagOut
wbInfo(i).pipeid := pipeid(mem_ctrl)
wbInfo(i).rd := mem_reg_inst(11,7)
}
}
}
val waddr = Mux(divSqrt_wen, divSqrt_waddr, wbInfo(0).rd)
val wb_cp = Mux(divSqrt_wen, divSqrt_cp, wbInfo(0).cp)
val wtypeTag = Mux(divSqrt_wen, divSqrt_typeTag, wbInfo(0).typeTag)
val wdata = box(Mux(divSqrt_wen, divSqrt_wdata, (pipes.map(_.res.data): Seq[UInt])(wbInfo(0).pipeid)), wtypeTag)
val wexc = (pipes.map(_.res.exc): Seq[UInt])(wbInfo(0).pipeid)
when ((!wbInfo(0).cp && wen(0)) || divSqrt_wen) {
assert(consistent(wdata))
regfile(waddr) := wdata
if (enableCommitLog) {
printf("f%d p%d 0x%x\n", waddr, waddr + 32.U, ieee(wdata))
}
frfWriteBundle(1).wrdst := waddr
frfWriteBundle(1).wrenf := true.B
frfWriteBundle(1).wrdata := ieee(wdata)
}
if (useDebugROB) {
DebugROB.pushWb(clock, reset, io.hartid, (!wbInfo(0).cp && wen(0)) || divSqrt_wen, waddr + 32.U, ieee(wdata))
}
when (wb_cp && (wen(0) || divSqrt_wen)) {
io.cp_resp.bits.data := wdata
io.cp_resp.valid := true.B
}
assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,
s"FPU only supports coprocessor if FMA pipes have uniform latency ${pipes.map(_.lat)}")
// Avoid structural hazards and nacking of external requests
// toint responds in the MEM stage, so an incoming toint can induce a structural hazard against inflight FMAs
io.cp_req.ready := !ex_reg_valid && !(cp_ctrl.toint && wen =/= 0.U) && !divSqrt_inFlight
val wb_toint_valid = wb_reg_valid && wb_ctrl.toint
val wb_toint_exc = RegEnable(fpiu.io.out.bits.exc, mem_ctrl.toint)
io.fcsr_flags.valid := wb_toint_valid || divSqrt_wen || wen(0)
io.fcsr_flags.bits :=
Mux(wb_toint_valid, wb_toint_exc, 0.U) |
Mux(divSqrt_wen, divSqrt_flags, 0.U) |
Mux(wen(0), wexc, 0.U)
val divSqrt_write_port_busy = (mem_ctrl.div || mem_ctrl.sqrt) && wen.orR
io.fcsr_rdy := !(ex_reg_valid && ex_ctrl.wflags || mem_reg_valid && mem_ctrl.wflags || wb_reg_valid && wb_ctrl.toint || wen.orR || divSqrt_inFlight)
io.nack_mem := (write_port_busy || divSqrt_write_port_busy || divSqrt_inFlight) && !mem_cp_valid
io.dec <> id_ctrl
def useScoreboard(f: ((Pipe, Int)) => Bool) = pipes.zipWithIndex.filter(_._1.lat > 3).map(x => f(x)).fold(false.B)(_||_)
io.sboard_set := wb_reg_valid && !wb_cp_valid && RegNext(useScoreboard(_._1.cond(mem_ctrl)) || mem_ctrl.div || mem_ctrl.sqrt || mem_ctrl.vec)
io.sboard_clr := !wb_cp_valid && (divSqrt_wen || (wen(0) && useScoreboard(x => wbInfo(0).pipeid === x._2.U)))
io.sboard_clra := waddr
ccover(io.sboard_clr && load_wb, "DUAL_WRITEBACK", "load and FMA writeback on same cycle")
// we don't currently support round-max-magnitude (rm=4)
io.illegal_rm := io.inst(14,12).isOneOf(5.U, 6.U) || io.inst(14,12) === 7.U && io.fcsr_rm >= 5.U
if (cfg.divSqrt) {
val divSqrt_inValid = mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt) && !divSqrt_inFlight
val divSqrt_killed = RegNext(divSqrt_inValid && killm, true.B)
when (divSqrt_inValid) {
divSqrt_waddr := mem_reg_inst(11,7)
divSqrt_cp := mem_cp_valid
}
ccover(divSqrt_inFlight && divSqrt_killed, "DIV_KILLED", "divide killed after issued to divider")
ccover(divSqrt_inFlight && mem_reg_valid && (mem_ctrl.div || mem_ctrl.sqrt), "DIV_BUSY", "divider structural hazard")
ccover(mem_reg_valid && divSqrt_write_port_busy, "DIV_WB_STRUCTURAL", "structural hazard on division writeback")
for (t <- floatTypes) {
val tag = mem_ctrl.typeTagOut
val divSqrt = withReset(divSqrt_killed) { Module(new hardfloat.DivSqrtRecFN_small(t.exp, t.sig, 0)) }
divSqrt.io.inValid := divSqrt_inValid && tag === typeTag(t).U
divSqrt.io.sqrtOp := mem_ctrl.sqrt
divSqrt.io.a := maxType.unsafeConvert(fpiu.io.out.bits.in.in1, t)
divSqrt.io.b := maxType.unsafeConvert(fpiu.io.out.bits.in.in2, t)
divSqrt.io.roundingMode := fpiu.io.out.bits.in.rm
divSqrt.io.detectTininess := hardfloat.consts.tininess_afterRounding
when (!divSqrt.io.inReady) { divSqrt_inFlight := true.B } // only 1 in flight
when (divSqrt.io.outValid_div || divSqrt.io.outValid_sqrt) {
divSqrt_wen := !divSqrt_killed
divSqrt_wdata := sanitizeNaN(divSqrt.io.out, t)
divSqrt_flags := divSqrt.io.exceptionFlags
divSqrt_typeTag := typeTag(t).U
}
}
when (divSqrt_killed) { divSqrt_inFlight := false.B }
} else {
when (id_ctrl.div || id_ctrl.sqrt) { io.illegal_rm := true.B }
}
// gate the clock
clock_en_reg := !useClockGating.B ||
io.keep_clock_enabled || // chicken bit
io.valid || // ID stage
req_valid || // EX stage
mem_reg_valid || mem_cp_valid || // MEM stage
wb_reg_valid || wb_cp_valid || // WB stage
wen.orR || divSqrt_inFlight || // post-WB stage
io.ll_resp_val // load writeback
} // leaving gated-clock domain
val fpuImpl = withClock (gated_clock) { new FPUImpl }
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"FPU_$label", "Core;;" + desc)
}
|
module FPToFP( // @[FPU.scala:573:7]
input clock, // @[FPU.scala:573:7]
input reset, // @[FPU.scala:573:7]
input io_in_valid, // @[FPU.scala:574:14]
input io_in_bits_ldst, // @[FPU.scala:574:14]
input io_in_bits_wen, // @[FPU.scala:574:14]
input io_in_bits_ren1, // @[FPU.scala:574:14]
input io_in_bits_ren2, // @[FPU.scala:574:14]
input io_in_bits_ren3, // @[FPU.scala:574:14]
input io_in_bits_swap12, // @[FPU.scala:574:14]
input io_in_bits_swap23, // @[FPU.scala:574:14]
input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:574:14]
input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:574:14]
input io_in_bits_fromint, // @[FPU.scala:574:14]
input io_in_bits_toint, // @[FPU.scala:574:14]
input io_in_bits_fastpipe, // @[FPU.scala:574:14]
input io_in_bits_fma, // @[FPU.scala:574:14]
input io_in_bits_div, // @[FPU.scala:574:14]
input io_in_bits_sqrt, // @[FPU.scala:574:14]
input io_in_bits_wflags, // @[FPU.scala:574:14]
input io_in_bits_vec, // @[FPU.scala:574:14]
input [2:0] io_in_bits_rm, // @[FPU.scala:574:14]
input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:574:14]
input [1:0] io_in_bits_typ, // @[FPU.scala:574:14]
input [1:0] io_in_bits_fmt, // @[FPU.scala:574:14]
input [64:0] io_in_bits_in1, // @[FPU.scala:574:14]
input [64:0] io_in_bits_in2, // @[FPU.scala:574:14]
input [64:0] io_in_bits_in3, // @[FPU.scala:574:14]
output [64:0] io_out_bits_data, // @[FPU.scala:574:14]
output [4:0] io_out_bits_exc, // @[FPU.scala:574:14]
input io_lt // @[FPU.scala:574:14]
);
wire [32:0] _narrower_1_io_out; // @[FPU.scala:619:30]
wire [4:0] _narrower_1_io_exceptionFlags; // @[FPU.scala:619:30]
wire [16:0] _narrower_io_out; // @[FPU.scala:619:30]
wire [4:0] _narrower_io_exceptionFlags; // @[FPU.scala:619:30]
wire io_in_valid_0 = io_in_valid; // @[FPU.scala:573:7]
wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:573:7]
wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:573:7]
wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:573:7]
wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:573:7]
wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:573:7]
wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:573:7]
wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:573:7]
wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:573:7]
wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:573:7]
wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:573:7]
wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:573:7]
wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:573:7]
wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:573:7]
wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:573:7]
wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:573:7]
wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:573:7]
wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:573:7]
wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:573:7]
wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:573:7]
wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:573:7]
wire io_lt_0 = io_lt; // @[FPU.scala:573:7]
wire [32:0] _narrowed_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27]
wire io_out_pipe_out_valid; // @[Valid.scala:135:21]
wire [64:0] io_out_pipe_out_bits_data; // @[Valid.scala:135:21]
wire [4:0] io_out_pipe_out_bits_exc; // @[Valid.scala:135:21]
wire [64:0] io_out_bits_data_0; // @[FPU.scala:573:7]
wire [4:0] io_out_bits_exc_0; // @[FPU.scala:573:7]
wire io_out_valid; // @[FPU.scala:573:7]
reg in_pipe_v; // @[Valid.scala:141:24]
wire in_valid = in_pipe_v; // @[Valid.scala:135:21, :141:24]
reg in_pipe_b_ldst; // @[Valid.scala:142:26]
wire in_bits_ldst = in_pipe_b_ldst; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_wen; // @[Valid.scala:142:26]
wire in_bits_wen = in_pipe_b_wen; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren1; // @[Valid.scala:142:26]
wire in_bits_ren1 = in_pipe_b_ren1; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren2; // @[Valid.scala:142:26]
wire in_bits_ren2 = in_pipe_b_ren2; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_ren3; // @[Valid.scala:142:26]
wire in_bits_ren3 = in_pipe_b_ren3; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_swap12; // @[Valid.scala:142:26]
wire in_bits_swap12 = in_pipe_b_swap12; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_swap23; // @[Valid.scala:142:26]
wire in_bits_swap23 = in_pipe_b_swap23; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typeTagIn; // @[Valid.scala:142:26]
wire [1:0] in_bits_typeTagIn = in_pipe_b_typeTagIn; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typeTagOut; // @[Valid.scala:142:26]
wire [1:0] in_bits_typeTagOut = in_pipe_b_typeTagOut; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fromint; // @[Valid.scala:142:26]
wire in_bits_fromint = in_pipe_b_fromint; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_toint; // @[Valid.scala:142:26]
wire in_bits_toint = in_pipe_b_toint; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fastpipe; // @[Valid.scala:142:26]
wire in_bits_fastpipe = in_pipe_b_fastpipe; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_fma; // @[Valid.scala:142:26]
wire in_bits_fma = in_pipe_b_fma; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_div; // @[Valid.scala:142:26]
wire in_bits_div = in_pipe_b_div; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_sqrt; // @[Valid.scala:142:26]
wire in_bits_sqrt = in_pipe_b_sqrt; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_wflags; // @[Valid.scala:142:26]
wire in_bits_wflags = in_pipe_b_wflags; // @[Valid.scala:135:21, :142:26]
reg in_pipe_b_vec; // @[Valid.scala:142:26]
wire in_bits_vec = in_pipe_b_vec; // @[Valid.scala:135:21, :142:26]
reg [2:0] in_pipe_b_rm; // @[Valid.scala:142:26]
wire [2:0] in_bits_rm = in_pipe_b_rm; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_fmaCmd; // @[Valid.scala:142:26]
wire [1:0] in_bits_fmaCmd = in_pipe_b_fmaCmd; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_typ; // @[Valid.scala:142:26]
wire [1:0] in_bits_typ = in_pipe_b_typ; // @[Valid.scala:135:21, :142:26]
reg [1:0] in_pipe_b_fmt; // @[Valid.scala:142:26]
wire [1:0] in_bits_fmt = in_pipe_b_fmt; // @[Valid.scala:135:21, :142:26]
reg [64:0] in_pipe_b_in1; // @[Valid.scala:142:26]
wire [64:0] in_bits_in1 = in_pipe_b_in1; // @[Valid.scala:135:21, :142:26]
reg [64:0] in_pipe_b_in2; // @[Valid.scala:142:26]
wire [64:0] in_bits_in2 = in_pipe_b_in2; // @[Valid.scala:135:21, :142:26]
reg [64:0] in_pipe_b_in3; // @[Valid.scala:142:26]
wire [64:0] in_bits_in3 = in_pipe_b_in3; // @[Valid.scala:135:21, :142:26]
wire _signNum_T = in_bits_rm[1]; // @[Valid.scala:135:21]
wire [64:0] _signNum_T_1 = in_bits_in1 ^ in_bits_in2; // @[Valid.scala:135:21]
wire _signNum_T_2 = in_bits_rm[0]; // @[Valid.scala:135:21]
wire _isLHS_T = in_bits_rm[0]; // @[Valid.scala:135:21]
wire [64:0] _signNum_T_3 = ~in_bits_in2; // @[Valid.scala:135:21]
wire [64:0] _signNum_T_4 = _signNum_T_2 ? _signNum_T_3 : in_bits_in2; // @[Valid.scala:135:21]
wire [64:0] signNum = _signNum_T ? _signNum_T_1 : _signNum_T_4; // @[FPU.scala:582:{20,31,48,66}]
wire _fsgnj_T = signNum[64]; // @[FPU.scala:582:20, :583:26]
wire [63:0] _fsgnj_T_1 = in_bits_in1[63:0]; // @[Valid.scala:135:21]
wire [64:0] fsgnj = {_fsgnj_T, _fsgnj_T_1}; // @[FPU.scala:583:{18,26,45}]
wire [64:0] fsgnjMux_data; // @[FPU.scala:585:22]
wire [4:0] fsgnjMux_exc; // @[FPU.scala:585:22]
wire [2:0] _isnan1_T = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire [2:0] _isInvalid_T = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire [2:0] _widened_T = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire [2:0] _fsgnjMux_exc_T_1 = in_bits_in1[63:61]; // @[Valid.scala:135:21]
wire isnan1 = &_isnan1_T; // @[FPU.scala:249:{25,56}]
wire [2:0] _isnan2_T = in_bits_in2[63:61]; // @[Valid.scala:135:21]
wire [2:0] _isInvalid_T_5 = in_bits_in2[63:61]; // @[Valid.scala:135:21]
wire isnan2 = &_isnan2_T; // @[FPU.scala:249:{25,56}]
wire _isInvalid_T_1 = &_isInvalid_T; // @[FPU.scala:249:{25,56}]
wire _isInvalid_T_2 = in_bits_in1[51]; // @[Valid.scala:135:21]
wire _fsgnjMux_exc_T_3 = in_bits_in1[51]; // @[Valid.scala:135:21]
wire _isInvalid_T_3 = ~_isInvalid_T_2; // @[FPU.scala:250:{37,39}]
wire _isInvalid_T_4 = _isInvalid_T_1 & _isInvalid_T_3; // @[FPU.scala:249:56, :250:{34,37}]
wire _isInvalid_T_6 = &_isInvalid_T_5; // @[FPU.scala:249:{25,56}]
wire _isInvalid_T_7 = in_bits_in2[51]; // @[Valid.scala:135:21]
wire _isInvalid_T_8 = ~_isInvalid_T_7; // @[FPU.scala:250:{37,39}]
wire _isInvalid_T_9 = _isInvalid_T_6 & _isInvalid_T_8; // @[FPU.scala:249:56, :250:{34,37}]
wire isInvalid = _isInvalid_T_4 | _isInvalid_T_9; // @[FPU.scala:250:34, :592:49]
wire isNaNOut = isnan1 & isnan2; // @[FPU.scala:249:56, :593:27]
wire _isLHS_T_1 = _isLHS_T != io_lt_0; // @[FPU.scala:573:7, :594:{37,41}]
wire _isLHS_T_2 = ~isnan1; // @[FPU.scala:249:56, :594:54]
wire _isLHS_T_3 = _isLHS_T_1 & _isLHS_T_2; // @[FPU.scala:594:{41,51,54}]
wire isLHS = isnan2 | _isLHS_T_3; // @[FPU.scala:249:56, :594:{24,51}]
wire [4:0] _fsgnjMux_exc_T = {isInvalid, 4'h0}; // @[FPU.scala:592:49, :595:31]
wire [64:0] _fsgnjMux_data_T = isLHS ? in_bits_in1 : in_bits_in2; // @[Valid.scala:135:21]
wire [64:0] _fsgnjMux_data_T_1 = isNaNOut ? 65'hE008000000000000 : _fsgnjMux_data_T; // @[FPU.scala:593:27, :596:{25,53}]
wire [64:0] mux_data; // @[FPU.scala:601:24]
wire [4:0] mux_exc; // @[FPU.scala:601:24]
wire _T_7 = in_bits_typeTagOut == 2'h0; // @[Valid.scala:135:21]
wire [47:0] _mux_data_T = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37]
wire [47:0] _mux_data_T_6 = fsgnjMux_data[64:17]; // @[FPU.scala:585:22, :604:37, :624:39]
wire mux_data_sign = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22]
wire mux_data_sign_1 = fsgnjMux_data[64]; // @[FPU.scala:274:17, :585:22]
wire [51:0] mux_data_fractIn = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22]
wire [51:0] mux_data_fractIn_1 = fsgnjMux_data[51:0]; // @[FPU.scala:275:20, :585:22]
wire [11:0] mux_data_expIn = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22]
wire [11:0] mux_data_expIn_1 = fsgnjMux_data[63:52]; // @[FPU.scala:276:18, :585:22]
wire [62:0] _mux_data_fractOut_T = {mux_data_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28]
wire [9:0] mux_data_fractOut = _mux_data_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] mux_data_expOut_expCode = mux_data_expIn[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _mux_data_expOut_commonCase_T = {1'h0, mux_data_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31]
wire [11:0] _mux_data_expOut_commonCase_T_1 = _mux_data_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31]
wire [12:0] _mux_data_expOut_commonCase_T_2 = {1'h0, _mux_data_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] mux_data_expOut_commonCase = _mux_data_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50]
wire _mux_data_expOut_T = mux_data_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _mux_data_expOut_T_1 = mux_data_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _mux_data_expOut_T_2 = _mux_data_expOut_T | _mux_data_expOut_T_1; // @[FPU.scala:281:{19,27,38}]
wire [2:0] _mux_data_expOut_T_3 = mux_data_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69]
wire [5:0] _mux_data_expOut_T_4 = {mux_data_expOut_expCode, _mux_data_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}]
wire [5:0] _mux_data_expOut_T_5 = mux_data_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97]
wire [5:0] mux_data_expOut = _mux_data_expOut_T_2 ? _mux_data_expOut_T_4 : _mux_data_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}]
wire [6:0] mux_data_hi = {mux_data_sign, mux_data_expOut}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [16:0] _mux_data_T_1 = {mux_data_hi, mux_data_fractOut}; // @[FPU.scala:277:38, :283:8]
wire [64:0] _mux_data_T_2 = {_mux_data_T, _mux_data_T_1}; // @[FPU.scala:283:8, :604:{22,37}]
wire _T_8 = in_bits_typeTagOut == 2'h1; // @[Valid.scala:135:21]
wire [31:0] _mux_data_T_3 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37]
wire [31:0] _mux_data_T_8 = fsgnjMux_data[64:33]; // @[FPU.scala:585:22, :604:37, :624:39]
wire [75:0] _mux_data_fractOut_T_1 = {mux_data_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28]
wire [22:0] mux_data_fractOut_1 = _mux_data_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}]
wire [2:0] mux_data_expOut_expCode_1 = mux_data_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26]
wire [12:0] _mux_data_expOut_commonCase_T_3 = {1'h0, mux_data_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31]
wire [11:0] _mux_data_expOut_commonCase_T_4 = _mux_data_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31]
wire [12:0] _mux_data_expOut_commonCase_T_5 = {1'h0, _mux_data_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}]
wire [11:0] mux_data_expOut_commonCase_1 = _mux_data_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50]
wire _mux_data_expOut_T_6 = mux_data_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19]
wire _mux_data_expOut_T_7 = mux_data_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38]
wire _mux_data_expOut_T_8 = _mux_data_expOut_T_6 | _mux_data_expOut_T_7; // @[FPU.scala:281:{19,27,38}]
wire [5:0] _mux_data_expOut_T_9 = mux_data_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69]
wire [8:0] _mux_data_expOut_T_10 = {mux_data_expOut_expCode_1, _mux_data_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}]
wire [8:0] _mux_data_expOut_T_11 = mux_data_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97]
wire [8:0] mux_data_expOut_1 = _mux_data_expOut_T_8 ? _mux_data_expOut_T_10 : _mux_data_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}]
wire [9:0] mux_data_hi_1 = {mux_data_sign_1, mux_data_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8]
wire [32:0] _mux_data_T_4 = {mux_data_hi_1, mux_data_fractOut_1}; // @[FPU.scala:277:38, :283:8]
wire [64:0] _mux_data_T_5 = {_mux_data_T_3, _mux_data_T_4}; // @[FPU.scala:283:8, :604:{22,37}]
wire _T_3 = in_bits_wflags & ~in_bits_ren2; // @[Valid.scala:135:21]
wire _widened_T_1 = &_widened_T; // @[FPU.scala:249:{25,56}]
wire [64:0] widened = _widened_T_1 ? 65'hE008000000000000 : in_bits_in1; // @[Valid.scala:135:21]
assign fsgnjMux_data = _T_3 ? widened : in_bits_wflags ? _fsgnjMux_data_T_1 : fsgnj; // @[Valid.scala:135:21]
wire _fsgnjMux_exc_T_2 = &_fsgnjMux_exc_T_1; // @[FPU.scala:249:{25,56}]
wire _fsgnjMux_exc_T_4 = ~_fsgnjMux_exc_T_3; // @[FPU.scala:250:{37,39}]
wire _fsgnjMux_exc_T_5 = _fsgnjMux_exc_T_2 & _fsgnjMux_exc_T_4; // @[FPU.scala:249:56, :250:{34,37}]
wire [4:0] _fsgnjMux_exc_T_6 = {_fsgnjMux_exc_T_5, 4'h0}; // @[FPU.scala:250:34, :595:31, :613:51]
assign fsgnjMux_exc = _T_3 ? _fsgnjMux_exc_T_6 : in_bits_wflags ? _fsgnjMux_exc_T : 5'h0; // @[Valid.scala:135:21]
wire [64:0] _mux_data_T_7 = {_mux_data_T_6, _narrower_io_out}; // @[FPU.scala:619:30, :624:{24,39}]
wire _T_11 = _T_8 & in_bits_typeTagOut < in_bits_typeTagIn; // @[Valid.scala:135:21]
wire [32:0] narrowed_maskedNaN = _narrower_1_io_out & 33'h1EF7FFFFF; // @[FPU.scala:413:25, :619:30]
wire [2:0] _narrowed_T = _narrower_1_io_out[31:29]; // @[FPU.scala:249:25, :619:30]
wire _narrowed_T_1 = &_narrowed_T; // @[FPU.scala:249:{25,56}]
wire [32:0] narrowed = _narrowed_T_1 ? narrowed_maskedNaN : _narrower_1_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :619:30]
wire [64:0] _mux_data_T_9 = {_mux_data_T_8, narrowed}; // @[FPU.scala:414:10, :624:{24,39}]
assign mux_data = _T_3 ? (_T_11 ? _mux_data_T_9 : _T_7 ? _mux_data_T_7 : _T_8 ? _mux_data_T_5 : fsgnjMux_data) : _T_8 ? _mux_data_T_5 : _T_7 ? _mux_data_T_2 : fsgnjMux_data; // @[FPU.scala:585:22, :601:24, :603:{18,36}, :604:{16,22}, :608:{24,42}, :618:{76,126}, :624:{18,24}]
assign mux_exc = _T_3 ? (_T_11 ? _narrower_1_io_exceptionFlags : _T_7 ? _narrower_io_exceptionFlags : fsgnjMux_exc) : fsgnjMux_exc; // @[FPU.scala:585:22, :601:24, :603:18, :608:{24,42}, :618:{76,126}, :619:30, :625:17]
reg io_out_pipe_v; // @[Valid.scala:141:24]
assign io_out_pipe_out_valid = io_out_pipe_v; // @[Valid.scala:135:21, :141:24]
reg [64:0] io_out_pipe_b_data; // @[Valid.scala:142:26]
assign io_out_pipe_out_bits_data = io_out_pipe_b_data; // @[Valid.scala:135:21, :142:26]
reg [4:0] io_out_pipe_b_exc; // @[Valid.scala:142:26]
assign io_out_pipe_out_bits_exc = io_out_pipe_b_exc; // @[Valid.scala:135:21, :142:26]
assign io_out_valid = io_out_pipe_out_valid; // @[Valid.scala:135:21]
assign io_out_bits_data_0 = io_out_pipe_out_bits_data; // @[Valid.scala:135:21]
assign io_out_bits_exc_0 = io_out_pipe_out_bits_exc; // @[Valid.scala:135:21]
always @(posedge clock) begin // @[FPU.scala:573:7]
if (reset) begin // @[FPU.scala:573:7]
in_pipe_v <= 1'h0; // @[Valid.scala:141:24]
io_out_pipe_v <= 1'h0; // @[Valid.scala:141:24]
end
else begin // @[FPU.scala:573:7]
in_pipe_v <= io_in_valid_0; // @[Valid.scala:141:24]
io_out_pipe_v <= in_valid; // @[Valid.scala:135:21, :141:24]
end
if (io_in_valid_0) begin // @[FPU.scala:573:7]
in_pipe_b_ldst <= io_in_bits_ldst_0; // @[Valid.scala:142:26]
in_pipe_b_wen <= io_in_bits_wen_0; // @[Valid.scala:142:26]
in_pipe_b_ren1 <= io_in_bits_ren1_0; // @[Valid.scala:142:26]
in_pipe_b_ren2 <= io_in_bits_ren2_0; // @[Valid.scala:142:26]
in_pipe_b_ren3 <= io_in_bits_ren3_0; // @[Valid.scala:142:26]
in_pipe_b_swap12 <= io_in_bits_swap12_0; // @[Valid.scala:142:26]
in_pipe_b_swap23 <= io_in_bits_swap23_0; // @[Valid.scala:142:26]
in_pipe_b_typeTagIn <= io_in_bits_typeTagIn_0; // @[Valid.scala:142:26]
in_pipe_b_typeTagOut <= io_in_bits_typeTagOut_0; // @[Valid.scala:142:26]
in_pipe_b_fromint <= io_in_bits_fromint_0; // @[Valid.scala:142:26]
in_pipe_b_toint <= io_in_bits_toint_0; // @[Valid.scala:142:26]
in_pipe_b_fastpipe <= io_in_bits_fastpipe_0; // @[Valid.scala:142:26]
in_pipe_b_fma <= io_in_bits_fma_0; // @[Valid.scala:142:26]
in_pipe_b_div <= io_in_bits_div_0; // @[Valid.scala:142:26]
in_pipe_b_sqrt <= io_in_bits_sqrt_0; // @[Valid.scala:142:26]
in_pipe_b_wflags <= io_in_bits_wflags_0; // @[Valid.scala:142:26]
in_pipe_b_vec <= io_in_bits_vec_0; // @[Valid.scala:142:26]
in_pipe_b_rm <= io_in_bits_rm_0; // @[Valid.scala:142:26]
in_pipe_b_fmaCmd <= io_in_bits_fmaCmd_0; // @[Valid.scala:142:26]
in_pipe_b_typ <= io_in_bits_typ_0; // @[Valid.scala:142:26]
in_pipe_b_fmt <= io_in_bits_fmt_0; // @[Valid.scala:142:26]
in_pipe_b_in1 <= io_in_bits_in1_0; // @[Valid.scala:142:26]
in_pipe_b_in2 <= io_in_bits_in2_0; // @[Valid.scala:142:26]
in_pipe_b_in3 <= io_in_bits_in3_0; // @[Valid.scala:142:26]
end
if (in_valid) begin // @[Valid.scala:135:21]
io_out_pipe_b_data <= mux_data; // @[Valid.scala:142:26]
io_out_pipe_b_exc <= mux_exc; // @[Valid.scala:142:26]
end
always @(posedge)
RecFNToRecFN_260 narrower ( // @[FPU.scala:619:30]
.io_in (in_bits_in1), // @[Valid.scala:135:21]
.io_roundingMode (in_bits_rm), // @[Valid.scala:135:21]
.io_out (_narrower_io_out),
.io_exceptionFlags (_narrower_io_exceptionFlags)
); // @[FPU.scala:619:30]
RecFNToRecFN_261 narrower_1 ( // @[FPU.scala:619:30]
.io_in (in_bits_in1), // @[Valid.scala:135:21]
.io_roundingMode (in_bits_rm), // @[Valid.scala:135:21]
.io_out (_narrower_1_io_out),
.io_exceptionFlags (_narrower_1_io_exceptionFlags)
); // @[FPU.scala:619:30]
assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:573:7]
assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:573:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_29( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_3( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [28:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire [127:0] _GEN_0 = {121'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_1 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_2 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [127:0] _GEN_3 = {121'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
|
module mem_40x75( // @[InputUnit.scala:85:18]
input [5:0] R0_addr,
input R0_en,
input R0_clk,
output [74:0] R0_data,
input [5:0] R1_addr,
input R1_en,
input R1_clk,
output [74:0] R1_data,
input [5:0] R2_addr,
input R2_en,
input R2_clk,
output [74:0] R2_data,
input [5:0] R3_addr,
input R3_en,
input R3_clk,
output [74:0] R3_data,
input [5:0] R4_addr,
input R4_en,
input R4_clk,
output [74:0] R4_data,
input [5:0] R5_addr,
input R5_en,
input R5_clk,
output [74:0] R5_data,
input [5:0] R6_addr,
input R6_en,
input R6_clk,
output [74:0] R6_data,
input [5:0] R7_addr,
input R7_en,
input R7_clk,
output [74:0] R7_data,
input [5:0] R8_addr,
input R8_en,
input R8_clk,
output [74:0] R8_data,
input [5:0] R9_addr,
input R9_en,
input R9_clk,
output [74:0] R9_data,
input [5:0] R10_addr,
input R10_en,
input R10_clk,
output [74:0] R10_data,
input [5:0] R11_addr,
input R11_en,
input R11_clk,
output [74:0] R11_data,
input [5:0] R12_addr,
input R12_en,
input R12_clk,
output [74:0] R12_data,
input [5:0] R13_addr,
input R13_en,
input R13_clk,
output [74:0] R13_data,
input [5:0] R14_addr,
input R14_en,
input R14_clk,
output [74:0] R14_data,
input [5:0] R15_addr,
input R15_en,
input R15_clk,
output [74:0] R15_data,
input [5:0] R16_addr,
input R16_en,
input R16_clk,
output [74:0] R16_data,
input [5:0] R17_addr,
input R17_en,
input R17_clk,
output [74:0] R17_data,
input [5:0] R18_addr,
input R18_en,
input R18_clk,
output [74:0] R18_data,
input [5:0] R19_addr,
input R19_en,
input R19_clk,
output [74:0] R19_data,
input [5:0] R20_addr,
input R20_en,
input R20_clk,
output [74:0] R20_data,
input [5:0] R21_addr,
input R21_en,
input R21_clk,
output [74:0] R21_data,
input [5:0] W0_addr,
input W0_en,
input W0_clk,
input [74:0] W0_data
);
reg [74:0] Memory[0:39]; // @[InputUnit.scala:85:18]
always @(posedge W0_clk) begin // @[InputUnit.scala:85:18]
if (W0_en & 1'h1) // @[InputUnit.scala:85:18]
Memory[W0_addr] <= W0_data; // @[InputUnit.scala:85:18]
always @(posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
|
module OptimizationBarrier_TLBEntryData_63( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File tile.scala:
//******************************************************************************
// Copyright (c) 2017 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
package boom.v3.common
import chisel3._
import chisel3.util.{RRArbiter, Queue}
import scala.collection.mutable.{ListBuffer}
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.rocket._
import freechips.rocketchip.subsystem.{RocketCrossingParams}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import boom.v3.exu._
import boom.v3.ifu._
import boom.v3.lsu._
import boom.v3.util.{BoomCoreStringPrefix}
import freechips.rocketchip.prci.ClockSinkParameters
case class BoomTileAttachParams(
tileParams: BoomTileParams,
crossingParams: RocketCrossingParams
) extends CanAttachTile {
type TileType = BoomTile
val lookup = PriorityMuxHartIdFromSeq(Seq(tileParams))
}
/**
* BOOM tile parameter class used in configurations
*
*/
case class BoomTileParams(
core: BoomCoreParams = BoomCoreParams(),
icache: Option[ICacheParams] = Some(ICacheParams()),
dcache: Option[DCacheParams] = Some(DCacheParams()),
btb: Option[BTBParams] = Some(BTBParams()),
name: Option[String] = Some("boom_tile"),
tileId: Int = 0
) extends InstantiableTileParams[BoomTile]
{
require(icache.isDefined)
require(dcache.isDefined)
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTile = {
new BoomTile(this, crossing, lookup)
}
val beuAddr: Option[BigInt] = None
val blockerCtrlAddr: Option[BigInt] = None
val boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
val baseName = name.getOrElse("boom_tile")
val uniqueName = s"${baseName}_$tileId"
}
/**
* BOOM tile
*
*/
class BoomTile private(
val boomParams: BoomTileParams,
crossing: ClockCrossingType,
lookup: LookupByHartIdImpl,
q: Parameters)
extends BaseTile(boomParams, crossing, lookup, q)
with SinksExternalInterrupts
with SourcesExternalNotifications
{
// Private constructor ensures altered LazyModule.p is used implicitly
def this(params: BoomTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)
val intOutwardNode = None
val masterNode = TLIdentityNode()
val slaveNode = TLIdentityNode()
val tile_master_blocker =
tileParams.blockerCtrlAddr
.map(BasicBusBlockerParams(_, xBytes, masterPortBeatBytes, deadlock = true))
.map(bp => LazyModule(new BasicBusBlocker(bp)))
tile_master_blocker.foreach(lm => connectTLSlave(lm.controlNode, xBytes))
// TODO: this doesn't block other masters, e.g. RoCCs
tlOtherMastersNode := tile_master_blocker.map { _.node := tlMasterXbar.node } getOrElse { tlMasterXbar.node }
masterNode :=* tlOtherMastersNode
val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("ucb-bar,boom0", "riscv")) {
override def parent = Some(ResourceAnchors.cpus)
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
Description(name, mapping ++
cpuProperties ++
nextLevelCacheProperty ++
tileProperties)
}
}
ResourceBinding {
Resource(cpuDevice, "reg").bind(ResourceAddress(tileId))
}
override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = crossing match {
case _: RationalCrossing =>
if (!boomParams.boundaryBuffers) TLBuffer(BufferParams.none)
else TLBuffer(BufferParams.none, BufferParams.flow, BufferParams.none, BufferParams.flow, BufferParams(1))
case _ => TLBuffer(BufferParams.none)
}
override def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = crossing match {
case _: RationalCrossing =>
if (!boomParams.boundaryBuffers) TLBuffer(BufferParams.none)
else TLBuffer(BufferParams.flow, BufferParams.none, BufferParams.none, BufferParams.none, BufferParams.none)
case _ => TLBuffer(BufferParams.none)
}
override lazy val module = new BoomTileModuleImp(this)
// DCache
lazy val dcache: BoomNonBlockingDCache = LazyModule(new BoomNonBlockingDCache(tileId))
val dCacheTap = TLIdentityNode()
tlMasterXbar.node := dCacheTap := TLWidthWidget(tileParams.dcache.get.rowBits/8) := visibilityNode := dcache.node
// Frontend/ICache
val frontend = LazyModule(new BoomFrontend(tileParams.icache.get, tileId))
frontend.resetVectorSinkNode := resetVectorNexusNode
tlMasterXbar.node := TLWidthWidget(tileParams.icache.get.rowBits/8) := frontend.masterNode
require(tileParams.dcache.get.rowBits == tileParams.icache.get.rowBits)
// ROCC
val roccs = p(BuildRoCC).map(_(p))
roccs.map(_.atlNode).foreach { atl => tlMasterXbar.node :=* atl }
roccs.map(_.tlNode).foreach { tl => tlOtherMastersNode :=* tl }
}
/**
* BOOM tile implementation
*
* @param outer top level BOOM tile
*/
class BoomTileModuleImp(outer: BoomTile) extends BaseTileModuleImp(outer){
Annotated.params(this, outer.boomParams)
val core = Module(new BoomCore()(outer.p))
val lsu = Module(new LSU()(outer.p, outer.dcache.module.edge))
val ptwPorts = ListBuffer(lsu.io.ptw, outer.frontend.module.io.ptw, core.io.ptw_tlb)
val hellaCachePorts = ListBuffer[HellaCacheIO]()
outer.reportWFI(None) // TODO: actually report this?
outer.decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
// Pass through various external constants and reports
outer.traceSourceNode.bundle <> core.io.trace
outer.bpwatchSourceNode.bundle <> DontCare // core.io.bpwatch
core.io.hartid := outer.hartIdSinkNode.bundle
// Connect the core pipeline to other intra-tile modules
outer.frontend.module.io.cpu <> core.io.ifu
core.io.lsu <> lsu.io.core
//fpuOpt foreach { fpu => core.io.fpu <> fpu.io } RocketFpu - not needed in boom
core.io.rocc := DontCare
// RoCC
if (outer.roccs.size > 0) {
val (respArb, cmdRouter) = {
val respArb = Module(new RRArbiter(new RoCCResponse()(outer.p), outer.roccs.size))
val cmdRouter = Module(new RoccCommandRouter(outer.roccs.map(_.opcodes))(outer.p))
outer.roccs.zipWithIndex.foreach { case (rocc, i) =>
ptwPorts ++= rocc.module.io.ptw
rocc.module.io.cmd <> cmdRouter.io.out(i)
val dcIF = Module(new SimpleHellaCacheIF()(outer.p))
dcIF.io.requestor <> rocc.module.io.mem
hellaCachePorts += dcIF.io.cache
respArb.io.in(i) <> Queue(rocc.module.io.resp)
}
// first keep fpu ios unconnected
val fp_ios = outer.roccs.map(r => {
val roccio = r.module.io
roccio.fpu_req.ready := true.B
roccio.fpu_resp.valid := false.B
roccio.fpu_resp.bits := DontCare
})
// Create this FPU just for RoCC
val nFPUPorts = outer.roccs.filter(_.usesFPU).size
if (nFPUPorts > 0) {
val fpuOpt = outer.tileParams.core.fpu.map(params => Module(new freechips.rocketchip.tile.FPU(params)(outer.p)))
// TODO: Check this FPU works properly
fpuOpt foreach { fpu =>
// This FPU does not get CPU requests
fpu.io := DontCare
fpu.io.fcsr_rm := core.io.fcsr_rm
fpu.io.ll_resp_val := false.B
fpu.io.valid := false.B
fpu.io.killx := false.B
fpu.io.killm := false.B
val fpArb = Module(new InOrderArbiter(new FPInput()(outer.p), new FPResult()(outer.p), nFPUPorts))
val fp_rocc_ios = outer.roccs.filter(_.usesFPU).map(_.module.io)
fpArb.io.in_req <> fp_rocc_ios.map(_.fpu_req)
fp_rocc_ios.zip(fpArb.io.in_resp).foreach {
case (rocc, arb) => rocc.fpu_resp <> arb
}
fpu.io.cp_req <> fpArb.io.out_req
fpArb.io.out_resp <> fpu.io.cp_resp
}
}
(respArb, cmdRouter)
}
cmdRouter.io.in <> core.io.rocc.cmd
outer.roccs.foreach(_.module.io.exception := core.io.rocc.exception)
core.io.rocc.resp <> respArb.io.out
core.io.rocc.busy <> (cmdRouter.io.busy || outer.roccs.map(_.module.io.busy).reduce(_||_))
core.io.rocc.interrupt := outer.roccs.map(_.module.io.interrupt).reduce(_||_)
}
// PTW
val ptw = Module(new PTW(ptwPorts.length)(outer.dcache.node.edges.out(0), outer.p))
core.io.ptw <> ptw.io.dpath
ptw.io.requestor <> ptwPorts.toSeq
ptw.io.mem +=: hellaCachePorts
// LSU IO
val hellaCacheArb = Module(new HellaCacheArbiter(hellaCachePorts.length)(outer.p))
hellaCacheArb.io.requestor <> hellaCachePorts.toSeq
lsu.io.hellacache <> hellaCacheArb.io.mem
outer.dcache.module.io.lsu <> lsu.io.dmem
// Generate a descriptive string
val frontendStr = outer.frontend.module.toString
val coreStr = core.toString
val boomTileStr =
(BoomCoreStringPrefix(s"======BOOM Tile ${outer.tileId} Params======") + "\n"
+ frontendStr
+ coreStr + "\n")
override def toString: String = boomTileStr
print(boomTileStr)
}
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File BaseTile.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tile
import chisel3._
import chisel3.util.{log2Ceil, log2Up}
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.bundlebridge._
import freechips.rocketchip.resources.{PropertyMap, PropertyOption, ResourceReference, DTSTimebase}
import freechips.rocketchip.interrupts.{IntInwardNode, IntOutwardNode}
import freechips.rocketchip.rocket.{ICacheParams, DCacheParams, BTBParams, ASIdBits, VMIdBits, TraceAux, BPWatch}
import freechips.rocketchip.subsystem.{
HierarchicalElementParams, InstantiableHierarchicalElementParams, HierarchicalElementCrossingParamsLike,
CacheBlockBytes, SystemBusKey, BaseHierarchicalElement, InsertTimingClosureRegistersOnHartIds, BaseHierarchicalElementModuleImp
}
import freechips.rocketchip.tilelink.{TLEphemeralNode, TLOutwardNode, TLNode, TLFragmenter, EarlyAck, TLWidthWidget, TLManagerParameters, ManagerUnification}
import freechips.rocketchip.prci.{ClockCrossingType, ClockSinkParameters}
import freechips.rocketchip.util.{TraceCoreParams, TraceCoreInterface}
import freechips.rocketchip.resources.{BigIntToProperty, IntToProperty, StringToProperty}
import freechips.rocketchip.util.BooleanToAugmentedBoolean
case object TileVisibilityNodeKey extends Field[TLEphemeralNode]
case object TileKey extends Field[TileParams]
case object LookupByHartId extends Field[LookupByHartIdImpl]
trait TileParams extends HierarchicalElementParams {
val core: CoreParams
val icache: Option[ICacheParams]
val dcache: Option[DCacheParams]
val btb: Option[BTBParams]
val tileId: Int // may not be hartid
val blockerCtrlAddr: Option[BigInt]
}
abstract class InstantiableTileParams[TileType <: BaseTile]
extends InstantiableHierarchicalElementParams[TileType]
with TileParams {
def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)
(implicit p: Parameters): TileType
}
/** These parameters values are not computed based on diplomacy negotiation
* and so are safe to use while diplomacy itself is running.
*/
trait HasNonDiplomaticTileParameters {
implicit val p: Parameters
def tileParams: TileParams = p(TileKey)
def usingVM: Boolean = tileParams.core.useVM
def usingUser: Boolean = tileParams.core.useUser || usingSupervisor
def usingSupervisor: Boolean = tileParams.core.hasSupervisorMode
def usingHypervisor: Boolean = usingVM && tileParams.core.useHypervisor
def usingDebug: Boolean = tileParams.core.useDebug
def usingRoCC: Boolean = !p(BuildRoCC).isEmpty
def usingBTB: Boolean = tileParams.btb.isDefined && tileParams.btb.get.nEntries > 0
def usingPTW: Boolean = usingVM
def usingDataScratchpad: Boolean = tileParams.dcache.flatMap(_.scratch).isDefined
def xLen: Int = tileParams.core.xLen
def xBytes: Int = xLen / 8
def iLen: Int = 32
def pgIdxBits: Int = 12
def pgLevelBits: Int = 10 - log2Ceil(xLen / 32)
def pgLevels: Int = tileParams.core.pgLevels
def maxSVAddrBits: Int = pgIdxBits + pgLevels * pgLevelBits
def maxHypervisorExtraAddrBits: Int = 2
def hypervisorExtraAddrBits: Int = {
if (usingHypervisor) maxHypervisorExtraAddrBits
else 0
}
def maxHVAddrBits: Int = maxSVAddrBits + hypervisorExtraAddrBits
def minPgLevels: Int = {
val res = xLen match { case 32 => 2; case 64 => 3 }
require(pgLevels >= res)
res
}
def asIdBits: Int = p(ASIdBits)
def vmIdBits: Int = p(VMIdBits)
lazy val maxPAddrBits: Int = {
require(xLen == 32 || xLen == 64, s"Only XLENs of 32 or 64 are supported, but got $xLen")
xLen match { case 32 => 34; case 64 => 56 }
}
def tileId: Int = tileParams.tileId
def cacheBlockBytes = p(CacheBlockBytes)
def lgCacheBlockBytes = log2Up(cacheBlockBytes)
def masterPortBeatBytes = p(SystemBusKey).beatBytes
// TODO make HellaCacheIO diplomatic and remove this brittle collection of hacks
// Core PTW DTIM coprocessors
def dcacheArbPorts = 1 + usingVM.toInt + usingDataScratchpad.toInt + p(BuildRoCC).size + (tileParams.core.useVector && tileParams.core.vectorUseDCache).toInt
// TODO merge with isaString in CSR.scala
def isaDTS: String = {
val ie = if (tileParams.core.useRVE) "e" else "i"
val m = if (tileParams.core.mulDiv.nonEmpty) "m" else ""
val a = if (tileParams.core.useAtomics) "a" else ""
val f = if (tileParams.core.fpu.nonEmpty) "f" else ""
val d = if (tileParams.core.fpu.nonEmpty && tileParams.core.fpu.get.fLen > 32) "d" else ""
val c = if (tileParams.core.useCompressed) "c" else ""
val b = if (tileParams.core.useBitmanip) "b" else ""
val v = if (tileParams.core.useVector && tileParams.core.vLen >= 128 && tileParams.core.eLen == 64 && tileParams.core.vfLen == 64) "v" else ""
val h = if (usingHypervisor) "h" else ""
val ext_strs = Seq(
(tileParams.core.useVector) -> s"zvl${tileParams.core.vLen}b",
(tileParams.core.useVector) -> {
val c = tileParams.core.vfLen match {
case 64 => "d"
case 32 => "f"
case 0 => "x"
}
s"zve${tileParams.core.eLen}$c"
},
(tileParams.core.useVector && tileParams.core.vfh) -> "zvfh",
(tileParams.core.fpu.map(_.fLen >= 16).getOrElse(false) && tileParams.core.minFLen <= 16) -> "zfh",
(tileParams.core.useZba) -> "zba",
(tileParams.core.useZbb) -> "zbb",
(tileParams.core.useZbs) -> "zbs",
(tileParams.core.useConditionalZero) -> "zicond"
).filter(_._1).map(_._2)
val multiLetterExt = (
// rdcycle[h], rdinstret[h] is implemented
// rdtime[h] is not implemented, and could be provided by software emulation
// see https://github.com/chipsalliance/rocket-chip/issues/3207
//Some(Seq("zicntr")) ++
Some(Seq("zicsr", "zifencei", "zihpm")) ++
Some(ext_strs) ++ Some(tileParams.core.vExts) ++
tileParams.core.customIsaExt.map(Seq(_))
).flatten
val multiLetterString = multiLetterExt.mkString("_")
s"rv$xLen$ie$m$a$f$d$c$b$v$h$multiLetterString"
}
def tileProperties: PropertyMap = {
val dcache = tileParams.dcache.filter(!_.scratch.isDefined).map(d => Map(
"d-cache-block-size" -> cacheBlockBytes.asProperty,
"d-cache-sets" -> d.nSets.asProperty,
"d-cache-size" -> (d.nSets * d.nWays * cacheBlockBytes).asProperty)
).getOrElse(Nil)
val incoherent = if (!tileParams.core.useAtomicsOnlyForIO) Nil else Map(
"sifive,d-cache-incoherent" -> Nil)
val icache = tileParams.icache.map(i => Map(
"i-cache-block-size" -> cacheBlockBytes.asProperty,
"i-cache-sets" -> i.nSets.asProperty,
"i-cache-size" -> (i.nSets * i.nWays * cacheBlockBytes).asProperty)
).getOrElse(Nil)
val dtlb = tileParams.dcache.filter(_ => tileParams.core.useVM).map(d => Map(
"d-tlb-size" -> (d.nTLBWays * d.nTLBSets).asProperty,
"d-tlb-sets" -> d.nTLBSets.asProperty)).getOrElse(Nil)
val itlb = tileParams.icache.filter(_ => tileParams.core.useVM).map(i => Map(
"i-tlb-size" -> (i.nTLBWays * i.nTLBSets).asProperty,
"i-tlb-sets" -> i.nTLBSets.asProperty)).getOrElse(Nil)
val mmu =
if (tileParams.core.useVM) {
if (tileParams.core.useHypervisor) {
Map("tlb-split" -> Nil, "mmu-type" -> s"riscv,sv${maxSVAddrBits},sv${maxSVAddrBits}x4".asProperty)
} else {
Map("tlb-split" -> Nil, "mmu-type" -> s"riscv,sv$maxSVAddrBits".asProperty)
}
} else {
Nil
}
val pmp = if (tileParams.core.nPMPs > 0) Map(
"riscv,pmpregions" -> tileParams.core.nPMPs.asProperty,
"riscv,pmpgranularity" -> tileParams.core.pmpGranularity.asProperty) else Nil
dcache ++ icache ++ dtlb ++ itlb ++ mmu ++ pmp ++ incoherent
}
}
/** These parameters values are computed based on diplomacy negotiations
* and so are NOT safe to use while diplomacy itself is running.
* Only mix this trait into LazyModuleImps, Modules, Bundles, Data, etc.
*/
trait HasTileParameters extends HasNonDiplomaticTileParameters {
protected def tlBundleParams = p(TileVisibilityNodeKey).edges.out.head.bundle
lazy val paddrBits: Int = {
val bits = tlBundleParams.addressBits
require(bits <= maxPAddrBits, s"Requested $bits paddr bits, but since xLen is $xLen only $maxPAddrBits will fit")
bits
}
def vaddrBits: Int =
if (usingVM) {
val v = maxHVAddrBits
require(v == xLen || xLen > v && v > paddrBits)
v
} else {
// since virtual addresses sign-extend but physical addresses
// zero-extend, make room for a zero sign bit for physical addresses
(paddrBits + 1) min xLen
}
def vpnBits: Int = vaddrBits - pgIdxBits
def ppnBits: Int = paddrBits - pgIdxBits
def vpnBitsExtended: Int = vpnBits + (if (vaddrBits < xLen) 1 + usingHypervisor.toInt else 0)
def vaddrBitsExtended: Int = vpnBitsExtended + pgIdxBits
}
/** Base class for all Tiles that use TileLink */
abstract class BaseTile private (crossing: ClockCrossingType, q: Parameters)
extends BaseHierarchicalElement(crossing)(q)
with HasNonDiplomaticTileParameters
{
// Public constructor alters Parameters to supply some legacy compatibility keys
def this(tileParams: TileParams, crossing: ClockCrossingType, lookup: LookupByHartIdImpl, p: Parameters) = {
this(crossing, p.alterMap(Map(
TileKey -> tileParams,
TileVisibilityNodeKey -> TLEphemeralNode()(ValName("tile_master")),
LookupByHartId -> lookup
)))
}
def intInwardNode: IntInwardNode // Interrupts to the core from external devices
def intOutwardNode: Option[IntOutwardNode] // Interrupts from tile-internal devices (e.g. BEU)
def haltNode: IntOutwardNode // Unrecoverable error has occurred; suggest reset
def ceaseNode: IntOutwardNode // Tile has ceased to retire instructions
def wfiNode: IntOutwardNode // Tile is waiting for an interrupt
def module: BaseTileModuleImp[BaseTile]
/** Node for broadcasting a hart id to diplomatic consumers within the tile. */
val hartIdNexusNode: BundleBridgeNode[UInt] = BundleBroadcast[UInt](registered = p(InsertTimingClosureRegistersOnHartIds))
/** Node for consuming the hart id input in tile-layer Chisel logic. */
val hartIdSinkNode = BundleBridgeSink[UInt]()
/** Node for driving a hart id input, which is to be broadcast to units within the tile.
*
* Making this id value an IO and then using it to do lookups of information
* that would make otherwise-homogeneous tiles heterogeneous is a useful trick
* to enable deduplication of tiles for hierarchical P&R flows.
*/
val hartIdNode: BundleBridgeInwardNode[UInt] =
hartIdSinkNode := hartIdNexusNode := BundleBridgeNameNode("hartid")
/** Node for broadcasting a reset vector to diplomatic consumers within the tile. */
val resetVectorNexusNode: BundleBridgeNode[UInt] = BundleBroadcast[UInt]()
/** Node for consuming the reset vector input in tile-layer Chisel logic.
*
* Its width is sized by looking at the size of the address space visible
* on the tile's master ports, but this lookup is not evaluated until
* diplomacy has completed and Chisel elaboration has begun.
*/
val resetVectorSinkNode = BundleBridgeSink[UInt](Some(() => UInt(visiblePhysAddrBits.W)))
/** Node for supplying a reset vector that processors in this tile might begin fetching instructions from as they come out of reset. */
val resetVectorNode: BundleBridgeInwardNode[UInt] =
resetVectorSinkNode := resetVectorNexusNode := BundleBridgeNameNode("reset_vector")
/** Nodes for connecting NMI interrupt sources and vectors into the tile */
val nmiSinkNode = Option.when(tileParams.core.useNMI) {
BundleBridgeSink[NMI](Some(() => new NMI(visiblePhysAddrBits)))
}
val nmiNode: Option[BundleBridgeInwardNode[NMI]] = nmiSinkNode.map(_ := BundleBridgeNameNode("nmi"))
/** Node for broadcasting an address prefix to diplomatic consumers within the tile.
*
* The prefix should be applied by consumers by or-ing ouputs of this node
* with a static base address (which is looked up based on the driven hartid value).
*/
val mmioAddressPrefixNexusNode = BundleBridgeNexus[UInt](
inputFn = BundleBridgeNexus.orReduction[UInt](registered = false) _,
outputFn = BundleBridgeNexus.fillN[UInt](registered = false) _,
default = Some(() => 0.U(1.W))
)
/** Node for external drivers to prefix base addresses of MMIO devices to which the core has a direct access path. */
val mmioAddressPrefixNode: BundleBridgeInwardNode[UInt] =
mmioAddressPrefixNexusNode :=* BundleBridgeNameNode("mmio_address_prefix")
// TODO: Any node marked "consumed by the core" or "driven by the core"
// should be moved to either be: a member of a specific BaseTile subclass,
// or actually just a member of the core's LazyModule itself,
// assuming the core itself is diplomatic.
// Then these nodes should just become IdentityNodes of their respective type
protected def traceRetireWidth = tileParams.core.retireWidth
/** Node for the core to drive legacy "raw" instruction trace. */
val traceSourceNode = BundleBridgeSource(() => new TraceBundle)
/** Node for external consumers to source a legacy instruction trace from the core. */
val traceNode = traceSourceNode
def traceCoreParams = new TraceCoreParams()
/** Node for core to drive instruction trace conforming to RISC-V Processor Trace spec V1.0 */
val traceCoreSourceNode = BundleBridgeSource(() => new TraceCoreInterface(traceCoreParams))
/** Node for external consumers to source a V1.0 instruction trace from the core. */
val traceCoreNode = traceCoreSourceNode
/** Node to broadcast collected trace sideband signals into the tile. */
val traceAuxNexusNode = BundleBridgeNexus[TraceAux](default = Some(() => {
val aux = Wire(new TraceAux)
aux.stall := false.B
aux.enable := false.B
aux
}))
/** Trace sideband signals to be consumed by the core. */
val traceAuxSinkNode = BundleBridgeSink[TraceAux]()
/** Trace sideband signals collected here to be driven into the tile. */
val traceAuxNode: BundleBridgeInwardNode[TraceAux] =
traceAuxSinkNode := traceAuxNexusNode :=* BundleBridgeNameNode("trace_aux")
/** Node for watchpoints to control trace driven by core. */
val bpwatchSourceNode = BundleBridgeSource(() => Vec(tileParams.core.nBreakpoints, new BPWatch(traceRetireWidth)))
/** Node to broadcast watchpoints to control trace. */
val bpwatchNexusNode = BundleBroadcast[Vec[BPWatch]]()
/** Node for external consumers to source watchpoints to control trace. */
val bpwatchNode: BundleBridgeOutwardNode[Vec[BPWatch]] =
BundleBridgeNameNode("bpwatch") :*= bpwatchNexusNode := bpwatchSourceNode
/** Helper function for connecting MMIO devices inside the tile to an xbar that will make them visible to external masters. */
def connectTLSlave(xbarNode: TLOutwardNode, node: TLNode, bytes: Int): Unit = {
DisableMonitors { implicit p =>
(Seq(node, TLFragmenter(bytes, cacheBlockBytes, earlyAck=EarlyAck.PutFulls))
++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
.foldRight(xbarNode)(_ :*= _)
}
}
def connectTLSlave(node: TLNode, bytes: Int): Unit = { connectTLSlave(tlSlaveXbar.node, node, bytes) }
/** TileLink node which represents the view that the intra-tile masters have of the rest of the system. */
val visibilityNode = p(TileVisibilityNodeKey)
protected def visibleManagers = visibilityNode.edges.out.flatMap(_.manager.managers)
protected def visiblePhysAddrBits = visibilityNode.edges.out.head.bundle.addressBits
def unifyManagers: List[TLManagerParameters] = ManagerUnification(visibleManagers)
/** Finds resource labels for all the outward caches. */
def nextLevelCacheProperty: PropertyOption = {
val outer = visibleManagers
.filter(_.supportsAcquireB)
.flatMap(_.resources.headOption)
.map(_.owner.label)
.distinct
if (outer.isEmpty) None
else Some("next-level-cache" -> outer.map(l => ResourceReference(l)).toList)
}
/** Create a DTS representation of this "cpu". */
def cpuProperties: PropertyMap = Map(
"device_type" -> "cpu".asProperty,
"status" -> "okay".asProperty,
"clock-frequency" -> tileParams.core.bootFreqHz.asProperty,
"riscv,isa" -> isaDTS.asProperty,
"timebase-frequency" -> p(DTSTimebase).asProperty,
"hardware-exec-breakpoint-count" -> tileParams.core.nBreakpoints.asProperty
)
/** Can be used to access derived params calculated by HasCoreParameters
*
* However, callers must ensure they do not access a diplomatically-determined parameter
* before the graph in question has been fully connected.
*/
protected lazy val lazyCoreParamsView: HasCoreParameters = {
class C(implicit val p: Parameters) extends HasCoreParameters
new C
}
this.suggestName(tileParams.baseName)
}
abstract class BaseTileModuleImp[+L <: BaseTile](outer: L) extends BaseHierarchicalElementModuleImp[L](outer)
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
File HierarchicalElement.scala:
package freechips.rocketchip.subsystem
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.devices.debug.TLDebugModule
import freechips.rocketchip.diplomacy.{BufferParams}
import freechips.rocketchip.interrupts.IntXbar
import freechips.rocketchip.prci.{ClockSinkParameters, ResetCrossingType, ClockCrossingType}
import freechips.rocketchip.tile.{LookupByHartIdImpl, TraceBundle}
import freechips.rocketchip.tilelink.{TLNode, TLIdentityNode, TLXbar, TLBuffer, TLInwardNode, TLOutwardNode}
trait HierarchicalElementParams {
val baseName: String // duplicated instances shouuld share a base name
val uniqueName: String
val clockSinkParams: ClockSinkParameters
}
abstract class InstantiableHierarchicalElementParams[ElementType <: BaseHierarchicalElement] extends HierarchicalElementParams
/** An interface for describing the parameteization of how HierarchicalElements are connected to interconnects */
trait HierarchicalElementCrossingParamsLike {
/** The type of clock crossing that should be inserted at the element boundary. */
def crossingType: ClockCrossingType
/** Parameters describing the contents and behavior of the point where the element is attached as an interconnect master. */
def master: HierarchicalElementPortParamsLike
/** Parameters describing the contents and behavior of the point where the element is attached as an interconnect slave. */
def slave: HierarchicalElementPortParamsLike
/** The subnetwork location of the device selecting the apparent base address of MMIO devices inside the element */
def mmioBaseAddressPrefixWhere: TLBusWrapperLocation
/** Inject a reset management subgraph that effects the element child reset only */
def resetCrossingType: ResetCrossingType
/** Keep the element clock separate from the interconnect clock (e.g. even if they are synchronous to one another) */
def forceSeparateClockReset: Boolean
}
/** An interface for describing the parameterization of how a particular element port is connected to an interconnect */
trait HierarchicalElementPortParamsLike {
/** The subnetwork location of the interconnect to which this element port should be connected. */
def where: TLBusWrapperLocation
/** Allows port-specific adapters to be injected into the interconnect side of the attachment point. */
def injectNode(context: Attachable)(implicit p: Parameters): TLNode
}
abstract class BaseHierarchicalElement (val crossing: ClockCrossingType)(implicit p: Parameters)
extends LazyModule()(p)
with CrossesToOnlyOneClockDomain
{
def module: BaseHierarchicalElementModuleImp[BaseHierarchicalElement]
protected val tlOtherMastersNode = TLIdentityNode()
protected val tlMasterXbar = LazyModule(new TLXbar(nameSuffix = Some(s"MasterXbar_$desiredName")))
protected val tlSlaveXbar = LazyModule(new TLXbar(nameSuffix = Some(s"SlaveXbar_$desiredName")))
protected val intXbar = LazyModule(new IntXbar)
def masterNode: TLOutwardNode
def slaveNode: TLInwardNode
/** Helper function to insert additional buffers on master ports at the boundary of the tile.
*
* The boundary buffering needed to cut feed-through paths is
* microarchitecture specific, so this may need to be overridden
* in subclasses of this class.
*/
def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none)
/** Helper function to insert additional buffers on slave ports at the boundary of the tile.
*
* The boundary buffering needed to cut feed-through paths is
* microarchitecture specific, so this may need to be overridden
* in subclasses of this class.
*/
def makeSlaveBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = TLBuffer(BufferParams.none)
}
abstract class BaseHierarchicalElementModuleImp[+L <: BaseHierarchicalElement](val outer: L) extends LazyModuleImp(outer)
File BundleBridgeNexus.scala:
package org.chipsalliance.diplomacy.bundlebridge
import chisel3.{chiselTypeOf, ActualDirection, Data, Reg}
import chisel3.reflect.DataMirror
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyRawModuleImp}
class BundleBridgeNexus[T <: Data](
inputFn: Seq[T] => T,
outputFn: (T, Int) => Seq[T],
default: Option[() => T] = None,
inputRequiresOutput: Boolean = false,
override val shouldBeInlined: Boolean = true
)(
implicit p: Parameters)
extends LazyModule {
val node = BundleBridgeNexusNode[T](default, inputRequiresOutput)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
val defaultWireOpt = default.map(_())
val inputs: Seq[T] = node.in.map(_._1)
inputs.foreach { i =>
require(
DataMirror.checkTypeEquivalence(i, inputs.head),
s"${node.context} requires all inputs have equivalent Chisel Data types, but got\n$i\nvs\n${inputs.head}"
)
}
inputs.flatMap(getElements).foreach { elt =>
DataMirror.directionOf(elt) match {
case ActualDirection.Output => ()
case ActualDirection.Unspecified => ()
case _ => require(false, s"${node.context} can only be used with Output-directed Bundles")
}
}
val outputs: Seq[T] =
if (node.out.size > 0) {
val broadcast: T = if (inputs.size >= 1) inputFn(inputs) else defaultWireOpt.get
outputFn(broadcast, node.out.size)
} else { Nil }
val typeName = outputs.headOption.map(_.typeName).getOrElse("NoOutput")
override def desiredName = s"BundleBridgeNexus_$typeName"
node.out.map(_._1).foreach { o =>
require(
DataMirror.checkTypeEquivalence(o, outputs.head),
s"${node.context} requires all outputs have equivalent Chisel Data types, but got\n$o\nvs\n${outputs.head}"
)
}
require(
outputs.size == node.out.size,
s"${node.context} outputFn must generate one output wire per edgeOut, but got ${outputs.size} vs ${node.out.size}"
)
node.out.zip(outputs).foreach { case ((out, _), bcast) => out := bcast }
}
}
object BundleBridgeNexus {
def safeRegNext[T <: Data](x: T): T = {
val reg = Reg(chiselTypeOf(x))
reg := x
reg
}
def requireOne[T <: Data](registered: Boolean)(seq: Seq[T]): T = {
require(seq.size == 1, "BundleBroadcast default requires one input")
if (registered) safeRegNext(seq.head) else seq.head
}
def orReduction[T <: Data](registered: Boolean)(seq: Seq[T]): T = {
val x = seq.reduce((a, b) => (a.asUInt | b.asUInt).asTypeOf(seq.head))
if (registered) safeRegNext(x) else x
}
def fillN[T <: Data](registered: Boolean)(x: T, n: Int): Seq[T] = Seq.fill(n) {
if (registered) safeRegNext(x) else x
}
def apply[T <: Data](
inputFn: Seq[T] => T = orReduction[T](false) _,
outputFn: (T, Int) => Seq[T] = fillN[T](false) _,
default: Option[() => T] = None,
inputRequiresOutput: Boolean = false,
shouldBeInlined: Boolean = true
)(
implicit p: Parameters
): BundleBridgeNexusNode[T] = {
val nexus = LazyModule(new BundleBridgeNexus[T](inputFn, outputFn, default, inputRequiresOutput, shouldBeInlined))
nexus.node
}
}
|
module BoomTile( // @[tile.scala:155:7]
input clock, // @[tile.scala:155:7]
input reset, // @[tile.scala:155:7]
input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_3_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_2_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_1_0, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_1_1, // @[LazyModuleImp.scala:107:25]
input auto_int_local_in_0_0, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_trace_source_out_time, // @[LazyModuleImp.scala:107:25]
output auto_trace_source_out_custom_rob_empty, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_hartid_in // @[LazyModuleImp.scala:107:25]
);
wire dCacheTapOut_e_ready; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_d_bits_data; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] dCacheTapOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapOut_c_ready; // @[MixedNode.scala:542:17]
wire dCacheTapOut_b_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_b_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_b_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] dCacheTapOut_b_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapOut_b_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_b_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_b_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] dCacheTapOut_b_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_b_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapOut_a_ready; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [31:0] tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17]
wire [127:0] tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire buffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_e_ready; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_ready; // @[Buffer.scala:40:9]
wire buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] broadcast_auto_in; // @[BundleBridgeNexus.scala:20:9]
wire _hellaCacheArb_io_requestor_0_req_ready; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_nack; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_resp_valid; // @[tile.scala:243:29]
wire [39:0] _hellaCacheArb_io_requestor_0_resp_bits_addr; // @[tile.scala:243:29]
wire [63:0] _hellaCacheArb_io_requestor_0_resp_bits_data; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ma_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_pf_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_gf_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_s2_xcpt_ae_st; // @[tile.scala:243:29]
wire _hellaCacheArb_io_requestor_0_store_pending; // @[tile.scala:243:29]
wire _hellaCacheArb_io_mem_req_valid; // @[tile.scala:243:29]
wire [39:0] _hellaCacheArb_io_mem_req_bits_addr; // @[tile.scala:243:29]
wire _hellaCacheArb_io_mem_req_bits_dv; // @[tile.scala:243:29]
wire _hellaCacheArb_io_mem_s1_kill; // @[tile.scala:243:29]
wire _ptw_io_requestor_0_req_ready; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_valid; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_ae_final; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pf; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_gf; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_hr; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_hw; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_hx; // @[tile.scala:237:20]
wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_d; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_g; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_u; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_r; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_pte_v; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[tile.scala:237:20]
wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[tile.scala:237:20]
wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_debug; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_cease; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_wfi; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_dprv; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_dv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_prv; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_v; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_sd; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mpv; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_gva; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_tsr; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_tw; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_tvm; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mxr; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_sum; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mprv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_fs; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_status_mpp; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_spp; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mpie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_spie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_mie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_status_sie; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_0_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_0_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_0_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_0_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_1_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_1_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_1_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_1_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_2_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_2_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_2_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_2_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_3_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_3_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_3_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_3_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_4_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_4_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_4_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_4_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_5_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_5_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_5_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_5_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_6_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_6_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_6_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_6_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_0_pmp_7_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_0_pmp_7_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_0_pmp_7_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_0_pmp_7_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_req_ready; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_valid; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_ae_ptw; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_ae_final; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pf; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_gf; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_hr; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_hw; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_hx; // @[tile.scala:237:20]
wire [9:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_future; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_1_resp_bits_pte_ppn; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_resp_bits_pte_reserved_for_software; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_d; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_g; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_u; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_r; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_pte_v; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_resp_bits_level; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_homogeneous; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_gpa_valid; // @[tile.scala:237:20]
wire [38:0] _ptw_io_requestor_1_resp_bits_gpa_bits; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_resp_bits_gpa_is_pte; // @[tile.scala:237:20]
wire [3:0] _ptw_io_requestor_1_ptbr_mode; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_1_ptbr_ppn; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_debug; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_cease; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_wfi; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_dprv; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_dv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_prv; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_v; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_sd; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mpv; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_gva; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_tsr; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_tw; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_tvm; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mxr; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_sum; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mprv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_fs; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_status_mpp; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_spp; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mpie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_spie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_mie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_status_sie; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_0_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_0_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_0_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_0_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_1_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_1_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_1_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_1_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_2_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_2_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_2_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_2_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_3_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_3_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_3_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_3_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_4_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_4_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_4_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_4_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_5_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_5_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_5_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_5_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_6_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_6_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_6_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_6_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_1_pmp_7_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_1_pmp_7_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_1_pmp_7_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_1_pmp_7_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_req_ready; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_valid; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_ae_ptw; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_ae_final; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pf; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_gf; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_hr; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_hw; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_hx; // @[tile.scala:237:20]
wire [9:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_future; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_2_resp_bits_pte_ppn; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_resp_bits_pte_reserved_for_software; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_d; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_g; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_u; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_r; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_pte_v; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_resp_bits_level; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_homogeneous; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_gpa_valid; // @[tile.scala:237:20]
wire [38:0] _ptw_io_requestor_2_resp_bits_gpa_bits; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_resp_bits_gpa_is_pte; // @[tile.scala:237:20]
wire [3:0] _ptw_io_requestor_2_ptbr_mode; // @[tile.scala:237:20]
wire [43:0] _ptw_io_requestor_2_ptbr_ppn; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_debug; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_cease; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_wfi; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_dprv; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_dv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_prv; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_v; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_sd; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mpv; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_gva; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_tsr; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_tw; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_tvm; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mxr; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_sum; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mprv; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_fs; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_status_mpp; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_spp; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mpie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_spie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_mie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_status_sie; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_0_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_0_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_0_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_0_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_1_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_1_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_1_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_1_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_2_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_2_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_2_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_2_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_3_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_3_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_3_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_3_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_4_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_4_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_4_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_4_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_5_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_5_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_5_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_5_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_6_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_6_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_6_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_6_mask; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_l; // @[tile.scala:237:20]
wire [1:0] _ptw_io_requestor_2_pmp_7_cfg_a; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_x; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_w; // @[tile.scala:237:20]
wire _ptw_io_requestor_2_pmp_7_cfg_r; // @[tile.scala:237:20]
wire [29:0] _ptw_io_requestor_2_pmp_7_addr; // @[tile.scala:237:20]
wire [31:0] _ptw_io_requestor_2_pmp_7_mask; // @[tile.scala:237:20]
wire _ptw_io_mem_req_valid; // @[tile.scala:237:20]
wire [39:0] _ptw_io_mem_req_bits_addr; // @[tile.scala:237:20]
wire _ptw_io_mem_req_bits_dv; // @[tile.scala:237:20]
wire _ptw_io_mem_s1_kill; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_l2miss; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_l2hit; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_pte_miss; // @[tile.scala:237:20]
wire _ptw_io_dpath_perf_pte_hit; // @[tile.scala:237:20]
wire _ptw_io_dpath_clock_enabled; // @[tile.scala:237:20]
wire _lsu_io_ptw_req_valid; // @[tile.scala:160:20]
wire _lsu_io_ptw_req_bits_valid; // @[tile.scala:160:20]
wire [26:0] _lsu_io_ptw_req_bits_bits_addr; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_iresp_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_core_exe_0_iresp_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_core_exe_0_iresp_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_iresp_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_core_exe_0_iresp_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_core_exe_0_iresp_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_iresp_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_exe_0_iresp_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_iresp_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_exe_0_iresp_bits_data; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_fresp_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_core_exe_0_fresp_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_core_exe_0_fresp_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_exe_0_fresp_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_core_exe_0_fresp_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_core_exe_0_fresp_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_exe_0_fresp_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_exe_0_fresp_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_exe_0_fresp_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [64:0] _lsu_io_core_exe_0_fresp_bits_data; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_ldq_idx_0; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_ldq_idx_1; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_ldq_idx_2; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_stq_idx_0; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_stq_idx_1; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_dis_stq_idx_2; // @[tile.scala:160:20]
wire _lsu_io_core_ldq_full_0; // @[tile.scala:160:20]
wire _lsu_io_core_ldq_full_1; // @[tile.scala:160:20]
wire _lsu_io_core_ldq_full_2; // @[tile.scala:160:20]
wire _lsu_io_core_stq_full_0; // @[tile.scala:160:20]
wire _lsu_io_core_stq_full_1; // @[tile.scala:160:20]
wire _lsu_io_core_stq_full_2; // @[tile.scala:160:20]
wire _lsu_io_core_fp_stdata_ready; // @[tile.scala:160:20]
wire _lsu_io_core_clr_bsy_0_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_clr_bsy_0_bits; // @[tile.scala:160:20]
wire _lsu_io_core_clr_bsy_1_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_clr_bsy_1_bits; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_clr_unsafe_0_bits; // @[tile.scala:160:20]
wire _lsu_io_core_spec_ld_wakeup_0_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_spec_ld_wakeup_0_bits; // @[tile.scala:160:20]
wire _lsu_io_core_ld_miss; // @[tile.scala:160:20]
wire _lsu_io_core_fencei_rdy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_lxcpt_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_core_lxcpt_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_lxcpt_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_core_lxcpt_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_lxcpt_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_core_lxcpt_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_core_lxcpt_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_core_lxcpt_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_core_lxcpt_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_core_lxcpt_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_core_lxcpt_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_core_lxcpt_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_core_lxcpt_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_core_lxcpt_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [4:0] _lsu_io_core_lxcpt_bits_cause; // @[tile.scala:160:20]
wire [39:0] _lsu_io_core_lxcpt_bits_badvaddr; // @[tile.scala:160:20]
wire _lsu_io_core_perf_acquire; // @[tile.scala:160:20]
wire _lsu_io_core_perf_release; // @[tile.scala:160:20]
wire _lsu_io_core_perf_tlbMiss; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_valid; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_valid; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_dmem_req_bits_0_bits_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_req_bits_0_bits_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_req_bits_0_bits_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_dmem_req_bits_0_bits_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_dmem_req_bits_0_bits_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_req_bits_0_bits_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_dmem_req_bits_0_bits_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_req_bits_0_bits_addr; // @[tile.scala:160:20]
wire [63:0] _lsu_io_dmem_req_bits_0_bits_data; // @[tile.scala:160:20]
wire _lsu_io_dmem_req_bits_0_bits_is_hella; // @[tile.scala:160:20]
wire _lsu_io_dmem_s1_kill_0; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_brupdate_b1_resolve_mask; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_brupdate_b1_mispredict_mask; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_uopc; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_brupdate_b2_uop_inst; // @[tile.scala:160:20]
wire [31:0] _lsu_io_dmem_brupdate_b2_uop_debug_inst; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_rvc; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_brupdate_b2_uop_debug_pc; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_iq_type; // @[tile.scala:160:20]
wire [9:0] _lsu_io_dmem_brupdate_b2_uop_fu_code; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_br_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_op1_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_op2_sel; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_imm_sel; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_op_fcn; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_fcn_dw; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_uop_ctrl_csr_cmd; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_is_load; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_is_sta; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ctrl_is_std; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_iw_state; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_iw_p1_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_iw_p2_poisoned; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_br; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_jalr; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_jal; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_sfb; // @[tile.scala:160:20]
wire [15:0] _lsu_io_dmem_brupdate_b2_uop_br_mask; // @[tile.scala:160:20]
wire [3:0] _lsu_io_dmem_brupdate_b2_uop_br_tag; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ftq_idx; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_edge_inst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_pc_lob; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_taken; // @[tile.scala:160:20]
wire [19:0] _lsu_io_dmem_brupdate_b2_uop_imm_packed; // @[tile.scala:160:20]
wire [11:0] _lsu_io_dmem_brupdate_b2_uop_csr_addr; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_rob_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ldq_idx; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_stq_idx; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_rxq_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_pdst; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs1; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs2; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_prs3; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_ppred; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_prs1_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_prs2_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_prs3_busy; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ppred_busy; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_brupdate_b2_uop_stale_pdst; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_exception; // @[tile.scala:160:20]
wire [63:0] _lsu_io_dmem_brupdate_b2_uop_exc_cause; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_bypassable; // @[tile.scala:160:20]
wire [4:0] _lsu_io_dmem_brupdate_b2_uop_mem_cmd; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_mem_size; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_mem_signed; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_fence; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_fencei; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_amo; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_uses_ldq; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_uses_stq; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_is_unique; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_flush_on_commit; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_ldst; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs1; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs2; // @[tile.scala:160:20]
wire [5:0] _lsu_io_dmem_brupdate_b2_uop_lrs3; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_ldst_val; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_dst_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_frs3_en; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_fp_val; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_fp_single; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_bp_debug_if; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_debug_fsrc; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_uop_debug_tsrc; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_valid; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_mispredict; // @[tile.scala:160:20]
wire _lsu_io_dmem_brupdate_b2_taken; // @[tile.scala:160:20]
wire [2:0] _lsu_io_dmem_brupdate_b2_cfi_type; // @[tile.scala:160:20]
wire [1:0] _lsu_io_dmem_brupdate_b2_pc_sel; // @[tile.scala:160:20]
wire [39:0] _lsu_io_dmem_brupdate_b2_jalr_target; // @[tile.scala:160:20]
wire [20:0] _lsu_io_dmem_brupdate_b2_target_offset; // @[tile.scala:160:20]
wire _lsu_io_dmem_exception; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_rob_pnr_idx; // @[tile.scala:160:20]
wire [6:0] _lsu_io_dmem_rob_head_idx; // @[tile.scala:160:20]
wire _lsu_io_dmem_release_ready; // @[tile.scala:160:20]
wire _lsu_io_dmem_force_order; // @[tile.scala:160:20]
wire _lsu_io_hellacache_req_ready; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_nack; // @[tile.scala:160:20]
wire _lsu_io_hellacache_resp_valid; // @[tile.scala:160:20]
wire [39:0] _lsu_io_hellacache_resp_bits_addr; // @[tile.scala:160:20]
wire [63:0] _lsu_io_hellacache_resp_bits_data; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ma_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ma_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_pf_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_pf_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_gf_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_gf_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ae_ld; // @[tile.scala:160:20]
wire _lsu_io_hellacache_s2_xcpt_ae_st; // @[tile.scala:160:20]
wire _lsu_io_hellacache_store_pending; // @[tile.scala:160:20]
wire _core_io_ifu_fetchpacket_ready; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_get_pc_0_ftq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_get_pc_1_ftq_idx; // @[tile.scala:159:20]
wire _core_io_ifu_status_debug; // @[tile.scala:159:20]
wire _core_io_ifu_status_cease; // @[tile.scala:159:20]
wire _core_io_ifu_status_wfi; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_dprv; // @[tile.scala:159:20]
wire _core_io_ifu_status_dv; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_prv; // @[tile.scala:159:20]
wire _core_io_ifu_status_v; // @[tile.scala:159:20]
wire _core_io_ifu_status_sd; // @[tile.scala:159:20]
wire _core_io_ifu_status_mpv; // @[tile.scala:159:20]
wire _core_io_ifu_status_gva; // @[tile.scala:159:20]
wire _core_io_ifu_status_tsr; // @[tile.scala:159:20]
wire _core_io_ifu_status_tw; // @[tile.scala:159:20]
wire _core_io_ifu_status_tvm; // @[tile.scala:159:20]
wire _core_io_ifu_status_mxr; // @[tile.scala:159:20]
wire _core_io_ifu_status_sum; // @[tile.scala:159:20]
wire _core_io_ifu_status_mprv; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_fs; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_status_mpp; // @[tile.scala:159:20]
wire _core_io_ifu_status_spp; // @[tile.scala:159:20]
wire _core_io_ifu_status_mpie; // @[tile.scala:159:20]
wire _core_io_ifu_status_spie; // @[tile.scala:159:20]
wire _core_io_ifu_status_mie; // @[tile.scala:159:20]
wire _core_io_ifu_status_sie; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_valid; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_bits_rs1; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_bits_rs2; // @[tile.scala:159:20]
wire [38:0] _core_io_ifu_sfence_bits_addr; // @[tile.scala:159:20]
wire _core_io_ifu_sfence_bits_asid; // @[tile.scala:159:20]
wire [15:0] _core_io_ifu_brupdate_b1_resolve_mask; // @[tile.scala:159:20]
wire [15:0] _core_io_ifu_brupdate_b1_mispredict_mask; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_ifu_brupdate_b2_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_ifu_brupdate_b2_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_ifu_brupdate_b2_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_ifu_brupdate_b2_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_ifu_brupdate_b2_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_br; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_ifu_brupdate_b2_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_ifu_brupdate_b2_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_ifu_brupdate_b2_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_ifu_brupdate_b2_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_ppred; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_ifu_brupdate_b2_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_ifu_brupdate_b2_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_brupdate_b2_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_ifu_brupdate_b2_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_uop_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_valid; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_mispredict; // @[tile.scala:159:20]
wire _core_io_ifu_brupdate_b2_taken; // @[tile.scala:159:20]
wire [2:0] _core_io_ifu_brupdate_b2_cfi_type; // @[tile.scala:159:20]
wire [1:0] _core_io_ifu_brupdate_b2_pc_sel; // @[tile.scala:159:20]
wire [39:0] _core_io_ifu_brupdate_b2_jalr_target; // @[tile.scala:159:20]
wire [20:0] _core_io_ifu_brupdate_b2_target_offset; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_flush; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_val; // @[tile.scala:159:20]
wire [39:0] _core_io_ifu_redirect_pc; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_redirect_ftq_idx; // @[tile.scala:159:20]
wire [63:0] _core_io_ifu_redirect_ghist_old_history; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_ghist_current_saw_branch_not_taken; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_ghist_new_saw_branch_not_taken; // @[tile.scala:159:20]
wire _core_io_ifu_redirect_ghist_new_saw_branch_taken; // @[tile.scala:159:20]
wire [4:0] _core_io_ifu_redirect_ghist_ras_idx; // @[tile.scala:159:20]
wire _core_io_ifu_commit_valid; // @[tile.scala:159:20]
wire [31:0] _core_io_ifu_commit_bits; // @[tile.scala:159:20]
wire _core_io_ifu_flush_icache; // @[tile.scala:159:20]
wire [3:0] _core_io_ptw_ptbr_mode; // @[tile.scala:159:20]
wire [43:0] _core_io_ptw_ptbr_ppn; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_valid; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_bits_rs1; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_bits_rs2; // @[tile.scala:159:20]
wire [38:0] _core_io_ptw_sfence_bits_addr; // @[tile.scala:159:20]
wire _core_io_ptw_sfence_bits_asid; // @[tile.scala:159:20]
wire _core_io_ptw_status_debug; // @[tile.scala:159:20]
wire _core_io_ptw_status_cease; // @[tile.scala:159:20]
wire _core_io_ptw_status_wfi; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_dprv; // @[tile.scala:159:20]
wire _core_io_ptw_status_dv; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_prv; // @[tile.scala:159:20]
wire _core_io_ptw_status_v; // @[tile.scala:159:20]
wire _core_io_ptw_status_sd; // @[tile.scala:159:20]
wire _core_io_ptw_status_mpv; // @[tile.scala:159:20]
wire _core_io_ptw_status_gva; // @[tile.scala:159:20]
wire _core_io_ptw_status_tsr; // @[tile.scala:159:20]
wire _core_io_ptw_status_tw; // @[tile.scala:159:20]
wire _core_io_ptw_status_tvm; // @[tile.scala:159:20]
wire _core_io_ptw_status_mxr; // @[tile.scala:159:20]
wire _core_io_ptw_status_sum; // @[tile.scala:159:20]
wire _core_io_ptw_status_mprv; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_fs; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_status_mpp; // @[tile.scala:159:20]
wire _core_io_ptw_status_spp; // @[tile.scala:159:20]
wire _core_io_ptw_status_mpie; // @[tile.scala:159:20]
wire _core_io_ptw_status_spie; // @[tile.scala:159:20]
wire _core_io_ptw_status_mie; // @[tile.scala:159:20]
wire _core_io_ptw_status_sie; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_0_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_0_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_0_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_0_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_1_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_1_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_1_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_1_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_2_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_2_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_2_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_2_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_3_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_3_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_3_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_3_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_4_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_4_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_4_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_4_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_5_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_5_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_5_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_5_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_6_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_6_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_6_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_6_mask; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_l; // @[tile.scala:159:20]
wire [1:0] _core_io_ptw_pmp_7_cfg_a; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_x; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_w; // @[tile.scala:159:20]
wire _core_io_ptw_pmp_7_cfg_r; // @[tile.scala:159:20]
wire [29:0] _core_io_ptw_pmp_7_addr; // @[tile.scala:159:20]
wire [31:0] _core_io_ptw_pmp_7_mask; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_exe_0_req_bits_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_exe_0_req_bits_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_exe_0_req_bits_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_exe_0_req_bits_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_exe_0_req_bits_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_exe_0_req_bits_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_exe_0_req_bits_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_exe_0_req_bits_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_exe_0_req_bits_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_exe_0_req_bits_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_exe_0_req_bits_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_exe_0_req_bits_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_exe_0_req_bits_uop_debug_tsrc; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_exe_0_req_bits_data; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_exe_0_req_bits_addr; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_mxcpt_valid; // @[tile.scala:159:20]
wire [24:0] _core_io_lsu_exe_0_req_bits_mxcpt_bits; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_valid; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_bits_rs1; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_bits_rs2; // @[tile.scala:159:20]
wire [38:0] _core_io_lsu_exe_0_req_bits_sfence_bits_addr; // @[tile.scala:159:20]
wire _core_io_lsu_exe_0_req_bits_sfence_bits_asid; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_0_bits_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_0_bits_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_dis_uops_0_bits_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_dis_uops_0_bits_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_0_bits_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_0_bits_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_dis_uops_0_bits_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_0_bits_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_dis_uops_0_bits_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_dis_uops_0_bits_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_prs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_prs3_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_0_bits_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_dis_uops_0_bits_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_0_bits_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_0_bits_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_0_bits_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_0_bits_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_1_bits_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_1_bits_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_dis_uops_1_bits_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_dis_uops_1_bits_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_1_bits_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_1_bits_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_dis_uops_1_bits_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_1_bits_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_dis_uops_1_bits_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_dis_uops_1_bits_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_prs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_prs3_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_1_bits_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_dis_uops_1_bits_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_1_bits_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_1_bits_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_1_bits_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_1_bits_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_2_bits_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_dis_uops_2_bits_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_dis_uops_2_bits_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_dis_uops_2_bits_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_2_bits_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_dis_uops_2_bits_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_dis_uops_2_bits_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_dis_uops_2_bits_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_dis_uops_2_bits_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_dis_uops_2_bits_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_prs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_prs3_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_dis_uops_2_bits_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_dis_uops_2_bits_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_dis_uops_2_bits_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_dis_uops_2_bits_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_dis_uops_2_bits_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_dis_uops_2_bits_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_fp_stdata_bits_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_fp_stdata_bits_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_fp_stdata_bits_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_fp_stdata_bits_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_fp_stdata_bits_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_fp_stdata_bits_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_uop_debug_tsrc; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_fp_stdata_bits_data; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_predicated; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_valid; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_fp_stdata_bits_fflags_bits_flags; // @[tile.scala:159:20]
wire _core_io_lsu_commit_valids_0; // @[tile.scala:159:20]
wire _core_io_lsu_commit_valids_1; // @[tile.scala:159:20]
wire _core_io_lsu_commit_valids_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_arch_valids_0; // @[tile.scala:159:20]
wire _core_io_lsu_commit_arch_valids_1; // @[tile.scala:159:20]
wire _core_io_lsu_commit_arch_valids_2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_0_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_0_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_commit_uops_0_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_commit_uops_0_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_0_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_0_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_commit_uops_0_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_0_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_commit_uops_0_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_commit_uops_0_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_0_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_uops_0_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_0_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_0_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_0_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_0_debug_tsrc; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_1_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_1_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_commit_uops_1_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_commit_uops_1_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_1_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_1_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_commit_uops_1_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_1_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_commit_uops_1_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_commit_uops_1_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_1_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_uops_1_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_1_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_1_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_1_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_1_debug_tsrc; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_2_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_uops_2_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_commit_uops_2_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_commit_uops_2_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_2_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_commit_uops_2_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_commit_uops_2_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_commit_uops_2_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_commit_uops_2_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_commit_uops_2_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_commit_uops_2_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_uops_2_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_uops_2_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_commit_uops_2_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_commit_uops_2_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_commit_uops_2_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_commit_fflags_valid; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_commit_fflags_bits; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_debug_insts_0; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_debug_insts_1; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_commit_debug_insts_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rbk_valids_0; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rbk_valids_1; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rbk_valids_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_rollback; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_debug_wdata_0; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_debug_wdata_1; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_commit_debug_wdata_2; // @[tile.scala:159:20]
wire _core_io_lsu_commit_load_at_rob_head; // @[tile.scala:159:20]
wire _core_io_lsu_fence_dmem; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_brupdate_b1_resolve_mask; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_brupdate_b1_mispredict_mask; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_uopc; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_brupdate_b2_uop_inst; // @[tile.scala:159:20]
wire [31:0] _core_io_lsu_brupdate_b2_uop_debug_inst; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_rvc; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_brupdate_b2_uop_debug_pc; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_iq_type; // @[tile.scala:159:20]
wire [9:0] _core_io_lsu_brupdate_b2_uop_fu_code; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_brupdate_b2_uop_ctrl_br_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_ctrl_op1_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_ctrl_op2_sel; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_ctrl_imm_sel; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ctrl_op_fcn; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_fcn_dw; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_uop_ctrl_csr_cmd; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_is_load; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_is_sta; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ctrl_is_std; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_iw_state; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_iw_p1_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_iw_p2_poisoned; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_br; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_jalr; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_jal; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_sfb; // @[tile.scala:159:20]
wire [15:0] _core_io_lsu_brupdate_b2_uop_br_mask; // @[tile.scala:159:20]
wire [3:0] _core_io_lsu_brupdate_b2_uop_br_tag; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ftq_idx; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_edge_inst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_pc_lob; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_taken; // @[tile.scala:159:20]
wire [19:0] _core_io_lsu_brupdate_b2_uop_imm_packed; // @[tile.scala:159:20]
wire [11:0] _core_io_lsu_brupdate_b2_uop_csr_addr; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_rob_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ldq_idx; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_stq_idx; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_rxq_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_pdst; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_prs1; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_prs2; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_prs3; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_ppred; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_prs1_busy; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_prs2_busy; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_prs3_busy; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ppred_busy; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_brupdate_b2_uop_stale_pdst; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_brupdate_b2_uop_exc_cause; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_bypassable; // @[tile.scala:159:20]
wire [4:0] _core_io_lsu_brupdate_b2_uop_mem_cmd; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_mem_size; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_mem_signed; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_fence; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_fencei; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_amo; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_uses_ldq; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_uses_stq; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_sys_pc2epc; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_is_unique; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_flush_on_commit; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ldst_is_rs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_ldst; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs1; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs2; // @[tile.scala:159:20]
wire [5:0] _core_io_lsu_brupdate_b2_uop_lrs3; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_ldst_val; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_dst_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_lrs1_rtype; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_lrs2_rtype; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_frs3_en; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_fp_val; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_fp_single; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_xcpt_pf_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_xcpt_ae_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_xcpt_ma_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_bp_debug_if; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_uop_bp_xcpt_if; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_debug_fsrc; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_uop_debug_tsrc; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_valid; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_mispredict; // @[tile.scala:159:20]
wire _core_io_lsu_brupdate_b2_taken; // @[tile.scala:159:20]
wire [2:0] _core_io_lsu_brupdate_b2_cfi_type; // @[tile.scala:159:20]
wire [1:0] _core_io_lsu_brupdate_b2_pc_sel; // @[tile.scala:159:20]
wire [39:0] _core_io_lsu_brupdate_b2_jalr_target; // @[tile.scala:159:20]
wire [20:0] _core_io_lsu_brupdate_b2_target_offset; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_rob_pnr_idx; // @[tile.scala:159:20]
wire [6:0] _core_io_lsu_rob_head_idx; // @[tile.scala:159:20]
wire _core_io_lsu_exception; // @[tile.scala:159:20]
wire [63:0] _core_io_lsu_tsc_reg; // @[tile.scala:159:20]
wire _frontend_io_cpu_fetchpacket_valid; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_valid; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst; // @[tile.scala:138:28]
wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if; // @[tile.scala:138:28]
wire [1:0] _frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_valid; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst; // @[tile.scala:138:28]
wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if; // @[tile.scala:138:28]
wire [1:0] _frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_valid; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_inst; // @[tile.scala:138:28]
wire [31:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_inst; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_rvc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_sfb; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_edge_inst; // @[tile.scala:138:28]
wire [5:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_pc_lob; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if; // @[tile.scala:138:28]
wire _frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if; // @[tile.scala:138:28]
wire [1:0] _frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_idx_valid; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_0_entry_cfi_idx_bits; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_mispredicted; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_0_entry_cfi_type; // @[tile.scala:138:28]
wire [7:0] _frontend_io_cpu_get_pc_0_entry_br_mask; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_is_call; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_is_ret; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_cfi_npc_plus4; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_entry_ras_top; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_get_pc_0_entry_ras_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_entry_start_bank; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_pc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_com_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_0_next_val; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_0_next_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_idx_valid; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_1_entry_cfi_idx_bits; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_mispredicted; // @[tile.scala:138:28]
wire [2:0] _frontend_io_cpu_get_pc_1_entry_cfi_type; // @[tile.scala:138:28]
wire [7:0] _frontend_io_cpu_get_pc_1_entry_br_mask; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_is_call; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_is_ret; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_cfi_npc_plus4; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_entry_ras_top; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_get_pc_1_entry_ras_idx; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_entry_start_bank; // @[tile.scala:138:28]
wire [63:0] _frontend_io_cpu_get_pc_1_ghist_old_history; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_ghist_current_saw_branch_not_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_ghist_new_saw_branch_not_taken; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_ghist_new_saw_branch_taken; // @[tile.scala:138:28]
wire [4:0] _frontend_io_cpu_get_pc_1_ghist_ras_idx; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_pc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_com_pc; // @[tile.scala:138:28]
wire _frontend_io_cpu_get_pc_1_next_val; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_get_pc_1_next_pc; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_debug_fetch_pc_0; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_debug_fetch_pc_1; // @[tile.scala:138:28]
wire [39:0] _frontend_io_cpu_debug_fetch_pc_2; // @[tile.scala:138:28]
wire _frontend_io_cpu_perf_acquire; // @[tile.scala:138:28]
wire _frontend_io_cpu_perf_tlbMiss; // @[tile.scala:138:28]
wire _frontend_io_ptw_req_valid; // @[tile.scala:138:28]
wire [26:0] _frontend_io_ptw_req_bits_bits_addr; // @[tile.scala:138:28]
wire _frontend_io_ptw_req_bits_bits_need_gpa; // @[tile.scala:138:28]
wire _dcache_io_lsu_req_ready; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_valid; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_uopc; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_resp_0_bits_uop_inst; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_resp_0_bits_uop_debug_inst; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_rvc; // @[tile.scala:132:54]
wire [39:0] _dcache_io_lsu_resp_0_bits_uop_debug_pc; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_iq_type; // @[tile.scala:132:54]
wire [9:0] _dcache_io_lsu_resp_0_bits_uop_fu_code; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_br_type; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_load; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ctrl_is_std; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_iw_state; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_br; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_jalr; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_jal; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_sfb; // @[tile.scala:132:54]
wire [15:0] _dcache_io_lsu_resp_0_bits_uop_br_mask; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_resp_0_bits_uop_br_tag; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ftq_idx; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_edge_inst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_pc_lob; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_taken; // @[tile.scala:132:54]
wire [19:0] _dcache_io_lsu_resp_0_bits_uop_imm_packed; // @[tile.scala:132:54]
wire [11:0] _dcache_io_lsu_resp_0_bits_uop_csr_addr; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_rob_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ldq_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_stq_idx; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_rxq_idx; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_pdst; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs1; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs2; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_prs3; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_ppred; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_prs1_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_prs2_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_prs3_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ppred_busy; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_resp_0_bits_uop_stale_pdst; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_exception; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_resp_0_bits_uop_exc_cause; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_bypassable; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_resp_0_bits_uop_mem_cmd; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_mem_size; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_mem_signed; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_fence; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_fencei; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_amo; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_uses_ldq; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_uses_stq; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_is_unique; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_flush_on_commit; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_ldst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs2; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_resp_0_bits_uop_lrs3; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_ldst_val; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_dst_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_frs3_en; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_fp_val; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_fp_single; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_bp_debug_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_debug_fsrc; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_resp_0_bits_uop_debug_tsrc; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_resp_0_bits_data; // @[tile.scala:132:54]
wire _dcache_io_lsu_resp_0_bits_is_hella; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_valid; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_uopc; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_nack_0_bits_uop_inst; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_nack_0_bits_uop_debug_inst; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_rvc; // @[tile.scala:132:54]
wire [39:0] _dcache_io_lsu_nack_0_bits_uop_debug_pc; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_iq_type; // @[tile.scala:132:54]
wire [9:0] _dcache_io_lsu_nack_0_bits_uop_fu_code; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_br_type; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_load; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ctrl_is_std; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_iw_state; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_br; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_jalr; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_jal; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_sfb; // @[tile.scala:132:54]
wire [15:0] _dcache_io_lsu_nack_0_bits_uop_br_mask; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_nack_0_bits_uop_br_tag; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ftq_idx; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_edge_inst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_pc_lob; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_taken; // @[tile.scala:132:54]
wire [19:0] _dcache_io_lsu_nack_0_bits_uop_imm_packed; // @[tile.scala:132:54]
wire [11:0] _dcache_io_lsu_nack_0_bits_uop_csr_addr; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_rob_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ldq_idx; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_stq_idx; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_rxq_idx; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_pdst; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs1; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs2; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_prs3; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_ppred; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_prs1_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_prs2_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_prs3_busy; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ppred_busy; // @[tile.scala:132:54]
wire [6:0] _dcache_io_lsu_nack_0_bits_uop_stale_pdst; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_exception; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_nack_0_bits_uop_exc_cause; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_bypassable; // @[tile.scala:132:54]
wire [4:0] _dcache_io_lsu_nack_0_bits_uop_mem_cmd; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_mem_size; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_mem_signed; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_fence; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_fencei; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_amo; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_uses_ldq; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_uses_stq; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_is_unique; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_flush_on_commit; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_ldst; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs1; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs2; // @[tile.scala:132:54]
wire [5:0] _dcache_io_lsu_nack_0_bits_uop_lrs3; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_ldst_val; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_dst_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs1_rtype; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_lrs2_rtype; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_frs3_en; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_fp_val; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_fp_single; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_bp_debug_if; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_debug_fsrc; // @[tile.scala:132:54]
wire [1:0] _dcache_io_lsu_nack_0_bits_uop_debug_tsrc; // @[tile.scala:132:54]
wire [39:0] _dcache_io_lsu_nack_0_bits_addr; // @[tile.scala:132:54]
wire [63:0] _dcache_io_lsu_nack_0_bits_data; // @[tile.scala:132:54]
wire _dcache_io_lsu_nack_0_bits_is_hella; // @[tile.scala:132:54]
wire _dcache_io_lsu_release_valid; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_release_bits_opcode; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_release_bits_param; // @[tile.scala:132:54]
wire [3:0] _dcache_io_lsu_release_bits_size; // @[tile.scala:132:54]
wire [2:0] _dcache_io_lsu_release_bits_source; // @[tile.scala:132:54]
wire [31:0] _dcache_io_lsu_release_bits_address; // @[tile.scala:132:54]
wire [127:0] _dcache_io_lsu_release_bits_data; // @[tile.scala:132:54]
wire _dcache_io_lsu_ordered; // @[tile.scala:132:54]
wire _dcache_io_lsu_perf_acquire; // @[tile.scala:132:54]
wire _dcache_io_lsu_perf_release; // @[tile.scala:132:54]
wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[tile.scala:155:7]
wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[tile.scala:155:7]
wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[tile.scala:155:7]
wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[tile.scala:155:7]
wire [15:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[tile.scala:155:7]
wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[tile.scala:155:7]
wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[tile.scala:155:7]
wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[tile.scala:155:7]
wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[tile.scala:155:7]
wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[tile.scala:155:7]
wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[tile.scala:155:7]
wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[tile.scala:155:7]
wire auto_int_local_in_3_0_0 = auto_int_local_in_3_0; // @[tile.scala:155:7]
wire auto_int_local_in_2_0_0 = auto_int_local_in_2_0; // @[tile.scala:155:7]
wire auto_int_local_in_1_0_0 = auto_int_local_in_1_0; // @[tile.scala:155:7]
wire auto_int_local_in_1_1_0 = auto_int_local_in_1_1; // @[tile.scala:155:7]
wire auto_int_local_in_0_0_0 = auto_int_local_in_0_0; // @[tile.scala:155:7]
wire [1:0] auto_hartid_in_0 = auto_hartid_in; // @[tile.scala:155:7]
wire auto_buffer_out_a_bits_corrupt = 1'h0; // @[tile.scala:155:7]
wire auto_buffer_out_c_bits_corrupt = 1'h0; // @[tile.scala:155:7]
wire auto_wfi_out_0 = 1'h0; // @[tile.scala:155:7]
wire auto_cease_out_0 = 1'h0; // @[tile.scala:155:7]
wire auto_halt_out_0 = 1'h0; // @[tile.scala:155:7]
wire auto_trace_core_source_out_group_0_iretire = 1'h0; // @[tile.scala:155:7]
wire auto_trace_core_source_out_group_0_ilastsize = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_0_valid = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_0_exception = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_0_interrupt = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_1_valid = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_1_exception = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_1_interrupt = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_2_valid = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_2_exception = 1'h0; // @[tile.scala:155:7]
wire auto_trace_source_out_insns_2_interrupt = 1'h0; // @[tile.scala:155:7]
wire broadcast_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire broadcast_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire nexus_1_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire nexus_1__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nexus_1_x1_bundleOut_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_x1_bundleOut_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_nodeOut_enable = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_nodeOut_stall = 1'h0; // @[MixedNode.scala:542:17]
wire nexus_1_defaultWireOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire nexus_1_defaultWireOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire broadcast_2_childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire broadcast_2_childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire broadcast_2__childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_auto_anon_in_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_bits_source = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire widget_1_anonIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_source = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_auto_in_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_in_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_bits_corrupt = 1'h0; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire buffer_nodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire tlOtherMastersNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire traceSourceNodeOut_insns_0_valid = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_0_exception = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_0_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_1_valid = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_1_exception = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_1_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_2_valid = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_2_exception = 1'h0; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_insns_2_interrupt = 1'h0; // @[MixedNode.scala:542:17]
wire traceCoreSourceNodeOut_group_0_iretire = 1'h0; // @[MixedNode.scala:542:17]
wire traceCoreSourceNodeOut_group_0_ilastsize = 1'h0; // @[MixedNode.scala:542:17]
wire bundleIn_x_sourceOpt_enable = 1'h0; // @[BaseTile.scala:305:19]
wire bundleIn_x_sourceOpt_stall = 1'h0; // @[BaseTile.scala:305:19]
wire traceAuxSinkNodeIn_enable = 1'h0; // @[MixedNode.scala:551:17]
wire traceAuxSinkNodeIn_stall = 1'h0; // @[MixedNode.scala:551:17]
wire haltNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire ceaseNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire wfiNodeOut_0 = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire masterNodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire masterNodeIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire dCacheTapOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire dCacheTapOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire dCacheTapIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire dCacheTapIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_auto_anon_in_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_opcode = 3'h4; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_out_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonIn_a_bits_size = 4'h6; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_auto_anon_in_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_auto_anon_out_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_anonOut_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [15:0] widget_1_anonIn_a_bits_mask = 16'hFFFF; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_in_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_out_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonOut_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonIn_a_bits_data = 128'h0; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_ready = 1'h1; // @[WidthWidget.scala:27:9]
wire [31:0] auto_reset_vector_in = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_auto_in = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_auto_out_1 = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_auto_out_0 = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_nodeIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_nodeOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] broadcast_1_x1_nodeOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] reset_vectorOut = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] reset_vectorIn = 32'h10000; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] auto_trace_source_out_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] auto_trace_source_out_insns_1_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] auto_trace_source_out_insns_2_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_0_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_1_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [63:0] traceSourceNodeOut_insns_2_cause = 64'h0; // @[MixedNode.scala:542:17]
wire [2:0] auto_trace_source_out_insns_0_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_trace_source_out_insns_1_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_trace_source_out_insns_2_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_out_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonIn_a_bits_param = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] traceSourceNodeOut_insns_0_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] traceSourceNodeOut_insns_1_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [2:0] traceSourceNodeOut_insns_2_priv = 3'h0; // @[WidthWidget.scala:27:9]
wire [39:0] auto_trace_source_out_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_2_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] auto_trace_source_out_insns_2_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_0_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_0_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_1_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_1_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_2_iaddr = 40'h0; // @[MixedNode.scala:542:17]
wire [39:0] traceSourceNodeOut_insns_2_tval = 40'h0; // @[MixedNode.scala:542:17]
wire [3:0] auto_trace_core_source_out_group_0_itype = 4'h0; // @[tile.scala:155:7]
wire [3:0] auto_trace_core_source_out_priv = 4'h0; // @[tile.scala:155:7]
wire [3:0] traceCoreSourceNodeOut_group_0_itype = 4'h0; // @[MixedNode.scala:542:17]
wire [3:0] traceCoreSourceNodeOut_priv = 4'h0; // @[MixedNode.scala:542:17]
wire [31:0] auto_trace_core_source_out_group_0_iaddr = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_core_source_out_tval = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_core_source_out_cause = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_source_out_insns_0_insn = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_source_out_insns_1_insn = 32'h0; // @[tile.scala:155:7]
wire [31:0] auto_trace_source_out_insns_2_insn = 32'h0; // @[tile.scala:155:7]
wire [31:0] traceSourceNodeOut_insns_0_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceSourceNodeOut_insns_1_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceSourceNodeOut_insns_2_insn = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_group_0_iaddr = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_tval = 32'h0; // @[MixedNode.scala:542:17]
wire [31:0] traceCoreSourceNodeOut_cause = 32'h0; // @[MixedNode.scala:542:17]
wire buffer_auto_out_a_ready = auto_buffer_out_a_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_valid = auto_buffer_out_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_b_bits_opcode = auto_buffer_out_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_b_bits_param = auto_buffer_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_b_bits_size = auto_buffer_out_b_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_b_bits_source = auto_buffer_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_b_bits_address = auto_buffer_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] buffer_auto_out_b_bits_mask = auto_buffer_out_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_b_bits_data = auto_buffer_out_b_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_b_bits_corrupt = auto_buffer_out_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_ready = auto_buffer_out_c_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_valid = auto_buffer_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] buffer_auto_out_d_bits_opcode = auto_buffer_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] buffer_auto_out_d_bits_param = auto_buffer_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_d_bits_size = auto_buffer_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_d_bits_source = auto_buffer_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_d_bits_sink = auto_buffer_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_denied = auto_buffer_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] buffer_auto_out_d_bits_data = auto_buffer_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_d_bits_corrupt = auto_buffer_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_e_ready = auto_buffer_out_e_ready_0; // @[Buffer.scala:40:9]
wire buffer_auto_out_e_valid; // @[Buffer.scala:40:9]
wire [3:0] buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
wire x1_int_localIn_2_0 = auto_int_local_in_3_0_0; // @[MixedNode.scala:551:17]
wire x1_int_localIn_1_0 = auto_int_local_in_2_0_0; // @[MixedNode.scala:551:17]
wire x1_int_localIn_0 = auto_int_local_in_1_0_0; // @[MixedNode.scala:551:17]
wire x1_int_localIn_1 = auto_int_local_in_1_1_0; // @[MixedNode.scala:551:17]
wire int_localIn_0 = auto_int_local_in_0_0_0; // @[MixedNode.scala:551:17]
wire [63:0] traceSourceNodeOut_time; // @[MixedNode.scala:542:17]
wire traceSourceNodeOut_custom_rob_empty; // @[MixedNode.scala:542:17]
wire [1:0] hartidIn = auto_hartid_in_0; // @[MixedNode.scala:551:17]
wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_a_bits_param_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_a_bits_size_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_a_bits_source_0; // @[tile.scala:155:7]
wire [31:0] auto_buffer_out_a_bits_address_0; // @[tile.scala:155:7]
wire [15:0] auto_buffer_out_a_bits_mask_0; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_a_bits_data_0; // @[tile.scala:155:7]
wire auto_buffer_out_a_valid_0; // @[tile.scala:155:7]
wire auto_buffer_out_b_ready_0; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[tile.scala:155:7]
wire [2:0] auto_buffer_out_c_bits_param_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_c_bits_size_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_c_bits_source_0; // @[tile.scala:155:7]
wire [31:0] auto_buffer_out_c_bits_address_0; // @[tile.scala:155:7]
wire [127:0] auto_buffer_out_c_bits_data_0; // @[tile.scala:155:7]
wire auto_buffer_out_c_valid_0; // @[tile.scala:155:7]
wire auto_buffer_out_d_ready_0; // @[tile.scala:155:7]
wire [3:0] auto_buffer_out_e_bits_sink_0; // @[tile.scala:155:7]
wire auto_buffer_out_e_valid_0; // @[tile.scala:155:7]
wire auto_trace_source_out_custom_rob_empty_0; // @[tile.scala:155:7]
wire [63:0] auto_trace_source_out_time_0; // @[tile.scala:155:7]
wire [1:0] hartidOut; // @[MixedNode.scala:542:17]
wire [1:0] broadcast_nodeIn = broadcast_auto_in; // @[MixedNode.scala:551:17]
wire [1:0] broadcast_nodeOut; // @[MixedNode.scala:542:17]
wire [1:0] broadcast_auto_out; // @[BundleBridgeNexus.scala:20:9]
wire [1:0] hartIdSinkNodeIn = broadcast_auto_out; // @[MixedNode.scala:551:17]
assign broadcast_nodeOut = broadcast_nodeIn; // @[MixedNode.scala:542:17, :551:17]
assign broadcast_auto_out = broadcast_nodeOut; // @[MixedNode.scala:542:17]
wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapIn_a_valid = widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_a_bits_opcode = widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_a_bits_param = widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapIn_a_bits_size = widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_a_bits_source = widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire [15:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapIn_a_bits_address = widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [15:0] dCacheTapIn_a_bits_mask = widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_a_bits_data = widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire dCacheTapIn_b_ready = widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_b_valid; // @[MixedNode.scala:551:17]
wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] dCacheTapIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] dCacheTapIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] dCacheTapIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [15:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_c_ready; // @[MixedNode.scala:551:17]
wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire dCacheTapIn_c_valid = widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_c_bits_opcode = widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_c_bits_param = widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapIn_c_bits_size = widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapIn_c_bits_source = widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire [127:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapIn_c_bits_address = widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_c_bits_data = widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire dCacheTapIn_d_ready = widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_d_valid; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] dCacheTapIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] dCacheTapIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] dCacheTapIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire dCacheTapIn_e_ready; // @[MixedNode.scala:551:17]
wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire dCacheTapIn_e_valid = widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
wire [3:0] dCacheTapIn_e_bits_sink = widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire widget_1_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_a_valid = widget_1_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_anonIn_a_bits_address = widget_1_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_1_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_1_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_1_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] widget_1_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] widget_1_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_1_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_1_anonOut_a_ready = widget_1_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [31:0] widget_1_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire widget_1_anonOut_d_valid = widget_1_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_anonOut_d_bits_opcode = widget_1_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_anonOut_d_bits_param = widget_1_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_d_bits_size = widget_1_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_anonOut_d_bits_sink = widget_1_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_bits_denied = widget_1_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_anonOut_d_bits_data = widget_1_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_anonOut_d_bits_corrupt = widget_1_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_1_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_1_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] widget_1_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] widget_1_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire [31:0] widget_1_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_1_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_a_ready = widget_1_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_out_a_valid = widget_1_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_out_a_bits_address = widget_1_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_1_anonIn_d_valid = widget_1_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_opcode = widget_1_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_param = widget_1_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_size = widget_1_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_sink = widget_1_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_denied = widget_1_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_data = widget_1_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonIn_d_bits_corrupt = widget_1_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_a_ready = widget_1_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_1_anonOut_a_valid = widget_1_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_anonOut_a_bits_address = widget_1_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_1_auto_anon_in_d_valid = widget_1_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_opcode = widget_1_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_param = widget_1_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_size = widget_1_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_sink = widget_1_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_denied = widget_1_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_data = widget_1_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_1_auto_anon_in_d_bits_corrupt = widget_1_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire buffer_nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire masterNodeOut_a_ready = buffer_auto_in_a_ready; // @[Buffer.scala:40:9]
wire masterNodeOut_a_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_a_valid = buffer_auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_opcode = buffer_auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_a_bits_param = buffer_auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_a_bits_size = buffer_auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_a_bits_source = buffer_auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] masterNodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_nodeIn_a_bits_address = buffer_auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] masterNodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [15:0] buffer_nodeIn_a_bits_mask = buffer_auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] masterNodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire [127:0] buffer_nodeIn_a_bits_data = buffer_auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire masterNodeOut_b_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_b_ready = buffer_auto_in_b_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeOut_b_valid = buffer_auto_in_b_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeOut_b_bits_opcode = buffer_auto_in_b_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] masterNodeOut_b_bits_param = buffer_auto_in_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_b_bits_size = buffer_auto_in_b_bits_size; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_b_bits_source = buffer_auto_in_b_bits_source; // @[Buffer.scala:40:9]
wire [15:0] buffer_nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] masterNodeOut_b_bits_address = buffer_auto_in_b_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [15:0] masterNodeOut_b_bits_mask = buffer_auto_in_b_bits_mask; // @[Buffer.scala:40:9]
wire buffer_nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] masterNodeOut_b_bits_data = buffer_auto_in_b_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire masterNodeOut_b_bits_corrupt = buffer_auto_in_b_bits_corrupt; // @[Buffer.scala:40:9]
wire masterNodeOut_c_ready = buffer_auto_in_c_ready; // @[Buffer.scala:40:9]
wire masterNodeOut_c_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_c_valid = buffer_auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_c_bits_opcode = buffer_auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] masterNodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] buffer_nodeIn_c_bits_param = buffer_auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_c_bits_size = buffer_auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_c_bits_source = buffer_auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] masterNodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [31:0] buffer_nodeIn_c_bits_address = buffer_auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] masterNodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire [127:0] buffer_nodeIn_c_bits_data = buffer_auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire masterNodeOut_d_ready; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_d_ready = buffer_auto_in_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] buffer_nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeOut_d_valid = buffer_auto_in_d_valid; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeOut_d_bits_opcode = buffer_auto_in_d_bits_opcode; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] masterNodeOut_d_bits_param = buffer_auto_in_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_d_bits_size = buffer_auto_in_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_d_bits_source = buffer_auto_in_d_bits_source; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeOut_d_bits_sink = buffer_auto_in_d_bits_sink; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire masterNodeOut_d_bits_denied = buffer_auto_in_d_bits_denied; // @[Buffer.scala:40:9]
wire buffer_nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [127:0] masterNodeOut_d_bits_data = buffer_auto_in_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire masterNodeOut_d_bits_corrupt = buffer_auto_in_d_bits_corrupt; // @[Buffer.scala:40:9]
wire masterNodeOut_e_ready = buffer_auto_in_e_ready; // @[Buffer.scala:40:9]
wire masterNodeOut_e_valid; // @[MixedNode.scala:542:17]
wire buffer_nodeIn_e_valid = buffer_auto_in_e_valid; // @[Buffer.scala:40:9]
wire [3:0] masterNodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire [3:0] buffer_nodeIn_e_bits_sink = buffer_auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_ready = buffer_auto_out_a_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_a_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_valid_0 = buffer_auto_out_a_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_opcode_0 = buffer_auto_out_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_param_0 = buffer_auto_out_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_size_0 = buffer_auto_out_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_source_0 = buffer_auto_out_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_address_0 = buffer_auto_out_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_mask_0 = buffer_auto_out_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_a_bits_data_0 = buffer_auto_out_a_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_b_ready_0 = buffer_auto_out_b_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_valid = buffer_auto_out_b_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_b_bits_opcode = buffer_auto_out_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_b_bits_param = buffer_auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_b_bits_size = buffer_auto_out_b_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_b_bits_source = buffer_auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_b_bits_address = buffer_auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire [15:0] buffer_nodeOut_b_bits_mask = buffer_auto_out_b_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_b_bits_data = buffer_auto_out_b_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_b_bits_corrupt = buffer_auto_out_b_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_nodeOut_c_ready = buffer_auto_out_c_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_c_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_valid_0 = buffer_auto_out_c_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_opcode_0 = buffer_auto_out_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_param_0 = buffer_auto_out_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_size_0 = buffer_auto_out_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_source_0 = buffer_auto_out_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] buffer_nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_address_0 = buffer_auto_out_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
assign auto_buffer_out_c_bits_data_0 = buffer_auto_out_c_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_ready; // @[MixedNode.scala:542:17]
assign auto_buffer_out_d_ready_0 = buffer_auto_out_d_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_valid = buffer_auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] buffer_nodeOut_d_bits_opcode = buffer_auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] buffer_nodeOut_d_bits_param = buffer_auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_size = buffer_auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_source = buffer_auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_d_bits_sink = buffer_auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_denied = buffer_auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] buffer_nodeOut_d_bits_data = buffer_auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire buffer_nodeOut_d_bits_corrupt = buffer_auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire buffer_nodeOut_e_ready = buffer_auto_out_e_ready; // @[Buffer.scala:40:9]
wire buffer_nodeOut_e_valid; // @[MixedNode.scala:542:17]
assign auto_buffer_out_e_valid_0 = buffer_auto_out_e_valid; // @[Buffer.scala:40:9]
wire [3:0] buffer_nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign auto_buffer_out_e_bits_sink_0 = buffer_auto_out_e_bits_sink; // @[Buffer.scala:40:9]
assign buffer_nodeIn_a_ready = buffer_nodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_a_valid = buffer_nodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_opcode = buffer_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_param = buffer_nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_size = buffer_nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_source = buffer_nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_address = buffer_nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_mask = buffer_nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_out_a_bits_data = buffer_nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_b_ready = buffer_nodeOut_b_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_b_valid = buffer_nodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_opcode = buffer_nodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_param = buffer_nodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_size = buffer_nodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_source = buffer_nodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_address = buffer_nodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_mask = buffer_nodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_data = buffer_nodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_b_bits_corrupt = buffer_nodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_c_ready = buffer_nodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_c_valid = buffer_nodeOut_c_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_opcode = buffer_nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_param = buffer_nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_size = buffer_nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_source = buffer_nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_address = buffer_nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_out_c_bits_data = buffer_nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_out_d_ready = buffer_nodeOut_d_ready; // @[Buffer.scala:40:9]
assign buffer_nodeIn_d_valid = buffer_nodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_opcode = buffer_nodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_param = buffer_nodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_size = buffer_nodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_source = buffer_nodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_sink = buffer_nodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_denied = buffer_nodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_data = buffer_nodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_d_bits_corrupt = buffer_nodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeIn_e_ready = buffer_nodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_out_e_valid = buffer_nodeOut_e_valid; // @[Buffer.scala:40:9]
assign buffer_auto_out_e_bits_sink = buffer_nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_ready = buffer_nodeIn_a_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_a_valid = buffer_nodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_opcode = buffer_nodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_param = buffer_nodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_size = buffer_nodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_source = buffer_nodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_address = buffer_nodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_mask = buffer_nodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_a_bits_data = buffer_nodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_b_ready = buffer_nodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_b_valid = buffer_nodeIn_b_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_opcode = buffer_nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_param = buffer_nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_size = buffer_nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_source = buffer_nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_address = buffer_nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_mask = buffer_nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_data = buffer_nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_bits_corrupt = buffer_nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_ready = buffer_nodeIn_c_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_c_valid = buffer_nodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_opcode = buffer_nodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_param = buffer_nodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_size = buffer_nodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_source = buffer_nodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_address = buffer_nodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_c_bits_data = buffer_nodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_d_ready = buffer_nodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_d_valid = buffer_nodeIn_d_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_opcode = buffer_nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_param = buffer_nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_size = buffer_nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_source = buffer_nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_sink = buffer_nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_denied = buffer_nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_data = buffer_nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_bits_corrupt = buffer_nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign buffer_auto_in_e_ready = buffer_nodeIn_e_ready; // @[Buffer.scala:40:9]
assign buffer_nodeOut_e_valid = buffer_nodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign buffer_nodeOut_e_bits_sink = buffer_nodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_a_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_a_ready = tlOtherMastersNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeIn_a_valid = tlOtherMastersNodeOut_a_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_a_bits_opcode = tlOtherMastersNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_a_bits_param = tlOtherMastersNodeOut_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_a_bits_size = tlOtherMastersNodeOut_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_a_bits_source = tlOtherMastersNodeOut_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] masterNodeIn_a_bits_address = tlOtherMastersNodeOut_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:551:17]
wire [15:0] masterNodeIn_a_bits_mask = tlOtherMastersNodeOut_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_a_bits_data = tlOtherMastersNodeOut_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:551:17]
wire masterNodeIn_b_ready = tlOtherMastersNodeOut_b_ready; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_b_valid; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_b_valid = tlOtherMastersNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] masterNodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_b_bits_opcode = tlOtherMastersNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] masterNodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeIn_b_bits_param = tlOtherMastersNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_b_bits_size = tlOtherMastersNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_b_bits_source = tlOtherMastersNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] masterNodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [31:0] tlOtherMastersNodeIn_b_bits_address = tlOtherMastersNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [15:0] masterNodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [15:0] tlOtherMastersNodeIn_b_bits_mask = tlOtherMastersNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] tlOtherMastersNodeIn_b_bits_data = tlOtherMastersNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_b_bits_corrupt = tlOtherMastersNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_c_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_c_ready = tlOtherMastersNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:551:17]
wire masterNodeIn_c_valid = tlOtherMastersNodeOut_c_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_c_bits_opcode = tlOtherMastersNodeOut_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:551:17]
wire [2:0] masterNodeIn_c_bits_param = tlOtherMastersNodeOut_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_c_bits_size = tlOtherMastersNodeOut_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [31:0] tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:551:17]
wire [3:0] masterNodeIn_c_bits_source = tlOtherMastersNodeOut_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:551:17]
wire [31:0] masterNodeIn_c_bits_address = tlOtherMastersNodeOut_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_c_bits_data = tlOtherMastersNodeOut_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:551:17]
wire masterNodeIn_d_ready = tlOtherMastersNodeOut_d_ready; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_d_valid; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_d_valid = tlOtherMastersNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] masterNodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [2:0] tlOtherMastersNodeIn_d_bits_opcode = tlOtherMastersNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] masterNodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [1:0] tlOtherMastersNodeIn_d_bits_param = tlOtherMastersNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_size = tlOtherMastersNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_source = tlOtherMastersNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_d_bits_sink = tlOtherMastersNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_d_bits_denied = tlOtherMastersNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [127:0] masterNodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire [127:0] tlOtherMastersNodeIn_d_bits_data = tlOtherMastersNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_d_bits_corrupt = tlOtherMastersNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
wire masterNodeIn_e_ready; // @[MixedNode.scala:551:17]
wire tlOtherMastersNodeIn_e_ready = tlOtherMastersNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:551:17]
wire [3:0] tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:551:17]
wire masterNodeIn_e_valid = tlOtherMastersNodeOut_e_valid; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] masterNodeIn_e_bits_sink = tlOtherMastersNodeOut_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_valid = tlOtherMastersNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_opcode = tlOtherMastersNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_param = tlOtherMastersNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_size = tlOtherMastersNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_source = tlOtherMastersNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_address = tlOtherMastersNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_mask = tlOtherMastersNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_a_bits_data = tlOtherMastersNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_ready = tlOtherMastersNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_valid = tlOtherMastersNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_opcode = tlOtherMastersNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_param = tlOtherMastersNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_size = tlOtherMastersNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_source = tlOtherMastersNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_address = tlOtherMastersNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_bits_data = tlOtherMastersNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_ready = tlOtherMastersNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_valid = tlOtherMastersNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_bits_sink = tlOtherMastersNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign broadcast_auto_in = hartidOut; // @[MixedNode.scala:542:17]
assign hartidOut = hartidIn; // @[MixedNode.scala:542:17, :551:17]
assign auto_trace_source_out_time_0 = traceSourceNodeOut_time; // @[MixedNode.scala:542:17]
assign auto_trace_source_out_custom_rob_empty_0 = traceSourceNodeOut_custom_rob_empty; // @[MixedNode.scala:542:17]
wire int_localOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_1; // @[MixedNode.scala:542:17]
wire x1_int_localOut_1_0; // @[MixedNode.scala:542:17]
wire x1_int_localOut_2_0; // @[MixedNode.scala:542:17]
assign int_localOut_0 = int_localIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_0 = x1_int_localIn_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_1 = x1_int_localIn_1; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_1_0 = x1_int_localIn_1_0; // @[MixedNode.scala:542:17, :551:17]
assign x1_int_localOut_2_0 = x1_int_localIn_2_0; // @[MixedNode.scala:542:17, :551:17]
wire intSinkNodeIn_0; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_1; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_2; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_3; // @[MixedNode.scala:551:17]
wire intSinkNodeIn_4; // @[MixedNode.scala:551:17]
assign masterNodeIn_a_ready = masterNodeOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_a_valid = masterNodeOut_a_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_opcode = masterNodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_param = masterNodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_size = masterNodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_source = masterNodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_address = masterNodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_mask = masterNodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign buffer_auto_in_a_bits_data = masterNodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_b_ready = masterNodeOut_b_ready; // @[Buffer.scala:40:9]
assign masterNodeIn_b_valid = masterNodeOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_opcode = masterNodeOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_param = masterNodeOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_size = masterNodeOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_source = masterNodeOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_address = masterNodeOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_mask = masterNodeOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_data = masterNodeOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_b_bits_corrupt = masterNodeOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_c_ready = masterNodeOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_c_valid = masterNodeOut_c_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_opcode = masterNodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_param = masterNodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_size = masterNodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_source = masterNodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_address = masterNodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign buffer_auto_in_c_bits_data = masterNodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign buffer_auto_in_d_ready = masterNodeOut_d_ready; // @[Buffer.scala:40:9]
assign masterNodeIn_d_valid = masterNodeOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_opcode = masterNodeOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_param = masterNodeOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_size = masterNodeOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_source = masterNodeOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_sink = masterNodeOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_denied = masterNodeOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_data = masterNodeOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_d_bits_corrupt = masterNodeOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeIn_e_ready = masterNodeOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign buffer_auto_in_e_valid = masterNodeOut_e_valid; // @[Buffer.scala:40:9]
assign buffer_auto_in_e_bits_sink = masterNodeOut_e_bits_sink; // @[Buffer.scala:40:9]
assign tlOtherMastersNodeOut_a_ready = masterNodeIn_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_valid = masterNodeIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_opcode = masterNodeIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_param = masterNodeIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_size = masterNodeIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_source = masterNodeIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_address = masterNodeIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_mask = masterNodeIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_a_bits_data = masterNodeIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_b_ready = masterNodeIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_valid = masterNodeIn_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_opcode = masterNodeIn_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_param = masterNodeIn_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_size = masterNodeIn_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_source = masterNodeIn_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_address = masterNodeIn_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_mask = masterNodeIn_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_data = masterNodeIn_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_b_bits_corrupt = masterNodeIn_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_c_ready = masterNodeIn_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_valid = masterNodeIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_opcode = masterNodeIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_param = masterNodeIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_size = masterNodeIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_source = masterNodeIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_address = masterNodeIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_c_bits_data = masterNodeIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_d_ready = masterNodeIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_valid = masterNodeIn_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_opcode = masterNodeIn_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_param = masterNodeIn_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_size = masterNodeIn_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_source = masterNodeIn_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_sink = masterNodeIn_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_denied = masterNodeIn_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_data = masterNodeIn_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_d_bits_corrupt = masterNodeIn_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOtherMastersNodeOut_e_ready = masterNodeIn_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_e_valid = masterNodeIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign masterNodeOut_e_bits_sink = masterNodeIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_a_ready = dCacheTapOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_valid = dCacheTapOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_opcode = dCacheTapOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_param = dCacheTapOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_size = dCacheTapOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_source = dCacheTapOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_address = dCacheTapOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_mask = dCacheTapOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_data = dCacheTapOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_b_bits_corrupt = dCacheTapOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_c_ready = dCacheTapOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_valid = dCacheTapOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_opcode = dCacheTapOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_param = dCacheTapOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_size = dCacheTapOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_source = dCacheTapOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_sink = dCacheTapOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_denied = dCacheTapOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_data = dCacheTapOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_d_bits_corrupt = dCacheTapOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapIn_e_ready = dCacheTapOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] dCacheTapOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] dCacheTapOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_a_bits_data; // @[MixedNode.scala:542:17]
wire dCacheTapOut_a_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_b_ready; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [2:0] dCacheTapOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] dCacheTapOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] dCacheTapOut_c_bits_data; // @[MixedNode.scala:542:17]
wire dCacheTapOut_c_valid; // @[MixedNode.scala:542:17]
wire dCacheTapOut_d_ready; // @[MixedNode.scala:542:17]
wire [3:0] dCacheTapOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire dCacheTapOut_e_valid; // @[MixedNode.scala:542:17]
assign widget_auto_anon_out_a_ready = dCacheTapIn_a_ready; // @[WidthWidget.scala:27:9]
assign dCacheTapOut_a_valid = dCacheTapIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_opcode = dCacheTapIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_param = dCacheTapIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_size = dCacheTapIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_source = dCacheTapIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_address = dCacheTapIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_mask = dCacheTapIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_a_bits_data = dCacheTapIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_b_ready = dCacheTapIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_b_valid = dCacheTapIn_b_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_opcode = dCacheTapIn_b_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_param = dCacheTapIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_size = dCacheTapIn_b_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_source = dCacheTapIn_b_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_address = dCacheTapIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_mask = dCacheTapIn_b_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_data = dCacheTapIn_b_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_bits_corrupt = dCacheTapIn_b_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_ready = dCacheTapIn_c_ready; // @[WidthWidget.scala:27:9]
assign dCacheTapOut_c_valid = dCacheTapIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_opcode = dCacheTapIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_param = dCacheTapIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_size = dCacheTapIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_source = dCacheTapIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_address = dCacheTapIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_c_bits_data = dCacheTapIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_d_ready = dCacheTapIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_d_valid = dCacheTapIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_opcode = dCacheTapIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_param = dCacheTapIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_size = dCacheTapIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_source = dCacheTapIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_sink = dCacheTapIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_denied = dCacheTapIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_data = dCacheTapIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_bits_corrupt = dCacheTapIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_e_ready = dCacheTapIn_e_ready; // @[WidthWidget.scala:27:9]
assign dCacheTapOut_e_valid = dCacheTapIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign dCacheTapOut_e_bits_sink = dCacheTapIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
TLXbar_MasterXbar_BoomTile_i2_o1_a32d128s4k4z4c tlMasterXbar ( // @[HierarchicalElement.scala:55:42]
.clock (clock),
.reset (reset),
.auto_anon_in_1_a_ready (widget_1_auto_anon_out_a_ready),
.auto_anon_in_1_a_valid (widget_1_auto_anon_out_a_valid), // @[WidthWidget.scala:27:9]
.auto_anon_in_1_a_bits_address (widget_1_auto_anon_out_a_bits_address), // @[WidthWidget.scala:27:9]
.auto_anon_in_1_d_valid (widget_1_auto_anon_out_d_valid),
.auto_anon_in_1_d_bits_opcode (widget_1_auto_anon_out_d_bits_opcode),
.auto_anon_in_1_d_bits_param (widget_1_auto_anon_out_d_bits_param),
.auto_anon_in_1_d_bits_size (widget_1_auto_anon_out_d_bits_size),
.auto_anon_in_1_d_bits_sink (widget_1_auto_anon_out_d_bits_sink),
.auto_anon_in_1_d_bits_denied (widget_1_auto_anon_out_d_bits_denied),
.auto_anon_in_1_d_bits_data (widget_1_auto_anon_out_d_bits_data),
.auto_anon_in_1_d_bits_corrupt (widget_1_auto_anon_out_d_bits_corrupt),
.auto_anon_in_0_a_ready (dCacheTapOut_a_ready),
.auto_anon_in_0_a_valid (dCacheTapOut_a_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_opcode (dCacheTapOut_a_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_param (dCacheTapOut_a_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_size (dCacheTapOut_a_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_source (dCacheTapOut_a_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_address (dCacheTapOut_a_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_mask (dCacheTapOut_a_bits_mask), // @[MixedNode.scala:542:17]
.auto_anon_in_0_a_bits_data (dCacheTapOut_a_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_0_b_ready (dCacheTapOut_b_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_0_b_valid (dCacheTapOut_b_valid),
.auto_anon_in_0_b_bits_opcode (dCacheTapOut_b_bits_opcode),
.auto_anon_in_0_b_bits_param (dCacheTapOut_b_bits_param),
.auto_anon_in_0_b_bits_size (dCacheTapOut_b_bits_size),
.auto_anon_in_0_b_bits_source (dCacheTapOut_b_bits_source),
.auto_anon_in_0_b_bits_address (dCacheTapOut_b_bits_address),
.auto_anon_in_0_b_bits_mask (dCacheTapOut_b_bits_mask),
.auto_anon_in_0_b_bits_data (dCacheTapOut_b_bits_data),
.auto_anon_in_0_b_bits_corrupt (dCacheTapOut_b_bits_corrupt),
.auto_anon_in_0_c_ready (dCacheTapOut_c_ready),
.auto_anon_in_0_c_valid (dCacheTapOut_c_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_opcode (dCacheTapOut_c_bits_opcode), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_param (dCacheTapOut_c_bits_param), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_size (dCacheTapOut_c_bits_size), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_source (dCacheTapOut_c_bits_source), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_address (dCacheTapOut_c_bits_address), // @[MixedNode.scala:542:17]
.auto_anon_in_0_c_bits_data (dCacheTapOut_c_bits_data), // @[MixedNode.scala:542:17]
.auto_anon_in_0_d_ready (dCacheTapOut_d_ready), // @[MixedNode.scala:542:17]
.auto_anon_in_0_d_valid (dCacheTapOut_d_valid),
.auto_anon_in_0_d_bits_opcode (dCacheTapOut_d_bits_opcode),
.auto_anon_in_0_d_bits_param (dCacheTapOut_d_bits_param),
.auto_anon_in_0_d_bits_size (dCacheTapOut_d_bits_size),
.auto_anon_in_0_d_bits_source (dCacheTapOut_d_bits_source),
.auto_anon_in_0_d_bits_sink (dCacheTapOut_d_bits_sink),
.auto_anon_in_0_d_bits_denied (dCacheTapOut_d_bits_denied),
.auto_anon_in_0_d_bits_data (dCacheTapOut_d_bits_data),
.auto_anon_in_0_d_bits_corrupt (dCacheTapOut_d_bits_corrupt),
.auto_anon_in_0_e_ready (dCacheTapOut_e_ready),
.auto_anon_in_0_e_valid (dCacheTapOut_e_valid), // @[MixedNode.scala:542:17]
.auto_anon_in_0_e_bits_sink (dCacheTapOut_e_bits_sink), // @[MixedNode.scala:542:17]
.auto_anon_out_a_ready (tlOtherMastersNodeIn_a_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_a_valid (tlOtherMastersNodeIn_a_valid),
.auto_anon_out_a_bits_opcode (tlOtherMastersNodeIn_a_bits_opcode),
.auto_anon_out_a_bits_param (tlOtherMastersNodeIn_a_bits_param),
.auto_anon_out_a_bits_size (tlOtherMastersNodeIn_a_bits_size),
.auto_anon_out_a_bits_source (tlOtherMastersNodeIn_a_bits_source),
.auto_anon_out_a_bits_address (tlOtherMastersNodeIn_a_bits_address),
.auto_anon_out_a_bits_mask (tlOtherMastersNodeIn_a_bits_mask),
.auto_anon_out_a_bits_data (tlOtherMastersNodeIn_a_bits_data),
.auto_anon_out_b_ready (tlOtherMastersNodeIn_b_ready),
.auto_anon_out_b_valid (tlOtherMastersNodeIn_b_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_opcode (tlOtherMastersNodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_param (tlOtherMastersNodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_size (tlOtherMastersNodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_source (tlOtherMastersNodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_address (tlOtherMastersNodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_mask (tlOtherMastersNodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_data (tlOtherMastersNodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_b_bits_corrupt (tlOtherMastersNodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_anon_out_c_ready (tlOtherMastersNodeIn_c_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_c_valid (tlOtherMastersNodeIn_c_valid),
.auto_anon_out_c_bits_opcode (tlOtherMastersNodeIn_c_bits_opcode),
.auto_anon_out_c_bits_param (tlOtherMastersNodeIn_c_bits_param),
.auto_anon_out_c_bits_size (tlOtherMastersNodeIn_c_bits_size),
.auto_anon_out_c_bits_source (tlOtherMastersNodeIn_c_bits_source),
.auto_anon_out_c_bits_address (tlOtherMastersNodeIn_c_bits_address),
.auto_anon_out_c_bits_data (tlOtherMastersNodeIn_c_bits_data),
.auto_anon_out_d_ready (tlOtherMastersNodeIn_d_ready),
.auto_anon_out_d_valid (tlOtherMastersNodeIn_d_valid), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_opcode (tlOtherMastersNodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_param (tlOtherMastersNodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_size (tlOtherMastersNodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_source (tlOtherMastersNodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_sink (tlOtherMastersNodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_denied (tlOtherMastersNodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_data (tlOtherMastersNodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_anon_out_d_bits_corrupt (tlOtherMastersNodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.auto_anon_out_e_ready (tlOtherMastersNodeIn_e_ready), // @[MixedNode.scala:551:17]
.auto_anon_out_e_valid (tlOtherMastersNodeIn_e_valid),
.auto_anon_out_e_bits_sink (tlOtherMastersNodeIn_e_bits_sink)
); // @[HierarchicalElement.scala:55:42]
TLXbar_SlaveXbar_BoomTile_i0_o0_a1d8s1k1z1u tlSlaveXbar ( // @[HierarchicalElement.scala:56:41]
.clock (clock),
.reset (reset)
); // @[HierarchicalElement.scala:56:41]
IntXbar_i4_o1_2 intXbar ( // @[HierarchicalElement.scala:57:37]
.auto_anon_in_3_0 (x1_int_localOut_2_0), // @[MixedNode.scala:542:17]
.auto_anon_in_2_0 (x1_int_localOut_1_0), // @[MixedNode.scala:542:17]
.auto_anon_in_1_0 (x1_int_localOut_0), // @[MixedNode.scala:542:17]
.auto_anon_in_1_1 (x1_int_localOut_1), // @[MixedNode.scala:542:17]
.auto_anon_in_0_0 (int_localOut_0), // @[MixedNode.scala:542:17]
.auto_anon_out_0 (intSinkNodeIn_0),
.auto_anon_out_1 (intSinkNodeIn_1),
.auto_anon_out_2 (intSinkNodeIn_2),
.auto_anon_out_3 (intSinkNodeIn_3),
.auto_anon_out_4 (intSinkNodeIn_4)
); // @[HierarchicalElement.scala:57:37]
BoomNonBlockingDCache dcache ( // @[tile.scala:132:54]
.clock (clock),
.reset (reset),
.auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_out_a_valid (widget_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (widget_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (widget_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (widget_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (widget_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (widget_auto_anon_in_a_bits_data),
.auto_out_b_ready (widget_auto_anon_in_b_ready),
.auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9]
.auto_out_c_valid (widget_auto_anon_in_c_valid),
.auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode),
.auto_out_c_bits_param (widget_auto_anon_in_c_bits_param),
.auto_out_c_bits_size (widget_auto_anon_in_c_bits_size),
.auto_out_c_bits_source (widget_auto_anon_in_c_bits_source),
.auto_out_c_bits_address (widget_auto_anon_in_c_bits_address),
.auto_out_c_bits_data (widget_auto_anon_in_c_bits_data),
.auto_out_d_ready (widget_auto_anon_in_d_ready),
.auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9]
.auto_out_e_valid (widget_auto_anon_in_e_valid),
.auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink),
.io_lsu_req_ready (_dcache_io_lsu_req_ready),
.io_lsu_req_valid (_lsu_io_dmem_req_valid), // @[tile.scala:160:20]
.io_lsu_req_bits_0_valid (_lsu_io_dmem_req_bits_0_valid), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_uopc (_lsu_io_dmem_req_bits_0_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_inst (_lsu_io_dmem_req_bits_0_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_inst (_lsu_io_dmem_req_bits_0_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_rvc (_lsu_io_dmem_req_bits_0_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_pc (_lsu_io_dmem_req_bits_0_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iq_type (_lsu_io_dmem_req_bits_0_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_fu_code (_lsu_io_dmem_req_bits_0_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_br_type (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_op1_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_op2_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_imm_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_op_fcn (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_fcn_dw (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_csr_cmd (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_is_load (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_is_sta (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ctrl_is_std (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iw_state (_lsu_io_dmem_req_bits_0_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iw_p1_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_iw_p2_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_br (_lsu_io_dmem_req_bits_0_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_jalr (_lsu_io_dmem_req_bits_0_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_jal (_lsu_io_dmem_req_bits_0_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_sfb (_lsu_io_dmem_req_bits_0_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_br_mask (_lsu_io_dmem_req_bits_0_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_br_tag (_lsu_io_dmem_req_bits_0_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ftq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_edge_inst (_lsu_io_dmem_req_bits_0_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_pc_lob (_lsu_io_dmem_req_bits_0_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_taken (_lsu_io_dmem_req_bits_0_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_imm_packed (_lsu_io_dmem_req_bits_0_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_csr_addr (_lsu_io_dmem_req_bits_0_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_rob_idx (_lsu_io_dmem_req_bits_0_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_stq_idx (_lsu_io_dmem_req_bits_0_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_rxq_idx (_lsu_io_dmem_req_bits_0_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_pdst (_lsu_io_dmem_req_bits_0_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs1 (_lsu_io_dmem_req_bits_0_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs2 (_lsu_io_dmem_req_bits_0_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs3 (_lsu_io_dmem_req_bits_0_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ppred (_lsu_io_dmem_req_bits_0_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs1_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs2_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_prs3_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ppred_busy (_lsu_io_dmem_req_bits_0_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_stale_pdst (_lsu_io_dmem_req_bits_0_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_exception (_lsu_io_dmem_req_bits_0_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_exc_cause (_lsu_io_dmem_req_bits_0_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_bypassable (_lsu_io_dmem_req_bits_0_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_mem_cmd (_lsu_io_dmem_req_bits_0_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_mem_size (_lsu_io_dmem_req_bits_0_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_mem_signed (_lsu_io_dmem_req_bits_0_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_fence (_lsu_io_dmem_req_bits_0_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_fencei (_lsu_io_dmem_req_bits_0_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_amo (_lsu_io_dmem_req_bits_0_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_uses_ldq (_lsu_io_dmem_req_bits_0_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_uses_stq (_lsu_io_dmem_req_bits_0_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_sys_pc2epc (_lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_is_unique (_lsu_io_dmem_req_bits_0_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_flush_on_commit (_lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldst_is_rs1 (_lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldst (_lsu_io_dmem_req_bits_0_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs1 (_lsu_io_dmem_req_bits_0_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs2 (_lsu_io_dmem_req_bits_0_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs3 (_lsu_io_dmem_req_bits_0_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_ldst_val (_lsu_io_dmem_req_bits_0_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_dst_rtype (_lsu_io_dmem_req_bits_0_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs1_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_lrs2_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_frs3_en (_lsu_io_dmem_req_bits_0_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_fp_val (_lsu_io_dmem_req_bits_0_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_fp_single (_lsu_io_dmem_req_bits_0_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_xcpt_pf_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_xcpt_ae_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_xcpt_ma_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_bp_debug_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_bp_xcpt_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_fsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_uop_debug_tsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_addr (_lsu_io_dmem_req_bits_0_bits_addr), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_data (_lsu_io_dmem_req_bits_0_bits_data), // @[tile.scala:160:20]
.io_lsu_req_bits_0_bits_is_hella (_lsu_io_dmem_req_bits_0_bits_is_hella), // @[tile.scala:160:20]
.io_lsu_s1_kill_0 (_lsu_io_dmem_s1_kill_0), // @[tile.scala:160:20]
.io_lsu_resp_0_valid (_dcache_io_lsu_resp_0_valid),
.io_lsu_resp_0_bits_uop_uopc (_dcache_io_lsu_resp_0_bits_uop_uopc),
.io_lsu_resp_0_bits_uop_inst (_dcache_io_lsu_resp_0_bits_uop_inst),
.io_lsu_resp_0_bits_uop_debug_inst (_dcache_io_lsu_resp_0_bits_uop_debug_inst),
.io_lsu_resp_0_bits_uop_is_rvc (_dcache_io_lsu_resp_0_bits_uop_is_rvc),
.io_lsu_resp_0_bits_uop_debug_pc (_dcache_io_lsu_resp_0_bits_uop_debug_pc),
.io_lsu_resp_0_bits_uop_iq_type (_dcache_io_lsu_resp_0_bits_uop_iq_type),
.io_lsu_resp_0_bits_uop_fu_code (_dcache_io_lsu_resp_0_bits_uop_fu_code),
.io_lsu_resp_0_bits_uop_ctrl_br_type (_dcache_io_lsu_resp_0_bits_uop_ctrl_br_type),
.io_lsu_resp_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel),
.io_lsu_resp_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel),
.io_lsu_resp_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel),
.io_lsu_resp_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn),
.io_lsu_resp_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw),
.io_lsu_resp_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd),
.io_lsu_resp_0_bits_uop_ctrl_is_load (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_load),
.io_lsu_resp_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta),
.io_lsu_resp_0_bits_uop_ctrl_is_std (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_std),
.io_lsu_resp_0_bits_uop_iw_state (_dcache_io_lsu_resp_0_bits_uop_iw_state),
.io_lsu_resp_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned),
.io_lsu_resp_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned),
.io_lsu_resp_0_bits_uop_is_br (_dcache_io_lsu_resp_0_bits_uop_is_br),
.io_lsu_resp_0_bits_uop_is_jalr (_dcache_io_lsu_resp_0_bits_uop_is_jalr),
.io_lsu_resp_0_bits_uop_is_jal (_dcache_io_lsu_resp_0_bits_uop_is_jal),
.io_lsu_resp_0_bits_uop_is_sfb (_dcache_io_lsu_resp_0_bits_uop_is_sfb),
.io_lsu_resp_0_bits_uop_br_mask (_dcache_io_lsu_resp_0_bits_uop_br_mask),
.io_lsu_resp_0_bits_uop_br_tag (_dcache_io_lsu_resp_0_bits_uop_br_tag),
.io_lsu_resp_0_bits_uop_ftq_idx (_dcache_io_lsu_resp_0_bits_uop_ftq_idx),
.io_lsu_resp_0_bits_uop_edge_inst (_dcache_io_lsu_resp_0_bits_uop_edge_inst),
.io_lsu_resp_0_bits_uop_pc_lob (_dcache_io_lsu_resp_0_bits_uop_pc_lob),
.io_lsu_resp_0_bits_uop_taken (_dcache_io_lsu_resp_0_bits_uop_taken),
.io_lsu_resp_0_bits_uop_imm_packed (_dcache_io_lsu_resp_0_bits_uop_imm_packed),
.io_lsu_resp_0_bits_uop_csr_addr (_dcache_io_lsu_resp_0_bits_uop_csr_addr),
.io_lsu_resp_0_bits_uop_rob_idx (_dcache_io_lsu_resp_0_bits_uop_rob_idx),
.io_lsu_resp_0_bits_uop_ldq_idx (_dcache_io_lsu_resp_0_bits_uop_ldq_idx),
.io_lsu_resp_0_bits_uop_stq_idx (_dcache_io_lsu_resp_0_bits_uop_stq_idx),
.io_lsu_resp_0_bits_uop_rxq_idx (_dcache_io_lsu_resp_0_bits_uop_rxq_idx),
.io_lsu_resp_0_bits_uop_pdst (_dcache_io_lsu_resp_0_bits_uop_pdst),
.io_lsu_resp_0_bits_uop_prs1 (_dcache_io_lsu_resp_0_bits_uop_prs1),
.io_lsu_resp_0_bits_uop_prs2 (_dcache_io_lsu_resp_0_bits_uop_prs2),
.io_lsu_resp_0_bits_uop_prs3 (_dcache_io_lsu_resp_0_bits_uop_prs3),
.io_lsu_resp_0_bits_uop_ppred (_dcache_io_lsu_resp_0_bits_uop_ppred),
.io_lsu_resp_0_bits_uop_prs1_busy (_dcache_io_lsu_resp_0_bits_uop_prs1_busy),
.io_lsu_resp_0_bits_uop_prs2_busy (_dcache_io_lsu_resp_0_bits_uop_prs2_busy),
.io_lsu_resp_0_bits_uop_prs3_busy (_dcache_io_lsu_resp_0_bits_uop_prs3_busy),
.io_lsu_resp_0_bits_uop_ppred_busy (_dcache_io_lsu_resp_0_bits_uop_ppred_busy),
.io_lsu_resp_0_bits_uop_stale_pdst (_dcache_io_lsu_resp_0_bits_uop_stale_pdst),
.io_lsu_resp_0_bits_uop_exception (_dcache_io_lsu_resp_0_bits_uop_exception),
.io_lsu_resp_0_bits_uop_exc_cause (_dcache_io_lsu_resp_0_bits_uop_exc_cause),
.io_lsu_resp_0_bits_uop_bypassable (_dcache_io_lsu_resp_0_bits_uop_bypassable),
.io_lsu_resp_0_bits_uop_mem_cmd (_dcache_io_lsu_resp_0_bits_uop_mem_cmd),
.io_lsu_resp_0_bits_uop_mem_size (_dcache_io_lsu_resp_0_bits_uop_mem_size),
.io_lsu_resp_0_bits_uop_mem_signed (_dcache_io_lsu_resp_0_bits_uop_mem_signed),
.io_lsu_resp_0_bits_uop_is_fence (_dcache_io_lsu_resp_0_bits_uop_is_fence),
.io_lsu_resp_0_bits_uop_is_fencei (_dcache_io_lsu_resp_0_bits_uop_is_fencei),
.io_lsu_resp_0_bits_uop_is_amo (_dcache_io_lsu_resp_0_bits_uop_is_amo),
.io_lsu_resp_0_bits_uop_uses_ldq (_dcache_io_lsu_resp_0_bits_uop_uses_ldq),
.io_lsu_resp_0_bits_uop_uses_stq (_dcache_io_lsu_resp_0_bits_uop_uses_stq),
.io_lsu_resp_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc),
.io_lsu_resp_0_bits_uop_is_unique (_dcache_io_lsu_resp_0_bits_uop_is_unique),
.io_lsu_resp_0_bits_uop_flush_on_commit (_dcache_io_lsu_resp_0_bits_uop_flush_on_commit),
.io_lsu_resp_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1),
.io_lsu_resp_0_bits_uop_ldst (_dcache_io_lsu_resp_0_bits_uop_ldst),
.io_lsu_resp_0_bits_uop_lrs1 (_dcache_io_lsu_resp_0_bits_uop_lrs1),
.io_lsu_resp_0_bits_uop_lrs2 (_dcache_io_lsu_resp_0_bits_uop_lrs2),
.io_lsu_resp_0_bits_uop_lrs3 (_dcache_io_lsu_resp_0_bits_uop_lrs3),
.io_lsu_resp_0_bits_uop_ldst_val (_dcache_io_lsu_resp_0_bits_uop_ldst_val),
.io_lsu_resp_0_bits_uop_dst_rtype (_dcache_io_lsu_resp_0_bits_uop_dst_rtype),
.io_lsu_resp_0_bits_uop_lrs1_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs1_rtype),
.io_lsu_resp_0_bits_uop_lrs2_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs2_rtype),
.io_lsu_resp_0_bits_uop_frs3_en (_dcache_io_lsu_resp_0_bits_uop_frs3_en),
.io_lsu_resp_0_bits_uop_fp_val (_dcache_io_lsu_resp_0_bits_uop_fp_val),
.io_lsu_resp_0_bits_uop_fp_single (_dcache_io_lsu_resp_0_bits_uop_fp_single),
.io_lsu_resp_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if),
.io_lsu_resp_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if),
.io_lsu_resp_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if),
.io_lsu_resp_0_bits_uop_bp_debug_if (_dcache_io_lsu_resp_0_bits_uop_bp_debug_if),
.io_lsu_resp_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if),
.io_lsu_resp_0_bits_uop_debug_fsrc (_dcache_io_lsu_resp_0_bits_uop_debug_fsrc),
.io_lsu_resp_0_bits_uop_debug_tsrc (_dcache_io_lsu_resp_0_bits_uop_debug_tsrc),
.io_lsu_resp_0_bits_data (_dcache_io_lsu_resp_0_bits_data),
.io_lsu_resp_0_bits_is_hella (_dcache_io_lsu_resp_0_bits_is_hella),
.io_lsu_nack_0_valid (_dcache_io_lsu_nack_0_valid),
.io_lsu_nack_0_bits_uop_uopc (_dcache_io_lsu_nack_0_bits_uop_uopc),
.io_lsu_nack_0_bits_uop_inst (_dcache_io_lsu_nack_0_bits_uop_inst),
.io_lsu_nack_0_bits_uop_debug_inst (_dcache_io_lsu_nack_0_bits_uop_debug_inst),
.io_lsu_nack_0_bits_uop_is_rvc (_dcache_io_lsu_nack_0_bits_uop_is_rvc),
.io_lsu_nack_0_bits_uop_debug_pc (_dcache_io_lsu_nack_0_bits_uop_debug_pc),
.io_lsu_nack_0_bits_uop_iq_type (_dcache_io_lsu_nack_0_bits_uop_iq_type),
.io_lsu_nack_0_bits_uop_fu_code (_dcache_io_lsu_nack_0_bits_uop_fu_code),
.io_lsu_nack_0_bits_uop_ctrl_br_type (_dcache_io_lsu_nack_0_bits_uop_ctrl_br_type),
.io_lsu_nack_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel),
.io_lsu_nack_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel),
.io_lsu_nack_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel),
.io_lsu_nack_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn),
.io_lsu_nack_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw),
.io_lsu_nack_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd),
.io_lsu_nack_0_bits_uop_ctrl_is_load (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_load),
.io_lsu_nack_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta),
.io_lsu_nack_0_bits_uop_ctrl_is_std (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_std),
.io_lsu_nack_0_bits_uop_iw_state (_dcache_io_lsu_nack_0_bits_uop_iw_state),
.io_lsu_nack_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned),
.io_lsu_nack_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned),
.io_lsu_nack_0_bits_uop_is_br (_dcache_io_lsu_nack_0_bits_uop_is_br),
.io_lsu_nack_0_bits_uop_is_jalr (_dcache_io_lsu_nack_0_bits_uop_is_jalr),
.io_lsu_nack_0_bits_uop_is_jal (_dcache_io_lsu_nack_0_bits_uop_is_jal),
.io_lsu_nack_0_bits_uop_is_sfb (_dcache_io_lsu_nack_0_bits_uop_is_sfb),
.io_lsu_nack_0_bits_uop_br_mask (_dcache_io_lsu_nack_0_bits_uop_br_mask),
.io_lsu_nack_0_bits_uop_br_tag (_dcache_io_lsu_nack_0_bits_uop_br_tag),
.io_lsu_nack_0_bits_uop_ftq_idx (_dcache_io_lsu_nack_0_bits_uop_ftq_idx),
.io_lsu_nack_0_bits_uop_edge_inst (_dcache_io_lsu_nack_0_bits_uop_edge_inst),
.io_lsu_nack_0_bits_uop_pc_lob (_dcache_io_lsu_nack_0_bits_uop_pc_lob),
.io_lsu_nack_0_bits_uop_taken (_dcache_io_lsu_nack_0_bits_uop_taken),
.io_lsu_nack_0_bits_uop_imm_packed (_dcache_io_lsu_nack_0_bits_uop_imm_packed),
.io_lsu_nack_0_bits_uop_csr_addr (_dcache_io_lsu_nack_0_bits_uop_csr_addr),
.io_lsu_nack_0_bits_uop_rob_idx (_dcache_io_lsu_nack_0_bits_uop_rob_idx),
.io_lsu_nack_0_bits_uop_ldq_idx (_dcache_io_lsu_nack_0_bits_uop_ldq_idx),
.io_lsu_nack_0_bits_uop_stq_idx (_dcache_io_lsu_nack_0_bits_uop_stq_idx),
.io_lsu_nack_0_bits_uop_rxq_idx (_dcache_io_lsu_nack_0_bits_uop_rxq_idx),
.io_lsu_nack_0_bits_uop_pdst (_dcache_io_lsu_nack_0_bits_uop_pdst),
.io_lsu_nack_0_bits_uop_prs1 (_dcache_io_lsu_nack_0_bits_uop_prs1),
.io_lsu_nack_0_bits_uop_prs2 (_dcache_io_lsu_nack_0_bits_uop_prs2),
.io_lsu_nack_0_bits_uop_prs3 (_dcache_io_lsu_nack_0_bits_uop_prs3),
.io_lsu_nack_0_bits_uop_ppred (_dcache_io_lsu_nack_0_bits_uop_ppred),
.io_lsu_nack_0_bits_uop_prs1_busy (_dcache_io_lsu_nack_0_bits_uop_prs1_busy),
.io_lsu_nack_0_bits_uop_prs2_busy (_dcache_io_lsu_nack_0_bits_uop_prs2_busy),
.io_lsu_nack_0_bits_uop_prs3_busy (_dcache_io_lsu_nack_0_bits_uop_prs3_busy),
.io_lsu_nack_0_bits_uop_ppred_busy (_dcache_io_lsu_nack_0_bits_uop_ppred_busy),
.io_lsu_nack_0_bits_uop_stale_pdst (_dcache_io_lsu_nack_0_bits_uop_stale_pdst),
.io_lsu_nack_0_bits_uop_exception (_dcache_io_lsu_nack_0_bits_uop_exception),
.io_lsu_nack_0_bits_uop_exc_cause (_dcache_io_lsu_nack_0_bits_uop_exc_cause),
.io_lsu_nack_0_bits_uop_bypassable (_dcache_io_lsu_nack_0_bits_uop_bypassable),
.io_lsu_nack_0_bits_uop_mem_cmd (_dcache_io_lsu_nack_0_bits_uop_mem_cmd),
.io_lsu_nack_0_bits_uop_mem_size (_dcache_io_lsu_nack_0_bits_uop_mem_size),
.io_lsu_nack_0_bits_uop_mem_signed (_dcache_io_lsu_nack_0_bits_uop_mem_signed),
.io_lsu_nack_0_bits_uop_is_fence (_dcache_io_lsu_nack_0_bits_uop_is_fence),
.io_lsu_nack_0_bits_uop_is_fencei (_dcache_io_lsu_nack_0_bits_uop_is_fencei),
.io_lsu_nack_0_bits_uop_is_amo (_dcache_io_lsu_nack_0_bits_uop_is_amo),
.io_lsu_nack_0_bits_uop_uses_ldq (_dcache_io_lsu_nack_0_bits_uop_uses_ldq),
.io_lsu_nack_0_bits_uop_uses_stq (_dcache_io_lsu_nack_0_bits_uop_uses_stq),
.io_lsu_nack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc),
.io_lsu_nack_0_bits_uop_is_unique (_dcache_io_lsu_nack_0_bits_uop_is_unique),
.io_lsu_nack_0_bits_uop_flush_on_commit (_dcache_io_lsu_nack_0_bits_uop_flush_on_commit),
.io_lsu_nack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1),
.io_lsu_nack_0_bits_uop_ldst (_dcache_io_lsu_nack_0_bits_uop_ldst),
.io_lsu_nack_0_bits_uop_lrs1 (_dcache_io_lsu_nack_0_bits_uop_lrs1),
.io_lsu_nack_0_bits_uop_lrs2 (_dcache_io_lsu_nack_0_bits_uop_lrs2),
.io_lsu_nack_0_bits_uop_lrs3 (_dcache_io_lsu_nack_0_bits_uop_lrs3),
.io_lsu_nack_0_bits_uop_ldst_val (_dcache_io_lsu_nack_0_bits_uop_ldst_val),
.io_lsu_nack_0_bits_uop_dst_rtype (_dcache_io_lsu_nack_0_bits_uop_dst_rtype),
.io_lsu_nack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs1_rtype),
.io_lsu_nack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs2_rtype),
.io_lsu_nack_0_bits_uop_frs3_en (_dcache_io_lsu_nack_0_bits_uop_frs3_en),
.io_lsu_nack_0_bits_uop_fp_val (_dcache_io_lsu_nack_0_bits_uop_fp_val),
.io_lsu_nack_0_bits_uop_fp_single (_dcache_io_lsu_nack_0_bits_uop_fp_single),
.io_lsu_nack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if),
.io_lsu_nack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if),
.io_lsu_nack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if),
.io_lsu_nack_0_bits_uop_bp_debug_if (_dcache_io_lsu_nack_0_bits_uop_bp_debug_if),
.io_lsu_nack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if),
.io_lsu_nack_0_bits_uop_debug_fsrc (_dcache_io_lsu_nack_0_bits_uop_debug_fsrc),
.io_lsu_nack_0_bits_uop_debug_tsrc (_dcache_io_lsu_nack_0_bits_uop_debug_tsrc),
.io_lsu_nack_0_bits_addr (_dcache_io_lsu_nack_0_bits_addr),
.io_lsu_nack_0_bits_data (_dcache_io_lsu_nack_0_bits_data),
.io_lsu_nack_0_bits_is_hella (_dcache_io_lsu_nack_0_bits_is_hella),
.io_lsu_brupdate_b1_resolve_mask (_lsu_io_dmem_brupdate_b1_resolve_mask), // @[tile.scala:160:20]
.io_lsu_brupdate_b1_mispredict_mask (_lsu_io_dmem_brupdate_b1_mispredict_mask), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_uopc (_lsu_io_dmem_brupdate_b2_uop_uopc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_inst (_lsu_io_dmem_brupdate_b2_uop_inst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_inst (_lsu_io_dmem_brupdate_b2_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_rvc (_lsu_io_dmem_brupdate_b2_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_pc (_lsu_io_dmem_brupdate_b2_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iq_type (_lsu_io_dmem_brupdate_b2_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_fu_code (_lsu_io_dmem_brupdate_b2_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_br_type (_lsu_io_dmem_brupdate_b2_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_op1_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_op2_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_imm_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_op_fcn (_lsu_io_dmem_brupdate_b2_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_fcn_dw (_lsu_io_dmem_brupdate_b2_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_csr_cmd (_lsu_io_dmem_brupdate_b2_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_is_load (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_is_sta (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ctrl_is_std (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iw_state (_lsu_io_dmem_brupdate_b2_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iw_p1_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_iw_p2_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_br (_lsu_io_dmem_brupdate_b2_uop_is_br), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_jalr (_lsu_io_dmem_brupdate_b2_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_jal (_lsu_io_dmem_brupdate_b2_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_sfb (_lsu_io_dmem_brupdate_b2_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_br_mask (_lsu_io_dmem_brupdate_b2_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_br_tag (_lsu_io_dmem_brupdate_b2_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ftq_idx (_lsu_io_dmem_brupdate_b2_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_edge_inst (_lsu_io_dmem_brupdate_b2_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_pc_lob (_lsu_io_dmem_brupdate_b2_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_taken (_lsu_io_dmem_brupdate_b2_uop_taken), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_imm_packed (_lsu_io_dmem_brupdate_b2_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_csr_addr (_lsu_io_dmem_brupdate_b2_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_rob_idx (_lsu_io_dmem_brupdate_b2_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldq_idx (_lsu_io_dmem_brupdate_b2_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_stq_idx (_lsu_io_dmem_brupdate_b2_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_rxq_idx (_lsu_io_dmem_brupdate_b2_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_pdst (_lsu_io_dmem_brupdate_b2_uop_pdst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs1 (_lsu_io_dmem_brupdate_b2_uop_prs1), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs2 (_lsu_io_dmem_brupdate_b2_uop_prs2), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs3 (_lsu_io_dmem_brupdate_b2_uop_prs3), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ppred (_lsu_io_dmem_brupdate_b2_uop_ppred), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs1_busy (_lsu_io_dmem_brupdate_b2_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs2_busy (_lsu_io_dmem_brupdate_b2_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_prs3_busy (_lsu_io_dmem_brupdate_b2_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ppred_busy (_lsu_io_dmem_brupdate_b2_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_stale_pdst (_lsu_io_dmem_brupdate_b2_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_exception (_lsu_io_dmem_brupdate_b2_uop_exception), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_exc_cause (_lsu_io_dmem_brupdate_b2_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_bypassable (_lsu_io_dmem_brupdate_b2_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_mem_cmd (_lsu_io_dmem_brupdate_b2_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_mem_size (_lsu_io_dmem_brupdate_b2_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_mem_signed (_lsu_io_dmem_brupdate_b2_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_fence (_lsu_io_dmem_brupdate_b2_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_fencei (_lsu_io_dmem_brupdate_b2_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_amo (_lsu_io_dmem_brupdate_b2_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_uses_ldq (_lsu_io_dmem_brupdate_b2_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_uses_stq (_lsu_io_dmem_brupdate_b2_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_sys_pc2epc (_lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_is_unique (_lsu_io_dmem_brupdate_b2_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_flush_on_commit (_lsu_io_dmem_brupdate_b2_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldst_is_rs1 (_lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldst (_lsu_io_dmem_brupdate_b2_uop_ldst), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs1 (_lsu_io_dmem_brupdate_b2_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs2 (_lsu_io_dmem_brupdate_b2_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs3 (_lsu_io_dmem_brupdate_b2_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_ldst_val (_lsu_io_dmem_brupdate_b2_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_dst_rtype (_lsu_io_dmem_brupdate_b2_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs1_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_lrs2_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_frs3_en (_lsu_io_dmem_brupdate_b2_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_fp_val (_lsu_io_dmem_brupdate_b2_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_fp_single (_lsu_io_dmem_brupdate_b2_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_xcpt_pf_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_xcpt_ae_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_xcpt_ma_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_bp_debug_if (_lsu_io_dmem_brupdate_b2_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_bp_xcpt_if (_lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_fsrc (_lsu_io_dmem_brupdate_b2_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_uop_debug_tsrc (_lsu_io_dmem_brupdate_b2_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_valid (_lsu_io_dmem_brupdate_b2_valid), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_mispredict (_lsu_io_dmem_brupdate_b2_mispredict), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_taken (_lsu_io_dmem_brupdate_b2_taken), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_cfi_type (_lsu_io_dmem_brupdate_b2_cfi_type), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_pc_sel (_lsu_io_dmem_brupdate_b2_pc_sel), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_jalr_target (_lsu_io_dmem_brupdate_b2_jalr_target), // @[tile.scala:160:20]
.io_lsu_brupdate_b2_target_offset (_lsu_io_dmem_brupdate_b2_target_offset), // @[tile.scala:160:20]
.io_lsu_exception (_lsu_io_dmem_exception), // @[tile.scala:160:20]
.io_lsu_rob_pnr_idx (_lsu_io_dmem_rob_pnr_idx), // @[tile.scala:160:20]
.io_lsu_rob_head_idx (_lsu_io_dmem_rob_head_idx), // @[tile.scala:160:20]
.io_lsu_release_ready (_lsu_io_dmem_release_ready), // @[tile.scala:160:20]
.io_lsu_release_valid (_dcache_io_lsu_release_valid),
.io_lsu_release_bits_opcode (_dcache_io_lsu_release_bits_opcode),
.io_lsu_release_bits_param (_dcache_io_lsu_release_bits_param),
.io_lsu_release_bits_size (_dcache_io_lsu_release_bits_size),
.io_lsu_release_bits_source (_dcache_io_lsu_release_bits_source),
.io_lsu_release_bits_address (_dcache_io_lsu_release_bits_address),
.io_lsu_release_bits_data (_dcache_io_lsu_release_bits_data),
.io_lsu_force_order (_lsu_io_dmem_force_order), // @[tile.scala:160:20]
.io_lsu_ordered (_dcache_io_lsu_ordered),
.io_lsu_perf_acquire (_dcache_io_lsu_perf_acquire),
.io_lsu_perf_release (_dcache_io_lsu_perf_release)
); // @[tile.scala:132:54]
BoomFrontend frontend ( // @[tile.scala:138:28]
.clock (clock),
.reset (reset),
.auto_icache_master_out_a_ready (widget_1_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_a_valid (widget_1_auto_anon_in_a_valid),
.auto_icache_master_out_a_bits_address (widget_1_auto_anon_in_a_bits_address),
.auto_icache_master_out_d_valid (widget_1_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_opcode (widget_1_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_param (widget_1_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_size (widget_1_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_sink (widget_1_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_denied (widget_1_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_data (widget_1_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_icache_master_out_d_bits_corrupt (widget_1_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.io_cpu_fetchpacket_ready (_core_io_ifu_fetchpacket_ready), // @[tile.scala:159:20]
.io_cpu_fetchpacket_valid (_frontend_io_cpu_fetchpacket_valid),
.io_cpu_fetchpacket_bits_uops_0_valid (_frontend_io_cpu_fetchpacket_bits_uops_0_valid),
.io_cpu_fetchpacket_bits_uops_0_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst),
.io_cpu_fetchpacket_bits_uops_0_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst),
.io_cpu_fetchpacket_bits_uops_0_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc),
.io_cpu_fetchpacket_bits_uops_0_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc),
.io_cpu_fetchpacket_bits_uops_0_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb),
.io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx),
.io_cpu_fetchpacket_bits_uops_0_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst),
.io_cpu_fetchpacket_bits_uops_0_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob),
.io_cpu_fetchpacket_bits_uops_0_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken),
.io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if),
.io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if),
.io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if),
.io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if),
.io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc),
.io_cpu_fetchpacket_bits_uops_1_valid (_frontend_io_cpu_fetchpacket_bits_uops_1_valid),
.io_cpu_fetchpacket_bits_uops_1_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst),
.io_cpu_fetchpacket_bits_uops_1_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst),
.io_cpu_fetchpacket_bits_uops_1_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc),
.io_cpu_fetchpacket_bits_uops_1_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc),
.io_cpu_fetchpacket_bits_uops_1_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb),
.io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx),
.io_cpu_fetchpacket_bits_uops_1_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst),
.io_cpu_fetchpacket_bits_uops_1_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob),
.io_cpu_fetchpacket_bits_uops_1_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken),
.io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if),
.io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if),
.io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if),
.io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if),
.io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc),
.io_cpu_fetchpacket_bits_uops_2_valid (_frontend_io_cpu_fetchpacket_bits_uops_2_valid),
.io_cpu_fetchpacket_bits_uops_2_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_inst),
.io_cpu_fetchpacket_bits_uops_2_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_inst),
.io_cpu_fetchpacket_bits_uops_2_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_rvc),
.io_cpu_fetchpacket_bits_uops_2_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_pc),
.io_cpu_fetchpacket_bits_uops_2_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_sfb),
.io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx),
.io_cpu_fetchpacket_bits_uops_2_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_edge_inst),
.io_cpu_fetchpacket_bits_uops_2_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_pc_lob),
.io_cpu_fetchpacket_bits_uops_2_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_taken),
.io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if),
.io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if),
.io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if),
.io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if),
.io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc),
.io_cpu_get_pc_0_ftq_idx (_core_io_ifu_get_pc_0_ftq_idx), // @[tile.scala:159:20]
.io_cpu_get_pc_0_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_0_entry_cfi_idx_valid),
.io_cpu_get_pc_0_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_0_entry_cfi_idx_bits),
.io_cpu_get_pc_0_entry_cfi_taken (_frontend_io_cpu_get_pc_0_entry_cfi_taken),
.io_cpu_get_pc_0_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_0_entry_cfi_mispredicted),
.io_cpu_get_pc_0_entry_cfi_type (_frontend_io_cpu_get_pc_0_entry_cfi_type),
.io_cpu_get_pc_0_entry_br_mask (_frontend_io_cpu_get_pc_0_entry_br_mask),
.io_cpu_get_pc_0_entry_cfi_is_call (_frontend_io_cpu_get_pc_0_entry_cfi_is_call),
.io_cpu_get_pc_0_entry_cfi_is_ret (_frontend_io_cpu_get_pc_0_entry_cfi_is_ret),
.io_cpu_get_pc_0_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_0_entry_cfi_npc_plus4),
.io_cpu_get_pc_0_entry_ras_top (_frontend_io_cpu_get_pc_0_entry_ras_top),
.io_cpu_get_pc_0_entry_ras_idx (_frontend_io_cpu_get_pc_0_entry_ras_idx),
.io_cpu_get_pc_0_entry_start_bank (_frontend_io_cpu_get_pc_0_entry_start_bank),
.io_cpu_get_pc_0_pc (_frontend_io_cpu_get_pc_0_pc),
.io_cpu_get_pc_0_com_pc (_frontend_io_cpu_get_pc_0_com_pc),
.io_cpu_get_pc_0_next_val (_frontend_io_cpu_get_pc_0_next_val),
.io_cpu_get_pc_0_next_pc (_frontend_io_cpu_get_pc_0_next_pc),
.io_cpu_get_pc_1_ftq_idx (_core_io_ifu_get_pc_1_ftq_idx), // @[tile.scala:159:20]
.io_cpu_get_pc_1_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_1_entry_cfi_idx_valid),
.io_cpu_get_pc_1_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_1_entry_cfi_idx_bits),
.io_cpu_get_pc_1_entry_cfi_taken (_frontend_io_cpu_get_pc_1_entry_cfi_taken),
.io_cpu_get_pc_1_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_1_entry_cfi_mispredicted),
.io_cpu_get_pc_1_entry_cfi_type (_frontend_io_cpu_get_pc_1_entry_cfi_type),
.io_cpu_get_pc_1_entry_br_mask (_frontend_io_cpu_get_pc_1_entry_br_mask),
.io_cpu_get_pc_1_entry_cfi_is_call (_frontend_io_cpu_get_pc_1_entry_cfi_is_call),
.io_cpu_get_pc_1_entry_cfi_is_ret (_frontend_io_cpu_get_pc_1_entry_cfi_is_ret),
.io_cpu_get_pc_1_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_1_entry_cfi_npc_plus4),
.io_cpu_get_pc_1_entry_ras_top (_frontend_io_cpu_get_pc_1_entry_ras_top),
.io_cpu_get_pc_1_entry_ras_idx (_frontend_io_cpu_get_pc_1_entry_ras_idx),
.io_cpu_get_pc_1_entry_start_bank (_frontend_io_cpu_get_pc_1_entry_start_bank),
.io_cpu_get_pc_1_ghist_old_history (_frontend_io_cpu_get_pc_1_ghist_old_history),
.io_cpu_get_pc_1_ghist_current_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_current_saw_branch_not_taken),
.io_cpu_get_pc_1_ghist_new_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_not_taken),
.io_cpu_get_pc_1_ghist_new_saw_branch_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_taken),
.io_cpu_get_pc_1_ghist_ras_idx (_frontend_io_cpu_get_pc_1_ghist_ras_idx),
.io_cpu_get_pc_1_pc (_frontend_io_cpu_get_pc_1_pc),
.io_cpu_get_pc_1_com_pc (_frontend_io_cpu_get_pc_1_com_pc),
.io_cpu_get_pc_1_next_val (_frontend_io_cpu_get_pc_1_next_val),
.io_cpu_get_pc_1_next_pc (_frontend_io_cpu_get_pc_1_next_pc),
.io_cpu_debug_fetch_pc_0 (_frontend_io_cpu_debug_fetch_pc_0),
.io_cpu_debug_fetch_pc_1 (_frontend_io_cpu_debug_fetch_pc_1),
.io_cpu_debug_fetch_pc_2 (_frontend_io_cpu_debug_fetch_pc_2),
.io_cpu_status_debug (_core_io_ifu_status_debug), // @[tile.scala:159:20]
.io_cpu_status_cease (_core_io_ifu_status_cease), // @[tile.scala:159:20]
.io_cpu_status_wfi (_core_io_ifu_status_wfi), // @[tile.scala:159:20]
.io_cpu_status_dprv (_core_io_ifu_status_dprv), // @[tile.scala:159:20]
.io_cpu_status_dv (_core_io_ifu_status_dv), // @[tile.scala:159:20]
.io_cpu_status_prv (_core_io_ifu_status_prv), // @[tile.scala:159:20]
.io_cpu_status_v (_core_io_ifu_status_v), // @[tile.scala:159:20]
.io_cpu_status_sd (_core_io_ifu_status_sd), // @[tile.scala:159:20]
.io_cpu_status_mpv (_core_io_ifu_status_mpv), // @[tile.scala:159:20]
.io_cpu_status_gva (_core_io_ifu_status_gva), // @[tile.scala:159:20]
.io_cpu_status_tsr (_core_io_ifu_status_tsr), // @[tile.scala:159:20]
.io_cpu_status_tw (_core_io_ifu_status_tw), // @[tile.scala:159:20]
.io_cpu_status_tvm (_core_io_ifu_status_tvm), // @[tile.scala:159:20]
.io_cpu_status_mxr (_core_io_ifu_status_mxr), // @[tile.scala:159:20]
.io_cpu_status_sum (_core_io_ifu_status_sum), // @[tile.scala:159:20]
.io_cpu_status_mprv (_core_io_ifu_status_mprv), // @[tile.scala:159:20]
.io_cpu_status_fs (_core_io_ifu_status_fs), // @[tile.scala:159:20]
.io_cpu_status_mpp (_core_io_ifu_status_mpp), // @[tile.scala:159:20]
.io_cpu_status_spp (_core_io_ifu_status_spp), // @[tile.scala:159:20]
.io_cpu_status_mpie (_core_io_ifu_status_mpie), // @[tile.scala:159:20]
.io_cpu_status_spie (_core_io_ifu_status_spie), // @[tile.scala:159:20]
.io_cpu_status_mie (_core_io_ifu_status_mie), // @[tile.scala:159:20]
.io_cpu_status_sie (_core_io_ifu_status_sie), // @[tile.scala:159:20]
.io_cpu_sfence_valid (_core_io_ifu_sfence_valid), // @[tile.scala:159:20]
.io_cpu_sfence_bits_rs1 (_core_io_ifu_sfence_bits_rs1), // @[tile.scala:159:20]
.io_cpu_sfence_bits_rs2 (_core_io_ifu_sfence_bits_rs2), // @[tile.scala:159:20]
.io_cpu_sfence_bits_addr (_core_io_ifu_sfence_bits_addr), // @[tile.scala:159:20]
.io_cpu_sfence_bits_asid (_core_io_ifu_sfence_bits_asid), // @[tile.scala:159:20]
.io_cpu_brupdate_b1_resolve_mask (_core_io_ifu_brupdate_b1_resolve_mask), // @[tile.scala:159:20]
.io_cpu_brupdate_b1_mispredict_mask (_core_io_ifu_brupdate_b1_mispredict_mask), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_uopc (_core_io_ifu_brupdate_b2_uop_uopc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_inst (_core_io_ifu_brupdate_b2_uop_inst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_inst (_core_io_ifu_brupdate_b2_uop_debug_inst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_rvc (_core_io_ifu_brupdate_b2_uop_is_rvc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_pc (_core_io_ifu_brupdate_b2_uop_debug_pc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iq_type (_core_io_ifu_brupdate_b2_uop_iq_type), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_fu_code (_core_io_ifu_brupdate_b2_uop_fu_code), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_br_type (_core_io_ifu_brupdate_b2_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_op1_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_op2_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_imm_sel (_core_io_ifu_brupdate_b2_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_op_fcn (_core_io_ifu_brupdate_b2_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_fcn_dw (_core_io_ifu_brupdate_b2_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_csr_cmd (_core_io_ifu_brupdate_b2_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_is_load (_core_io_ifu_brupdate_b2_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_is_sta (_core_io_ifu_brupdate_b2_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ctrl_is_std (_core_io_ifu_brupdate_b2_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iw_state (_core_io_ifu_brupdate_b2_uop_iw_state), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iw_p1_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_iw_p2_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_br (_core_io_ifu_brupdate_b2_uop_is_br), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_jalr (_core_io_ifu_brupdate_b2_uop_is_jalr), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_jal (_core_io_ifu_brupdate_b2_uop_is_jal), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_sfb (_core_io_ifu_brupdate_b2_uop_is_sfb), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_br_mask (_core_io_ifu_brupdate_b2_uop_br_mask), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_br_tag (_core_io_ifu_brupdate_b2_uop_br_tag), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ftq_idx (_core_io_ifu_brupdate_b2_uop_ftq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_edge_inst (_core_io_ifu_brupdate_b2_uop_edge_inst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_pc_lob (_core_io_ifu_brupdate_b2_uop_pc_lob), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_taken (_core_io_ifu_brupdate_b2_uop_taken), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_imm_packed (_core_io_ifu_brupdate_b2_uop_imm_packed), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_csr_addr (_core_io_ifu_brupdate_b2_uop_csr_addr), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_rob_idx (_core_io_ifu_brupdate_b2_uop_rob_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldq_idx (_core_io_ifu_brupdate_b2_uop_ldq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_stq_idx (_core_io_ifu_brupdate_b2_uop_stq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_rxq_idx (_core_io_ifu_brupdate_b2_uop_rxq_idx), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_pdst (_core_io_ifu_brupdate_b2_uop_pdst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs1 (_core_io_ifu_brupdate_b2_uop_prs1), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs2 (_core_io_ifu_brupdate_b2_uop_prs2), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs3 (_core_io_ifu_brupdate_b2_uop_prs3), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ppred (_core_io_ifu_brupdate_b2_uop_ppred), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs1_busy (_core_io_ifu_brupdate_b2_uop_prs1_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs2_busy (_core_io_ifu_brupdate_b2_uop_prs2_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_prs3_busy (_core_io_ifu_brupdate_b2_uop_prs3_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ppred_busy (_core_io_ifu_brupdate_b2_uop_ppred_busy), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_stale_pdst (_core_io_ifu_brupdate_b2_uop_stale_pdst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_exception (_core_io_ifu_brupdate_b2_uop_exception), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_exc_cause (_core_io_ifu_brupdate_b2_uop_exc_cause), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_bypassable (_core_io_ifu_brupdate_b2_uop_bypassable), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_mem_cmd (_core_io_ifu_brupdate_b2_uop_mem_cmd), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_mem_size (_core_io_ifu_brupdate_b2_uop_mem_size), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_mem_signed (_core_io_ifu_brupdate_b2_uop_mem_signed), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_fence (_core_io_ifu_brupdate_b2_uop_is_fence), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_fencei (_core_io_ifu_brupdate_b2_uop_is_fencei), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_amo (_core_io_ifu_brupdate_b2_uop_is_amo), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_uses_ldq (_core_io_ifu_brupdate_b2_uop_uses_ldq), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_uses_stq (_core_io_ifu_brupdate_b2_uop_uses_stq), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_sys_pc2epc (_core_io_ifu_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_is_unique (_core_io_ifu_brupdate_b2_uop_is_unique), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_flush_on_commit (_core_io_ifu_brupdate_b2_uop_flush_on_commit), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldst_is_rs1 (_core_io_ifu_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldst (_core_io_ifu_brupdate_b2_uop_ldst), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs1 (_core_io_ifu_brupdate_b2_uop_lrs1), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs2 (_core_io_ifu_brupdate_b2_uop_lrs2), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs3 (_core_io_ifu_brupdate_b2_uop_lrs3), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_ldst_val (_core_io_ifu_brupdate_b2_uop_ldst_val), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_dst_rtype (_core_io_ifu_brupdate_b2_uop_dst_rtype), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs1_rtype (_core_io_ifu_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_lrs2_rtype (_core_io_ifu_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_frs3_en (_core_io_ifu_brupdate_b2_uop_frs3_en), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_fp_val (_core_io_ifu_brupdate_b2_uop_fp_val), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_fp_single (_core_io_ifu_brupdate_b2_uop_fp_single), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_xcpt_pf_if (_core_io_ifu_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_xcpt_ae_if (_core_io_ifu_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_xcpt_ma_if (_core_io_ifu_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_bp_debug_if (_core_io_ifu_brupdate_b2_uop_bp_debug_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_bp_xcpt_if (_core_io_ifu_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_fsrc (_core_io_ifu_brupdate_b2_uop_debug_fsrc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_uop_debug_tsrc (_core_io_ifu_brupdate_b2_uop_debug_tsrc), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_valid (_core_io_ifu_brupdate_b2_valid), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_mispredict (_core_io_ifu_brupdate_b2_mispredict), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_taken (_core_io_ifu_brupdate_b2_taken), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_cfi_type (_core_io_ifu_brupdate_b2_cfi_type), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_pc_sel (_core_io_ifu_brupdate_b2_pc_sel), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_jalr_target (_core_io_ifu_brupdate_b2_jalr_target), // @[tile.scala:159:20]
.io_cpu_brupdate_b2_target_offset (_core_io_ifu_brupdate_b2_target_offset), // @[tile.scala:159:20]
.io_cpu_redirect_flush (_core_io_ifu_redirect_flush), // @[tile.scala:159:20]
.io_cpu_redirect_val (_core_io_ifu_redirect_val), // @[tile.scala:159:20]
.io_cpu_redirect_pc (_core_io_ifu_redirect_pc), // @[tile.scala:159:20]
.io_cpu_redirect_ftq_idx (_core_io_ifu_redirect_ftq_idx), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_old_history (_core_io_ifu_redirect_ghist_old_history), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_current_saw_branch_not_taken (_core_io_ifu_redirect_ghist_current_saw_branch_not_taken), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_new_saw_branch_not_taken (_core_io_ifu_redirect_ghist_new_saw_branch_not_taken), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_new_saw_branch_taken (_core_io_ifu_redirect_ghist_new_saw_branch_taken), // @[tile.scala:159:20]
.io_cpu_redirect_ghist_ras_idx (_core_io_ifu_redirect_ghist_ras_idx), // @[tile.scala:159:20]
.io_cpu_commit_valid (_core_io_ifu_commit_valid), // @[tile.scala:159:20]
.io_cpu_commit_bits (_core_io_ifu_commit_bits), // @[tile.scala:159:20]
.io_cpu_flush_icache (_core_io_ifu_flush_icache), // @[tile.scala:159:20]
.io_cpu_perf_acquire (_frontend_io_cpu_perf_acquire),
.io_cpu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss),
.io_ptw_req_ready (_ptw_io_requestor_1_req_ready), // @[tile.scala:237:20]
.io_ptw_req_valid (_frontend_io_ptw_req_valid),
.io_ptw_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr),
.io_ptw_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa),
.io_ptw_resp_valid (_ptw_io_requestor_1_resp_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final), // @[tile.scala:237:20]
.io_ptw_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf), // @[tile.scala:237:20]
.io_ptw_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf), // @[tile.scala:237:20]
.io_ptw_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr), // @[tile.scala:237:20]
.io_ptw_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw), // @[tile.scala:237:20]
.io_ptw_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v), // @[tile.scala:237:20]
.io_ptw_resp_bits_level (_ptw_io_requestor_1_resp_bits_level), // @[tile.scala:237:20]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte), // @[tile.scala:237:20]
.io_ptw_ptbr_mode (_ptw_io_requestor_1_ptbr_mode), // @[tile.scala:237:20]
.io_ptw_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn), // @[tile.scala:237:20]
.io_ptw_status_debug (_ptw_io_requestor_1_status_debug), // @[tile.scala:237:20]
.io_ptw_status_cease (_ptw_io_requestor_1_status_cease), // @[tile.scala:237:20]
.io_ptw_status_wfi (_ptw_io_requestor_1_status_wfi), // @[tile.scala:237:20]
.io_ptw_status_dprv (_ptw_io_requestor_1_status_dprv), // @[tile.scala:237:20]
.io_ptw_status_dv (_ptw_io_requestor_1_status_dv), // @[tile.scala:237:20]
.io_ptw_status_prv (_ptw_io_requestor_1_status_prv), // @[tile.scala:237:20]
.io_ptw_status_v (_ptw_io_requestor_1_status_v), // @[tile.scala:237:20]
.io_ptw_status_sd (_ptw_io_requestor_1_status_sd), // @[tile.scala:237:20]
.io_ptw_status_mpv (_ptw_io_requestor_1_status_mpv), // @[tile.scala:237:20]
.io_ptw_status_gva (_ptw_io_requestor_1_status_gva), // @[tile.scala:237:20]
.io_ptw_status_tsr (_ptw_io_requestor_1_status_tsr), // @[tile.scala:237:20]
.io_ptw_status_tw (_ptw_io_requestor_1_status_tw), // @[tile.scala:237:20]
.io_ptw_status_tvm (_ptw_io_requestor_1_status_tvm), // @[tile.scala:237:20]
.io_ptw_status_mxr (_ptw_io_requestor_1_status_mxr), // @[tile.scala:237:20]
.io_ptw_status_sum (_ptw_io_requestor_1_status_sum), // @[tile.scala:237:20]
.io_ptw_status_mprv (_ptw_io_requestor_1_status_mprv), // @[tile.scala:237:20]
.io_ptw_status_fs (_ptw_io_requestor_1_status_fs), // @[tile.scala:237:20]
.io_ptw_status_mpp (_ptw_io_requestor_1_status_mpp), // @[tile.scala:237:20]
.io_ptw_status_spp (_ptw_io_requestor_1_status_spp), // @[tile.scala:237:20]
.io_ptw_status_mpie (_ptw_io_requestor_1_status_mpie), // @[tile.scala:237:20]
.io_ptw_status_spie (_ptw_io_requestor_1_status_spie), // @[tile.scala:237:20]
.io_ptw_status_mie (_ptw_io_requestor_1_status_mie), // @[tile.scala:237:20]
.io_ptw_status_sie (_ptw_io_requestor_1_status_sie), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr), // @[tile.scala:237:20]
.io_ptw_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr), // @[tile.scala:237:20]
.io_ptw_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr), // @[tile.scala:237:20]
.io_ptw_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr), // @[tile.scala:237:20]
.io_ptw_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr), // @[tile.scala:237:20]
.io_ptw_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr), // @[tile.scala:237:20]
.io_ptw_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr), // @[tile.scala:237:20]
.io_ptw_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr), // @[tile.scala:237:20]
.io_ptw_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask) // @[tile.scala:237:20]
); // @[tile.scala:138:28]
BoomCore core ( // @[tile.scala:159:20]
.clock (clock),
.reset (reset),
.io_hartid (hartIdSinkNodeIn), // @[MixedNode.scala:551:17]
.io_interrupts_debug (intSinkNodeIn_0), // @[MixedNode.scala:551:17]
.io_interrupts_mtip (intSinkNodeIn_2), // @[MixedNode.scala:551:17]
.io_interrupts_msip (intSinkNodeIn_1), // @[MixedNode.scala:551:17]
.io_interrupts_meip (intSinkNodeIn_3), // @[MixedNode.scala:551:17]
.io_interrupts_seip (intSinkNodeIn_4), // @[MixedNode.scala:551:17]
.io_ifu_fetchpacket_ready (_core_io_ifu_fetchpacket_ready),
.io_ifu_fetchpacket_valid (_frontend_io_cpu_fetchpacket_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_valid (_frontend_io_cpu_fetchpacket_bits_uops_0_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_rvc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_pc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_is_sfb), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_ftq_idx), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_edge_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_pc_lob), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_taken), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_pf_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_xcpt_ae_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_debug_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_bp_xcpt_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_0_bits_debug_fsrc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_valid (_frontend_io_cpu_fetchpacket_bits_uops_1_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_rvc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_pc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_is_sfb), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_ftq_idx), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_edge_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_pc_lob), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_taken), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_pf_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_xcpt_ae_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_debug_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_bp_xcpt_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_1_bits_debug_fsrc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_valid (_frontend_io_cpu_fetchpacket_bits_uops_2_valid), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_debug_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_is_rvc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_rvc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_debug_pc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_pc), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_is_sfb (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_is_sfb), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_ftq_idx (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_ftq_idx), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_edge_inst (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_edge_inst), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_pc_lob (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_pc_lob), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_taken (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_taken), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_xcpt_pf_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_pf_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_xcpt_ae_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_xcpt_ae_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_bp_debug_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_debug_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_bp_xcpt_if (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_bp_xcpt_if), // @[tile.scala:138:28]
.io_ifu_fetchpacket_bits_uops_2_bits_debug_fsrc (_frontend_io_cpu_fetchpacket_bits_uops_2_bits_debug_fsrc), // @[tile.scala:138:28]
.io_ifu_get_pc_0_ftq_idx (_core_io_ifu_get_pc_0_ftq_idx),
.io_ifu_get_pc_0_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_0_entry_cfi_idx_valid), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_0_entry_cfi_idx_bits), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_taken (_frontend_io_cpu_get_pc_0_entry_cfi_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_0_entry_cfi_mispredicted), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_type (_frontend_io_cpu_get_pc_0_entry_cfi_type), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_br_mask (_frontend_io_cpu_get_pc_0_entry_br_mask), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_is_call (_frontend_io_cpu_get_pc_0_entry_cfi_is_call), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_is_ret (_frontend_io_cpu_get_pc_0_entry_cfi_is_ret), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_0_entry_cfi_npc_plus4), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_ras_top (_frontend_io_cpu_get_pc_0_entry_ras_top), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_ras_idx (_frontend_io_cpu_get_pc_0_entry_ras_idx), // @[tile.scala:138:28]
.io_ifu_get_pc_0_entry_start_bank (_frontend_io_cpu_get_pc_0_entry_start_bank), // @[tile.scala:138:28]
.io_ifu_get_pc_0_pc (_frontend_io_cpu_get_pc_0_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_0_com_pc (_frontend_io_cpu_get_pc_0_com_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_0_next_val (_frontend_io_cpu_get_pc_0_next_val), // @[tile.scala:138:28]
.io_ifu_get_pc_0_next_pc (_frontend_io_cpu_get_pc_0_next_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ftq_idx (_core_io_ifu_get_pc_1_ftq_idx),
.io_ifu_get_pc_1_entry_cfi_idx_valid (_frontend_io_cpu_get_pc_1_entry_cfi_idx_valid), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_idx_bits (_frontend_io_cpu_get_pc_1_entry_cfi_idx_bits), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_taken (_frontend_io_cpu_get_pc_1_entry_cfi_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_mispredicted (_frontend_io_cpu_get_pc_1_entry_cfi_mispredicted), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_type (_frontend_io_cpu_get_pc_1_entry_cfi_type), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_br_mask (_frontend_io_cpu_get_pc_1_entry_br_mask), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_is_call (_frontend_io_cpu_get_pc_1_entry_cfi_is_call), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_is_ret (_frontend_io_cpu_get_pc_1_entry_cfi_is_ret), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_cfi_npc_plus4 (_frontend_io_cpu_get_pc_1_entry_cfi_npc_plus4), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_ras_top (_frontend_io_cpu_get_pc_1_entry_ras_top), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_ras_idx (_frontend_io_cpu_get_pc_1_entry_ras_idx), // @[tile.scala:138:28]
.io_ifu_get_pc_1_entry_start_bank (_frontend_io_cpu_get_pc_1_entry_start_bank), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_old_history (_frontend_io_cpu_get_pc_1_ghist_old_history), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_current_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_current_saw_branch_not_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_new_saw_branch_not_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_not_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_new_saw_branch_taken (_frontend_io_cpu_get_pc_1_ghist_new_saw_branch_taken), // @[tile.scala:138:28]
.io_ifu_get_pc_1_ghist_ras_idx (_frontend_io_cpu_get_pc_1_ghist_ras_idx), // @[tile.scala:138:28]
.io_ifu_get_pc_1_pc (_frontend_io_cpu_get_pc_1_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_1_com_pc (_frontend_io_cpu_get_pc_1_com_pc), // @[tile.scala:138:28]
.io_ifu_get_pc_1_next_val (_frontend_io_cpu_get_pc_1_next_val), // @[tile.scala:138:28]
.io_ifu_get_pc_1_next_pc (_frontend_io_cpu_get_pc_1_next_pc), // @[tile.scala:138:28]
.io_ifu_debug_fetch_pc_0 (_frontend_io_cpu_debug_fetch_pc_0), // @[tile.scala:138:28]
.io_ifu_debug_fetch_pc_1 (_frontend_io_cpu_debug_fetch_pc_1), // @[tile.scala:138:28]
.io_ifu_debug_fetch_pc_2 (_frontend_io_cpu_debug_fetch_pc_2), // @[tile.scala:138:28]
.io_ifu_status_debug (_core_io_ifu_status_debug),
.io_ifu_status_cease (_core_io_ifu_status_cease),
.io_ifu_status_wfi (_core_io_ifu_status_wfi),
.io_ifu_status_dprv (_core_io_ifu_status_dprv),
.io_ifu_status_dv (_core_io_ifu_status_dv),
.io_ifu_status_prv (_core_io_ifu_status_prv),
.io_ifu_status_v (_core_io_ifu_status_v),
.io_ifu_status_sd (_core_io_ifu_status_sd),
.io_ifu_status_mpv (_core_io_ifu_status_mpv),
.io_ifu_status_gva (_core_io_ifu_status_gva),
.io_ifu_status_tsr (_core_io_ifu_status_tsr),
.io_ifu_status_tw (_core_io_ifu_status_tw),
.io_ifu_status_tvm (_core_io_ifu_status_tvm),
.io_ifu_status_mxr (_core_io_ifu_status_mxr),
.io_ifu_status_sum (_core_io_ifu_status_sum),
.io_ifu_status_mprv (_core_io_ifu_status_mprv),
.io_ifu_status_fs (_core_io_ifu_status_fs),
.io_ifu_status_mpp (_core_io_ifu_status_mpp),
.io_ifu_status_spp (_core_io_ifu_status_spp),
.io_ifu_status_mpie (_core_io_ifu_status_mpie),
.io_ifu_status_spie (_core_io_ifu_status_spie),
.io_ifu_status_mie (_core_io_ifu_status_mie),
.io_ifu_status_sie (_core_io_ifu_status_sie),
.io_ifu_sfence_valid (_core_io_ifu_sfence_valid),
.io_ifu_sfence_bits_rs1 (_core_io_ifu_sfence_bits_rs1),
.io_ifu_sfence_bits_rs2 (_core_io_ifu_sfence_bits_rs2),
.io_ifu_sfence_bits_addr (_core_io_ifu_sfence_bits_addr),
.io_ifu_sfence_bits_asid (_core_io_ifu_sfence_bits_asid),
.io_ifu_brupdate_b1_resolve_mask (_core_io_ifu_brupdate_b1_resolve_mask),
.io_ifu_brupdate_b1_mispredict_mask (_core_io_ifu_brupdate_b1_mispredict_mask),
.io_ifu_brupdate_b2_uop_uopc (_core_io_ifu_brupdate_b2_uop_uopc),
.io_ifu_brupdate_b2_uop_inst (_core_io_ifu_brupdate_b2_uop_inst),
.io_ifu_brupdate_b2_uop_debug_inst (_core_io_ifu_brupdate_b2_uop_debug_inst),
.io_ifu_brupdate_b2_uop_is_rvc (_core_io_ifu_brupdate_b2_uop_is_rvc),
.io_ifu_brupdate_b2_uop_debug_pc (_core_io_ifu_brupdate_b2_uop_debug_pc),
.io_ifu_brupdate_b2_uop_iq_type (_core_io_ifu_brupdate_b2_uop_iq_type),
.io_ifu_brupdate_b2_uop_fu_code (_core_io_ifu_brupdate_b2_uop_fu_code),
.io_ifu_brupdate_b2_uop_ctrl_br_type (_core_io_ifu_brupdate_b2_uop_ctrl_br_type),
.io_ifu_brupdate_b2_uop_ctrl_op1_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op1_sel),
.io_ifu_brupdate_b2_uop_ctrl_op2_sel (_core_io_ifu_brupdate_b2_uop_ctrl_op2_sel),
.io_ifu_brupdate_b2_uop_ctrl_imm_sel (_core_io_ifu_brupdate_b2_uop_ctrl_imm_sel),
.io_ifu_brupdate_b2_uop_ctrl_op_fcn (_core_io_ifu_brupdate_b2_uop_ctrl_op_fcn),
.io_ifu_brupdate_b2_uop_ctrl_fcn_dw (_core_io_ifu_brupdate_b2_uop_ctrl_fcn_dw),
.io_ifu_brupdate_b2_uop_ctrl_csr_cmd (_core_io_ifu_brupdate_b2_uop_ctrl_csr_cmd),
.io_ifu_brupdate_b2_uop_ctrl_is_load (_core_io_ifu_brupdate_b2_uop_ctrl_is_load),
.io_ifu_brupdate_b2_uop_ctrl_is_sta (_core_io_ifu_brupdate_b2_uop_ctrl_is_sta),
.io_ifu_brupdate_b2_uop_ctrl_is_std (_core_io_ifu_brupdate_b2_uop_ctrl_is_std),
.io_ifu_brupdate_b2_uop_iw_state (_core_io_ifu_brupdate_b2_uop_iw_state),
.io_ifu_brupdate_b2_uop_iw_p1_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p1_poisoned),
.io_ifu_brupdate_b2_uop_iw_p2_poisoned (_core_io_ifu_brupdate_b2_uop_iw_p2_poisoned),
.io_ifu_brupdate_b2_uop_is_br (_core_io_ifu_brupdate_b2_uop_is_br),
.io_ifu_brupdate_b2_uop_is_jalr (_core_io_ifu_brupdate_b2_uop_is_jalr),
.io_ifu_brupdate_b2_uop_is_jal (_core_io_ifu_brupdate_b2_uop_is_jal),
.io_ifu_brupdate_b2_uop_is_sfb (_core_io_ifu_brupdate_b2_uop_is_sfb),
.io_ifu_brupdate_b2_uop_br_mask (_core_io_ifu_brupdate_b2_uop_br_mask),
.io_ifu_brupdate_b2_uop_br_tag (_core_io_ifu_brupdate_b2_uop_br_tag),
.io_ifu_brupdate_b2_uop_ftq_idx (_core_io_ifu_brupdate_b2_uop_ftq_idx),
.io_ifu_brupdate_b2_uop_edge_inst (_core_io_ifu_brupdate_b2_uop_edge_inst),
.io_ifu_brupdate_b2_uop_pc_lob (_core_io_ifu_brupdate_b2_uop_pc_lob),
.io_ifu_brupdate_b2_uop_taken (_core_io_ifu_brupdate_b2_uop_taken),
.io_ifu_brupdate_b2_uop_imm_packed (_core_io_ifu_brupdate_b2_uop_imm_packed),
.io_ifu_brupdate_b2_uop_csr_addr (_core_io_ifu_brupdate_b2_uop_csr_addr),
.io_ifu_brupdate_b2_uop_rob_idx (_core_io_ifu_brupdate_b2_uop_rob_idx),
.io_ifu_brupdate_b2_uop_ldq_idx (_core_io_ifu_brupdate_b2_uop_ldq_idx),
.io_ifu_brupdate_b2_uop_stq_idx (_core_io_ifu_brupdate_b2_uop_stq_idx),
.io_ifu_brupdate_b2_uop_rxq_idx (_core_io_ifu_brupdate_b2_uop_rxq_idx),
.io_ifu_brupdate_b2_uop_pdst (_core_io_ifu_brupdate_b2_uop_pdst),
.io_ifu_brupdate_b2_uop_prs1 (_core_io_ifu_brupdate_b2_uop_prs1),
.io_ifu_brupdate_b2_uop_prs2 (_core_io_ifu_brupdate_b2_uop_prs2),
.io_ifu_brupdate_b2_uop_prs3 (_core_io_ifu_brupdate_b2_uop_prs3),
.io_ifu_brupdate_b2_uop_ppred (_core_io_ifu_brupdate_b2_uop_ppred),
.io_ifu_brupdate_b2_uop_prs1_busy (_core_io_ifu_brupdate_b2_uop_prs1_busy),
.io_ifu_brupdate_b2_uop_prs2_busy (_core_io_ifu_brupdate_b2_uop_prs2_busy),
.io_ifu_brupdate_b2_uop_prs3_busy (_core_io_ifu_brupdate_b2_uop_prs3_busy),
.io_ifu_brupdate_b2_uop_ppred_busy (_core_io_ifu_brupdate_b2_uop_ppred_busy),
.io_ifu_brupdate_b2_uop_stale_pdst (_core_io_ifu_brupdate_b2_uop_stale_pdst),
.io_ifu_brupdate_b2_uop_exception (_core_io_ifu_brupdate_b2_uop_exception),
.io_ifu_brupdate_b2_uop_exc_cause (_core_io_ifu_brupdate_b2_uop_exc_cause),
.io_ifu_brupdate_b2_uop_bypassable (_core_io_ifu_brupdate_b2_uop_bypassable),
.io_ifu_brupdate_b2_uop_mem_cmd (_core_io_ifu_brupdate_b2_uop_mem_cmd),
.io_ifu_brupdate_b2_uop_mem_size (_core_io_ifu_brupdate_b2_uop_mem_size),
.io_ifu_brupdate_b2_uop_mem_signed (_core_io_ifu_brupdate_b2_uop_mem_signed),
.io_ifu_brupdate_b2_uop_is_fence (_core_io_ifu_brupdate_b2_uop_is_fence),
.io_ifu_brupdate_b2_uop_is_fencei (_core_io_ifu_brupdate_b2_uop_is_fencei),
.io_ifu_brupdate_b2_uop_is_amo (_core_io_ifu_brupdate_b2_uop_is_amo),
.io_ifu_brupdate_b2_uop_uses_ldq (_core_io_ifu_brupdate_b2_uop_uses_ldq),
.io_ifu_brupdate_b2_uop_uses_stq (_core_io_ifu_brupdate_b2_uop_uses_stq),
.io_ifu_brupdate_b2_uop_is_sys_pc2epc (_core_io_ifu_brupdate_b2_uop_is_sys_pc2epc),
.io_ifu_brupdate_b2_uop_is_unique (_core_io_ifu_brupdate_b2_uop_is_unique),
.io_ifu_brupdate_b2_uop_flush_on_commit (_core_io_ifu_brupdate_b2_uop_flush_on_commit),
.io_ifu_brupdate_b2_uop_ldst_is_rs1 (_core_io_ifu_brupdate_b2_uop_ldst_is_rs1),
.io_ifu_brupdate_b2_uop_ldst (_core_io_ifu_brupdate_b2_uop_ldst),
.io_ifu_brupdate_b2_uop_lrs1 (_core_io_ifu_brupdate_b2_uop_lrs1),
.io_ifu_brupdate_b2_uop_lrs2 (_core_io_ifu_brupdate_b2_uop_lrs2),
.io_ifu_brupdate_b2_uop_lrs3 (_core_io_ifu_brupdate_b2_uop_lrs3),
.io_ifu_brupdate_b2_uop_ldst_val (_core_io_ifu_brupdate_b2_uop_ldst_val),
.io_ifu_brupdate_b2_uop_dst_rtype (_core_io_ifu_brupdate_b2_uop_dst_rtype),
.io_ifu_brupdate_b2_uop_lrs1_rtype (_core_io_ifu_brupdate_b2_uop_lrs1_rtype),
.io_ifu_brupdate_b2_uop_lrs2_rtype (_core_io_ifu_brupdate_b2_uop_lrs2_rtype),
.io_ifu_brupdate_b2_uop_frs3_en (_core_io_ifu_brupdate_b2_uop_frs3_en),
.io_ifu_brupdate_b2_uop_fp_val (_core_io_ifu_brupdate_b2_uop_fp_val),
.io_ifu_brupdate_b2_uop_fp_single (_core_io_ifu_brupdate_b2_uop_fp_single),
.io_ifu_brupdate_b2_uop_xcpt_pf_if (_core_io_ifu_brupdate_b2_uop_xcpt_pf_if),
.io_ifu_brupdate_b2_uop_xcpt_ae_if (_core_io_ifu_brupdate_b2_uop_xcpt_ae_if),
.io_ifu_brupdate_b2_uop_xcpt_ma_if (_core_io_ifu_brupdate_b2_uop_xcpt_ma_if),
.io_ifu_brupdate_b2_uop_bp_debug_if (_core_io_ifu_brupdate_b2_uop_bp_debug_if),
.io_ifu_brupdate_b2_uop_bp_xcpt_if (_core_io_ifu_brupdate_b2_uop_bp_xcpt_if),
.io_ifu_brupdate_b2_uop_debug_fsrc (_core_io_ifu_brupdate_b2_uop_debug_fsrc),
.io_ifu_brupdate_b2_uop_debug_tsrc (_core_io_ifu_brupdate_b2_uop_debug_tsrc),
.io_ifu_brupdate_b2_valid (_core_io_ifu_brupdate_b2_valid),
.io_ifu_brupdate_b2_mispredict (_core_io_ifu_brupdate_b2_mispredict),
.io_ifu_brupdate_b2_taken (_core_io_ifu_brupdate_b2_taken),
.io_ifu_brupdate_b2_cfi_type (_core_io_ifu_brupdate_b2_cfi_type),
.io_ifu_brupdate_b2_pc_sel (_core_io_ifu_brupdate_b2_pc_sel),
.io_ifu_brupdate_b2_jalr_target (_core_io_ifu_brupdate_b2_jalr_target),
.io_ifu_brupdate_b2_target_offset (_core_io_ifu_brupdate_b2_target_offset),
.io_ifu_redirect_flush (_core_io_ifu_redirect_flush),
.io_ifu_redirect_val (_core_io_ifu_redirect_val),
.io_ifu_redirect_pc (_core_io_ifu_redirect_pc),
.io_ifu_redirect_ftq_idx (_core_io_ifu_redirect_ftq_idx),
.io_ifu_redirect_ghist_old_history (_core_io_ifu_redirect_ghist_old_history),
.io_ifu_redirect_ghist_current_saw_branch_not_taken (_core_io_ifu_redirect_ghist_current_saw_branch_not_taken),
.io_ifu_redirect_ghist_new_saw_branch_not_taken (_core_io_ifu_redirect_ghist_new_saw_branch_not_taken),
.io_ifu_redirect_ghist_new_saw_branch_taken (_core_io_ifu_redirect_ghist_new_saw_branch_taken),
.io_ifu_redirect_ghist_ras_idx (_core_io_ifu_redirect_ghist_ras_idx),
.io_ifu_commit_valid (_core_io_ifu_commit_valid),
.io_ifu_commit_bits (_core_io_ifu_commit_bits),
.io_ifu_flush_icache (_core_io_ifu_flush_icache),
.io_ifu_perf_acquire (_frontend_io_cpu_perf_acquire), // @[tile.scala:138:28]
.io_ifu_perf_tlbMiss (_frontend_io_cpu_perf_tlbMiss), // @[tile.scala:138:28]
.io_ptw_ptbr_mode (_core_io_ptw_ptbr_mode),
.io_ptw_ptbr_ppn (_core_io_ptw_ptbr_ppn),
.io_ptw_sfence_valid (_core_io_ptw_sfence_valid),
.io_ptw_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1),
.io_ptw_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2),
.io_ptw_sfence_bits_addr (_core_io_ptw_sfence_bits_addr),
.io_ptw_sfence_bits_asid (_core_io_ptw_sfence_bits_asid),
.io_ptw_status_debug (_core_io_ptw_status_debug),
.io_ptw_status_cease (_core_io_ptw_status_cease),
.io_ptw_status_wfi (_core_io_ptw_status_wfi),
.io_ptw_status_dprv (_core_io_ptw_status_dprv),
.io_ptw_status_dv (_core_io_ptw_status_dv),
.io_ptw_status_prv (_core_io_ptw_status_prv),
.io_ptw_status_v (_core_io_ptw_status_v),
.io_ptw_status_sd (_core_io_ptw_status_sd),
.io_ptw_status_mpv (_core_io_ptw_status_mpv),
.io_ptw_status_gva (_core_io_ptw_status_gva),
.io_ptw_status_tsr (_core_io_ptw_status_tsr),
.io_ptw_status_tw (_core_io_ptw_status_tw),
.io_ptw_status_tvm (_core_io_ptw_status_tvm),
.io_ptw_status_mxr (_core_io_ptw_status_mxr),
.io_ptw_status_sum (_core_io_ptw_status_sum),
.io_ptw_status_mprv (_core_io_ptw_status_mprv),
.io_ptw_status_fs (_core_io_ptw_status_fs),
.io_ptw_status_mpp (_core_io_ptw_status_mpp),
.io_ptw_status_spp (_core_io_ptw_status_spp),
.io_ptw_status_mpie (_core_io_ptw_status_mpie),
.io_ptw_status_spie (_core_io_ptw_status_spie),
.io_ptw_status_mie (_core_io_ptw_status_mie),
.io_ptw_status_sie (_core_io_ptw_status_sie),
.io_ptw_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l),
.io_ptw_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a),
.io_ptw_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x),
.io_ptw_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w),
.io_ptw_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r),
.io_ptw_pmp_0_addr (_core_io_ptw_pmp_0_addr),
.io_ptw_pmp_0_mask (_core_io_ptw_pmp_0_mask),
.io_ptw_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l),
.io_ptw_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a),
.io_ptw_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x),
.io_ptw_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w),
.io_ptw_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r),
.io_ptw_pmp_1_addr (_core_io_ptw_pmp_1_addr),
.io_ptw_pmp_1_mask (_core_io_ptw_pmp_1_mask),
.io_ptw_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l),
.io_ptw_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a),
.io_ptw_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x),
.io_ptw_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w),
.io_ptw_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r),
.io_ptw_pmp_2_addr (_core_io_ptw_pmp_2_addr),
.io_ptw_pmp_2_mask (_core_io_ptw_pmp_2_mask),
.io_ptw_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l),
.io_ptw_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a),
.io_ptw_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x),
.io_ptw_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w),
.io_ptw_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r),
.io_ptw_pmp_3_addr (_core_io_ptw_pmp_3_addr),
.io_ptw_pmp_3_mask (_core_io_ptw_pmp_3_mask),
.io_ptw_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l),
.io_ptw_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a),
.io_ptw_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x),
.io_ptw_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w),
.io_ptw_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r),
.io_ptw_pmp_4_addr (_core_io_ptw_pmp_4_addr),
.io_ptw_pmp_4_mask (_core_io_ptw_pmp_4_mask),
.io_ptw_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l),
.io_ptw_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a),
.io_ptw_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x),
.io_ptw_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w),
.io_ptw_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r),
.io_ptw_pmp_5_addr (_core_io_ptw_pmp_5_addr),
.io_ptw_pmp_5_mask (_core_io_ptw_pmp_5_mask),
.io_ptw_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l),
.io_ptw_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a),
.io_ptw_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x),
.io_ptw_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w),
.io_ptw_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r),
.io_ptw_pmp_6_addr (_core_io_ptw_pmp_6_addr),
.io_ptw_pmp_6_mask (_core_io_ptw_pmp_6_mask),
.io_ptw_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l),
.io_ptw_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a),
.io_ptw_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x),
.io_ptw_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w),
.io_ptw_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r),
.io_ptw_pmp_7_addr (_core_io_ptw_pmp_7_addr),
.io_ptw_pmp_7_mask (_core_io_ptw_pmp_7_mask),
.io_ptw_perf_l2miss (_ptw_io_dpath_perf_l2miss), // @[tile.scala:237:20]
.io_ptw_perf_l2hit (_ptw_io_dpath_perf_l2hit), // @[tile.scala:237:20]
.io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[tile.scala:237:20]
.io_ptw_perf_pte_hit (_ptw_io_dpath_perf_pte_hit), // @[tile.scala:237:20]
.io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled), // @[tile.scala:237:20]
.io_lsu_exe_0_req_valid (_core_io_lsu_exe_0_req_valid),
.io_lsu_exe_0_req_bits_uop_uopc (_core_io_lsu_exe_0_req_bits_uop_uopc),
.io_lsu_exe_0_req_bits_uop_inst (_core_io_lsu_exe_0_req_bits_uop_inst),
.io_lsu_exe_0_req_bits_uop_debug_inst (_core_io_lsu_exe_0_req_bits_uop_debug_inst),
.io_lsu_exe_0_req_bits_uop_is_rvc (_core_io_lsu_exe_0_req_bits_uop_is_rvc),
.io_lsu_exe_0_req_bits_uop_debug_pc (_core_io_lsu_exe_0_req_bits_uop_debug_pc),
.io_lsu_exe_0_req_bits_uop_iq_type (_core_io_lsu_exe_0_req_bits_uop_iq_type),
.io_lsu_exe_0_req_bits_uop_fu_code (_core_io_lsu_exe_0_req_bits_uop_fu_code),
.io_lsu_exe_0_req_bits_uop_ctrl_br_type (_core_io_lsu_exe_0_req_bits_uop_ctrl_br_type),
.io_lsu_exe_0_req_bits_uop_ctrl_op1_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op1_sel),
.io_lsu_exe_0_req_bits_uop_ctrl_op2_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op2_sel),
.io_lsu_exe_0_req_bits_uop_ctrl_imm_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_imm_sel),
.io_lsu_exe_0_req_bits_uop_ctrl_op_fcn (_core_io_lsu_exe_0_req_bits_uop_ctrl_op_fcn),
.io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw (_core_io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw),
.io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd (_core_io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd),
.io_lsu_exe_0_req_bits_uop_ctrl_is_load (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_load),
.io_lsu_exe_0_req_bits_uop_ctrl_is_sta (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_sta),
.io_lsu_exe_0_req_bits_uop_ctrl_is_std (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_std),
.io_lsu_exe_0_req_bits_uop_iw_state (_core_io_lsu_exe_0_req_bits_uop_iw_state),
.io_lsu_exe_0_req_bits_uop_iw_p1_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p1_poisoned),
.io_lsu_exe_0_req_bits_uop_iw_p2_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p2_poisoned),
.io_lsu_exe_0_req_bits_uop_is_br (_core_io_lsu_exe_0_req_bits_uop_is_br),
.io_lsu_exe_0_req_bits_uop_is_jalr (_core_io_lsu_exe_0_req_bits_uop_is_jalr),
.io_lsu_exe_0_req_bits_uop_is_jal (_core_io_lsu_exe_0_req_bits_uop_is_jal),
.io_lsu_exe_0_req_bits_uop_is_sfb (_core_io_lsu_exe_0_req_bits_uop_is_sfb),
.io_lsu_exe_0_req_bits_uop_br_mask (_core_io_lsu_exe_0_req_bits_uop_br_mask),
.io_lsu_exe_0_req_bits_uop_br_tag (_core_io_lsu_exe_0_req_bits_uop_br_tag),
.io_lsu_exe_0_req_bits_uop_ftq_idx (_core_io_lsu_exe_0_req_bits_uop_ftq_idx),
.io_lsu_exe_0_req_bits_uop_edge_inst (_core_io_lsu_exe_0_req_bits_uop_edge_inst),
.io_lsu_exe_0_req_bits_uop_pc_lob (_core_io_lsu_exe_0_req_bits_uop_pc_lob),
.io_lsu_exe_0_req_bits_uop_taken (_core_io_lsu_exe_0_req_bits_uop_taken),
.io_lsu_exe_0_req_bits_uop_imm_packed (_core_io_lsu_exe_0_req_bits_uop_imm_packed),
.io_lsu_exe_0_req_bits_uop_csr_addr (_core_io_lsu_exe_0_req_bits_uop_csr_addr),
.io_lsu_exe_0_req_bits_uop_rob_idx (_core_io_lsu_exe_0_req_bits_uop_rob_idx),
.io_lsu_exe_0_req_bits_uop_ldq_idx (_core_io_lsu_exe_0_req_bits_uop_ldq_idx),
.io_lsu_exe_0_req_bits_uop_stq_idx (_core_io_lsu_exe_0_req_bits_uop_stq_idx),
.io_lsu_exe_0_req_bits_uop_rxq_idx (_core_io_lsu_exe_0_req_bits_uop_rxq_idx),
.io_lsu_exe_0_req_bits_uop_pdst (_core_io_lsu_exe_0_req_bits_uop_pdst),
.io_lsu_exe_0_req_bits_uop_prs1 (_core_io_lsu_exe_0_req_bits_uop_prs1),
.io_lsu_exe_0_req_bits_uop_prs2 (_core_io_lsu_exe_0_req_bits_uop_prs2),
.io_lsu_exe_0_req_bits_uop_prs3 (_core_io_lsu_exe_0_req_bits_uop_prs3),
.io_lsu_exe_0_req_bits_uop_ppred (_core_io_lsu_exe_0_req_bits_uop_ppred),
.io_lsu_exe_0_req_bits_uop_prs1_busy (_core_io_lsu_exe_0_req_bits_uop_prs1_busy),
.io_lsu_exe_0_req_bits_uop_prs2_busy (_core_io_lsu_exe_0_req_bits_uop_prs2_busy),
.io_lsu_exe_0_req_bits_uop_prs3_busy (_core_io_lsu_exe_0_req_bits_uop_prs3_busy),
.io_lsu_exe_0_req_bits_uop_ppred_busy (_core_io_lsu_exe_0_req_bits_uop_ppred_busy),
.io_lsu_exe_0_req_bits_uop_stale_pdst (_core_io_lsu_exe_0_req_bits_uop_stale_pdst),
.io_lsu_exe_0_req_bits_uop_exception (_core_io_lsu_exe_0_req_bits_uop_exception),
.io_lsu_exe_0_req_bits_uop_exc_cause (_core_io_lsu_exe_0_req_bits_uop_exc_cause),
.io_lsu_exe_0_req_bits_uop_bypassable (_core_io_lsu_exe_0_req_bits_uop_bypassable),
.io_lsu_exe_0_req_bits_uop_mem_cmd (_core_io_lsu_exe_0_req_bits_uop_mem_cmd),
.io_lsu_exe_0_req_bits_uop_mem_size (_core_io_lsu_exe_0_req_bits_uop_mem_size),
.io_lsu_exe_0_req_bits_uop_mem_signed (_core_io_lsu_exe_0_req_bits_uop_mem_signed),
.io_lsu_exe_0_req_bits_uop_is_fence (_core_io_lsu_exe_0_req_bits_uop_is_fence),
.io_lsu_exe_0_req_bits_uop_is_fencei (_core_io_lsu_exe_0_req_bits_uop_is_fencei),
.io_lsu_exe_0_req_bits_uop_is_amo (_core_io_lsu_exe_0_req_bits_uop_is_amo),
.io_lsu_exe_0_req_bits_uop_uses_ldq (_core_io_lsu_exe_0_req_bits_uop_uses_ldq),
.io_lsu_exe_0_req_bits_uop_uses_stq (_core_io_lsu_exe_0_req_bits_uop_uses_stq),
.io_lsu_exe_0_req_bits_uop_is_sys_pc2epc (_core_io_lsu_exe_0_req_bits_uop_is_sys_pc2epc),
.io_lsu_exe_0_req_bits_uop_is_unique (_core_io_lsu_exe_0_req_bits_uop_is_unique),
.io_lsu_exe_0_req_bits_uop_flush_on_commit (_core_io_lsu_exe_0_req_bits_uop_flush_on_commit),
.io_lsu_exe_0_req_bits_uop_ldst_is_rs1 (_core_io_lsu_exe_0_req_bits_uop_ldst_is_rs1),
.io_lsu_exe_0_req_bits_uop_ldst (_core_io_lsu_exe_0_req_bits_uop_ldst),
.io_lsu_exe_0_req_bits_uop_lrs1 (_core_io_lsu_exe_0_req_bits_uop_lrs1),
.io_lsu_exe_0_req_bits_uop_lrs2 (_core_io_lsu_exe_0_req_bits_uop_lrs2),
.io_lsu_exe_0_req_bits_uop_lrs3 (_core_io_lsu_exe_0_req_bits_uop_lrs3),
.io_lsu_exe_0_req_bits_uop_ldst_val (_core_io_lsu_exe_0_req_bits_uop_ldst_val),
.io_lsu_exe_0_req_bits_uop_dst_rtype (_core_io_lsu_exe_0_req_bits_uop_dst_rtype),
.io_lsu_exe_0_req_bits_uop_lrs1_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs1_rtype),
.io_lsu_exe_0_req_bits_uop_lrs2_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs2_rtype),
.io_lsu_exe_0_req_bits_uop_frs3_en (_core_io_lsu_exe_0_req_bits_uop_frs3_en),
.io_lsu_exe_0_req_bits_uop_fp_val (_core_io_lsu_exe_0_req_bits_uop_fp_val),
.io_lsu_exe_0_req_bits_uop_fp_single (_core_io_lsu_exe_0_req_bits_uop_fp_single),
.io_lsu_exe_0_req_bits_uop_xcpt_pf_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_pf_if),
.io_lsu_exe_0_req_bits_uop_xcpt_ae_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ae_if),
.io_lsu_exe_0_req_bits_uop_xcpt_ma_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ma_if),
.io_lsu_exe_0_req_bits_uop_bp_debug_if (_core_io_lsu_exe_0_req_bits_uop_bp_debug_if),
.io_lsu_exe_0_req_bits_uop_bp_xcpt_if (_core_io_lsu_exe_0_req_bits_uop_bp_xcpt_if),
.io_lsu_exe_0_req_bits_uop_debug_fsrc (_core_io_lsu_exe_0_req_bits_uop_debug_fsrc),
.io_lsu_exe_0_req_bits_uop_debug_tsrc (_core_io_lsu_exe_0_req_bits_uop_debug_tsrc),
.io_lsu_exe_0_req_bits_data (_core_io_lsu_exe_0_req_bits_data),
.io_lsu_exe_0_req_bits_addr (_core_io_lsu_exe_0_req_bits_addr),
.io_lsu_exe_0_req_bits_mxcpt_valid (_core_io_lsu_exe_0_req_bits_mxcpt_valid),
.io_lsu_exe_0_req_bits_mxcpt_bits (_core_io_lsu_exe_0_req_bits_mxcpt_bits),
.io_lsu_exe_0_req_bits_sfence_valid (_core_io_lsu_exe_0_req_bits_sfence_valid),
.io_lsu_exe_0_req_bits_sfence_bits_rs1 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs1),
.io_lsu_exe_0_req_bits_sfence_bits_rs2 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs2),
.io_lsu_exe_0_req_bits_sfence_bits_addr (_core_io_lsu_exe_0_req_bits_sfence_bits_addr),
.io_lsu_exe_0_req_bits_sfence_bits_asid (_core_io_lsu_exe_0_req_bits_sfence_bits_asid),
.io_lsu_exe_0_iresp_valid (_lsu_io_core_exe_0_iresp_valid), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_uopc (_lsu_io_core_exe_0_iresp_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_inst (_lsu_io_core_exe_0_iresp_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_inst (_lsu_io_core_exe_0_iresp_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_rvc (_lsu_io_core_exe_0_iresp_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_pc (_lsu_io_core_exe_0_iresp_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iq_type (_lsu_io_core_exe_0_iresp_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_fu_code (_lsu_io_core_exe_0_iresp_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iw_state (_lsu_io_core_exe_0_iresp_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_br (_lsu_io_core_exe_0_iresp_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_jalr (_lsu_io_core_exe_0_iresp_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_jal (_lsu_io_core_exe_0_iresp_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_sfb (_lsu_io_core_exe_0_iresp_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_br_mask (_lsu_io_core_exe_0_iresp_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_br_tag (_lsu_io_core_exe_0_iresp_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_edge_inst (_lsu_io_core_exe_0_iresp_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_pc_lob (_lsu_io_core_exe_0_iresp_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_taken (_lsu_io_core_exe_0_iresp_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_imm_packed (_lsu_io_core_exe_0_iresp_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_csr_addr (_lsu_io_core_exe_0_iresp_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_rob_idx (_lsu_io_core_exe_0_iresp_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_stq_idx (_lsu_io_core_exe_0_iresp_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_iresp_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_pdst (_lsu_io_core_exe_0_iresp_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs1 (_lsu_io_core_exe_0_iresp_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs2 (_lsu_io_core_exe_0_iresp_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs3 (_lsu_io_core_exe_0_iresp_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ppred (_lsu_io_core_exe_0_iresp_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_iresp_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_iresp_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_exception (_lsu_io_core_exe_0_iresp_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_exc_cause (_lsu_io_core_exe_0_iresp_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_bypassable (_lsu_io_core_exe_0_iresp_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_iresp_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_mem_size (_lsu_io_core_exe_0_iresp_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_mem_signed (_lsu_io_core_exe_0_iresp_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_fence (_lsu_io_core_exe_0_iresp_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_fencei (_lsu_io_core_exe_0_iresp_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_amo (_lsu_io_core_exe_0_iresp_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_iresp_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_uses_stq (_lsu_io_core_exe_0_iresp_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_is_unique (_lsu_io_core_exe_0_iresp_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldst (_lsu_io_core_exe_0_iresp_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs1 (_lsu_io_core_exe_0_iresp_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs2 (_lsu_io_core_exe_0_iresp_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs3 (_lsu_io_core_exe_0_iresp_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_ldst_val (_lsu_io_core_exe_0_iresp_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_iresp_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_frs3_en (_lsu_io_core_exe_0_iresp_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_fp_val (_lsu_io_core_exe_0_iresp_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_fp_single (_lsu_io_core_exe_0_iresp_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_iresp_bits_data (_lsu_io_core_exe_0_iresp_bits_data), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_valid (_lsu_io_core_exe_0_fresp_valid), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_uopc (_lsu_io_core_exe_0_fresp_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_inst (_lsu_io_core_exe_0_fresp_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_inst (_lsu_io_core_exe_0_fresp_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_rvc (_lsu_io_core_exe_0_fresp_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_pc (_lsu_io_core_exe_0_fresp_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iq_type (_lsu_io_core_exe_0_fresp_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_fu_code (_lsu_io_core_exe_0_fresp_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iw_state (_lsu_io_core_exe_0_fresp_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_br (_lsu_io_core_exe_0_fresp_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_jalr (_lsu_io_core_exe_0_fresp_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_jal (_lsu_io_core_exe_0_fresp_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_sfb (_lsu_io_core_exe_0_fresp_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_br_mask (_lsu_io_core_exe_0_fresp_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_br_tag (_lsu_io_core_exe_0_fresp_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_edge_inst (_lsu_io_core_exe_0_fresp_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_pc_lob (_lsu_io_core_exe_0_fresp_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_taken (_lsu_io_core_exe_0_fresp_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_imm_packed (_lsu_io_core_exe_0_fresp_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_csr_addr (_lsu_io_core_exe_0_fresp_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_rob_idx (_lsu_io_core_exe_0_fresp_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_stq_idx (_lsu_io_core_exe_0_fresp_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_fresp_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_pdst (_lsu_io_core_exe_0_fresp_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs1 (_lsu_io_core_exe_0_fresp_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs2 (_lsu_io_core_exe_0_fresp_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs3 (_lsu_io_core_exe_0_fresp_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ppred (_lsu_io_core_exe_0_fresp_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_fresp_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_fresp_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_exception (_lsu_io_core_exe_0_fresp_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_exc_cause (_lsu_io_core_exe_0_fresp_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_bypassable (_lsu_io_core_exe_0_fresp_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_fresp_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_mem_size (_lsu_io_core_exe_0_fresp_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_mem_signed (_lsu_io_core_exe_0_fresp_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_fence (_lsu_io_core_exe_0_fresp_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_fencei (_lsu_io_core_exe_0_fresp_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_amo (_lsu_io_core_exe_0_fresp_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_fresp_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_uses_stq (_lsu_io_core_exe_0_fresp_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_is_unique (_lsu_io_core_exe_0_fresp_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldst (_lsu_io_core_exe_0_fresp_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs1 (_lsu_io_core_exe_0_fresp_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs2 (_lsu_io_core_exe_0_fresp_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs3 (_lsu_io_core_exe_0_fresp_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_ldst_val (_lsu_io_core_exe_0_fresp_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_fresp_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_frs3_en (_lsu_io_core_exe_0_fresp_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_fp_val (_lsu_io_core_exe_0_fresp_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_fp_single (_lsu_io_core_exe_0_fresp_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_exe_0_fresp_bits_data (_lsu_io_core_exe_0_fresp_bits_data), // @[tile.scala:160:20]
.io_lsu_dis_uops_0_valid (_core_io_lsu_dis_uops_0_valid),
.io_lsu_dis_uops_0_bits_uopc (_core_io_lsu_dis_uops_0_bits_uopc),
.io_lsu_dis_uops_0_bits_inst (_core_io_lsu_dis_uops_0_bits_inst),
.io_lsu_dis_uops_0_bits_debug_inst (_core_io_lsu_dis_uops_0_bits_debug_inst),
.io_lsu_dis_uops_0_bits_is_rvc (_core_io_lsu_dis_uops_0_bits_is_rvc),
.io_lsu_dis_uops_0_bits_debug_pc (_core_io_lsu_dis_uops_0_bits_debug_pc),
.io_lsu_dis_uops_0_bits_iq_type (_core_io_lsu_dis_uops_0_bits_iq_type),
.io_lsu_dis_uops_0_bits_fu_code (_core_io_lsu_dis_uops_0_bits_fu_code),
.io_lsu_dis_uops_0_bits_ctrl_br_type (_core_io_lsu_dis_uops_0_bits_ctrl_br_type),
.io_lsu_dis_uops_0_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op1_sel),
.io_lsu_dis_uops_0_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op2_sel),
.io_lsu_dis_uops_0_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_0_bits_ctrl_imm_sel),
.io_lsu_dis_uops_0_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_0_bits_ctrl_op_fcn),
.io_lsu_dis_uops_0_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_0_bits_ctrl_fcn_dw),
.io_lsu_dis_uops_0_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_0_bits_ctrl_csr_cmd),
.io_lsu_dis_uops_0_bits_ctrl_is_load (_core_io_lsu_dis_uops_0_bits_ctrl_is_load),
.io_lsu_dis_uops_0_bits_ctrl_is_sta (_core_io_lsu_dis_uops_0_bits_ctrl_is_sta),
.io_lsu_dis_uops_0_bits_ctrl_is_std (_core_io_lsu_dis_uops_0_bits_ctrl_is_std),
.io_lsu_dis_uops_0_bits_iw_state (_core_io_lsu_dis_uops_0_bits_iw_state),
.io_lsu_dis_uops_0_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p1_poisoned),
.io_lsu_dis_uops_0_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p2_poisoned),
.io_lsu_dis_uops_0_bits_is_br (_core_io_lsu_dis_uops_0_bits_is_br),
.io_lsu_dis_uops_0_bits_is_jalr (_core_io_lsu_dis_uops_0_bits_is_jalr),
.io_lsu_dis_uops_0_bits_is_jal (_core_io_lsu_dis_uops_0_bits_is_jal),
.io_lsu_dis_uops_0_bits_is_sfb (_core_io_lsu_dis_uops_0_bits_is_sfb),
.io_lsu_dis_uops_0_bits_br_mask (_core_io_lsu_dis_uops_0_bits_br_mask),
.io_lsu_dis_uops_0_bits_br_tag (_core_io_lsu_dis_uops_0_bits_br_tag),
.io_lsu_dis_uops_0_bits_ftq_idx (_core_io_lsu_dis_uops_0_bits_ftq_idx),
.io_lsu_dis_uops_0_bits_edge_inst (_core_io_lsu_dis_uops_0_bits_edge_inst),
.io_lsu_dis_uops_0_bits_pc_lob (_core_io_lsu_dis_uops_0_bits_pc_lob),
.io_lsu_dis_uops_0_bits_taken (_core_io_lsu_dis_uops_0_bits_taken),
.io_lsu_dis_uops_0_bits_imm_packed (_core_io_lsu_dis_uops_0_bits_imm_packed),
.io_lsu_dis_uops_0_bits_csr_addr (_core_io_lsu_dis_uops_0_bits_csr_addr),
.io_lsu_dis_uops_0_bits_rob_idx (_core_io_lsu_dis_uops_0_bits_rob_idx),
.io_lsu_dis_uops_0_bits_ldq_idx (_core_io_lsu_dis_uops_0_bits_ldq_idx),
.io_lsu_dis_uops_0_bits_stq_idx (_core_io_lsu_dis_uops_0_bits_stq_idx),
.io_lsu_dis_uops_0_bits_rxq_idx (_core_io_lsu_dis_uops_0_bits_rxq_idx),
.io_lsu_dis_uops_0_bits_pdst (_core_io_lsu_dis_uops_0_bits_pdst),
.io_lsu_dis_uops_0_bits_prs1 (_core_io_lsu_dis_uops_0_bits_prs1),
.io_lsu_dis_uops_0_bits_prs2 (_core_io_lsu_dis_uops_0_bits_prs2),
.io_lsu_dis_uops_0_bits_prs3 (_core_io_lsu_dis_uops_0_bits_prs3),
.io_lsu_dis_uops_0_bits_prs1_busy (_core_io_lsu_dis_uops_0_bits_prs1_busy),
.io_lsu_dis_uops_0_bits_prs2_busy (_core_io_lsu_dis_uops_0_bits_prs2_busy),
.io_lsu_dis_uops_0_bits_prs3_busy (_core_io_lsu_dis_uops_0_bits_prs3_busy),
.io_lsu_dis_uops_0_bits_stale_pdst (_core_io_lsu_dis_uops_0_bits_stale_pdst),
.io_lsu_dis_uops_0_bits_exception (_core_io_lsu_dis_uops_0_bits_exception),
.io_lsu_dis_uops_0_bits_exc_cause (_core_io_lsu_dis_uops_0_bits_exc_cause),
.io_lsu_dis_uops_0_bits_bypassable (_core_io_lsu_dis_uops_0_bits_bypassable),
.io_lsu_dis_uops_0_bits_mem_cmd (_core_io_lsu_dis_uops_0_bits_mem_cmd),
.io_lsu_dis_uops_0_bits_mem_size (_core_io_lsu_dis_uops_0_bits_mem_size),
.io_lsu_dis_uops_0_bits_mem_signed (_core_io_lsu_dis_uops_0_bits_mem_signed),
.io_lsu_dis_uops_0_bits_is_fence (_core_io_lsu_dis_uops_0_bits_is_fence),
.io_lsu_dis_uops_0_bits_is_fencei (_core_io_lsu_dis_uops_0_bits_is_fencei),
.io_lsu_dis_uops_0_bits_is_amo (_core_io_lsu_dis_uops_0_bits_is_amo),
.io_lsu_dis_uops_0_bits_uses_ldq (_core_io_lsu_dis_uops_0_bits_uses_ldq),
.io_lsu_dis_uops_0_bits_uses_stq (_core_io_lsu_dis_uops_0_bits_uses_stq),
.io_lsu_dis_uops_0_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_0_bits_is_sys_pc2epc),
.io_lsu_dis_uops_0_bits_is_unique (_core_io_lsu_dis_uops_0_bits_is_unique),
.io_lsu_dis_uops_0_bits_flush_on_commit (_core_io_lsu_dis_uops_0_bits_flush_on_commit),
.io_lsu_dis_uops_0_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_0_bits_ldst_is_rs1),
.io_lsu_dis_uops_0_bits_ldst (_core_io_lsu_dis_uops_0_bits_ldst),
.io_lsu_dis_uops_0_bits_lrs1 (_core_io_lsu_dis_uops_0_bits_lrs1),
.io_lsu_dis_uops_0_bits_lrs2 (_core_io_lsu_dis_uops_0_bits_lrs2),
.io_lsu_dis_uops_0_bits_lrs3 (_core_io_lsu_dis_uops_0_bits_lrs3),
.io_lsu_dis_uops_0_bits_ldst_val (_core_io_lsu_dis_uops_0_bits_ldst_val),
.io_lsu_dis_uops_0_bits_dst_rtype (_core_io_lsu_dis_uops_0_bits_dst_rtype),
.io_lsu_dis_uops_0_bits_lrs1_rtype (_core_io_lsu_dis_uops_0_bits_lrs1_rtype),
.io_lsu_dis_uops_0_bits_lrs2_rtype (_core_io_lsu_dis_uops_0_bits_lrs2_rtype),
.io_lsu_dis_uops_0_bits_frs3_en (_core_io_lsu_dis_uops_0_bits_frs3_en),
.io_lsu_dis_uops_0_bits_fp_val (_core_io_lsu_dis_uops_0_bits_fp_val),
.io_lsu_dis_uops_0_bits_fp_single (_core_io_lsu_dis_uops_0_bits_fp_single),
.io_lsu_dis_uops_0_bits_xcpt_pf_if (_core_io_lsu_dis_uops_0_bits_xcpt_pf_if),
.io_lsu_dis_uops_0_bits_xcpt_ae_if (_core_io_lsu_dis_uops_0_bits_xcpt_ae_if),
.io_lsu_dis_uops_0_bits_xcpt_ma_if (_core_io_lsu_dis_uops_0_bits_xcpt_ma_if),
.io_lsu_dis_uops_0_bits_bp_debug_if (_core_io_lsu_dis_uops_0_bits_bp_debug_if),
.io_lsu_dis_uops_0_bits_bp_xcpt_if (_core_io_lsu_dis_uops_0_bits_bp_xcpt_if),
.io_lsu_dis_uops_0_bits_debug_fsrc (_core_io_lsu_dis_uops_0_bits_debug_fsrc),
.io_lsu_dis_uops_0_bits_debug_tsrc (_core_io_lsu_dis_uops_0_bits_debug_tsrc),
.io_lsu_dis_uops_1_valid (_core_io_lsu_dis_uops_1_valid),
.io_lsu_dis_uops_1_bits_uopc (_core_io_lsu_dis_uops_1_bits_uopc),
.io_lsu_dis_uops_1_bits_inst (_core_io_lsu_dis_uops_1_bits_inst),
.io_lsu_dis_uops_1_bits_debug_inst (_core_io_lsu_dis_uops_1_bits_debug_inst),
.io_lsu_dis_uops_1_bits_is_rvc (_core_io_lsu_dis_uops_1_bits_is_rvc),
.io_lsu_dis_uops_1_bits_debug_pc (_core_io_lsu_dis_uops_1_bits_debug_pc),
.io_lsu_dis_uops_1_bits_iq_type (_core_io_lsu_dis_uops_1_bits_iq_type),
.io_lsu_dis_uops_1_bits_fu_code (_core_io_lsu_dis_uops_1_bits_fu_code),
.io_lsu_dis_uops_1_bits_ctrl_br_type (_core_io_lsu_dis_uops_1_bits_ctrl_br_type),
.io_lsu_dis_uops_1_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op1_sel),
.io_lsu_dis_uops_1_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op2_sel),
.io_lsu_dis_uops_1_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_1_bits_ctrl_imm_sel),
.io_lsu_dis_uops_1_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_1_bits_ctrl_op_fcn),
.io_lsu_dis_uops_1_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_1_bits_ctrl_fcn_dw),
.io_lsu_dis_uops_1_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_1_bits_ctrl_csr_cmd),
.io_lsu_dis_uops_1_bits_ctrl_is_load (_core_io_lsu_dis_uops_1_bits_ctrl_is_load),
.io_lsu_dis_uops_1_bits_ctrl_is_sta (_core_io_lsu_dis_uops_1_bits_ctrl_is_sta),
.io_lsu_dis_uops_1_bits_ctrl_is_std (_core_io_lsu_dis_uops_1_bits_ctrl_is_std),
.io_lsu_dis_uops_1_bits_iw_state (_core_io_lsu_dis_uops_1_bits_iw_state),
.io_lsu_dis_uops_1_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p1_poisoned),
.io_lsu_dis_uops_1_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p2_poisoned),
.io_lsu_dis_uops_1_bits_is_br (_core_io_lsu_dis_uops_1_bits_is_br),
.io_lsu_dis_uops_1_bits_is_jalr (_core_io_lsu_dis_uops_1_bits_is_jalr),
.io_lsu_dis_uops_1_bits_is_jal (_core_io_lsu_dis_uops_1_bits_is_jal),
.io_lsu_dis_uops_1_bits_is_sfb (_core_io_lsu_dis_uops_1_bits_is_sfb),
.io_lsu_dis_uops_1_bits_br_mask (_core_io_lsu_dis_uops_1_bits_br_mask),
.io_lsu_dis_uops_1_bits_br_tag (_core_io_lsu_dis_uops_1_bits_br_tag),
.io_lsu_dis_uops_1_bits_ftq_idx (_core_io_lsu_dis_uops_1_bits_ftq_idx),
.io_lsu_dis_uops_1_bits_edge_inst (_core_io_lsu_dis_uops_1_bits_edge_inst),
.io_lsu_dis_uops_1_bits_pc_lob (_core_io_lsu_dis_uops_1_bits_pc_lob),
.io_lsu_dis_uops_1_bits_taken (_core_io_lsu_dis_uops_1_bits_taken),
.io_lsu_dis_uops_1_bits_imm_packed (_core_io_lsu_dis_uops_1_bits_imm_packed),
.io_lsu_dis_uops_1_bits_csr_addr (_core_io_lsu_dis_uops_1_bits_csr_addr),
.io_lsu_dis_uops_1_bits_rob_idx (_core_io_lsu_dis_uops_1_bits_rob_idx),
.io_lsu_dis_uops_1_bits_ldq_idx (_core_io_lsu_dis_uops_1_bits_ldq_idx),
.io_lsu_dis_uops_1_bits_stq_idx (_core_io_lsu_dis_uops_1_bits_stq_idx),
.io_lsu_dis_uops_1_bits_rxq_idx (_core_io_lsu_dis_uops_1_bits_rxq_idx),
.io_lsu_dis_uops_1_bits_pdst (_core_io_lsu_dis_uops_1_bits_pdst),
.io_lsu_dis_uops_1_bits_prs1 (_core_io_lsu_dis_uops_1_bits_prs1),
.io_lsu_dis_uops_1_bits_prs2 (_core_io_lsu_dis_uops_1_bits_prs2),
.io_lsu_dis_uops_1_bits_prs3 (_core_io_lsu_dis_uops_1_bits_prs3),
.io_lsu_dis_uops_1_bits_prs1_busy (_core_io_lsu_dis_uops_1_bits_prs1_busy),
.io_lsu_dis_uops_1_bits_prs2_busy (_core_io_lsu_dis_uops_1_bits_prs2_busy),
.io_lsu_dis_uops_1_bits_prs3_busy (_core_io_lsu_dis_uops_1_bits_prs3_busy),
.io_lsu_dis_uops_1_bits_stale_pdst (_core_io_lsu_dis_uops_1_bits_stale_pdst),
.io_lsu_dis_uops_1_bits_exception (_core_io_lsu_dis_uops_1_bits_exception),
.io_lsu_dis_uops_1_bits_exc_cause (_core_io_lsu_dis_uops_1_bits_exc_cause),
.io_lsu_dis_uops_1_bits_bypassable (_core_io_lsu_dis_uops_1_bits_bypassable),
.io_lsu_dis_uops_1_bits_mem_cmd (_core_io_lsu_dis_uops_1_bits_mem_cmd),
.io_lsu_dis_uops_1_bits_mem_size (_core_io_lsu_dis_uops_1_bits_mem_size),
.io_lsu_dis_uops_1_bits_mem_signed (_core_io_lsu_dis_uops_1_bits_mem_signed),
.io_lsu_dis_uops_1_bits_is_fence (_core_io_lsu_dis_uops_1_bits_is_fence),
.io_lsu_dis_uops_1_bits_is_fencei (_core_io_lsu_dis_uops_1_bits_is_fencei),
.io_lsu_dis_uops_1_bits_is_amo (_core_io_lsu_dis_uops_1_bits_is_amo),
.io_lsu_dis_uops_1_bits_uses_ldq (_core_io_lsu_dis_uops_1_bits_uses_ldq),
.io_lsu_dis_uops_1_bits_uses_stq (_core_io_lsu_dis_uops_1_bits_uses_stq),
.io_lsu_dis_uops_1_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_1_bits_is_sys_pc2epc),
.io_lsu_dis_uops_1_bits_is_unique (_core_io_lsu_dis_uops_1_bits_is_unique),
.io_lsu_dis_uops_1_bits_flush_on_commit (_core_io_lsu_dis_uops_1_bits_flush_on_commit),
.io_lsu_dis_uops_1_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_1_bits_ldst_is_rs1),
.io_lsu_dis_uops_1_bits_ldst (_core_io_lsu_dis_uops_1_bits_ldst),
.io_lsu_dis_uops_1_bits_lrs1 (_core_io_lsu_dis_uops_1_bits_lrs1),
.io_lsu_dis_uops_1_bits_lrs2 (_core_io_lsu_dis_uops_1_bits_lrs2),
.io_lsu_dis_uops_1_bits_lrs3 (_core_io_lsu_dis_uops_1_bits_lrs3),
.io_lsu_dis_uops_1_bits_ldst_val (_core_io_lsu_dis_uops_1_bits_ldst_val),
.io_lsu_dis_uops_1_bits_dst_rtype (_core_io_lsu_dis_uops_1_bits_dst_rtype),
.io_lsu_dis_uops_1_bits_lrs1_rtype (_core_io_lsu_dis_uops_1_bits_lrs1_rtype),
.io_lsu_dis_uops_1_bits_lrs2_rtype (_core_io_lsu_dis_uops_1_bits_lrs2_rtype),
.io_lsu_dis_uops_1_bits_frs3_en (_core_io_lsu_dis_uops_1_bits_frs3_en),
.io_lsu_dis_uops_1_bits_fp_val (_core_io_lsu_dis_uops_1_bits_fp_val),
.io_lsu_dis_uops_1_bits_fp_single (_core_io_lsu_dis_uops_1_bits_fp_single),
.io_lsu_dis_uops_1_bits_xcpt_pf_if (_core_io_lsu_dis_uops_1_bits_xcpt_pf_if),
.io_lsu_dis_uops_1_bits_xcpt_ae_if (_core_io_lsu_dis_uops_1_bits_xcpt_ae_if),
.io_lsu_dis_uops_1_bits_xcpt_ma_if (_core_io_lsu_dis_uops_1_bits_xcpt_ma_if),
.io_lsu_dis_uops_1_bits_bp_debug_if (_core_io_lsu_dis_uops_1_bits_bp_debug_if),
.io_lsu_dis_uops_1_bits_bp_xcpt_if (_core_io_lsu_dis_uops_1_bits_bp_xcpt_if),
.io_lsu_dis_uops_1_bits_debug_fsrc (_core_io_lsu_dis_uops_1_bits_debug_fsrc),
.io_lsu_dis_uops_1_bits_debug_tsrc (_core_io_lsu_dis_uops_1_bits_debug_tsrc),
.io_lsu_dis_uops_2_valid (_core_io_lsu_dis_uops_2_valid),
.io_lsu_dis_uops_2_bits_uopc (_core_io_lsu_dis_uops_2_bits_uopc),
.io_lsu_dis_uops_2_bits_inst (_core_io_lsu_dis_uops_2_bits_inst),
.io_lsu_dis_uops_2_bits_debug_inst (_core_io_lsu_dis_uops_2_bits_debug_inst),
.io_lsu_dis_uops_2_bits_is_rvc (_core_io_lsu_dis_uops_2_bits_is_rvc),
.io_lsu_dis_uops_2_bits_debug_pc (_core_io_lsu_dis_uops_2_bits_debug_pc),
.io_lsu_dis_uops_2_bits_iq_type (_core_io_lsu_dis_uops_2_bits_iq_type),
.io_lsu_dis_uops_2_bits_fu_code (_core_io_lsu_dis_uops_2_bits_fu_code),
.io_lsu_dis_uops_2_bits_ctrl_br_type (_core_io_lsu_dis_uops_2_bits_ctrl_br_type),
.io_lsu_dis_uops_2_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op1_sel),
.io_lsu_dis_uops_2_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op2_sel),
.io_lsu_dis_uops_2_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_2_bits_ctrl_imm_sel),
.io_lsu_dis_uops_2_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_2_bits_ctrl_op_fcn),
.io_lsu_dis_uops_2_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_2_bits_ctrl_fcn_dw),
.io_lsu_dis_uops_2_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_2_bits_ctrl_csr_cmd),
.io_lsu_dis_uops_2_bits_ctrl_is_load (_core_io_lsu_dis_uops_2_bits_ctrl_is_load),
.io_lsu_dis_uops_2_bits_ctrl_is_sta (_core_io_lsu_dis_uops_2_bits_ctrl_is_sta),
.io_lsu_dis_uops_2_bits_ctrl_is_std (_core_io_lsu_dis_uops_2_bits_ctrl_is_std),
.io_lsu_dis_uops_2_bits_iw_state (_core_io_lsu_dis_uops_2_bits_iw_state),
.io_lsu_dis_uops_2_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p1_poisoned),
.io_lsu_dis_uops_2_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p2_poisoned),
.io_lsu_dis_uops_2_bits_is_br (_core_io_lsu_dis_uops_2_bits_is_br),
.io_lsu_dis_uops_2_bits_is_jalr (_core_io_lsu_dis_uops_2_bits_is_jalr),
.io_lsu_dis_uops_2_bits_is_jal (_core_io_lsu_dis_uops_2_bits_is_jal),
.io_lsu_dis_uops_2_bits_is_sfb (_core_io_lsu_dis_uops_2_bits_is_sfb),
.io_lsu_dis_uops_2_bits_br_mask (_core_io_lsu_dis_uops_2_bits_br_mask),
.io_lsu_dis_uops_2_bits_br_tag (_core_io_lsu_dis_uops_2_bits_br_tag),
.io_lsu_dis_uops_2_bits_ftq_idx (_core_io_lsu_dis_uops_2_bits_ftq_idx),
.io_lsu_dis_uops_2_bits_edge_inst (_core_io_lsu_dis_uops_2_bits_edge_inst),
.io_lsu_dis_uops_2_bits_pc_lob (_core_io_lsu_dis_uops_2_bits_pc_lob),
.io_lsu_dis_uops_2_bits_taken (_core_io_lsu_dis_uops_2_bits_taken),
.io_lsu_dis_uops_2_bits_imm_packed (_core_io_lsu_dis_uops_2_bits_imm_packed),
.io_lsu_dis_uops_2_bits_csr_addr (_core_io_lsu_dis_uops_2_bits_csr_addr),
.io_lsu_dis_uops_2_bits_rob_idx (_core_io_lsu_dis_uops_2_bits_rob_idx),
.io_lsu_dis_uops_2_bits_ldq_idx (_core_io_lsu_dis_uops_2_bits_ldq_idx),
.io_lsu_dis_uops_2_bits_stq_idx (_core_io_lsu_dis_uops_2_bits_stq_idx),
.io_lsu_dis_uops_2_bits_rxq_idx (_core_io_lsu_dis_uops_2_bits_rxq_idx),
.io_lsu_dis_uops_2_bits_pdst (_core_io_lsu_dis_uops_2_bits_pdst),
.io_lsu_dis_uops_2_bits_prs1 (_core_io_lsu_dis_uops_2_bits_prs1),
.io_lsu_dis_uops_2_bits_prs2 (_core_io_lsu_dis_uops_2_bits_prs2),
.io_lsu_dis_uops_2_bits_prs3 (_core_io_lsu_dis_uops_2_bits_prs3),
.io_lsu_dis_uops_2_bits_prs1_busy (_core_io_lsu_dis_uops_2_bits_prs1_busy),
.io_lsu_dis_uops_2_bits_prs2_busy (_core_io_lsu_dis_uops_2_bits_prs2_busy),
.io_lsu_dis_uops_2_bits_prs3_busy (_core_io_lsu_dis_uops_2_bits_prs3_busy),
.io_lsu_dis_uops_2_bits_stale_pdst (_core_io_lsu_dis_uops_2_bits_stale_pdst),
.io_lsu_dis_uops_2_bits_exception (_core_io_lsu_dis_uops_2_bits_exception),
.io_lsu_dis_uops_2_bits_exc_cause (_core_io_lsu_dis_uops_2_bits_exc_cause),
.io_lsu_dis_uops_2_bits_bypassable (_core_io_lsu_dis_uops_2_bits_bypassable),
.io_lsu_dis_uops_2_bits_mem_cmd (_core_io_lsu_dis_uops_2_bits_mem_cmd),
.io_lsu_dis_uops_2_bits_mem_size (_core_io_lsu_dis_uops_2_bits_mem_size),
.io_lsu_dis_uops_2_bits_mem_signed (_core_io_lsu_dis_uops_2_bits_mem_signed),
.io_lsu_dis_uops_2_bits_is_fence (_core_io_lsu_dis_uops_2_bits_is_fence),
.io_lsu_dis_uops_2_bits_is_fencei (_core_io_lsu_dis_uops_2_bits_is_fencei),
.io_lsu_dis_uops_2_bits_is_amo (_core_io_lsu_dis_uops_2_bits_is_amo),
.io_lsu_dis_uops_2_bits_uses_ldq (_core_io_lsu_dis_uops_2_bits_uses_ldq),
.io_lsu_dis_uops_2_bits_uses_stq (_core_io_lsu_dis_uops_2_bits_uses_stq),
.io_lsu_dis_uops_2_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_2_bits_is_sys_pc2epc),
.io_lsu_dis_uops_2_bits_is_unique (_core_io_lsu_dis_uops_2_bits_is_unique),
.io_lsu_dis_uops_2_bits_flush_on_commit (_core_io_lsu_dis_uops_2_bits_flush_on_commit),
.io_lsu_dis_uops_2_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_2_bits_ldst_is_rs1),
.io_lsu_dis_uops_2_bits_ldst (_core_io_lsu_dis_uops_2_bits_ldst),
.io_lsu_dis_uops_2_bits_lrs1 (_core_io_lsu_dis_uops_2_bits_lrs1),
.io_lsu_dis_uops_2_bits_lrs2 (_core_io_lsu_dis_uops_2_bits_lrs2),
.io_lsu_dis_uops_2_bits_lrs3 (_core_io_lsu_dis_uops_2_bits_lrs3),
.io_lsu_dis_uops_2_bits_ldst_val (_core_io_lsu_dis_uops_2_bits_ldst_val),
.io_lsu_dis_uops_2_bits_dst_rtype (_core_io_lsu_dis_uops_2_bits_dst_rtype),
.io_lsu_dis_uops_2_bits_lrs1_rtype (_core_io_lsu_dis_uops_2_bits_lrs1_rtype),
.io_lsu_dis_uops_2_bits_lrs2_rtype (_core_io_lsu_dis_uops_2_bits_lrs2_rtype),
.io_lsu_dis_uops_2_bits_frs3_en (_core_io_lsu_dis_uops_2_bits_frs3_en),
.io_lsu_dis_uops_2_bits_fp_val (_core_io_lsu_dis_uops_2_bits_fp_val),
.io_lsu_dis_uops_2_bits_fp_single (_core_io_lsu_dis_uops_2_bits_fp_single),
.io_lsu_dis_uops_2_bits_xcpt_pf_if (_core_io_lsu_dis_uops_2_bits_xcpt_pf_if),
.io_lsu_dis_uops_2_bits_xcpt_ae_if (_core_io_lsu_dis_uops_2_bits_xcpt_ae_if),
.io_lsu_dis_uops_2_bits_xcpt_ma_if (_core_io_lsu_dis_uops_2_bits_xcpt_ma_if),
.io_lsu_dis_uops_2_bits_bp_debug_if (_core_io_lsu_dis_uops_2_bits_bp_debug_if),
.io_lsu_dis_uops_2_bits_bp_xcpt_if (_core_io_lsu_dis_uops_2_bits_bp_xcpt_if),
.io_lsu_dis_uops_2_bits_debug_fsrc (_core_io_lsu_dis_uops_2_bits_debug_fsrc),
.io_lsu_dis_uops_2_bits_debug_tsrc (_core_io_lsu_dis_uops_2_bits_debug_tsrc),
.io_lsu_dis_ldq_idx_0 (_lsu_io_core_dis_ldq_idx_0), // @[tile.scala:160:20]
.io_lsu_dis_ldq_idx_1 (_lsu_io_core_dis_ldq_idx_1), // @[tile.scala:160:20]
.io_lsu_dis_ldq_idx_2 (_lsu_io_core_dis_ldq_idx_2), // @[tile.scala:160:20]
.io_lsu_dis_stq_idx_0 (_lsu_io_core_dis_stq_idx_0), // @[tile.scala:160:20]
.io_lsu_dis_stq_idx_1 (_lsu_io_core_dis_stq_idx_1), // @[tile.scala:160:20]
.io_lsu_dis_stq_idx_2 (_lsu_io_core_dis_stq_idx_2), // @[tile.scala:160:20]
.io_lsu_ldq_full_0 (_lsu_io_core_ldq_full_0), // @[tile.scala:160:20]
.io_lsu_ldq_full_1 (_lsu_io_core_ldq_full_1), // @[tile.scala:160:20]
.io_lsu_ldq_full_2 (_lsu_io_core_ldq_full_2), // @[tile.scala:160:20]
.io_lsu_stq_full_0 (_lsu_io_core_stq_full_0), // @[tile.scala:160:20]
.io_lsu_stq_full_1 (_lsu_io_core_stq_full_1), // @[tile.scala:160:20]
.io_lsu_stq_full_2 (_lsu_io_core_stq_full_2), // @[tile.scala:160:20]
.io_lsu_fp_stdata_ready (_lsu_io_core_fp_stdata_ready), // @[tile.scala:160:20]
.io_lsu_fp_stdata_valid (_core_io_lsu_fp_stdata_valid),
.io_lsu_fp_stdata_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_uop_uopc),
.io_lsu_fp_stdata_bits_uop_inst (_core_io_lsu_fp_stdata_bits_uop_inst),
.io_lsu_fp_stdata_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_uop_debug_inst),
.io_lsu_fp_stdata_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_uop_is_rvc),
.io_lsu_fp_stdata_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_uop_debug_pc),
.io_lsu_fp_stdata_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_uop_iq_type),
.io_lsu_fp_stdata_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_uop_fu_code),
.io_lsu_fp_stdata_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_uop_ctrl_br_type),
.io_lsu_fp_stdata_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op1_sel),
.io_lsu_fp_stdata_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op2_sel),
.io_lsu_fp_stdata_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_imm_sel),
.io_lsu_fp_stdata_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_uop_ctrl_op_fcn),
.io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw),
.io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd),
.io_lsu_fp_stdata_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_load),
.io_lsu_fp_stdata_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_sta),
.io_lsu_fp_stdata_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_std),
.io_lsu_fp_stdata_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_uop_iw_state),
.io_lsu_fp_stdata_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p1_poisoned),
.io_lsu_fp_stdata_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p2_poisoned),
.io_lsu_fp_stdata_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_uop_is_br),
.io_lsu_fp_stdata_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_uop_is_jalr),
.io_lsu_fp_stdata_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_uop_is_jal),
.io_lsu_fp_stdata_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_uop_is_sfb),
.io_lsu_fp_stdata_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_uop_br_mask),
.io_lsu_fp_stdata_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_uop_br_tag),
.io_lsu_fp_stdata_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_uop_ftq_idx),
.io_lsu_fp_stdata_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_uop_edge_inst),
.io_lsu_fp_stdata_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_uop_pc_lob),
.io_lsu_fp_stdata_bits_uop_taken (_core_io_lsu_fp_stdata_bits_uop_taken),
.io_lsu_fp_stdata_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_uop_imm_packed),
.io_lsu_fp_stdata_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_uop_csr_addr),
.io_lsu_fp_stdata_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_uop_rob_idx),
.io_lsu_fp_stdata_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_uop_ldq_idx),
.io_lsu_fp_stdata_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_uop_stq_idx),
.io_lsu_fp_stdata_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_uop_rxq_idx),
.io_lsu_fp_stdata_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_uop_pdst),
.io_lsu_fp_stdata_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_uop_prs1),
.io_lsu_fp_stdata_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_uop_prs2),
.io_lsu_fp_stdata_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_uop_prs3),
.io_lsu_fp_stdata_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_uop_ppred),
.io_lsu_fp_stdata_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_uop_prs1_busy),
.io_lsu_fp_stdata_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_uop_prs2_busy),
.io_lsu_fp_stdata_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_uop_prs3_busy),
.io_lsu_fp_stdata_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_uop_ppred_busy),
.io_lsu_fp_stdata_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_uop_stale_pdst),
.io_lsu_fp_stdata_bits_uop_exception (_core_io_lsu_fp_stdata_bits_uop_exception),
.io_lsu_fp_stdata_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_uop_exc_cause),
.io_lsu_fp_stdata_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_uop_bypassable),
.io_lsu_fp_stdata_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_uop_mem_cmd),
.io_lsu_fp_stdata_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_uop_mem_size),
.io_lsu_fp_stdata_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_uop_mem_signed),
.io_lsu_fp_stdata_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_uop_is_fence),
.io_lsu_fp_stdata_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_uop_is_fencei),
.io_lsu_fp_stdata_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_uop_is_amo),
.io_lsu_fp_stdata_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_uop_uses_ldq),
.io_lsu_fp_stdata_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_uop_uses_stq),
.io_lsu_fp_stdata_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_uop_is_sys_pc2epc),
.io_lsu_fp_stdata_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_uop_is_unique),
.io_lsu_fp_stdata_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_uop_flush_on_commit),
.io_lsu_fp_stdata_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_uop_ldst_is_rs1),
.io_lsu_fp_stdata_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_uop_ldst),
.io_lsu_fp_stdata_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_uop_lrs1),
.io_lsu_fp_stdata_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_uop_lrs2),
.io_lsu_fp_stdata_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_uop_lrs3),
.io_lsu_fp_stdata_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_uop_ldst_val),
.io_lsu_fp_stdata_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_uop_dst_rtype),
.io_lsu_fp_stdata_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs1_rtype),
.io_lsu_fp_stdata_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs2_rtype),
.io_lsu_fp_stdata_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_uop_frs3_en),
.io_lsu_fp_stdata_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_uop_fp_val),
.io_lsu_fp_stdata_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_uop_fp_single),
.io_lsu_fp_stdata_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_pf_if),
.io_lsu_fp_stdata_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ae_if),
.io_lsu_fp_stdata_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ma_if),
.io_lsu_fp_stdata_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_uop_bp_debug_if),
.io_lsu_fp_stdata_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_uop_bp_xcpt_if),
.io_lsu_fp_stdata_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_uop_debug_fsrc),
.io_lsu_fp_stdata_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_uop_debug_tsrc),
.io_lsu_fp_stdata_bits_data (_core_io_lsu_fp_stdata_bits_data),
.io_lsu_fp_stdata_bits_predicated (_core_io_lsu_fp_stdata_bits_predicated),
.io_lsu_fp_stdata_bits_fflags_valid (_core_io_lsu_fp_stdata_bits_fflags_valid),
.io_lsu_fp_stdata_bits_fflags_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uopc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_inst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type),
.io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned),
.io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_br),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb),
.io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask),
.io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob),
.io_lsu_fp_stdata_bits_fflags_bits_uop_taken (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_taken),
.io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed),
.io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr),
.io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx),
.io_lsu_fp_stdata_bits_fflags_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pdst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy),
.io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_exception (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exception),
.io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause),
.io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable),
.io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd),
.io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size),
.io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo),
.io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq),
.io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique),
.io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3),
.io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val),
.io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype),
.io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype),
.io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en),
.io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val),
.io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single),
.io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc),
.io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc),
.io_lsu_fp_stdata_bits_fflags_bits_flags (_core_io_lsu_fp_stdata_bits_fflags_bits_flags),
.io_lsu_commit_valids_0 (_core_io_lsu_commit_valids_0),
.io_lsu_commit_valids_1 (_core_io_lsu_commit_valids_1),
.io_lsu_commit_valids_2 (_core_io_lsu_commit_valids_2),
.io_lsu_commit_arch_valids_0 (_core_io_lsu_commit_arch_valids_0),
.io_lsu_commit_arch_valids_1 (_core_io_lsu_commit_arch_valids_1),
.io_lsu_commit_arch_valids_2 (_core_io_lsu_commit_arch_valids_2),
.io_lsu_commit_uops_0_uopc (_core_io_lsu_commit_uops_0_uopc),
.io_lsu_commit_uops_0_inst (_core_io_lsu_commit_uops_0_inst),
.io_lsu_commit_uops_0_debug_inst (_core_io_lsu_commit_uops_0_debug_inst),
.io_lsu_commit_uops_0_is_rvc (_core_io_lsu_commit_uops_0_is_rvc),
.io_lsu_commit_uops_0_debug_pc (_core_io_lsu_commit_uops_0_debug_pc),
.io_lsu_commit_uops_0_iq_type (_core_io_lsu_commit_uops_0_iq_type),
.io_lsu_commit_uops_0_fu_code (_core_io_lsu_commit_uops_0_fu_code),
.io_lsu_commit_uops_0_ctrl_br_type (_core_io_lsu_commit_uops_0_ctrl_br_type),
.io_lsu_commit_uops_0_ctrl_op1_sel (_core_io_lsu_commit_uops_0_ctrl_op1_sel),
.io_lsu_commit_uops_0_ctrl_op2_sel (_core_io_lsu_commit_uops_0_ctrl_op2_sel),
.io_lsu_commit_uops_0_ctrl_imm_sel (_core_io_lsu_commit_uops_0_ctrl_imm_sel),
.io_lsu_commit_uops_0_ctrl_op_fcn (_core_io_lsu_commit_uops_0_ctrl_op_fcn),
.io_lsu_commit_uops_0_ctrl_fcn_dw (_core_io_lsu_commit_uops_0_ctrl_fcn_dw),
.io_lsu_commit_uops_0_ctrl_csr_cmd (_core_io_lsu_commit_uops_0_ctrl_csr_cmd),
.io_lsu_commit_uops_0_ctrl_is_load (_core_io_lsu_commit_uops_0_ctrl_is_load),
.io_lsu_commit_uops_0_ctrl_is_sta (_core_io_lsu_commit_uops_0_ctrl_is_sta),
.io_lsu_commit_uops_0_ctrl_is_std (_core_io_lsu_commit_uops_0_ctrl_is_std),
.io_lsu_commit_uops_0_iw_state (_core_io_lsu_commit_uops_0_iw_state),
.io_lsu_commit_uops_0_iw_p1_poisoned (_core_io_lsu_commit_uops_0_iw_p1_poisoned),
.io_lsu_commit_uops_0_iw_p2_poisoned (_core_io_lsu_commit_uops_0_iw_p2_poisoned),
.io_lsu_commit_uops_0_is_br (_core_io_lsu_commit_uops_0_is_br),
.io_lsu_commit_uops_0_is_jalr (_core_io_lsu_commit_uops_0_is_jalr),
.io_lsu_commit_uops_0_is_jal (_core_io_lsu_commit_uops_0_is_jal),
.io_lsu_commit_uops_0_is_sfb (_core_io_lsu_commit_uops_0_is_sfb),
.io_lsu_commit_uops_0_br_mask (_core_io_lsu_commit_uops_0_br_mask),
.io_lsu_commit_uops_0_br_tag (_core_io_lsu_commit_uops_0_br_tag),
.io_lsu_commit_uops_0_ftq_idx (_core_io_lsu_commit_uops_0_ftq_idx),
.io_lsu_commit_uops_0_edge_inst (_core_io_lsu_commit_uops_0_edge_inst),
.io_lsu_commit_uops_0_pc_lob (_core_io_lsu_commit_uops_0_pc_lob),
.io_lsu_commit_uops_0_taken (_core_io_lsu_commit_uops_0_taken),
.io_lsu_commit_uops_0_imm_packed (_core_io_lsu_commit_uops_0_imm_packed),
.io_lsu_commit_uops_0_csr_addr (_core_io_lsu_commit_uops_0_csr_addr),
.io_lsu_commit_uops_0_rob_idx (_core_io_lsu_commit_uops_0_rob_idx),
.io_lsu_commit_uops_0_ldq_idx (_core_io_lsu_commit_uops_0_ldq_idx),
.io_lsu_commit_uops_0_stq_idx (_core_io_lsu_commit_uops_0_stq_idx),
.io_lsu_commit_uops_0_rxq_idx (_core_io_lsu_commit_uops_0_rxq_idx),
.io_lsu_commit_uops_0_pdst (_core_io_lsu_commit_uops_0_pdst),
.io_lsu_commit_uops_0_prs1 (_core_io_lsu_commit_uops_0_prs1),
.io_lsu_commit_uops_0_prs2 (_core_io_lsu_commit_uops_0_prs2),
.io_lsu_commit_uops_0_prs3 (_core_io_lsu_commit_uops_0_prs3),
.io_lsu_commit_uops_0_ppred (_core_io_lsu_commit_uops_0_ppred),
.io_lsu_commit_uops_0_prs1_busy (_core_io_lsu_commit_uops_0_prs1_busy),
.io_lsu_commit_uops_0_prs2_busy (_core_io_lsu_commit_uops_0_prs2_busy),
.io_lsu_commit_uops_0_prs3_busy (_core_io_lsu_commit_uops_0_prs3_busy),
.io_lsu_commit_uops_0_ppred_busy (_core_io_lsu_commit_uops_0_ppred_busy),
.io_lsu_commit_uops_0_stale_pdst (_core_io_lsu_commit_uops_0_stale_pdst),
.io_lsu_commit_uops_0_exception (_core_io_lsu_commit_uops_0_exception),
.io_lsu_commit_uops_0_exc_cause (_core_io_lsu_commit_uops_0_exc_cause),
.io_lsu_commit_uops_0_bypassable (_core_io_lsu_commit_uops_0_bypassable),
.io_lsu_commit_uops_0_mem_cmd (_core_io_lsu_commit_uops_0_mem_cmd),
.io_lsu_commit_uops_0_mem_size (_core_io_lsu_commit_uops_0_mem_size),
.io_lsu_commit_uops_0_mem_signed (_core_io_lsu_commit_uops_0_mem_signed),
.io_lsu_commit_uops_0_is_fence (_core_io_lsu_commit_uops_0_is_fence),
.io_lsu_commit_uops_0_is_fencei (_core_io_lsu_commit_uops_0_is_fencei),
.io_lsu_commit_uops_0_is_amo (_core_io_lsu_commit_uops_0_is_amo),
.io_lsu_commit_uops_0_uses_ldq (_core_io_lsu_commit_uops_0_uses_ldq),
.io_lsu_commit_uops_0_uses_stq (_core_io_lsu_commit_uops_0_uses_stq),
.io_lsu_commit_uops_0_is_sys_pc2epc (_core_io_lsu_commit_uops_0_is_sys_pc2epc),
.io_lsu_commit_uops_0_is_unique (_core_io_lsu_commit_uops_0_is_unique),
.io_lsu_commit_uops_0_flush_on_commit (_core_io_lsu_commit_uops_0_flush_on_commit),
.io_lsu_commit_uops_0_ldst_is_rs1 (_core_io_lsu_commit_uops_0_ldst_is_rs1),
.io_lsu_commit_uops_0_ldst (_core_io_lsu_commit_uops_0_ldst),
.io_lsu_commit_uops_0_lrs1 (_core_io_lsu_commit_uops_0_lrs1),
.io_lsu_commit_uops_0_lrs2 (_core_io_lsu_commit_uops_0_lrs2),
.io_lsu_commit_uops_0_lrs3 (_core_io_lsu_commit_uops_0_lrs3),
.io_lsu_commit_uops_0_ldst_val (_core_io_lsu_commit_uops_0_ldst_val),
.io_lsu_commit_uops_0_dst_rtype (_core_io_lsu_commit_uops_0_dst_rtype),
.io_lsu_commit_uops_0_lrs1_rtype (_core_io_lsu_commit_uops_0_lrs1_rtype),
.io_lsu_commit_uops_0_lrs2_rtype (_core_io_lsu_commit_uops_0_lrs2_rtype),
.io_lsu_commit_uops_0_frs3_en (_core_io_lsu_commit_uops_0_frs3_en),
.io_lsu_commit_uops_0_fp_val (_core_io_lsu_commit_uops_0_fp_val),
.io_lsu_commit_uops_0_fp_single (_core_io_lsu_commit_uops_0_fp_single),
.io_lsu_commit_uops_0_xcpt_pf_if (_core_io_lsu_commit_uops_0_xcpt_pf_if),
.io_lsu_commit_uops_0_xcpt_ae_if (_core_io_lsu_commit_uops_0_xcpt_ae_if),
.io_lsu_commit_uops_0_xcpt_ma_if (_core_io_lsu_commit_uops_0_xcpt_ma_if),
.io_lsu_commit_uops_0_bp_debug_if (_core_io_lsu_commit_uops_0_bp_debug_if),
.io_lsu_commit_uops_0_bp_xcpt_if (_core_io_lsu_commit_uops_0_bp_xcpt_if),
.io_lsu_commit_uops_0_debug_fsrc (_core_io_lsu_commit_uops_0_debug_fsrc),
.io_lsu_commit_uops_0_debug_tsrc (_core_io_lsu_commit_uops_0_debug_tsrc),
.io_lsu_commit_uops_1_uopc (_core_io_lsu_commit_uops_1_uopc),
.io_lsu_commit_uops_1_inst (_core_io_lsu_commit_uops_1_inst),
.io_lsu_commit_uops_1_debug_inst (_core_io_lsu_commit_uops_1_debug_inst),
.io_lsu_commit_uops_1_is_rvc (_core_io_lsu_commit_uops_1_is_rvc),
.io_lsu_commit_uops_1_debug_pc (_core_io_lsu_commit_uops_1_debug_pc),
.io_lsu_commit_uops_1_iq_type (_core_io_lsu_commit_uops_1_iq_type),
.io_lsu_commit_uops_1_fu_code (_core_io_lsu_commit_uops_1_fu_code),
.io_lsu_commit_uops_1_ctrl_br_type (_core_io_lsu_commit_uops_1_ctrl_br_type),
.io_lsu_commit_uops_1_ctrl_op1_sel (_core_io_lsu_commit_uops_1_ctrl_op1_sel),
.io_lsu_commit_uops_1_ctrl_op2_sel (_core_io_lsu_commit_uops_1_ctrl_op2_sel),
.io_lsu_commit_uops_1_ctrl_imm_sel (_core_io_lsu_commit_uops_1_ctrl_imm_sel),
.io_lsu_commit_uops_1_ctrl_op_fcn (_core_io_lsu_commit_uops_1_ctrl_op_fcn),
.io_lsu_commit_uops_1_ctrl_fcn_dw (_core_io_lsu_commit_uops_1_ctrl_fcn_dw),
.io_lsu_commit_uops_1_ctrl_csr_cmd (_core_io_lsu_commit_uops_1_ctrl_csr_cmd),
.io_lsu_commit_uops_1_ctrl_is_load (_core_io_lsu_commit_uops_1_ctrl_is_load),
.io_lsu_commit_uops_1_ctrl_is_sta (_core_io_lsu_commit_uops_1_ctrl_is_sta),
.io_lsu_commit_uops_1_ctrl_is_std (_core_io_lsu_commit_uops_1_ctrl_is_std),
.io_lsu_commit_uops_1_iw_state (_core_io_lsu_commit_uops_1_iw_state),
.io_lsu_commit_uops_1_iw_p1_poisoned (_core_io_lsu_commit_uops_1_iw_p1_poisoned),
.io_lsu_commit_uops_1_iw_p2_poisoned (_core_io_lsu_commit_uops_1_iw_p2_poisoned),
.io_lsu_commit_uops_1_is_br (_core_io_lsu_commit_uops_1_is_br),
.io_lsu_commit_uops_1_is_jalr (_core_io_lsu_commit_uops_1_is_jalr),
.io_lsu_commit_uops_1_is_jal (_core_io_lsu_commit_uops_1_is_jal),
.io_lsu_commit_uops_1_is_sfb (_core_io_lsu_commit_uops_1_is_sfb),
.io_lsu_commit_uops_1_br_mask (_core_io_lsu_commit_uops_1_br_mask),
.io_lsu_commit_uops_1_br_tag (_core_io_lsu_commit_uops_1_br_tag),
.io_lsu_commit_uops_1_ftq_idx (_core_io_lsu_commit_uops_1_ftq_idx),
.io_lsu_commit_uops_1_edge_inst (_core_io_lsu_commit_uops_1_edge_inst),
.io_lsu_commit_uops_1_pc_lob (_core_io_lsu_commit_uops_1_pc_lob),
.io_lsu_commit_uops_1_taken (_core_io_lsu_commit_uops_1_taken),
.io_lsu_commit_uops_1_imm_packed (_core_io_lsu_commit_uops_1_imm_packed),
.io_lsu_commit_uops_1_csr_addr (_core_io_lsu_commit_uops_1_csr_addr),
.io_lsu_commit_uops_1_rob_idx (_core_io_lsu_commit_uops_1_rob_idx),
.io_lsu_commit_uops_1_ldq_idx (_core_io_lsu_commit_uops_1_ldq_idx),
.io_lsu_commit_uops_1_stq_idx (_core_io_lsu_commit_uops_1_stq_idx),
.io_lsu_commit_uops_1_rxq_idx (_core_io_lsu_commit_uops_1_rxq_idx),
.io_lsu_commit_uops_1_pdst (_core_io_lsu_commit_uops_1_pdst),
.io_lsu_commit_uops_1_prs1 (_core_io_lsu_commit_uops_1_prs1),
.io_lsu_commit_uops_1_prs2 (_core_io_lsu_commit_uops_1_prs2),
.io_lsu_commit_uops_1_prs3 (_core_io_lsu_commit_uops_1_prs3),
.io_lsu_commit_uops_1_ppred (_core_io_lsu_commit_uops_1_ppred),
.io_lsu_commit_uops_1_prs1_busy (_core_io_lsu_commit_uops_1_prs1_busy),
.io_lsu_commit_uops_1_prs2_busy (_core_io_lsu_commit_uops_1_prs2_busy),
.io_lsu_commit_uops_1_prs3_busy (_core_io_lsu_commit_uops_1_prs3_busy),
.io_lsu_commit_uops_1_ppred_busy (_core_io_lsu_commit_uops_1_ppred_busy),
.io_lsu_commit_uops_1_stale_pdst (_core_io_lsu_commit_uops_1_stale_pdst),
.io_lsu_commit_uops_1_exception (_core_io_lsu_commit_uops_1_exception),
.io_lsu_commit_uops_1_exc_cause (_core_io_lsu_commit_uops_1_exc_cause),
.io_lsu_commit_uops_1_bypassable (_core_io_lsu_commit_uops_1_bypassable),
.io_lsu_commit_uops_1_mem_cmd (_core_io_lsu_commit_uops_1_mem_cmd),
.io_lsu_commit_uops_1_mem_size (_core_io_lsu_commit_uops_1_mem_size),
.io_lsu_commit_uops_1_mem_signed (_core_io_lsu_commit_uops_1_mem_signed),
.io_lsu_commit_uops_1_is_fence (_core_io_lsu_commit_uops_1_is_fence),
.io_lsu_commit_uops_1_is_fencei (_core_io_lsu_commit_uops_1_is_fencei),
.io_lsu_commit_uops_1_is_amo (_core_io_lsu_commit_uops_1_is_amo),
.io_lsu_commit_uops_1_uses_ldq (_core_io_lsu_commit_uops_1_uses_ldq),
.io_lsu_commit_uops_1_uses_stq (_core_io_lsu_commit_uops_1_uses_stq),
.io_lsu_commit_uops_1_is_sys_pc2epc (_core_io_lsu_commit_uops_1_is_sys_pc2epc),
.io_lsu_commit_uops_1_is_unique (_core_io_lsu_commit_uops_1_is_unique),
.io_lsu_commit_uops_1_flush_on_commit (_core_io_lsu_commit_uops_1_flush_on_commit),
.io_lsu_commit_uops_1_ldst_is_rs1 (_core_io_lsu_commit_uops_1_ldst_is_rs1),
.io_lsu_commit_uops_1_ldst (_core_io_lsu_commit_uops_1_ldst),
.io_lsu_commit_uops_1_lrs1 (_core_io_lsu_commit_uops_1_lrs1),
.io_lsu_commit_uops_1_lrs2 (_core_io_lsu_commit_uops_1_lrs2),
.io_lsu_commit_uops_1_lrs3 (_core_io_lsu_commit_uops_1_lrs3),
.io_lsu_commit_uops_1_ldst_val (_core_io_lsu_commit_uops_1_ldst_val),
.io_lsu_commit_uops_1_dst_rtype (_core_io_lsu_commit_uops_1_dst_rtype),
.io_lsu_commit_uops_1_lrs1_rtype (_core_io_lsu_commit_uops_1_lrs1_rtype),
.io_lsu_commit_uops_1_lrs2_rtype (_core_io_lsu_commit_uops_1_lrs2_rtype),
.io_lsu_commit_uops_1_frs3_en (_core_io_lsu_commit_uops_1_frs3_en),
.io_lsu_commit_uops_1_fp_val (_core_io_lsu_commit_uops_1_fp_val),
.io_lsu_commit_uops_1_fp_single (_core_io_lsu_commit_uops_1_fp_single),
.io_lsu_commit_uops_1_xcpt_pf_if (_core_io_lsu_commit_uops_1_xcpt_pf_if),
.io_lsu_commit_uops_1_xcpt_ae_if (_core_io_lsu_commit_uops_1_xcpt_ae_if),
.io_lsu_commit_uops_1_xcpt_ma_if (_core_io_lsu_commit_uops_1_xcpt_ma_if),
.io_lsu_commit_uops_1_bp_debug_if (_core_io_lsu_commit_uops_1_bp_debug_if),
.io_lsu_commit_uops_1_bp_xcpt_if (_core_io_lsu_commit_uops_1_bp_xcpt_if),
.io_lsu_commit_uops_1_debug_fsrc (_core_io_lsu_commit_uops_1_debug_fsrc),
.io_lsu_commit_uops_1_debug_tsrc (_core_io_lsu_commit_uops_1_debug_tsrc),
.io_lsu_commit_uops_2_uopc (_core_io_lsu_commit_uops_2_uopc),
.io_lsu_commit_uops_2_inst (_core_io_lsu_commit_uops_2_inst),
.io_lsu_commit_uops_2_debug_inst (_core_io_lsu_commit_uops_2_debug_inst),
.io_lsu_commit_uops_2_is_rvc (_core_io_lsu_commit_uops_2_is_rvc),
.io_lsu_commit_uops_2_debug_pc (_core_io_lsu_commit_uops_2_debug_pc),
.io_lsu_commit_uops_2_iq_type (_core_io_lsu_commit_uops_2_iq_type),
.io_lsu_commit_uops_2_fu_code (_core_io_lsu_commit_uops_2_fu_code),
.io_lsu_commit_uops_2_ctrl_br_type (_core_io_lsu_commit_uops_2_ctrl_br_type),
.io_lsu_commit_uops_2_ctrl_op1_sel (_core_io_lsu_commit_uops_2_ctrl_op1_sel),
.io_lsu_commit_uops_2_ctrl_op2_sel (_core_io_lsu_commit_uops_2_ctrl_op2_sel),
.io_lsu_commit_uops_2_ctrl_imm_sel (_core_io_lsu_commit_uops_2_ctrl_imm_sel),
.io_lsu_commit_uops_2_ctrl_op_fcn (_core_io_lsu_commit_uops_2_ctrl_op_fcn),
.io_lsu_commit_uops_2_ctrl_fcn_dw (_core_io_lsu_commit_uops_2_ctrl_fcn_dw),
.io_lsu_commit_uops_2_ctrl_csr_cmd (_core_io_lsu_commit_uops_2_ctrl_csr_cmd),
.io_lsu_commit_uops_2_ctrl_is_load (_core_io_lsu_commit_uops_2_ctrl_is_load),
.io_lsu_commit_uops_2_ctrl_is_sta (_core_io_lsu_commit_uops_2_ctrl_is_sta),
.io_lsu_commit_uops_2_ctrl_is_std (_core_io_lsu_commit_uops_2_ctrl_is_std),
.io_lsu_commit_uops_2_iw_state (_core_io_lsu_commit_uops_2_iw_state),
.io_lsu_commit_uops_2_iw_p1_poisoned (_core_io_lsu_commit_uops_2_iw_p1_poisoned),
.io_lsu_commit_uops_2_iw_p2_poisoned (_core_io_lsu_commit_uops_2_iw_p2_poisoned),
.io_lsu_commit_uops_2_is_br (_core_io_lsu_commit_uops_2_is_br),
.io_lsu_commit_uops_2_is_jalr (_core_io_lsu_commit_uops_2_is_jalr),
.io_lsu_commit_uops_2_is_jal (_core_io_lsu_commit_uops_2_is_jal),
.io_lsu_commit_uops_2_is_sfb (_core_io_lsu_commit_uops_2_is_sfb),
.io_lsu_commit_uops_2_br_mask (_core_io_lsu_commit_uops_2_br_mask),
.io_lsu_commit_uops_2_br_tag (_core_io_lsu_commit_uops_2_br_tag),
.io_lsu_commit_uops_2_ftq_idx (_core_io_lsu_commit_uops_2_ftq_idx),
.io_lsu_commit_uops_2_edge_inst (_core_io_lsu_commit_uops_2_edge_inst),
.io_lsu_commit_uops_2_pc_lob (_core_io_lsu_commit_uops_2_pc_lob),
.io_lsu_commit_uops_2_taken (_core_io_lsu_commit_uops_2_taken),
.io_lsu_commit_uops_2_imm_packed (_core_io_lsu_commit_uops_2_imm_packed),
.io_lsu_commit_uops_2_csr_addr (_core_io_lsu_commit_uops_2_csr_addr),
.io_lsu_commit_uops_2_rob_idx (_core_io_lsu_commit_uops_2_rob_idx),
.io_lsu_commit_uops_2_ldq_idx (_core_io_lsu_commit_uops_2_ldq_idx),
.io_lsu_commit_uops_2_stq_idx (_core_io_lsu_commit_uops_2_stq_idx),
.io_lsu_commit_uops_2_rxq_idx (_core_io_lsu_commit_uops_2_rxq_idx),
.io_lsu_commit_uops_2_pdst (_core_io_lsu_commit_uops_2_pdst),
.io_lsu_commit_uops_2_prs1 (_core_io_lsu_commit_uops_2_prs1),
.io_lsu_commit_uops_2_prs2 (_core_io_lsu_commit_uops_2_prs2),
.io_lsu_commit_uops_2_prs3 (_core_io_lsu_commit_uops_2_prs3),
.io_lsu_commit_uops_2_ppred (_core_io_lsu_commit_uops_2_ppred),
.io_lsu_commit_uops_2_prs1_busy (_core_io_lsu_commit_uops_2_prs1_busy),
.io_lsu_commit_uops_2_prs2_busy (_core_io_lsu_commit_uops_2_prs2_busy),
.io_lsu_commit_uops_2_prs3_busy (_core_io_lsu_commit_uops_2_prs3_busy),
.io_lsu_commit_uops_2_ppred_busy (_core_io_lsu_commit_uops_2_ppred_busy),
.io_lsu_commit_uops_2_stale_pdst (_core_io_lsu_commit_uops_2_stale_pdst),
.io_lsu_commit_uops_2_exception (_core_io_lsu_commit_uops_2_exception),
.io_lsu_commit_uops_2_exc_cause (_core_io_lsu_commit_uops_2_exc_cause),
.io_lsu_commit_uops_2_bypassable (_core_io_lsu_commit_uops_2_bypassable),
.io_lsu_commit_uops_2_mem_cmd (_core_io_lsu_commit_uops_2_mem_cmd),
.io_lsu_commit_uops_2_mem_size (_core_io_lsu_commit_uops_2_mem_size),
.io_lsu_commit_uops_2_mem_signed (_core_io_lsu_commit_uops_2_mem_signed),
.io_lsu_commit_uops_2_is_fence (_core_io_lsu_commit_uops_2_is_fence),
.io_lsu_commit_uops_2_is_fencei (_core_io_lsu_commit_uops_2_is_fencei),
.io_lsu_commit_uops_2_is_amo (_core_io_lsu_commit_uops_2_is_amo),
.io_lsu_commit_uops_2_uses_ldq (_core_io_lsu_commit_uops_2_uses_ldq),
.io_lsu_commit_uops_2_uses_stq (_core_io_lsu_commit_uops_2_uses_stq),
.io_lsu_commit_uops_2_is_sys_pc2epc (_core_io_lsu_commit_uops_2_is_sys_pc2epc),
.io_lsu_commit_uops_2_is_unique (_core_io_lsu_commit_uops_2_is_unique),
.io_lsu_commit_uops_2_flush_on_commit (_core_io_lsu_commit_uops_2_flush_on_commit),
.io_lsu_commit_uops_2_ldst_is_rs1 (_core_io_lsu_commit_uops_2_ldst_is_rs1),
.io_lsu_commit_uops_2_ldst (_core_io_lsu_commit_uops_2_ldst),
.io_lsu_commit_uops_2_lrs1 (_core_io_lsu_commit_uops_2_lrs1),
.io_lsu_commit_uops_2_lrs2 (_core_io_lsu_commit_uops_2_lrs2),
.io_lsu_commit_uops_2_lrs3 (_core_io_lsu_commit_uops_2_lrs3),
.io_lsu_commit_uops_2_ldst_val (_core_io_lsu_commit_uops_2_ldst_val),
.io_lsu_commit_uops_2_dst_rtype (_core_io_lsu_commit_uops_2_dst_rtype),
.io_lsu_commit_uops_2_lrs1_rtype (_core_io_lsu_commit_uops_2_lrs1_rtype),
.io_lsu_commit_uops_2_lrs2_rtype (_core_io_lsu_commit_uops_2_lrs2_rtype),
.io_lsu_commit_uops_2_frs3_en (_core_io_lsu_commit_uops_2_frs3_en),
.io_lsu_commit_uops_2_fp_val (_core_io_lsu_commit_uops_2_fp_val),
.io_lsu_commit_uops_2_fp_single (_core_io_lsu_commit_uops_2_fp_single),
.io_lsu_commit_uops_2_xcpt_pf_if (_core_io_lsu_commit_uops_2_xcpt_pf_if),
.io_lsu_commit_uops_2_xcpt_ae_if (_core_io_lsu_commit_uops_2_xcpt_ae_if),
.io_lsu_commit_uops_2_xcpt_ma_if (_core_io_lsu_commit_uops_2_xcpt_ma_if),
.io_lsu_commit_uops_2_bp_debug_if (_core_io_lsu_commit_uops_2_bp_debug_if),
.io_lsu_commit_uops_2_bp_xcpt_if (_core_io_lsu_commit_uops_2_bp_xcpt_if),
.io_lsu_commit_uops_2_debug_fsrc (_core_io_lsu_commit_uops_2_debug_fsrc),
.io_lsu_commit_uops_2_debug_tsrc (_core_io_lsu_commit_uops_2_debug_tsrc),
.io_lsu_commit_fflags_valid (_core_io_lsu_commit_fflags_valid),
.io_lsu_commit_fflags_bits (_core_io_lsu_commit_fflags_bits),
.io_lsu_commit_debug_insts_0 (_core_io_lsu_commit_debug_insts_0),
.io_lsu_commit_debug_insts_1 (_core_io_lsu_commit_debug_insts_1),
.io_lsu_commit_debug_insts_2 (_core_io_lsu_commit_debug_insts_2),
.io_lsu_commit_rbk_valids_0 (_core_io_lsu_commit_rbk_valids_0),
.io_lsu_commit_rbk_valids_1 (_core_io_lsu_commit_rbk_valids_1),
.io_lsu_commit_rbk_valids_2 (_core_io_lsu_commit_rbk_valids_2),
.io_lsu_commit_rollback (_core_io_lsu_commit_rollback),
.io_lsu_commit_debug_wdata_0 (_core_io_lsu_commit_debug_wdata_0),
.io_lsu_commit_debug_wdata_1 (_core_io_lsu_commit_debug_wdata_1),
.io_lsu_commit_debug_wdata_2 (_core_io_lsu_commit_debug_wdata_2),
.io_lsu_commit_load_at_rob_head (_core_io_lsu_commit_load_at_rob_head),
.io_lsu_clr_bsy_0_valid (_lsu_io_core_clr_bsy_0_valid), // @[tile.scala:160:20]
.io_lsu_clr_bsy_0_bits (_lsu_io_core_clr_bsy_0_bits), // @[tile.scala:160:20]
.io_lsu_clr_bsy_1_valid (_lsu_io_core_clr_bsy_1_valid), // @[tile.scala:160:20]
.io_lsu_clr_bsy_1_bits (_lsu_io_core_clr_bsy_1_bits), // @[tile.scala:160:20]
.io_lsu_clr_unsafe_0_bits (_lsu_io_core_clr_unsafe_0_bits), // @[tile.scala:160:20]
.io_lsu_fence_dmem (_core_io_lsu_fence_dmem),
.io_lsu_spec_ld_wakeup_0_valid (_lsu_io_core_spec_ld_wakeup_0_valid), // @[tile.scala:160:20]
.io_lsu_spec_ld_wakeup_0_bits (_lsu_io_core_spec_ld_wakeup_0_bits), // @[tile.scala:160:20]
.io_lsu_ld_miss (_lsu_io_core_ld_miss), // @[tile.scala:160:20]
.io_lsu_brupdate_b1_resolve_mask (_core_io_lsu_brupdate_b1_resolve_mask),
.io_lsu_brupdate_b1_mispredict_mask (_core_io_lsu_brupdate_b1_mispredict_mask),
.io_lsu_brupdate_b2_uop_uopc (_core_io_lsu_brupdate_b2_uop_uopc),
.io_lsu_brupdate_b2_uop_inst (_core_io_lsu_brupdate_b2_uop_inst),
.io_lsu_brupdate_b2_uop_debug_inst (_core_io_lsu_brupdate_b2_uop_debug_inst),
.io_lsu_brupdate_b2_uop_is_rvc (_core_io_lsu_brupdate_b2_uop_is_rvc),
.io_lsu_brupdate_b2_uop_debug_pc (_core_io_lsu_brupdate_b2_uop_debug_pc),
.io_lsu_brupdate_b2_uop_iq_type (_core_io_lsu_brupdate_b2_uop_iq_type),
.io_lsu_brupdate_b2_uop_fu_code (_core_io_lsu_brupdate_b2_uop_fu_code),
.io_lsu_brupdate_b2_uop_ctrl_br_type (_core_io_lsu_brupdate_b2_uop_ctrl_br_type),
.io_lsu_brupdate_b2_uop_ctrl_op1_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op1_sel),
.io_lsu_brupdate_b2_uop_ctrl_op2_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op2_sel),
.io_lsu_brupdate_b2_uop_ctrl_imm_sel (_core_io_lsu_brupdate_b2_uop_ctrl_imm_sel),
.io_lsu_brupdate_b2_uop_ctrl_op_fcn (_core_io_lsu_brupdate_b2_uop_ctrl_op_fcn),
.io_lsu_brupdate_b2_uop_ctrl_fcn_dw (_core_io_lsu_brupdate_b2_uop_ctrl_fcn_dw),
.io_lsu_brupdate_b2_uop_ctrl_csr_cmd (_core_io_lsu_brupdate_b2_uop_ctrl_csr_cmd),
.io_lsu_brupdate_b2_uop_ctrl_is_load (_core_io_lsu_brupdate_b2_uop_ctrl_is_load),
.io_lsu_brupdate_b2_uop_ctrl_is_sta (_core_io_lsu_brupdate_b2_uop_ctrl_is_sta),
.io_lsu_brupdate_b2_uop_ctrl_is_std (_core_io_lsu_brupdate_b2_uop_ctrl_is_std),
.io_lsu_brupdate_b2_uop_iw_state (_core_io_lsu_brupdate_b2_uop_iw_state),
.io_lsu_brupdate_b2_uop_iw_p1_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p1_poisoned),
.io_lsu_brupdate_b2_uop_iw_p2_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p2_poisoned),
.io_lsu_brupdate_b2_uop_is_br (_core_io_lsu_brupdate_b2_uop_is_br),
.io_lsu_brupdate_b2_uop_is_jalr (_core_io_lsu_brupdate_b2_uop_is_jalr),
.io_lsu_brupdate_b2_uop_is_jal (_core_io_lsu_brupdate_b2_uop_is_jal),
.io_lsu_brupdate_b2_uop_is_sfb (_core_io_lsu_brupdate_b2_uop_is_sfb),
.io_lsu_brupdate_b2_uop_br_mask (_core_io_lsu_brupdate_b2_uop_br_mask),
.io_lsu_brupdate_b2_uop_br_tag (_core_io_lsu_brupdate_b2_uop_br_tag),
.io_lsu_brupdate_b2_uop_ftq_idx (_core_io_lsu_brupdate_b2_uop_ftq_idx),
.io_lsu_brupdate_b2_uop_edge_inst (_core_io_lsu_brupdate_b2_uop_edge_inst),
.io_lsu_brupdate_b2_uop_pc_lob (_core_io_lsu_brupdate_b2_uop_pc_lob),
.io_lsu_brupdate_b2_uop_taken (_core_io_lsu_brupdate_b2_uop_taken),
.io_lsu_brupdate_b2_uop_imm_packed (_core_io_lsu_brupdate_b2_uop_imm_packed),
.io_lsu_brupdate_b2_uop_csr_addr (_core_io_lsu_brupdate_b2_uop_csr_addr),
.io_lsu_brupdate_b2_uop_rob_idx (_core_io_lsu_brupdate_b2_uop_rob_idx),
.io_lsu_brupdate_b2_uop_ldq_idx (_core_io_lsu_brupdate_b2_uop_ldq_idx),
.io_lsu_brupdate_b2_uop_stq_idx (_core_io_lsu_brupdate_b2_uop_stq_idx),
.io_lsu_brupdate_b2_uop_rxq_idx (_core_io_lsu_brupdate_b2_uop_rxq_idx),
.io_lsu_brupdate_b2_uop_pdst (_core_io_lsu_brupdate_b2_uop_pdst),
.io_lsu_brupdate_b2_uop_prs1 (_core_io_lsu_brupdate_b2_uop_prs1),
.io_lsu_brupdate_b2_uop_prs2 (_core_io_lsu_brupdate_b2_uop_prs2),
.io_lsu_brupdate_b2_uop_prs3 (_core_io_lsu_brupdate_b2_uop_prs3),
.io_lsu_brupdate_b2_uop_ppred (_core_io_lsu_brupdate_b2_uop_ppred),
.io_lsu_brupdate_b2_uop_prs1_busy (_core_io_lsu_brupdate_b2_uop_prs1_busy),
.io_lsu_brupdate_b2_uop_prs2_busy (_core_io_lsu_brupdate_b2_uop_prs2_busy),
.io_lsu_brupdate_b2_uop_prs3_busy (_core_io_lsu_brupdate_b2_uop_prs3_busy),
.io_lsu_brupdate_b2_uop_ppred_busy (_core_io_lsu_brupdate_b2_uop_ppred_busy),
.io_lsu_brupdate_b2_uop_stale_pdst (_core_io_lsu_brupdate_b2_uop_stale_pdst),
.io_lsu_brupdate_b2_uop_exception (_core_io_lsu_brupdate_b2_uop_exception),
.io_lsu_brupdate_b2_uop_exc_cause (_core_io_lsu_brupdate_b2_uop_exc_cause),
.io_lsu_brupdate_b2_uop_bypassable (_core_io_lsu_brupdate_b2_uop_bypassable),
.io_lsu_brupdate_b2_uop_mem_cmd (_core_io_lsu_brupdate_b2_uop_mem_cmd),
.io_lsu_brupdate_b2_uop_mem_size (_core_io_lsu_brupdate_b2_uop_mem_size),
.io_lsu_brupdate_b2_uop_mem_signed (_core_io_lsu_brupdate_b2_uop_mem_signed),
.io_lsu_brupdate_b2_uop_is_fence (_core_io_lsu_brupdate_b2_uop_is_fence),
.io_lsu_brupdate_b2_uop_is_fencei (_core_io_lsu_brupdate_b2_uop_is_fencei),
.io_lsu_brupdate_b2_uop_is_amo (_core_io_lsu_brupdate_b2_uop_is_amo),
.io_lsu_brupdate_b2_uop_uses_ldq (_core_io_lsu_brupdate_b2_uop_uses_ldq),
.io_lsu_brupdate_b2_uop_uses_stq (_core_io_lsu_brupdate_b2_uop_uses_stq),
.io_lsu_brupdate_b2_uop_is_sys_pc2epc (_core_io_lsu_brupdate_b2_uop_is_sys_pc2epc),
.io_lsu_brupdate_b2_uop_is_unique (_core_io_lsu_brupdate_b2_uop_is_unique),
.io_lsu_brupdate_b2_uop_flush_on_commit (_core_io_lsu_brupdate_b2_uop_flush_on_commit),
.io_lsu_brupdate_b2_uop_ldst_is_rs1 (_core_io_lsu_brupdate_b2_uop_ldst_is_rs1),
.io_lsu_brupdate_b2_uop_ldst (_core_io_lsu_brupdate_b2_uop_ldst),
.io_lsu_brupdate_b2_uop_lrs1 (_core_io_lsu_brupdate_b2_uop_lrs1),
.io_lsu_brupdate_b2_uop_lrs2 (_core_io_lsu_brupdate_b2_uop_lrs2),
.io_lsu_brupdate_b2_uop_lrs3 (_core_io_lsu_brupdate_b2_uop_lrs3),
.io_lsu_brupdate_b2_uop_ldst_val (_core_io_lsu_brupdate_b2_uop_ldst_val),
.io_lsu_brupdate_b2_uop_dst_rtype (_core_io_lsu_brupdate_b2_uop_dst_rtype),
.io_lsu_brupdate_b2_uop_lrs1_rtype (_core_io_lsu_brupdate_b2_uop_lrs1_rtype),
.io_lsu_brupdate_b2_uop_lrs2_rtype (_core_io_lsu_brupdate_b2_uop_lrs2_rtype),
.io_lsu_brupdate_b2_uop_frs3_en (_core_io_lsu_brupdate_b2_uop_frs3_en),
.io_lsu_brupdate_b2_uop_fp_val (_core_io_lsu_brupdate_b2_uop_fp_val),
.io_lsu_brupdate_b2_uop_fp_single (_core_io_lsu_brupdate_b2_uop_fp_single),
.io_lsu_brupdate_b2_uop_xcpt_pf_if (_core_io_lsu_brupdate_b2_uop_xcpt_pf_if),
.io_lsu_brupdate_b2_uop_xcpt_ae_if (_core_io_lsu_brupdate_b2_uop_xcpt_ae_if),
.io_lsu_brupdate_b2_uop_xcpt_ma_if (_core_io_lsu_brupdate_b2_uop_xcpt_ma_if),
.io_lsu_brupdate_b2_uop_bp_debug_if (_core_io_lsu_brupdate_b2_uop_bp_debug_if),
.io_lsu_brupdate_b2_uop_bp_xcpt_if (_core_io_lsu_brupdate_b2_uop_bp_xcpt_if),
.io_lsu_brupdate_b2_uop_debug_fsrc (_core_io_lsu_brupdate_b2_uop_debug_fsrc),
.io_lsu_brupdate_b2_uop_debug_tsrc (_core_io_lsu_brupdate_b2_uop_debug_tsrc),
.io_lsu_brupdate_b2_valid (_core_io_lsu_brupdate_b2_valid),
.io_lsu_brupdate_b2_mispredict (_core_io_lsu_brupdate_b2_mispredict),
.io_lsu_brupdate_b2_taken (_core_io_lsu_brupdate_b2_taken),
.io_lsu_brupdate_b2_cfi_type (_core_io_lsu_brupdate_b2_cfi_type),
.io_lsu_brupdate_b2_pc_sel (_core_io_lsu_brupdate_b2_pc_sel),
.io_lsu_brupdate_b2_jalr_target (_core_io_lsu_brupdate_b2_jalr_target),
.io_lsu_brupdate_b2_target_offset (_core_io_lsu_brupdate_b2_target_offset),
.io_lsu_rob_pnr_idx (_core_io_lsu_rob_pnr_idx),
.io_lsu_rob_head_idx (_core_io_lsu_rob_head_idx),
.io_lsu_exception (_core_io_lsu_exception),
.io_lsu_fencei_rdy (_lsu_io_core_fencei_rdy), // @[tile.scala:160:20]
.io_lsu_lxcpt_valid (_lsu_io_core_lxcpt_valid), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_uopc (_lsu_io_core_lxcpt_bits_uop_uopc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_inst (_lsu_io_core_lxcpt_bits_uop_inst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_inst (_lsu_io_core_lxcpt_bits_uop_debug_inst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_rvc (_lsu_io_core_lxcpt_bits_uop_is_rvc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_pc (_lsu_io_core_lxcpt_bits_uop_debug_pc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iq_type (_lsu_io_core_lxcpt_bits_uop_iq_type), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_fu_code (_lsu_io_core_lxcpt_bits_uop_fu_code), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_br_type (_lsu_io_core_lxcpt_bits_uop_ctrl_br_type), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_op1_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_op2_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_imm_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_op_fcn (_lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_fcn_dw (_lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_csr_cmd (_lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_is_load (_lsu_io_core_lxcpt_bits_uop_ctrl_is_load), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_is_sta (_lsu_io_core_lxcpt_bits_uop_ctrl_is_sta), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ctrl_is_std (_lsu_io_core_lxcpt_bits_uop_ctrl_is_std), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iw_state (_lsu_io_core_lxcpt_bits_uop_iw_state), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iw_p1_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_iw_p2_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_br (_lsu_io_core_lxcpt_bits_uop_is_br), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_jalr (_lsu_io_core_lxcpt_bits_uop_is_jalr), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_jal (_lsu_io_core_lxcpt_bits_uop_is_jal), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_sfb (_lsu_io_core_lxcpt_bits_uop_is_sfb), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_br_mask (_lsu_io_core_lxcpt_bits_uop_br_mask), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_br_tag (_lsu_io_core_lxcpt_bits_uop_br_tag), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ftq_idx (_lsu_io_core_lxcpt_bits_uop_ftq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_edge_inst (_lsu_io_core_lxcpt_bits_uop_edge_inst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_pc_lob (_lsu_io_core_lxcpt_bits_uop_pc_lob), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_taken (_lsu_io_core_lxcpt_bits_uop_taken), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_imm_packed (_lsu_io_core_lxcpt_bits_uop_imm_packed), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_csr_addr (_lsu_io_core_lxcpt_bits_uop_csr_addr), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_rob_idx (_lsu_io_core_lxcpt_bits_uop_rob_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldq_idx (_lsu_io_core_lxcpt_bits_uop_ldq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_stq_idx (_lsu_io_core_lxcpt_bits_uop_stq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_rxq_idx (_lsu_io_core_lxcpt_bits_uop_rxq_idx), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_pdst (_lsu_io_core_lxcpt_bits_uop_pdst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs1 (_lsu_io_core_lxcpt_bits_uop_prs1), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs2 (_lsu_io_core_lxcpt_bits_uop_prs2), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs3 (_lsu_io_core_lxcpt_bits_uop_prs3), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ppred (_lsu_io_core_lxcpt_bits_uop_ppred), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs1_busy (_lsu_io_core_lxcpt_bits_uop_prs1_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs2_busy (_lsu_io_core_lxcpt_bits_uop_prs2_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_prs3_busy (_lsu_io_core_lxcpt_bits_uop_prs3_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ppred_busy (_lsu_io_core_lxcpt_bits_uop_ppred_busy), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_stale_pdst (_lsu_io_core_lxcpt_bits_uop_stale_pdst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_exception (_lsu_io_core_lxcpt_bits_uop_exception), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_exc_cause (_lsu_io_core_lxcpt_bits_uop_exc_cause), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_bypassable (_lsu_io_core_lxcpt_bits_uop_bypassable), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_mem_cmd (_lsu_io_core_lxcpt_bits_uop_mem_cmd), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_mem_size (_lsu_io_core_lxcpt_bits_uop_mem_size), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_mem_signed (_lsu_io_core_lxcpt_bits_uop_mem_signed), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_fence (_lsu_io_core_lxcpt_bits_uop_is_fence), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_fencei (_lsu_io_core_lxcpt_bits_uop_is_fencei), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_amo (_lsu_io_core_lxcpt_bits_uop_is_amo), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_uses_ldq (_lsu_io_core_lxcpt_bits_uop_uses_ldq), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_uses_stq (_lsu_io_core_lxcpt_bits_uop_uses_stq), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_sys_pc2epc (_lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_is_unique (_lsu_io_core_lxcpt_bits_uop_is_unique), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_flush_on_commit (_lsu_io_core_lxcpt_bits_uop_flush_on_commit), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldst_is_rs1 (_lsu_io_core_lxcpt_bits_uop_ldst_is_rs1), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldst (_lsu_io_core_lxcpt_bits_uop_ldst), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs1 (_lsu_io_core_lxcpt_bits_uop_lrs1), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs2 (_lsu_io_core_lxcpt_bits_uop_lrs2), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs3 (_lsu_io_core_lxcpt_bits_uop_lrs3), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_ldst_val (_lsu_io_core_lxcpt_bits_uop_ldst_val), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_dst_rtype (_lsu_io_core_lxcpt_bits_uop_dst_rtype), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs1_rtype (_lsu_io_core_lxcpt_bits_uop_lrs1_rtype), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_lrs2_rtype (_lsu_io_core_lxcpt_bits_uop_lrs2_rtype), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_frs3_en (_lsu_io_core_lxcpt_bits_uop_frs3_en), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_fp_val (_lsu_io_core_lxcpt_bits_uop_fp_val), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_fp_single (_lsu_io_core_lxcpt_bits_uop_fp_single), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_xcpt_pf_if (_lsu_io_core_lxcpt_bits_uop_xcpt_pf_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_xcpt_ae_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ae_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_xcpt_ma_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ma_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_bp_debug_if (_lsu_io_core_lxcpt_bits_uop_bp_debug_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_bp_xcpt_if (_lsu_io_core_lxcpt_bits_uop_bp_xcpt_if), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_fsrc (_lsu_io_core_lxcpt_bits_uop_debug_fsrc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_uop_debug_tsrc (_lsu_io_core_lxcpt_bits_uop_debug_tsrc), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_cause (_lsu_io_core_lxcpt_bits_cause), // @[tile.scala:160:20]
.io_lsu_lxcpt_bits_badvaddr (_lsu_io_core_lxcpt_bits_badvaddr), // @[tile.scala:160:20]
.io_lsu_tsc_reg (_core_io_lsu_tsc_reg),
.io_lsu_perf_acquire (_lsu_io_core_perf_acquire), // @[tile.scala:160:20]
.io_lsu_perf_release (_lsu_io_core_perf_release), // @[tile.scala:160:20]
.io_lsu_perf_tlbMiss (_lsu_io_core_perf_tlbMiss), // @[tile.scala:160:20]
.io_ptw_tlb_req_ready (_ptw_io_requestor_2_req_ready), // @[tile.scala:237:20]
.io_ptw_tlb_resp_valid (_ptw_io_requestor_2_resp_valid), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_level (_ptw_io_requestor_2_resp_bits_level), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits), // @[tile.scala:237:20]
.io_ptw_tlb_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte), // @[tile.scala:237:20]
.io_ptw_tlb_ptbr_mode (_ptw_io_requestor_2_ptbr_mode), // @[tile.scala:237:20]
.io_ptw_tlb_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn), // @[tile.scala:237:20]
.io_ptw_tlb_status_debug (_ptw_io_requestor_2_status_debug), // @[tile.scala:237:20]
.io_ptw_tlb_status_cease (_ptw_io_requestor_2_status_cease), // @[tile.scala:237:20]
.io_ptw_tlb_status_wfi (_ptw_io_requestor_2_status_wfi), // @[tile.scala:237:20]
.io_ptw_tlb_status_dprv (_ptw_io_requestor_2_status_dprv), // @[tile.scala:237:20]
.io_ptw_tlb_status_dv (_ptw_io_requestor_2_status_dv), // @[tile.scala:237:20]
.io_ptw_tlb_status_prv (_ptw_io_requestor_2_status_prv), // @[tile.scala:237:20]
.io_ptw_tlb_status_v (_ptw_io_requestor_2_status_v), // @[tile.scala:237:20]
.io_ptw_tlb_status_sd (_ptw_io_requestor_2_status_sd), // @[tile.scala:237:20]
.io_ptw_tlb_status_mpv (_ptw_io_requestor_2_status_mpv), // @[tile.scala:237:20]
.io_ptw_tlb_status_gva (_ptw_io_requestor_2_status_gva), // @[tile.scala:237:20]
.io_ptw_tlb_status_tsr (_ptw_io_requestor_2_status_tsr), // @[tile.scala:237:20]
.io_ptw_tlb_status_tw (_ptw_io_requestor_2_status_tw), // @[tile.scala:237:20]
.io_ptw_tlb_status_tvm (_ptw_io_requestor_2_status_tvm), // @[tile.scala:237:20]
.io_ptw_tlb_status_mxr (_ptw_io_requestor_2_status_mxr), // @[tile.scala:237:20]
.io_ptw_tlb_status_sum (_ptw_io_requestor_2_status_sum), // @[tile.scala:237:20]
.io_ptw_tlb_status_mprv (_ptw_io_requestor_2_status_mprv), // @[tile.scala:237:20]
.io_ptw_tlb_status_fs (_ptw_io_requestor_2_status_fs), // @[tile.scala:237:20]
.io_ptw_tlb_status_mpp (_ptw_io_requestor_2_status_mpp), // @[tile.scala:237:20]
.io_ptw_tlb_status_spp (_ptw_io_requestor_2_status_spp), // @[tile.scala:237:20]
.io_ptw_tlb_status_mpie (_ptw_io_requestor_2_status_mpie), // @[tile.scala:237:20]
.io_ptw_tlb_status_spie (_ptw_io_requestor_2_status_spie), // @[tile.scala:237:20]
.io_ptw_tlb_status_mie (_ptw_io_requestor_2_status_mie), // @[tile.scala:237:20]
.io_ptw_tlb_status_sie (_ptw_io_requestor_2_status_sie), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr), // @[tile.scala:237:20]
.io_ptw_tlb_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask), // @[tile.scala:237:20]
.io_trace_time (traceSourceNodeOut_time),
.io_trace_custom_rob_empty (traceSourceNodeOut_custom_rob_empty)
); // @[tile.scala:159:20]
LSU lsu ( // @[tile.scala:160:20]
.clock (clock),
.reset (reset),
.io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[tile.scala:237:20]
.io_ptw_req_valid (_lsu_io_ptw_req_valid),
.io_ptw_req_bits_valid (_lsu_io_ptw_req_bits_valid),
.io_ptw_req_bits_bits_addr (_lsu_io_ptw_req_bits_bits_addr),
.io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[tile.scala:237:20]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[tile.scala:237:20]
.io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[tile.scala:237:20]
.io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[tile.scala:237:20]
.io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[tile.scala:237:20]
.io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[tile.scala:237:20]
.io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[tile.scala:237:20]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[tile.scala:237:20]
.io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[tile.scala:237:20]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[tile.scala:237:20]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[tile.scala:237:20]
.io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[tile.scala:237:20]
.io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[tile.scala:237:20]
.io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[tile.scala:237:20]
.io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[tile.scala:237:20]
.io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[tile.scala:237:20]
.io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[tile.scala:237:20]
.io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[tile.scala:237:20]
.io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[tile.scala:237:20]
.io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[tile.scala:237:20]
.io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[tile.scala:237:20]
.io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[tile.scala:237:20]
.io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[tile.scala:237:20]
.io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[tile.scala:237:20]
.io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[tile.scala:237:20]
.io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[tile.scala:237:20]
.io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[tile.scala:237:20]
.io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[tile.scala:237:20]
.io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[tile.scala:237:20]
.io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[tile.scala:237:20]
.io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[tile.scala:237:20]
.io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[tile.scala:237:20]
.io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[tile.scala:237:20]
.io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[tile.scala:237:20]
.io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[tile.scala:237:20]
.io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr), // @[tile.scala:237:20]
.io_ptw_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr), // @[tile.scala:237:20]
.io_ptw_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr), // @[tile.scala:237:20]
.io_ptw_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr), // @[tile.scala:237:20]
.io_ptw_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr), // @[tile.scala:237:20]
.io_ptw_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr), // @[tile.scala:237:20]
.io_ptw_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr), // @[tile.scala:237:20]
.io_ptw_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w), // @[tile.scala:237:20]
.io_ptw_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r), // @[tile.scala:237:20]
.io_ptw_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr), // @[tile.scala:237:20]
.io_ptw_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask), // @[tile.scala:237:20]
.io_core_exe_0_req_valid (_core_io_lsu_exe_0_req_valid), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_uopc (_core_io_lsu_exe_0_req_bits_uop_uopc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_inst (_core_io_lsu_exe_0_req_bits_uop_inst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_inst (_core_io_lsu_exe_0_req_bits_uop_debug_inst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_rvc (_core_io_lsu_exe_0_req_bits_uop_is_rvc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_pc (_core_io_lsu_exe_0_req_bits_uop_debug_pc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iq_type (_core_io_lsu_exe_0_req_bits_uop_iq_type), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_fu_code (_core_io_lsu_exe_0_req_bits_uop_fu_code), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_br_type (_core_io_lsu_exe_0_req_bits_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_op1_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_op2_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_imm_sel (_core_io_lsu_exe_0_req_bits_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_op_fcn (_core_io_lsu_exe_0_req_bits_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_fcn_dw (_core_io_lsu_exe_0_req_bits_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_csr_cmd (_core_io_lsu_exe_0_req_bits_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_is_load (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_is_sta (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ctrl_is_std (_core_io_lsu_exe_0_req_bits_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iw_state (_core_io_lsu_exe_0_req_bits_uop_iw_state), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iw_p1_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_iw_p2_poisoned (_core_io_lsu_exe_0_req_bits_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_br (_core_io_lsu_exe_0_req_bits_uop_is_br), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_jalr (_core_io_lsu_exe_0_req_bits_uop_is_jalr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_jal (_core_io_lsu_exe_0_req_bits_uop_is_jal), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_sfb (_core_io_lsu_exe_0_req_bits_uop_is_sfb), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_br_mask (_core_io_lsu_exe_0_req_bits_uop_br_mask), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_br_tag (_core_io_lsu_exe_0_req_bits_uop_br_tag), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ftq_idx (_core_io_lsu_exe_0_req_bits_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_edge_inst (_core_io_lsu_exe_0_req_bits_uop_edge_inst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_pc_lob (_core_io_lsu_exe_0_req_bits_uop_pc_lob), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_taken (_core_io_lsu_exe_0_req_bits_uop_taken), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_imm_packed (_core_io_lsu_exe_0_req_bits_uop_imm_packed), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_csr_addr (_core_io_lsu_exe_0_req_bits_uop_csr_addr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_rob_idx (_core_io_lsu_exe_0_req_bits_uop_rob_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldq_idx (_core_io_lsu_exe_0_req_bits_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_stq_idx (_core_io_lsu_exe_0_req_bits_uop_stq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_rxq_idx (_core_io_lsu_exe_0_req_bits_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_pdst (_core_io_lsu_exe_0_req_bits_uop_pdst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs1 (_core_io_lsu_exe_0_req_bits_uop_prs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs2 (_core_io_lsu_exe_0_req_bits_uop_prs2), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs3 (_core_io_lsu_exe_0_req_bits_uop_prs3), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ppred (_core_io_lsu_exe_0_req_bits_uop_ppred), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs1_busy (_core_io_lsu_exe_0_req_bits_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs2_busy (_core_io_lsu_exe_0_req_bits_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_prs3_busy (_core_io_lsu_exe_0_req_bits_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ppred_busy (_core_io_lsu_exe_0_req_bits_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_stale_pdst (_core_io_lsu_exe_0_req_bits_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_exception (_core_io_lsu_exe_0_req_bits_uop_exception), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_exc_cause (_core_io_lsu_exe_0_req_bits_uop_exc_cause), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_bypassable (_core_io_lsu_exe_0_req_bits_uop_bypassable), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_mem_cmd (_core_io_lsu_exe_0_req_bits_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_mem_size (_core_io_lsu_exe_0_req_bits_uop_mem_size), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_mem_signed (_core_io_lsu_exe_0_req_bits_uop_mem_signed), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_fence (_core_io_lsu_exe_0_req_bits_uop_is_fence), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_fencei (_core_io_lsu_exe_0_req_bits_uop_is_fencei), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_amo (_core_io_lsu_exe_0_req_bits_uop_is_amo), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_uses_ldq (_core_io_lsu_exe_0_req_bits_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_uses_stq (_core_io_lsu_exe_0_req_bits_uop_uses_stq), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_sys_pc2epc (_core_io_lsu_exe_0_req_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_is_unique (_core_io_lsu_exe_0_req_bits_uop_is_unique), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_flush_on_commit (_core_io_lsu_exe_0_req_bits_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldst_is_rs1 (_core_io_lsu_exe_0_req_bits_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldst (_core_io_lsu_exe_0_req_bits_uop_ldst), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs1 (_core_io_lsu_exe_0_req_bits_uop_lrs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs2 (_core_io_lsu_exe_0_req_bits_uop_lrs2), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs3 (_core_io_lsu_exe_0_req_bits_uop_lrs3), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_ldst_val (_core_io_lsu_exe_0_req_bits_uop_ldst_val), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_dst_rtype (_core_io_lsu_exe_0_req_bits_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs1_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_lrs2_rtype (_core_io_lsu_exe_0_req_bits_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_frs3_en (_core_io_lsu_exe_0_req_bits_uop_frs3_en), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_fp_val (_core_io_lsu_exe_0_req_bits_uop_fp_val), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_fp_single (_core_io_lsu_exe_0_req_bits_uop_fp_single), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_xcpt_pf_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_xcpt_ae_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_xcpt_ma_if (_core_io_lsu_exe_0_req_bits_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_bp_debug_if (_core_io_lsu_exe_0_req_bits_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_bp_xcpt_if (_core_io_lsu_exe_0_req_bits_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_fsrc (_core_io_lsu_exe_0_req_bits_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_uop_debug_tsrc (_core_io_lsu_exe_0_req_bits_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_data (_core_io_lsu_exe_0_req_bits_data), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_addr (_core_io_lsu_exe_0_req_bits_addr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_mxcpt_valid (_core_io_lsu_exe_0_req_bits_mxcpt_valid), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_mxcpt_bits (_core_io_lsu_exe_0_req_bits_mxcpt_bits), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_valid (_core_io_lsu_exe_0_req_bits_sfence_valid), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_rs1 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs1), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_rs2 (_core_io_lsu_exe_0_req_bits_sfence_bits_rs2), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_addr (_core_io_lsu_exe_0_req_bits_sfence_bits_addr), // @[tile.scala:159:20]
.io_core_exe_0_req_bits_sfence_bits_asid (_core_io_lsu_exe_0_req_bits_sfence_bits_asid), // @[tile.scala:159:20]
.io_core_exe_0_iresp_valid (_lsu_io_core_exe_0_iresp_valid),
.io_core_exe_0_iresp_bits_uop_uopc (_lsu_io_core_exe_0_iresp_bits_uop_uopc),
.io_core_exe_0_iresp_bits_uop_inst (_lsu_io_core_exe_0_iresp_bits_uop_inst),
.io_core_exe_0_iresp_bits_uop_debug_inst (_lsu_io_core_exe_0_iresp_bits_uop_debug_inst),
.io_core_exe_0_iresp_bits_uop_is_rvc (_lsu_io_core_exe_0_iresp_bits_uop_is_rvc),
.io_core_exe_0_iresp_bits_uop_debug_pc (_lsu_io_core_exe_0_iresp_bits_uop_debug_pc),
.io_core_exe_0_iresp_bits_uop_iq_type (_lsu_io_core_exe_0_iresp_bits_uop_iq_type),
.io_core_exe_0_iresp_bits_uop_fu_code (_lsu_io_core_exe_0_iresp_bits_uop_fu_code),
.io_core_exe_0_iresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_br_type),
.io_core_exe_0_iresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op1_sel),
.io_core_exe_0_iresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op2_sel),
.io_core_exe_0_iresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_imm_sel),
.io_core_exe_0_iresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_op_fcn),
.io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_fcn_dw),
.io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_csr_cmd),
.io_core_exe_0_iresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_load),
.io_core_exe_0_iresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_sta),
.io_core_exe_0_iresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_iresp_bits_uop_ctrl_is_std),
.io_core_exe_0_iresp_bits_uop_iw_state (_lsu_io_core_exe_0_iresp_bits_uop_iw_state),
.io_core_exe_0_iresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p1_poisoned),
.io_core_exe_0_iresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_iresp_bits_uop_iw_p2_poisoned),
.io_core_exe_0_iresp_bits_uop_is_br (_lsu_io_core_exe_0_iresp_bits_uop_is_br),
.io_core_exe_0_iresp_bits_uop_is_jalr (_lsu_io_core_exe_0_iresp_bits_uop_is_jalr),
.io_core_exe_0_iresp_bits_uop_is_jal (_lsu_io_core_exe_0_iresp_bits_uop_is_jal),
.io_core_exe_0_iresp_bits_uop_is_sfb (_lsu_io_core_exe_0_iresp_bits_uop_is_sfb),
.io_core_exe_0_iresp_bits_uop_br_mask (_lsu_io_core_exe_0_iresp_bits_uop_br_mask),
.io_core_exe_0_iresp_bits_uop_br_tag (_lsu_io_core_exe_0_iresp_bits_uop_br_tag),
.io_core_exe_0_iresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ftq_idx),
.io_core_exe_0_iresp_bits_uop_edge_inst (_lsu_io_core_exe_0_iresp_bits_uop_edge_inst),
.io_core_exe_0_iresp_bits_uop_pc_lob (_lsu_io_core_exe_0_iresp_bits_uop_pc_lob),
.io_core_exe_0_iresp_bits_uop_taken (_lsu_io_core_exe_0_iresp_bits_uop_taken),
.io_core_exe_0_iresp_bits_uop_imm_packed (_lsu_io_core_exe_0_iresp_bits_uop_imm_packed),
.io_core_exe_0_iresp_bits_uop_csr_addr (_lsu_io_core_exe_0_iresp_bits_uop_csr_addr),
.io_core_exe_0_iresp_bits_uop_rob_idx (_lsu_io_core_exe_0_iresp_bits_uop_rob_idx),
.io_core_exe_0_iresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_iresp_bits_uop_ldq_idx),
.io_core_exe_0_iresp_bits_uop_stq_idx (_lsu_io_core_exe_0_iresp_bits_uop_stq_idx),
.io_core_exe_0_iresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_iresp_bits_uop_rxq_idx),
.io_core_exe_0_iresp_bits_uop_pdst (_lsu_io_core_exe_0_iresp_bits_uop_pdst),
.io_core_exe_0_iresp_bits_uop_prs1 (_lsu_io_core_exe_0_iresp_bits_uop_prs1),
.io_core_exe_0_iresp_bits_uop_prs2 (_lsu_io_core_exe_0_iresp_bits_uop_prs2),
.io_core_exe_0_iresp_bits_uop_prs3 (_lsu_io_core_exe_0_iresp_bits_uop_prs3),
.io_core_exe_0_iresp_bits_uop_ppred (_lsu_io_core_exe_0_iresp_bits_uop_ppred),
.io_core_exe_0_iresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs1_busy),
.io_core_exe_0_iresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs2_busy),
.io_core_exe_0_iresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_iresp_bits_uop_prs3_busy),
.io_core_exe_0_iresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_iresp_bits_uop_ppred_busy),
.io_core_exe_0_iresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_iresp_bits_uop_stale_pdst),
.io_core_exe_0_iresp_bits_uop_exception (_lsu_io_core_exe_0_iresp_bits_uop_exception),
.io_core_exe_0_iresp_bits_uop_exc_cause (_lsu_io_core_exe_0_iresp_bits_uop_exc_cause),
.io_core_exe_0_iresp_bits_uop_bypassable (_lsu_io_core_exe_0_iresp_bits_uop_bypassable),
.io_core_exe_0_iresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_iresp_bits_uop_mem_cmd),
.io_core_exe_0_iresp_bits_uop_mem_size (_lsu_io_core_exe_0_iresp_bits_uop_mem_size),
.io_core_exe_0_iresp_bits_uop_mem_signed (_lsu_io_core_exe_0_iresp_bits_uop_mem_signed),
.io_core_exe_0_iresp_bits_uop_is_fence (_lsu_io_core_exe_0_iresp_bits_uop_is_fence),
.io_core_exe_0_iresp_bits_uop_is_fencei (_lsu_io_core_exe_0_iresp_bits_uop_is_fencei),
.io_core_exe_0_iresp_bits_uop_is_amo (_lsu_io_core_exe_0_iresp_bits_uop_is_amo),
.io_core_exe_0_iresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_iresp_bits_uop_uses_ldq),
.io_core_exe_0_iresp_bits_uop_uses_stq (_lsu_io_core_exe_0_iresp_bits_uop_uses_stq),
.io_core_exe_0_iresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_iresp_bits_uop_is_sys_pc2epc),
.io_core_exe_0_iresp_bits_uop_is_unique (_lsu_io_core_exe_0_iresp_bits_uop_is_unique),
.io_core_exe_0_iresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_iresp_bits_uop_flush_on_commit),
.io_core_exe_0_iresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_iresp_bits_uop_ldst_is_rs1),
.io_core_exe_0_iresp_bits_uop_ldst (_lsu_io_core_exe_0_iresp_bits_uop_ldst),
.io_core_exe_0_iresp_bits_uop_lrs1 (_lsu_io_core_exe_0_iresp_bits_uop_lrs1),
.io_core_exe_0_iresp_bits_uop_lrs2 (_lsu_io_core_exe_0_iresp_bits_uop_lrs2),
.io_core_exe_0_iresp_bits_uop_lrs3 (_lsu_io_core_exe_0_iresp_bits_uop_lrs3),
.io_core_exe_0_iresp_bits_uop_ldst_val (_lsu_io_core_exe_0_iresp_bits_uop_ldst_val),
.io_core_exe_0_iresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_iresp_bits_uop_dst_rtype),
.io_core_exe_0_iresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs1_rtype),
.io_core_exe_0_iresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_iresp_bits_uop_lrs2_rtype),
.io_core_exe_0_iresp_bits_uop_frs3_en (_lsu_io_core_exe_0_iresp_bits_uop_frs3_en),
.io_core_exe_0_iresp_bits_uop_fp_val (_lsu_io_core_exe_0_iresp_bits_uop_fp_val),
.io_core_exe_0_iresp_bits_uop_fp_single (_lsu_io_core_exe_0_iresp_bits_uop_fp_single),
.io_core_exe_0_iresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_pf_if),
.io_core_exe_0_iresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ae_if),
.io_core_exe_0_iresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_iresp_bits_uop_xcpt_ma_if),
.io_core_exe_0_iresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_debug_if),
.io_core_exe_0_iresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_iresp_bits_uop_bp_xcpt_if),
.io_core_exe_0_iresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_fsrc),
.io_core_exe_0_iresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_iresp_bits_uop_debug_tsrc),
.io_core_exe_0_iresp_bits_data (_lsu_io_core_exe_0_iresp_bits_data),
.io_core_exe_0_fresp_valid (_lsu_io_core_exe_0_fresp_valid),
.io_core_exe_0_fresp_bits_uop_uopc (_lsu_io_core_exe_0_fresp_bits_uop_uopc),
.io_core_exe_0_fresp_bits_uop_inst (_lsu_io_core_exe_0_fresp_bits_uop_inst),
.io_core_exe_0_fresp_bits_uop_debug_inst (_lsu_io_core_exe_0_fresp_bits_uop_debug_inst),
.io_core_exe_0_fresp_bits_uop_is_rvc (_lsu_io_core_exe_0_fresp_bits_uop_is_rvc),
.io_core_exe_0_fresp_bits_uop_debug_pc (_lsu_io_core_exe_0_fresp_bits_uop_debug_pc),
.io_core_exe_0_fresp_bits_uop_iq_type (_lsu_io_core_exe_0_fresp_bits_uop_iq_type),
.io_core_exe_0_fresp_bits_uop_fu_code (_lsu_io_core_exe_0_fresp_bits_uop_fu_code),
.io_core_exe_0_fresp_bits_uop_ctrl_br_type (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_br_type),
.io_core_exe_0_fresp_bits_uop_ctrl_op1_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op1_sel),
.io_core_exe_0_fresp_bits_uop_ctrl_op2_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op2_sel),
.io_core_exe_0_fresp_bits_uop_ctrl_imm_sel (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_imm_sel),
.io_core_exe_0_fresp_bits_uop_ctrl_op_fcn (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_op_fcn),
.io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_fcn_dw),
.io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_csr_cmd),
.io_core_exe_0_fresp_bits_uop_ctrl_is_load (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_load),
.io_core_exe_0_fresp_bits_uop_ctrl_is_sta (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_sta),
.io_core_exe_0_fresp_bits_uop_ctrl_is_std (_lsu_io_core_exe_0_fresp_bits_uop_ctrl_is_std),
.io_core_exe_0_fresp_bits_uop_iw_state (_lsu_io_core_exe_0_fresp_bits_uop_iw_state),
.io_core_exe_0_fresp_bits_uop_iw_p1_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p1_poisoned),
.io_core_exe_0_fresp_bits_uop_iw_p2_poisoned (_lsu_io_core_exe_0_fresp_bits_uop_iw_p2_poisoned),
.io_core_exe_0_fresp_bits_uop_is_br (_lsu_io_core_exe_0_fresp_bits_uop_is_br),
.io_core_exe_0_fresp_bits_uop_is_jalr (_lsu_io_core_exe_0_fresp_bits_uop_is_jalr),
.io_core_exe_0_fresp_bits_uop_is_jal (_lsu_io_core_exe_0_fresp_bits_uop_is_jal),
.io_core_exe_0_fresp_bits_uop_is_sfb (_lsu_io_core_exe_0_fresp_bits_uop_is_sfb),
.io_core_exe_0_fresp_bits_uop_br_mask (_lsu_io_core_exe_0_fresp_bits_uop_br_mask),
.io_core_exe_0_fresp_bits_uop_br_tag (_lsu_io_core_exe_0_fresp_bits_uop_br_tag),
.io_core_exe_0_fresp_bits_uop_ftq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ftq_idx),
.io_core_exe_0_fresp_bits_uop_edge_inst (_lsu_io_core_exe_0_fresp_bits_uop_edge_inst),
.io_core_exe_0_fresp_bits_uop_pc_lob (_lsu_io_core_exe_0_fresp_bits_uop_pc_lob),
.io_core_exe_0_fresp_bits_uop_taken (_lsu_io_core_exe_0_fresp_bits_uop_taken),
.io_core_exe_0_fresp_bits_uop_imm_packed (_lsu_io_core_exe_0_fresp_bits_uop_imm_packed),
.io_core_exe_0_fresp_bits_uop_csr_addr (_lsu_io_core_exe_0_fresp_bits_uop_csr_addr),
.io_core_exe_0_fresp_bits_uop_rob_idx (_lsu_io_core_exe_0_fresp_bits_uop_rob_idx),
.io_core_exe_0_fresp_bits_uop_ldq_idx (_lsu_io_core_exe_0_fresp_bits_uop_ldq_idx),
.io_core_exe_0_fresp_bits_uop_stq_idx (_lsu_io_core_exe_0_fresp_bits_uop_stq_idx),
.io_core_exe_0_fresp_bits_uop_rxq_idx (_lsu_io_core_exe_0_fresp_bits_uop_rxq_idx),
.io_core_exe_0_fresp_bits_uop_pdst (_lsu_io_core_exe_0_fresp_bits_uop_pdst),
.io_core_exe_0_fresp_bits_uop_prs1 (_lsu_io_core_exe_0_fresp_bits_uop_prs1),
.io_core_exe_0_fresp_bits_uop_prs2 (_lsu_io_core_exe_0_fresp_bits_uop_prs2),
.io_core_exe_0_fresp_bits_uop_prs3 (_lsu_io_core_exe_0_fresp_bits_uop_prs3),
.io_core_exe_0_fresp_bits_uop_ppred (_lsu_io_core_exe_0_fresp_bits_uop_ppred),
.io_core_exe_0_fresp_bits_uop_prs1_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs1_busy),
.io_core_exe_0_fresp_bits_uop_prs2_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs2_busy),
.io_core_exe_0_fresp_bits_uop_prs3_busy (_lsu_io_core_exe_0_fresp_bits_uop_prs3_busy),
.io_core_exe_0_fresp_bits_uop_ppred_busy (_lsu_io_core_exe_0_fresp_bits_uop_ppred_busy),
.io_core_exe_0_fresp_bits_uop_stale_pdst (_lsu_io_core_exe_0_fresp_bits_uop_stale_pdst),
.io_core_exe_0_fresp_bits_uop_exception (_lsu_io_core_exe_0_fresp_bits_uop_exception),
.io_core_exe_0_fresp_bits_uop_exc_cause (_lsu_io_core_exe_0_fresp_bits_uop_exc_cause),
.io_core_exe_0_fresp_bits_uop_bypassable (_lsu_io_core_exe_0_fresp_bits_uop_bypassable),
.io_core_exe_0_fresp_bits_uop_mem_cmd (_lsu_io_core_exe_0_fresp_bits_uop_mem_cmd),
.io_core_exe_0_fresp_bits_uop_mem_size (_lsu_io_core_exe_0_fresp_bits_uop_mem_size),
.io_core_exe_0_fresp_bits_uop_mem_signed (_lsu_io_core_exe_0_fresp_bits_uop_mem_signed),
.io_core_exe_0_fresp_bits_uop_is_fence (_lsu_io_core_exe_0_fresp_bits_uop_is_fence),
.io_core_exe_0_fresp_bits_uop_is_fencei (_lsu_io_core_exe_0_fresp_bits_uop_is_fencei),
.io_core_exe_0_fresp_bits_uop_is_amo (_lsu_io_core_exe_0_fresp_bits_uop_is_amo),
.io_core_exe_0_fresp_bits_uop_uses_ldq (_lsu_io_core_exe_0_fresp_bits_uop_uses_ldq),
.io_core_exe_0_fresp_bits_uop_uses_stq (_lsu_io_core_exe_0_fresp_bits_uop_uses_stq),
.io_core_exe_0_fresp_bits_uop_is_sys_pc2epc (_lsu_io_core_exe_0_fresp_bits_uop_is_sys_pc2epc),
.io_core_exe_0_fresp_bits_uop_is_unique (_lsu_io_core_exe_0_fresp_bits_uop_is_unique),
.io_core_exe_0_fresp_bits_uop_flush_on_commit (_lsu_io_core_exe_0_fresp_bits_uop_flush_on_commit),
.io_core_exe_0_fresp_bits_uop_ldst_is_rs1 (_lsu_io_core_exe_0_fresp_bits_uop_ldst_is_rs1),
.io_core_exe_0_fresp_bits_uop_ldst (_lsu_io_core_exe_0_fresp_bits_uop_ldst),
.io_core_exe_0_fresp_bits_uop_lrs1 (_lsu_io_core_exe_0_fresp_bits_uop_lrs1),
.io_core_exe_0_fresp_bits_uop_lrs2 (_lsu_io_core_exe_0_fresp_bits_uop_lrs2),
.io_core_exe_0_fresp_bits_uop_lrs3 (_lsu_io_core_exe_0_fresp_bits_uop_lrs3),
.io_core_exe_0_fresp_bits_uop_ldst_val (_lsu_io_core_exe_0_fresp_bits_uop_ldst_val),
.io_core_exe_0_fresp_bits_uop_dst_rtype (_lsu_io_core_exe_0_fresp_bits_uop_dst_rtype),
.io_core_exe_0_fresp_bits_uop_lrs1_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs1_rtype),
.io_core_exe_0_fresp_bits_uop_lrs2_rtype (_lsu_io_core_exe_0_fresp_bits_uop_lrs2_rtype),
.io_core_exe_0_fresp_bits_uop_frs3_en (_lsu_io_core_exe_0_fresp_bits_uop_frs3_en),
.io_core_exe_0_fresp_bits_uop_fp_val (_lsu_io_core_exe_0_fresp_bits_uop_fp_val),
.io_core_exe_0_fresp_bits_uop_fp_single (_lsu_io_core_exe_0_fresp_bits_uop_fp_single),
.io_core_exe_0_fresp_bits_uop_xcpt_pf_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_pf_if),
.io_core_exe_0_fresp_bits_uop_xcpt_ae_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ae_if),
.io_core_exe_0_fresp_bits_uop_xcpt_ma_if (_lsu_io_core_exe_0_fresp_bits_uop_xcpt_ma_if),
.io_core_exe_0_fresp_bits_uop_bp_debug_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_debug_if),
.io_core_exe_0_fresp_bits_uop_bp_xcpt_if (_lsu_io_core_exe_0_fresp_bits_uop_bp_xcpt_if),
.io_core_exe_0_fresp_bits_uop_debug_fsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_fsrc),
.io_core_exe_0_fresp_bits_uop_debug_tsrc (_lsu_io_core_exe_0_fresp_bits_uop_debug_tsrc),
.io_core_exe_0_fresp_bits_data (_lsu_io_core_exe_0_fresp_bits_data),
.io_core_dis_uops_0_valid (_core_io_lsu_dis_uops_0_valid), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_uopc (_core_io_lsu_dis_uops_0_bits_uopc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_inst (_core_io_lsu_dis_uops_0_bits_inst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_inst (_core_io_lsu_dis_uops_0_bits_debug_inst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_rvc (_core_io_lsu_dis_uops_0_bits_is_rvc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_pc (_core_io_lsu_dis_uops_0_bits_debug_pc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iq_type (_core_io_lsu_dis_uops_0_bits_iq_type), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_fu_code (_core_io_lsu_dis_uops_0_bits_fu_code), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_br_type (_core_io_lsu_dis_uops_0_bits_ctrl_br_type), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_0_bits_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_0_bits_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_0_bits_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_0_bits_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_0_bits_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_is_load (_core_io_lsu_dis_uops_0_bits_ctrl_is_load), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_is_sta (_core_io_lsu_dis_uops_0_bits_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ctrl_is_std (_core_io_lsu_dis_uops_0_bits_ctrl_is_std), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iw_state (_core_io_lsu_dis_uops_0_bits_iw_state), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_0_bits_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_br (_core_io_lsu_dis_uops_0_bits_is_br), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_jalr (_core_io_lsu_dis_uops_0_bits_is_jalr), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_jal (_core_io_lsu_dis_uops_0_bits_is_jal), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_sfb (_core_io_lsu_dis_uops_0_bits_is_sfb), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_br_mask (_core_io_lsu_dis_uops_0_bits_br_mask), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_br_tag (_core_io_lsu_dis_uops_0_bits_br_tag), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ftq_idx (_core_io_lsu_dis_uops_0_bits_ftq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_edge_inst (_core_io_lsu_dis_uops_0_bits_edge_inst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_pc_lob (_core_io_lsu_dis_uops_0_bits_pc_lob), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_taken (_core_io_lsu_dis_uops_0_bits_taken), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_imm_packed (_core_io_lsu_dis_uops_0_bits_imm_packed), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_csr_addr (_core_io_lsu_dis_uops_0_bits_csr_addr), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_rob_idx (_core_io_lsu_dis_uops_0_bits_rob_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldq_idx (_core_io_lsu_dis_uops_0_bits_ldq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_stq_idx (_core_io_lsu_dis_uops_0_bits_stq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_rxq_idx (_core_io_lsu_dis_uops_0_bits_rxq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_pdst (_core_io_lsu_dis_uops_0_bits_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs1 (_core_io_lsu_dis_uops_0_bits_prs1), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs2 (_core_io_lsu_dis_uops_0_bits_prs2), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs3 (_core_io_lsu_dis_uops_0_bits_prs3), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs1_busy (_core_io_lsu_dis_uops_0_bits_prs1_busy), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs2_busy (_core_io_lsu_dis_uops_0_bits_prs2_busy), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_prs3_busy (_core_io_lsu_dis_uops_0_bits_prs3_busy), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_stale_pdst (_core_io_lsu_dis_uops_0_bits_stale_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_exception (_core_io_lsu_dis_uops_0_bits_exception), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_exc_cause (_core_io_lsu_dis_uops_0_bits_exc_cause), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_bypassable (_core_io_lsu_dis_uops_0_bits_bypassable), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_mem_cmd (_core_io_lsu_dis_uops_0_bits_mem_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_mem_size (_core_io_lsu_dis_uops_0_bits_mem_size), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_mem_signed (_core_io_lsu_dis_uops_0_bits_mem_signed), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_fence (_core_io_lsu_dis_uops_0_bits_is_fence), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_fencei (_core_io_lsu_dis_uops_0_bits_is_fencei), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_amo (_core_io_lsu_dis_uops_0_bits_is_amo), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_uses_ldq (_core_io_lsu_dis_uops_0_bits_uses_ldq), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_uses_stq (_core_io_lsu_dis_uops_0_bits_uses_stq), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_0_bits_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_is_unique (_core_io_lsu_dis_uops_0_bits_is_unique), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_flush_on_commit (_core_io_lsu_dis_uops_0_bits_flush_on_commit), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_0_bits_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldst (_core_io_lsu_dis_uops_0_bits_ldst), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs1 (_core_io_lsu_dis_uops_0_bits_lrs1), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs2 (_core_io_lsu_dis_uops_0_bits_lrs2), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs3 (_core_io_lsu_dis_uops_0_bits_lrs3), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_ldst_val (_core_io_lsu_dis_uops_0_bits_ldst_val), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_dst_rtype (_core_io_lsu_dis_uops_0_bits_dst_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs1_rtype (_core_io_lsu_dis_uops_0_bits_lrs1_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_lrs2_rtype (_core_io_lsu_dis_uops_0_bits_lrs2_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_frs3_en (_core_io_lsu_dis_uops_0_bits_frs3_en), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_fp_val (_core_io_lsu_dis_uops_0_bits_fp_val), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_fp_single (_core_io_lsu_dis_uops_0_bits_fp_single), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_xcpt_pf_if (_core_io_lsu_dis_uops_0_bits_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_xcpt_ae_if (_core_io_lsu_dis_uops_0_bits_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_xcpt_ma_if (_core_io_lsu_dis_uops_0_bits_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_bp_debug_if (_core_io_lsu_dis_uops_0_bits_bp_debug_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_bp_xcpt_if (_core_io_lsu_dis_uops_0_bits_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_fsrc (_core_io_lsu_dis_uops_0_bits_debug_fsrc), // @[tile.scala:159:20]
.io_core_dis_uops_0_bits_debug_tsrc (_core_io_lsu_dis_uops_0_bits_debug_tsrc), // @[tile.scala:159:20]
.io_core_dis_uops_1_valid (_core_io_lsu_dis_uops_1_valid), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_uopc (_core_io_lsu_dis_uops_1_bits_uopc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_inst (_core_io_lsu_dis_uops_1_bits_inst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_inst (_core_io_lsu_dis_uops_1_bits_debug_inst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_rvc (_core_io_lsu_dis_uops_1_bits_is_rvc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_pc (_core_io_lsu_dis_uops_1_bits_debug_pc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iq_type (_core_io_lsu_dis_uops_1_bits_iq_type), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_fu_code (_core_io_lsu_dis_uops_1_bits_fu_code), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_br_type (_core_io_lsu_dis_uops_1_bits_ctrl_br_type), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_1_bits_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_1_bits_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_1_bits_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_1_bits_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_1_bits_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_is_load (_core_io_lsu_dis_uops_1_bits_ctrl_is_load), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_is_sta (_core_io_lsu_dis_uops_1_bits_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ctrl_is_std (_core_io_lsu_dis_uops_1_bits_ctrl_is_std), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iw_state (_core_io_lsu_dis_uops_1_bits_iw_state), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_1_bits_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_br (_core_io_lsu_dis_uops_1_bits_is_br), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_jalr (_core_io_lsu_dis_uops_1_bits_is_jalr), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_jal (_core_io_lsu_dis_uops_1_bits_is_jal), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_sfb (_core_io_lsu_dis_uops_1_bits_is_sfb), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_br_mask (_core_io_lsu_dis_uops_1_bits_br_mask), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_br_tag (_core_io_lsu_dis_uops_1_bits_br_tag), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ftq_idx (_core_io_lsu_dis_uops_1_bits_ftq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_edge_inst (_core_io_lsu_dis_uops_1_bits_edge_inst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_pc_lob (_core_io_lsu_dis_uops_1_bits_pc_lob), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_taken (_core_io_lsu_dis_uops_1_bits_taken), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_imm_packed (_core_io_lsu_dis_uops_1_bits_imm_packed), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_csr_addr (_core_io_lsu_dis_uops_1_bits_csr_addr), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_rob_idx (_core_io_lsu_dis_uops_1_bits_rob_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldq_idx (_core_io_lsu_dis_uops_1_bits_ldq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_stq_idx (_core_io_lsu_dis_uops_1_bits_stq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_rxq_idx (_core_io_lsu_dis_uops_1_bits_rxq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_pdst (_core_io_lsu_dis_uops_1_bits_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs1 (_core_io_lsu_dis_uops_1_bits_prs1), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs2 (_core_io_lsu_dis_uops_1_bits_prs2), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs3 (_core_io_lsu_dis_uops_1_bits_prs3), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs1_busy (_core_io_lsu_dis_uops_1_bits_prs1_busy), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs2_busy (_core_io_lsu_dis_uops_1_bits_prs2_busy), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_prs3_busy (_core_io_lsu_dis_uops_1_bits_prs3_busy), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_stale_pdst (_core_io_lsu_dis_uops_1_bits_stale_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_exception (_core_io_lsu_dis_uops_1_bits_exception), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_exc_cause (_core_io_lsu_dis_uops_1_bits_exc_cause), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_bypassable (_core_io_lsu_dis_uops_1_bits_bypassable), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_mem_cmd (_core_io_lsu_dis_uops_1_bits_mem_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_mem_size (_core_io_lsu_dis_uops_1_bits_mem_size), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_mem_signed (_core_io_lsu_dis_uops_1_bits_mem_signed), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_fence (_core_io_lsu_dis_uops_1_bits_is_fence), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_fencei (_core_io_lsu_dis_uops_1_bits_is_fencei), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_amo (_core_io_lsu_dis_uops_1_bits_is_amo), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_uses_ldq (_core_io_lsu_dis_uops_1_bits_uses_ldq), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_uses_stq (_core_io_lsu_dis_uops_1_bits_uses_stq), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_1_bits_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_is_unique (_core_io_lsu_dis_uops_1_bits_is_unique), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_flush_on_commit (_core_io_lsu_dis_uops_1_bits_flush_on_commit), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_1_bits_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldst (_core_io_lsu_dis_uops_1_bits_ldst), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs1 (_core_io_lsu_dis_uops_1_bits_lrs1), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs2 (_core_io_lsu_dis_uops_1_bits_lrs2), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs3 (_core_io_lsu_dis_uops_1_bits_lrs3), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_ldst_val (_core_io_lsu_dis_uops_1_bits_ldst_val), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_dst_rtype (_core_io_lsu_dis_uops_1_bits_dst_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs1_rtype (_core_io_lsu_dis_uops_1_bits_lrs1_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_lrs2_rtype (_core_io_lsu_dis_uops_1_bits_lrs2_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_frs3_en (_core_io_lsu_dis_uops_1_bits_frs3_en), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_fp_val (_core_io_lsu_dis_uops_1_bits_fp_val), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_fp_single (_core_io_lsu_dis_uops_1_bits_fp_single), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_xcpt_pf_if (_core_io_lsu_dis_uops_1_bits_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_xcpt_ae_if (_core_io_lsu_dis_uops_1_bits_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_xcpt_ma_if (_core_io_lsu_dis_uops_1_bits_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_bp_debug_if (_core_io_lsu_dis_uops_1_bits_bp_debug_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_bp_xcpt_if (_core_io_lsu_dis_uops_1_bits_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_fsrc (_core_io_lsu_dis_uops_1_bits_debug_fsrc), // @[tile.scala:159:20]
.io_core_dis_uops_1_bits_debug_tsrc (_core_io_lsu_dis_uops_1_bits_debug_tsrc), // @[tile.scala:159:20]
.io_core_dis_uops_2_valid (_core_io_lsu_dis_uops_2_valid), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_uopc (_core_io_lsu_dis_uops_2_bits_uopc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_inst (_core_io_lsu_dis_uops_2_bits_inst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_inst (_core_io_lsu_dis_uops_2_bits_debug_inst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_rvc (_core_io_lsu_dis_uops_2_bits_is_rvc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_pc (_core_io_lsu_dis_uops_2_bits_debug_pc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iq_type (_core_io_lsu_dis_uops_2_bits_iq_type), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_fu_code (_core_io_lsu_dis_uops_2_bits_fu_code), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_br_type (_core_io_lsu_dis_uops_2_bits_ctrl_br_type), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_op1_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_op2_sel (_core_io_lsu_dis_uops_2_bits_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_imm_sel (_core_io_lsu_dis_uops_2_bits_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_op_fcn (_core_io_lsu_dis_uops_2_bits_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_fcn_dw (_core_io_lsu_dis_uops_2_bits_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_csr_cmd (_core_io_lsu_dis_uops_2_bits_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_is_load (_core_io_lsu_dis_uops_2_bits_ctrl_is_load), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_is_sta (_core_io_lsu_dis_uops_2_bits_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ctrl_is_std (_core_io_lsu_dis_uops_2_bits_ctrl_is_std), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iw_state (_core_io_lsu_dis_uops_2_bits_iw_state), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iw_p1_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_iw_p2_poisoned (_core_io_lsu_dis_uops_2_bits_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_br (_core_io_lsu_dis_uops_2_bits_is_br), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_jalr (_core_io_lsu_dis_uops_2_bits_is_jalr), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_jal (_core_io_lsu_dis_uops_2_bits_is_jal), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_sfb (_core_io_lsu_dis_uops_2_bits_is_sfb), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_br_mask (_core_io_lsu_dis_uops_2_bits_br_mask), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_br_tag (_core_io_lsu_dis_uops_2_bits_br_tag), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ftq_idx (_core_io_lsu_dis_uops_2_bits_ftq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_edge_inst (_core_io_lsu_dis_uops_2_bits_edge_inst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_pc_lob (_core_io_lsu_dis_uops_2_bits_pc_lob), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_taken (_core_io_lsu_dis_uops_2_bits_taken), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_imm_packed (_core_io_lsu_dis_uops_2_bits_imm_packed), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_csr_addr (_core_io_lsu_dis_uops_2_bits_csr_addr), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_rob_idx (_core_io_lsu_dis_uops_2_bits_rob_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldq_idx (_core_io_lsu_dis_uops_2_bits_ldq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_stq_idx (_core_io_lsu_dis_uops_2_bits_stq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_rxq_idx (_core_io_lsu_dis_uops_2_bits_rxq_idx), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_pdst (_core_io_lsu_dis_uops_2_bits_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs1 (_core_io_lsu_dis_uops_2_bits_prs1), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs2 (_core_io_lsu_dis_uops_2_bits_prs2), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs3 (_core_io_lsu_dis_uops_2_bits_prs3), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs1_busy (_core_io_lsu_dis_uops_2_bits_prs1_busy), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs2_busy (_core_io_lsu_dis_uops_2_bits_prs2_busy), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_prs3_busy (_core_io_lsu_dis_uops_2_bits_prs3_busy), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_stale_pdst (_core_io_lsu_dis_uops_2_bits_stale_pdst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_exception (_core_io_lsu_dis_uops_2_bits_exception), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_exc_cause (_core_io_lsu_dis_uops_2_bits_exc_cause), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_bypassable (_core_io_lsu_dis_uops_2_bits_bypassable), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_mem_cmd (_core_io_lsu_dis_uops_2_bits_mem_cmd), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_mem_size (_core_io_lsu_dis_uops_2_bits_mem_size), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_mem_signed (_core_io_lsu_dis_uops_2_bits_mem_signed), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_fence (_core_io_lsu_dis_uops_2_bits_is_fence), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_fencei (_core_io_lsu_dis_uops_2_bits_is_fencei), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_amo (_core_io_lsu_dis_uops_2_bits_is_amo), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_uses_ldq (_core_io_lsu_dis_uops_2_bits_uses_ldq), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_uses_stq (_core_io_lsu_dis_uops_2_bits_uses_stq), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_sys_pc2epc (_core_io_lsu_dis_uops_2_bits_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_is_unique (_core_io_lsu_dis_uops_2_bits_is_unique), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_flush_on_commit (_core_io_lsu_dis_uops_2_bits_flush_on_commit), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldst_is_rs1 (_core_io_lsu_dis_uops_2_bits_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldst (_core_io_lsu_dis_uops_2_bits_ldst), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs1 (_core_io_lsu_dis_uops_2_bits_lrs1), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs2 (_core_io_lsu_dis_uops_2_bits_lrs2), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs3 (_core_io_lsu_dis_uops_2_bits_lrs3), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_ldst_val (_core_io_lsu_dis_uops_2_bits_ldst_val), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_dst_rtype (_core_io_lsu_dis_uops_2_bits_dst_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs1_rtype (_core_io_lsu_dis_uops_2_bits_lrs1_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_lrs2_rtype (_core_io_lsu_dis_uops_2_bits_lrs2_rtype), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_frs3_en (_core_io_lsu_dis_uops_2_bits_frs3_en), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_fp_val (_core_io_lsu_dis_uops_2_bits_fp_val), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_fp_single (_core_io_lsu_dis_uops_2_bits_fp_single), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_xcpt_pf_if (_core_io_lsu_dis_uops_2_bits_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_xcpt_ae_if (_core_io_lsu_dis_uops_2_bits_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_xcpt_ma_if (_core_io_lsu_dis_uops_2_bits_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_bp_debug_if (_core_io_lsu_dis_uops_2_bits_bp_debug_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_bp_xcpt_if (_core_io_lsu_dis_uops_2_bits_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_fsrc (_core_io_lsu_dis_uops_2_bits_debug_fsrc), // @[tile.scala:159:20]
.io_core_dis_uops_2_bits_debug_tsrc (_core_io_lsu_dis_uops_2_bits_debug_tsrc), // @[tile.scala:159:20]
.io_core_dis_ldq_idx_0 (_lsu_io_core_dis_ldq_idx_0),
.io_core_dis_ldq_idx_1 (_lsu_io_core_dis_ldq_idx_1),
.io_core_dis_ldq_idx_2 (_lsu_io_core_dis_ldq_idx_2),
.io_core_dis_stq_idx_0 (_lsu_io_core_dis_stq_idx_0),
.io_core_dis_stq_idx_1 (_lsu_io_core_dis_stq_idx_1),
.io_core_dis_stq_idx_2 (_lsu_io_core_dis_stq_idx_2),
.io_core_ldq_full_0 (_lsu_io_core_ldq_full_0),
.io_core_ldq_full_1 (_lsu_io_core_ldq_full_1),
.io_core_ldq_full_2 (_lsu_io_core_ldq_full_2),
.io_core_stq_full_0 (_lsu_io_core_stq_full_0),
.io_core_stq_full_1 (_lsu_io_core_stq_full_1),
.io_core_stq_full_2 (_lsu_io_core_stq_full_2),
.io_core_fp_stdata_ready (_lsu_io_core_fp_stdata_ready),
.io_core_fp_stdata_valid (_core_io_lsu_fp_stdata_valid), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_uop_uopc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_inst (_core_io_lsu_fp_stdata_bits_uop_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_uop_debug_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_uop_is_rvc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_uop_debug_pc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_uop_iq_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_uop_fu_code), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_uop_iw_state), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_uop_is_br), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_uop_is_jalr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_uop_is_jal), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_uop_is_sfb), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_uop_br_mask), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_uop_br_tag), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_uop_edge_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_uop_pc_lob), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_taken (_core_io_lsu_fp_stdata_bits_uop_taken), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_uop_imm_packed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_uop_csr_addr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_uop_rob_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_uop_stq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_uop_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_uop_prs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_uop_prs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_uop_prs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_uop_ppred), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_exception (_core_io_lsu_fp_stdata_bits_uop_exception), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_uop_exc_cause), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_uop_bypassable), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_uop_mem_size), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_uop_mem_signed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_uop_is_fence), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_uop_is_fencei), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_uop_is_amo), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_uop_uses_stq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_uop_is_unique), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_uop_ldst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_uop_lrs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_uop_lrs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_uop_lrs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_uop_ldst_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_uop_frs3_en), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_uop_fp_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_uop_fp_single), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_data (_core_io_lsu_fp_stdata_bits_data), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_predicated (_core_io_lsu_fp_stdata_bits_predicated), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_valid (_core_io_lsu_fp_stdata_bits_fflags_valid), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_uopc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uopc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_rvc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_rvc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_pc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_pc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iq_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iq_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_fu_code (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fu_code), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_br_type (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_load (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ctrl_is_std (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iw_state (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_state), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_br (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_br), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_jalr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jalr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_jal (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_jal), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_sfb (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sfb), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_br_mask (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_mask), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_br_tag (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_br_tag), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ftq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_edge_inst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_edge_inst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_pc_lob (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pc_lob), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_taken (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_taken), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_imm_packed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_imm_packed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_csr_addr (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_csr_addr), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_rob_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rob_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_stq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_rxq_idx (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ppred (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs1_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs2_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_prs3_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ppred_busy (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_stale_pdst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_exception (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exception), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_exc_cause (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_exc_cause), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_bypassable (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bypassable), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_mem_cmd (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_mem_size (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_size), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_mem_signed (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_mem_signed), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_fence (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fence), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_fencei (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_fencei), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_amo (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_amo), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_uses_ldq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_uses_stq (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_uses_stq), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_is_unique (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_is_unique), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_flush_on_commit (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldst (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs1 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs2 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs3 (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs3), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_ldst_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_ldst_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_dst_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs1_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_lrs2_rtype (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_frs3_en (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_frs3_en), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_fp_val (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_val), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_fp_single (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_fp_single), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_bp_debug_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_fsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_uop_debug_tsrc (_core_io_lsu_fp_stdata_bits_fflags_bits_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_fp_stdata_bits_fflags_bits_flags (_core_io_lsu_fp_stdata_bits_fflags_bits_flags), // @[tile.scala:159:20]
.io_core_commit_valids_0 (_core_io_lsu_commit_valids_0), // @[tile.scala:159:20]
.io_core_commit_valids_1 (_core_io_lsu_commit_valids_1), // @[tile.scala:159:20]
.io_core_commit_valids_2 (_core_io_lsu_commit_valids_2), // @[tile.scala:159:20]
.io_core_commit_arch_valids_0 (_core_io_lsu_commit_arch_valids_0), // @[tile.scala:159:20]
.io_core_commit_arch_valids_1 (_core_io_lsu_commit_arch_valids_1), // @[tile.scala:159:20]
.io_core_commit_arch_valids_2 (_core_io_lsu_commit_arch_valids_2), // @[tile.scala:159:20]
.io_core_commit_uops_0_uopc (_core_io_lsu_commit_uops_0_uopc), // @[tile.scala:159:20]
.io_core_commit_uops_0_inst (_core_io_lsu_commit_uops_0_inst), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_inst (_core_io_lsu_commit_uops_0_debug_inst), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_rvc (_core_io_lsu_commit_uops_0_is_rvc), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_pc (_core_io_lsu_commit_uops_0_debug_pc), // @[tile.scala:159:20]
.io_core_commit_uops_0_iq_type (_core_io_lsu_commit_uops_0_iq_type), // @[tile.scala:159:20]
.io_core_commit_uops_0_fu_code (_core_io_lsu_commit_uops_0_fu_code), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_br_type (_core_io_lsu_commit_uops_0_ctrl_br_type), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_op1_sel (_core_io_lsu_commit_uops_0_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_op2_sel (_core_io_lsu_commit_uops_0_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_imm_sel (_core_io_lsu_commit_uops_0_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_op_fcn (_core_io_lsu_commit_uops_0_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_fcn_dw (_core_io_lsu_commit_uops_0_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_csr_cmd (_core_io_lsu_commit_uops_0_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_is_load (_core_io_lsu_commit_uops_0_ctrl_is_load), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_is_sta (_core_io_lsu_commit_uops_0_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_commit_uops_0_ctrl_is_std (_core_io_lsu_commit_uops_0_ctrl_is_std), // @[tile.scala:159:20]
.io_core_commit_uops_0_iw_state (_core_io_lsu_commit_uops_0_iw_state), // @[tile.scala:159:20]
.io_core_commit_uops_0_iw_p1_poisoned (_core_io_lsu_commit_uops_0_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_0_iw_p2_poisoned (_core_io_lsu_commit_uops_0_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_br (_core_io_lsu_commit_uops_0_is_br), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_jalr (_core_io_lsu_commit_uops_0_is_jalr), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_jal (_core_io_lsu_commit_uops_0_is_jal), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_sfb (_core_io_lsu_commit_uops_0_is_sfb), // @[tile.scala:159:20]
.io_core_commit_uops_0_br_mask (_core_io_lsu_commit_uops_0_br_mask), // @[tile.scala:159:20]
.io_core_commit_uops_0_br_tag (_core_io_lsu_commit_uops_0_br_tag), // @[tile.scala:159:20]
.io_core_commit_uops_0_ftq_idx (_core_io_lsu_commit_uops_0_ftq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_edge_inst (_core_io_lsu_commit_uops_0_edge_inst), // @[tile.scala:159:20]
.io_core_commit_uops_0_pc_lob (_core_io_lsu_commit_uops_0_pc_lob), // @[tile.scala:159:20]
.io_core_commit_uops_0_taken (_core_io_lsu_commit_uops_0_taken), // @[tile.scala:159:20]
.io_core_commit_uops_0_imm_packed (_core_io_lsu_commit_uops_0_imm_packed), // @[tile.scala:159:20]
.io_core_commit_uops_0_csr_addr (_core_io_lsu_commit_uops_0_csr_addr), // @[tile.scala:159:20]
.io_core_commit_uops_0_rob_idx (_core_io_lsu_commit_uops_0_rob_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldq_idx (_core_io_lsu_commit_uops_0_ldq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_stq_idx (_core_io_lsu_commit_uops_0_stq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_rxq_idx (_core_io_lsu_commit_uops_0_rxq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_0_pdst (_core_io_lsu_commit_uops_0_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs1 (_core_io_lsu_commit_uops_0_prs1), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs2 (_core_io_lsu_commit_uops_0_prs2), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs3 (_core_io_lsu_commit_uops_0_prs3), // @[tile.scala:159:20]
.io_core_commit_uops_0_ppred (_core_io_lsu_commit_uops_0_ppred), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs1_busy (_core_io_lsu_commit_uops_0_prs1_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs2_busy (_core_io_lsu_commit_uops_0_prs2_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_prs3_busy (_core_io_lsu_commit_uops_0_prs3_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_ppred_busy (_core_io_lsu_commit_uops_0_ppred_busy), // @[tile.scala:159:20]
.io_core_commit_uops_0_stale_pdst (_core_io_lsu_commit_uops_0_stale_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_0_exception (_core_io_lsu_commit_uops_0_exception), // @[tile.scala:159:20]
.io_core_commit_uops_0_exc_cause (_core_io_lsu_commit_uops_0_exc_cause), // @[tile.scala:159:20]
.io_core_commit_uops_0_bypassable (_core_io_lsu_commit_uops_0_bypassable), // @[tile.scala:159:20]
.io_core_commit_uops_0_mem_cmd (_core_io_lsu_commit_uops_0_mem_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_0_mem_size (_core_io_lsu_commit_uops_0_mem_size), // @[tile.scala:159:20]
.io_core_commit_uops_0_mem_signed (_core_io_lsu_commit_uops_0_mem_signed), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_fence (_core_io_lsu_commit_uops_0_is_fence), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_fencei (_core_io_lsu_commit_uops_0_is_fencei), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_amo (_core_io_lsu_commit_uops_0_is_amo), // @[tile.scala:159:20]
.io_core_commit_uops_0_uses_ldq (_core_io_lsu_commit_uops_0_uses_ldq), // @[tile.scala:159:20]
.io_core_commit_uops_0_uses_stq (_core_io_lsu_commit_uops_0_uses_stq), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_sys_pc2epc (_core_io_lsu_commit_uops_0_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_commit_uops_0_is_unique (_core_io_lsu_commit_uops_0_is_unique), // @[tile.scala:159:20]
.io_core_commit_uops_0_flush_on_commit (_core_io_lsu_commit_uops_0_flush_on_commit), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldst_is_rs1 (_core_io_lsu_commit_uops_0_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldst (_core_io_lsu_commit_uops_0_ldst), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs1 (_core_io_lsu_commit_uops_0_lrs1), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs2 (_core_io_lsu_commit_uops_0_lrs2), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs3 (_core_io_lsu_commit_uops_0_lrs3), // @[tile.scala:159:20]
.io_core_commit_uops_0_ldst_val (_core_io_lsu_commit_uops_0_ldst_val), // @[tile.scala:159:20]
.io_core_commit_uops_0_dst_rtype (_core_io_lsu_commit_uops_0_dst_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs1_rtype (_core_io_lsu_commit_uops_0_lrs1_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_0_lrs2_rtype (_core_io_lsu_commit_uops_0_lrs2_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_0_frs3_en (_core_io_lsu_commit_uops_0_frs3_en), // @[tile.scala:159:20]
.io_core_commit_uops_0_fp_val (_core_io_lsu_commit_uops_0_fp_val), // @[tile.scala:159:20]
.io_core_commit_uops_0_fp_single (_core_io_lsu_commit_uops_0_fp_single), // @[tile.scala:159:20]
.io_core_commit_uops_0_xcpt_pf_if (_core_io_lsu_commit_uops_0_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_xcpt_ae_if (_core_io_lsu_commit_uops_0_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_xcpt_ma_if (_core_io_lsu_commit_uops_0_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_bp_debug_if (_core_io_lsu_commit_uops_0_bp_debug_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_bp_xcpt_if (_core_io_lsu_commit_uops_0_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_fsrc (_core_io_lsu_commit_uops_0_debug_fsrc), // @[tile.scala:159:20]
.io_core_commit_uops_0_debug_tsrc (_core_io_lsu_commit_uops_0_debug_tsrc), // @[tile.scala:159:20]
.io_core_commit_uops_1_uopc (_core_io_lsu_commit_uops_1_uopc), // @[tile.scala:159:20]
.io_core_commit_uops_1_inst (_core_io_lsu_commit_uops_1_inst), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_inst (_core_io_lsu_commit_uops_1_debug_inst), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_rvc (_core_io_lsu_commit_uops_1_is_rvc), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_pc (_core_io_lsu_commit_uops_1_debug_pc), // @[tile.scala:159:20]
.io_core_commit_uops_1_iq_type (_core_io_lsu_commit_uops_1_iq_type), // @[tile.scala:159:20]
.io_core_commit_uops_1_fu_code (_core_io_lsu_commit_uops_1_fu_code), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_br_type (_core_io_lsu_commit_uops_1_ctrl_br_type), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_op1_sel (_core_io_lsu_commit_uops_1_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_op2_sel (_core_io_lsu_commit_uops_1_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_imm_sel (_core_io_lsu_commit_uops_1_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_op_fcn (_core_io_lsu_commit_uops_1_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_fcn_dw (_core_io_lsu_commit_uops_1_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_csr_cmd (_core_io_lsu_commit_uops_1_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_is_load (_core_io_lsu_commit_uops_1_ctrl_is_load), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_is_sta (_core_io_lsu_commit_uops_1_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_commit_uops_1_ctrl_is_std (_core_io_lsu_commit_uops_1_ctrl_is_std), // @[tile.scala:159:20]
.io_core_commit_uops_1_iw_state (_core_io_lsu_commit_uops_1_iw_state), // @[tile.scala:159:20]
.io_core_commit_uops_1_iw_p1_poisoned (_core_io_lsu_commit_uops_1_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_1_iw_p2_poisoned (_core_io_lsu_commit_uops_1_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_br (_core_io_lsu_commit_uops_1_is_br), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_jalr (_core_io_lsu_commit_uops_1_is_jalr), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_jal (_core_io_lsu_commit_uops_1_is_jal), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_sfb (_core_io_lsu_commit_uops_1_is_sfb), // @[tile.scala:159:20]
.io_core_commit_uops_1_br_mask (_core_io_lsu_commit_uops_1_br_mask), // @[tile.scala:159:20]
.io_core_commit_uops_1_br_tag (_core_io_lsu_commit_uops_1_br_tag), // @[tile.scala:159:20]
.io_core_commit_uops_1_ftq_idx (_core_io_lsu_commit_uops_1_ftq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_edge_inst (_core_io_lsu_commit_uops_1_edge_inst), // @[tile.scala:159:20]
.io_core_commit_uops_1_pc_lob (_core_io_lsu_commit_uops_1_pc_lob), // @[tile.scala:159:20]
.io_core_commit_uops_1_taken (_core_io_lsu_commit_uops_1_taken), // @[tile.scala:159:20]
.io_core_commit_uops_1_imm_packed (_core_io_lsu_commit_uops_1_imm_packed), // @[tile.scala:159:20]
.io_core_commit_uops_1_csr_addr (_core_io_lsu_commit_uops_1_csr_addr), // @[tile.scala:159:20]
.io_core_commit_uops_1_rob_idx (_core_io_lsu_commit_uops_1_rob_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldq_idx (_core_io_lsu_commit_uops_1_ldq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_stq_idx (_core_io_lsu_commit_uops_1_stq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_rxq_idx (_core_io_lsu_commit_uops_1_rxq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_1_pdst (_core_io_lsu_commit_uops_1_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs1 (_core_io_lsu_commit_uops_1_prs1), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs2 (_core_io_lsu_commit_uops_1_prs2), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs3 (_core_io_lsu_commit_uops_1_prs3), // @[tile.scala:159:20]
.io_core_commit_uops_1_ppred (_core_io_lsu_commit_uops_1_ppred), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs1_busy (_core_io_lsu_commit_uops_1_prs1_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs2_busy (_core_io_lsu_commit_uops_1_prs2_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_prs3_busy (_core_io_lsu_commit_uops_1_prs3_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_ppred_busy (_core_io_lsu_commit_uops_1_ppred_busy), // @[tile.scala:159:20]
.io_core_commit_uops_1_stale_pdst (_core_io_lsu_commit_uops_1_stale_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_1_exception (_core_io_lsu_commit_uops_1_exception), // @[tile.scala:159:20]
.io_core_commit_uops_1_exc_cause (_core_io_lsu_commit_uops_1_exc_cause), // @[tile.scala:159:20]
.io_core_commit_uops_1_bypassable (_core_io_lsu_commit_uops_1_bypassable), // @[tile.scala:159:20]
.io_core_commit_uops_1_mem_cmd (_core_io_lsu_commit_uops_1_mem_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_1_mem_size (_core_io_lsu_commit_uops_1_mem_size), // @[tile.scala:159:20]
.io_core_commit_uops_1_mem_signed (_core_io_lsu_commit_uops_1_mem_signed), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_fence (_core_io_lsu_commit_uops_1_is_fence), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_fencei (_core_io_lsu_commit_uops_1_is_fencei), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_amo (_core_io_lsu_commit_uops_1_is_amo), // @[tile.scala:159:20]
.io_core_commit_uops_1_uses_ldq (_core_io_lsu_commit_uops_1_uses_ldq), // @[tile.scala:159:20]
.io_core_commit_uops_1_uses_stq (_core_io_lsu_commit_uops_1_uses_stq), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_sys_pc2epc (_core_io_lsu_commit_uops_1_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_commit_uops_1_is_unique (_core_io_lsu_commit_uops_1_is_unique), // @[tile.scala:159:20]
.io_core_commit_uops_1_flush_on_commit (_core_io_lsu_commit_uops_1_flush_on_commit), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldst_is_rs1 (_core_io_lsu_commit_uops_1_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldst (_core_io_lsu_commit_uops_1_ldst), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs1 (_core_io_lsu_commit_uops_1_lrs1), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs2 (_core_io_lsu_commit_uops_1_lrs2), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs3 (_core_io_lsu_commit_uops_1_lrs3), // @[tile.scala:159:20]
.io_core_commit_uops_1_ldst_val (_core_io_lsu_commit_uops_1_ldst_val), // @[tile.scala:159:20]
.io_core_commit_uops_1_dst_rtype (_core_io_lsu_commit_uops_1_dst_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs1_rtype (_core_io_lsu_commit_uops_1_lrs1_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_1_lrs2_rtype (_core_io_lsu_commit_uops_1_lrs2_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_1_frs3_en (_core_io_lsu_commit_uops_1_frs3_en), // @[tile.scala:159:20]
.io_core_commit_uops_1_fp_val (_core_io_lsu_commit_uops_1_fp_val), // @[tile.scala:159:20]
.io_core_commit_uops_1_fp_single (_core_io_lsu_commit_uops_1_fp_single), // @[tile.scala:159:20]
.io_core_commit_uops_1_xcpt_pf_if (_core_io_lsu_commit_uops_1_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_xcpt_ae_if (_core_io_lsu_commit_uops_1_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_xcpt_ma_if (_core_io_lsu_commit_uops_1_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_bp_debug_if (_core_io_lsu_commit_uops_1_bp_debug_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_bp_xcpt_if (_core_io_lsu_commit_uops_1_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_fsrc (_core_io_lsu_commit_uops_1_debug_fsrc), // @[tile.scala:159:20]
.io_core_commit_uops_1_debug_tsrc (_core_io_lsu_commit_uops_1_debug_tsrc), // @[tile.scala:159:20]
.io_core_commit_uops_2_uopc (_core_io_lsu_commit_uops_2_uopc), // @[tile.scala:159:20]
.io_core_commit_uops_2_inst (_core_io_lsu_commit_uops_2_inst), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_inst (_core_io_lsu_commit_uops_2_debug_inst), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_rvc (_core_io_lsu_commit_uops_2_is_rvc), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_pc (_core_io_lsu_commit_uops_2_debug_pc), // @[tile.scala:159:20]
.io_core_commit_uops_2_iq_type (_core_io_lsu_commit_uops_2_iq_type), // @[tile.scala:159:20]
.io_core_commit_uops_2_fu_code (_core_io_lsu_commit_uops_2_fu_code), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_br_type (_core_io_lsu_commit_uops_2_ctrl_br_type), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_op1_sel (_core_io_lsu_commit_uops_2_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_op2_sel (_core_io_lsu_commit_uops_2_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_imm_sel (_core_io_lsu_commit_uops_2_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_op_fcn (_core_io_lsu_commit_uops_2_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_fcn_dw (_core_io_lsu_commit_uops_2_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_csr_cmd (_core_io_lsu_commit_uops_2_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_is_load (_core_io_lsu_commit_uops_2_ctrl_is_load), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_is_sta (_core_io_lsu_commit_uops_2_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_commit_uops_2_ctrl_is_std (_core_io_lsu_commit_uops_2_ctrl_is_std), // @[tile.scala:159:20]
.io_core_commit_uops_2_iw_state (_core_io_lsu_commit_uops_2_iw_state), // @[tile.scala:159:20]
.io_core_commit_uops_2_iw_p1_poisoned (_core_io_lsu_commit_uops_2_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_2_iw_p2_poisoned (_core_io_lsu_commit_uops_2_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_br (_core_io_lsu_commit_uops_2_is_br), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_jalr (_core_io_lsu_commit_uops_2_is_jalr), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_jal (_core_io_lsu_commit_uops_2_is_jal), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_sfb (_core_io_lsu_commit_uops_2_is_sfb), // @[tile.scala:159:20]
.io_core_commit_uops_2_br_mask (_core_io_lsu_commit_uops_2_br_mask), // @[tile.scala:159:20]
.io_core_commit_uops_2_br_tag (_core_io_lsu_commit_uops_2_br_tag), // @[tile.scala:159:20]
.io_core_commit_uops_2_ftq_idx (_core_io_lsu_commit_uops_2_ftq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_edge_inst (_core_io_lsu_commit_uops_2_edge_inst), // @[tile.scala:159:20]
.io_core_commit_uops_2_pc_lob (_core_io_lsu_commit_uops_2_pc_lob), // @[tile.scala:159:20]
.io_core_commit_uops_2_taken (_core_io_lsu_commit_uops_2_taken), // @[tile.scala:159:20]
.io_core_commit_uops_2_imm_packed (_core_io_lsu_commit_uops_2_imm_packed), // @[tile.scala:159:20]
.io_core_commit_uops_2_csr_addr (_core_io_lsu_commit_uops_2_csr_addr), // @[tile.scala:159:20]
.io_core_commit_uops_2_rob_idx (_core_io_lsu_commit_uops_2_rob_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldq_idx (_core_io_lsu_commit_uops_2_ldq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_stq_idx (_core_io_lsu_commit_uops_2_stq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_rxq_idx (_core_io_lsu_commit_uops_2_rxq_idx), // @[tile.scala:159:20]
.io_core_commit_uops_2_pdst (_core_io_lsu_commit_uops_2_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs1 (_core_io_lsu_commit_uops_2_prs1), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs2 (_core_io_lsu_commit_uops_2_prs2), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs3 (_core_io_lsu_commit_uops_2_prs3), // @[tile.scala:159:20]
.io_core_commit_uops_2_ppred (_core_io_lsu_commit_uops_2_ppred), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs1_busy (_core_io_lsu_commit_uops_2_prs1_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs2_busy (_core_io_lsu_commit_uops_2_prs2_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_prs3_busy (_core_io_lsu_commit_uops_2_prs3_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_ppred_busy (_core_io_lsu_commit_uops_2_ppred_busy), // @[tile.scala:159:20]
.io_core_commit_uops_2_stale_pdst (_core_io_lsu_commit_uops_2_stale_pdst), // @[tile.scala:159:20]
.io_core_commit_uops_2_exception (_core_io_lsu_commit_uops_2_exception), // @[tile.scala:159:20]
.io_core_commit_uops_2_exc_cause (_core_io_lsu_commit_uops_2_exc_cause), // @[tile.scala:159:20]
.io_core_commit_uops_2_bypassable (_core_io_lsu_commit_uops_2_bypassable), // @[tile.scala:159:20]
.io_core_commit_uops_2_mem_cmd (_core_io_lsu_commit_uops_2_mem_cmd), // @[tile.scala:159:20]
.io_core_commit_uops_2_mem_size (_core_io_lsu_commit_uops_2_mem_size), // @[tile.scala:159:20]
.io_core_commit_uops_2_mem_signed (_core_io_lsu_commit_uops_2_mem_signed), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_fence (_core_io_lsu_commit_uops_2_is_fence), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_fencei (_core_io_lsu_commit_uops_2_is_fencei), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_amo (_core_io_lsu_commit_uops_2_is_amo), // @[tile.scala:159:20]
.io_core_commit_uops_2_uses_ldq (_core_io_lsu_commit_uops_2_uses_ldq), // @[tile.scala:159:20]
.io_core_commit_uops_2_uses_stq (_core_io_lsu_commit_uops_2_uses_stq), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_sys_pc2epc (_core_io_lsu_commit_uops_2_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_commit_uops_2_is_unique (_core_io_lsu_commit_uops_2_is_unique), // @[tile.scala:159:20]
.io_core_commit_uops_2_flush_on_commit (_core_io_lsu_commit_uops_2_flush_on_commit), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldst_is_rs1 (_core_io_lsu_commit_uops_2_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldst (_core_io_lsu_commit_uops_2_ldst), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs1 (_core_io_lsu_commit_uops_2_lrs1), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs2 (_core_io_lsu_commit_uops_2_lrs2), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs3 (_core_io_lsu_commit_uops_2_lrs3), // @[tile.scala:159:20]
.io_core_commit_uops_2_ldst_val (_core_io_lsu_commit_uops_2_ldst_val), // @[tile.scala:159:20]
.io_core_commit_uops_2_dst_rtype (_core_io_lsu_commit_uops_2_dst_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs1_rtype (_core_io_lsu_commit_uops_2_lrs1_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_2_lrs2_rtype (_core_io_lsu_commit_uops_2_lrs2_rtype), // @[tile.scala:159:20]
.io_core_commit_uops_2_frs3_en (_core_io_lsu_commit_uops_2_frs3_en), // @[tile.scala:159:20]
.io_core_commit_uops_2_fp_val (_core_io_lsu_commit_uops_2_fp_val), // @[tile.scala:159:20]
.io_core_commit_uops_2_fp_single (_core_io_lsu_commit_uops_2_fp_single), // @[tile.scala:159:20]
.io_core_commit_uops_2_xcpt_pf_if (_core_io_lsu_commit_uops_2_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_xcpt_ae_if (_core_io_lsu_commit_uops_2_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_xcpt_ma_if (_core_io_lsu_commit_uops_2_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_bp_debug_if (_core_io_lsu_commit_uops_2_bp_debug_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_bp_xcpt_if (_core_io_lsu_commit_uops_2_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_fsrc (_core_io_lsu_commit_uops_2_debug_fsrc), // @[tile.scala:159:20]
.io_core_commit_uops_2_debug_tsrc (_core_io_lsu_commit_uops_2_debug_tsrc), // @[tile.scala:159:20]
.io_core_commit_fflags_valid (_core_io_lsu_commit_fflags_valid), // @[tile.scala:159:20]
.io_core_commit_fflags_bits (_core_io_lsu_commit_fflags_bits), // @[tile.scala:159:20]
.io_core_commit_debug_insts_0 (_core_io_lsu_commit_debug_insts_0), // @[tile.scala:159:20]
.io_core_commit_debug_insts_1 (_core_io_lsu_commit_debug_insts_1), // @[tile.scala:159:20]
.io_core_commit_debug_insts_2 (_core_io_lsu_commit_debug_insts_2), // @[tile.scala:159:20]
.io_core_commit_rbk_valids_0 (_core_io_lsu_commit_rbk_valids_0), // @[tile.scala:159:20]
.io_core_commit_rbk_valids_1 (_core_io_lsu_commit_rbk_valids_1), // @[tile.scala:159:20]
.io_core_commit_rbk_valids_2 (_core_io_lsu_commit_rbk_valids_2), // @[tile.scala:159:20]
.io_core_commit_rollback (_core_io_lsu_commit_rollback), // @[tile.scala:159:20]
.io_core_commit_debug_wdata_0 (_core_io_lsu_commit_debug_wdata_0), // @[tile.scala:159:20]
.io_core_commit_debug_wdata_1 (_core_io_lsu_commit_debug_wdata_1), // @[tile.scala:159:20]
.io_core_commit_debug_wdata_2 (_core_io_lsu_commit_debug_wdata_2), // @[tile.scala:159:20]
.io_core_commit_load_at_rob_head (_core_io_lsu_commit_load_at_rob_head), // @[tile.scala:159:20]
.io_core_clr_bsy_0_valid (_lsu_io_core_clr_bsy_0_valid),
.io_core_clr_bsy_0_bits (_lsu_io_core_clr_bsy_0_bits),
.io_core_clr_bsy_1_valid (_lsu_io_core_clr_bsy_1_valid),
.io_core_clr_bsy_1_bits (_lsu_io_core_clr_bsy_1_bits),
.io_core_clr_unsafe_0_bits (_lsu_io_core_clr_unsafe_0_bits),
.io_core_fence_dmem (_core_io_lsu_fence_dmem), // @[tile.scala:159:20]
.io_core_spec_ld_wakeup_0_valid (_lsu_io_core_spec_ld_wakeup_0_valid),
.io_core_spec_ld_wakeup_0_bits (_lsu_io_core_spec_ld_wakeup_0_bits),
.io_core_ld_miss (_lsu_io_core_ld_miss),
.io_core_brupdate_b1_resolve_mask (_core_io_lsu_brupdate_b1_resolve_mask), // @[tile.scala:159:20]
.io_core_brupdate_b1_mispredict_mask (_core_io_lsu_brupdate_b1_mispredict_mask), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_uopc (_core_io_lsu_brupdate_b2_uop_uopc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_inst (_core_io_lsu_brupdate_b2_uop_inst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_inst (_core_io_lsu_brupdate_b2_uop_debug_inst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_rvc (_core_io_lsu_brupdate_b2_uop_is_rvc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_pc (_core_io_lsu_brupdate_b2_uop_debug_pc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iq_type (_core_io_lsu_brupdate_b2_uop_iq_type), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_fu_code (_core_io_lsu_brupdate_b2_uop_fu_code), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_br_type (_core_io_lsu_brupdate_b2_uop_ctrl_br_type), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_op1_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op1_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_op2_sel (_core_io_lsu_brupdate_b2_uop_ctrl_op2_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_imm_sel (_core_io_lsu_brupdate_b2_uop_ctrl_imm_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_op_fcn (_core_io_lsu_brupdate_b2_uop_ctrl_op_fcn), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_fcn_dw (_core_io_lsu_brupdate_b2_uop_ctrl_fcn_dw), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_csr_cmd (_core_io_lsu_brupdate_b2_uop_ctrl_csr_cmd), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_is_load (_core_io_lsu_brupdate_b2_uop_ctrl_is_load), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_is_sta (_core_io_lsu_brupdate_b2_uop_ctrl_is_sta), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ctrl_is_std (_core_io_lsu_brupdate_b2_uop_ctrl_is_std), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iw_state (_core_io_lsu_brupdate_b2_uop_iw_state), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iw_p1_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p1_poisoned), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_iw_p2_poisoned (_core_io_lsu_brupdate_b2_uop_iw_p2_poisoned), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_br (_core_io_lsu_brupdate_b2_uop_is_br), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_jalr (_core_io_lsu_brupdate_b2_uop_is_jalr), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_jal (_core_io_lsu_brupdate_b2_uop_is_jal), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_sfb (_core_io_lsu_brupdate_b2_uop_is_sfb), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_br_mask (_core_io_lsu_brupdate_b2_uop_br_mask), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_br_tag (_core_io_lsu_brupdate_b2_uop_br_tag), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ftq_idx (_core_io_lsu_brupdate_b2_uop_ftq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_edge_inst (_core_io_lsu_brupdate_b2_uop_edge_inst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_pc_lob (_core_io_lsu_brupdate_b2_uop_pc_lob), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_taken (_core_io_lsu_brupdate_b2_uop_taken), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_imm_packed (_core_io_lsu_brupdate_b2_uop_imm_packed), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_csr_addr (_core_io_lsu_brupdate_b2_uop_csr_addr), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_rob_idx (_core_io_lsu_brupdate_b2_uop_rob_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldq_idx (_core_io_lsu_brupdate_b2_uop_ldq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_stq_idx (_core_io_lsu_brupdate_b2_uop_stq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_rxq_idx (_core_io_lsu_brupdate_b2_uop_rxq_idx), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_pdst (_core_io_lsu_brupdate_b2_uop_pdst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs1 (_core_io_lsu_brupdate_b2_uop_prs1), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs2 (_core_io_lsu_brupdate_b2_uop_prs2), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs3 (_core_io_lsu_brupdate_b2_uop_prs3), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ppred (_core_io_lsu_brupdate_b2_uop_ppred), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs1_busy (_core_io_lsu_brupdate_b2_uop_prs1_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs2_busy (_core_io_lsu_brupdate_b2_uop_prs2_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_prs3_busy (_core_io_lsu_brupdate_b2_uop_prs3_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ppred_busy (_core_io_lsu_brupdate_b2_uop_ppred_busy), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_stale_pdst (_core_io_lsu_brupdate_b2_uop_stale_pdst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_exception (_core_io_lsu_brupdate_b2_uop_exception), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_exc_cause (_core_io_lsu_brupdate_b2_uop_exc_cause), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_bypassable (_core_io_lsu_brupdate_b2_uop_bypassable), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_mem_cmd (_core_io_lsu_brupdate_b2_uop_mem_cmd), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_mem_size (_core_io_lsu_brupdate_b2_uop_mem_size), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_mem_signed (_core_io_lsu_brupdate_b2_uop_mem_signed), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_fence (_core_io_lsu_brupdate_b2_uop_is_fence), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_fencei (_core_io_lsu_brupdate_b2_uop_is_fencei), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_amo (_core_io_lsu_brupdate_b2_uop_is_amo), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_uses_ldq (_core_io_lsu_brupdate_b2_uop_uses_ldq), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_uses_stq (_core_io_lsu_brupdate_b2_uop_uses_stq), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_sys_pc2epc (_core_io_lsu_brupdate_b2_uop_is_sys_pc2epc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_is_unique (_core_io_lsu_brupdate_b2_uop_is_unique), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_flush_on_commit (_core_io_lsu_brupdate_b2_uop_flush_on_commit), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldst_is_rs1 (_core_io_lsu_brupdate_b2_uop_ldst_is_rs1), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldst (_core_io_lsu_brupdate_b2_uop_ldst), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs1 (_core_io_lsu_brupdate_b2_uop_lrs1), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs2 (_core_io_lsu_brupdate_b2_uop_lrs2), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs3 (_core_io_lsu_brupdate_b2_uop_lrs3), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_ldst_val (_core_io_lsu_brupdate_b2_uop_ldst_val), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_dst_rtype (_core_io_lsu_brupdate_b2_uop_dst_rtype), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs1_rtype (_core_io_lsu_brupdate_b2_uop_lrs1_rtype), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_lrs2_rtype (_core_io_lsu_brupdate_b2_uop_lrs2_rtype), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_frs3_en (_core_io_lsu_brupdate_b2_uop_frs3_en), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_fp_val (_core_io_lsu_brupdate_b2_uop_fp_val), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_fp_single (_core_io_lsu_brupdate_b2_uop_fp_single), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_xcpt_pf_if (_core_io_lsu_brupdate_b2_uop_xcpt_pf_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_xcpt_ae_if (_core_io_lsu_brupdate_b2_uop_xcpt_ae_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_xcpt_ma_if (_core_io_lsu_brupdate_b2_uop_xcpt_ma_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_bp_debug_if (_core_io_lsu_brupdate_b2_uop_bp_debug_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_bp_xcpt_if (_core_io_lsu_brupdate_b2_uop_bp_xcpt_if), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_fsrc (_core_io_lsu_brupdate_b2_uop_debug_fsrc), // @[tile.scala:159:20]
.io_core_brupdate_b2_uop_debug_tsrc (_core_io_lsu_brupdate_b2_uop_debug_tsrc), // @[tile.scala:159:20]
.io_core_brupdate_b2_valid (_core_io_lsu_brupdate_b2_valid), // @[tile.scala:159:20]
.io_core_brupdate_b2_mispredict (_core_io_lsu_brupdate_b2_mispredict), // @[tile.scala:159:20]
.io_core_brupdate_b2_taken (_core_io_lsu_brupdate_b2_taken), // @[tile.scala:159:20]
.io_core_brupdate_b2_cfi_type (_core_io_lsu_brupdate_b2_cfi_type), // @[tile.scala:159:20]
.io_core_brupdate_b2_pc_sel (_core_io_lsu_brupdate_b2_pc_sel), // @[tile.scala:159:20]
.io_core_brupdate_b2_jalr_target (_core_io_lsu_brupdate_b2_jalr_target), // @[tile.scala:159:20]
.io_core_brupdate_b2_target_offset (_core_io_lsu_brupdate_b2_target_offset), // @[tile.scala:159:20]
.io_core_rob_pnr_idx (_core_io_lsu_rob_pnr_idx), // @[tile.scala:159:20]
.io_core_rob_head_idx (_core_io_lsu_rob_head_idx), // @[tile.scala:159:20]
.io_core_exception (_core_io_lsu_exception), // @[tile.scala:159:20]
.io_core_fencei_rdy (_lsu_io_core_fencei_rdy),
.io_core_lxcpt_valid (_lsu_io_core_lxcpt_valid),
.io_core_lxcpt_bits_uop_uopc (_lsu_io_core_lxcpt_bits_uop_uopc),
.io_core_lxcpt_bits_uop_inst (_lsu_io_core_lxcpt_bits_uop_inst),
.io_core_lxcpt_bits_uop_debug_inst (_lsu_io_core_lxcpt_bits_uop_debug_inst),
.io_core_lxcpt_bits_uop_is_rvc (_lsu_io_core_lxcpt_bits_uop_is_rvc),
.io_core_lxcpt_bits_uop_debug_pc (_lsu_io_core_lxcpt_bits_uop_debug_pc),
.io_core_lxcpt_bits_uop_iq_type (_lsu_io_core_lxcpt_bits_uop_iq_type),
.io_core_lxcpt_bits_uop_fu_code (_lsu_io_core_lxcpt_bits_uop_fu_code),
.io_core_lxcpt_bits_uop_ctrl_br_type (_lsu_io_core_lxcpt_bits_uop_ctrl_br_type),
.io_core_lxcpt_bits_uop_ctrl_op1_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op1_sel),
.io_core_lxcpt_bits_uop_ctrl_op2_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_op2_sel),
.io_core_lxcpt_bits_uop_ctrl_imm_sel (_lsu_io_core_lxcpt_bits_uop_ctrl_imm_sel),
.io_core_lxcpt_bits_uop_ctrl_op_fcn (_lsu_io_core_lxcpt_bits_uop_ctrl_op_fcn),
.io_core_lxcpt_bits_uop_ctrl_fcn_dw (_lsu_io_core_lxcpt_bits_uop_ctrl_fcn_dw),
.io_core_lxcpt_bits_uop_ctrl_csr_cmd (_lsu_io_core_lxcpt_bits_uop_ctrl_csr_cmd),
.io_core_lxcpt_bits_uop_ctrl_is_load (_lsu_io_core_lxcpt_bits_uop_ctrl_is_load),
.io_core_lxcpt_bits_uop_ctrl_is_sta (_lsu_io_core_lxcpt_bits_uop_ctrl_is_sta),
.io_core_lxcpt_bits_uop_ctrl_is_std (_lsu_io_core_lxcpt_bits_uop_ctrl_is_std),
.io_core_lxcpt_bits_uop_iw_state (_lsu_io_core_lxcpt_bits_uop_iw_state),
.io_core_lxcpt_bits_uop_iw_p1_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p1_poisoned),
.io_core_lxcpt_bits_uop_iw_p2_poisoned (_lsu_io_core_lxcpt_bits_uop_iw_p2_poisoned),
.io_core_lxcpt_bits_uop_is_br (_lsu_io_core_lxcpt_bits_uop_is_br),
.io_core_lxcpt_bits_uop_is_jalr (_lsu_io_core_lxcpt_bits_uop_is_jalr),
.io_core_lxcpt_bits_uop_is_jal (_lsu_io_core_lxcpt_bits_uop_is_jal),
.io_core_lxcpt_bits_uop_is_sfb (_lsu_io_core_lxcpt_bits_uop_is_sfb),
.io_core_lxcpt_bits_uop_br_mask (_lsu_io_core_lxcpt_bits_uop_br_mask),
.io_core_lxcpt_bits_uop_br_tag (_lsu_io_core_lxcpt_bits_uop_br_tag),
.io_core_lxcpt_bits_uop_ftq_idx (_lsu_io_core_lxcpt_bits_uop_ftq_idx),
.io_core_lxcpt_bits_uop_edge_inst (_lsu_io_core_lxcpt_bits_uop_edge_inst),
.io_core_lxcpt_bits_uop_pc_lob (_lsu_io_core_lxcpt_bits_uop_pc_lob),
.io_core_lxcpt_bits_uop_taken (_lsu_io_core_lxcpt_bits_uop_taken),
.io_core_lxcpt_bits_uop_imm_packed (_lsu_io_core_lxcpt_bits_uop_imm_packed),
.io_core_lxcpt_bits_uop_csr_addr (_lsu_io_core_lxcpt_bits_uop_csr_addr),
.io_core_lxcpt_bits_uop_rob_idx (_lsu_io_core_lxcpt_bits_uop_rob_idx),
.io_core_lxcpt_bits_uop_ldq_idx (_lsu_io_core_lxcpt_bits_uop_ldq_idx),
.io_core_lxcpt_bits_uop_stq_idx (_lsu_io_core_lxcpt_bits_uop_stq_idx),
.io_core_lxcpt_bits_uop_rxq_idx (_lsu_io_core_lxcpt_bits_uop_rxq_idx),
.io_core_lxcpt_bits_uop_pdst (_lsu_io_core_lxcpt_bits_uop_pdst),
.io_core_lxcpt_bits_uop_prs1 (_lsu_io_core_lxcpt_bits_uop_prs1),
.io_core_lxcpt_bits_uop_prs2 (_lsu_io_core_lxcpt_bits_uop_prs2),
.io_core_lxcpt_bits_uop_prs3 (_lsu_io_core_lxcpt_bits_uop_prs3),
.io_core_lxcpt_bits_uop_ppred (_lsu_io_core_lxcpt_bits_uop_ppred),
.io_core_lxcpt_bits_uop_prs1_busy (_lsu_io_core_lxcpt_bits_uop_prs1_busy),
.io_core_lxcpt_bits_uop_prs2_busy (_lsu_io_core_lxcpt_bits_uop_prs2_busy),
.io_core_lxcpt_bits_uop_prs3_busy (_lsu_io_core_lxcpt_bits_uop_prs3_busy),
.io_core_lxcpt_bits_uop_ppred_busy (_lsu_io_core_lxcpt_bits_uop_ppred_busy),
.io_core_lxcpt_bits_uop_stale_pdst (_lsu_io_core_lxcpt_bits_uop_stale_pdst),
.io_core_lxcpt_bits_uop_exception (_lsu_io_core_lxcpt_bits_uop_exception),
.io_core_lxcpt_bits_uop_exc_cause (_lsu_io_core_lxcpt_bits_uop_exc_cause),
.io_core_lxcpt_bits_uop_bypassable (_lsu_io_core_lxcpt_bits_uop_bypassable),
.io_core_lxcpt_bits_uop_mem_cmd (_lsu_io_core_lxcpt_bits_uop_mem_cmd),
.io_core_lxcpt_bits_uop_mem_size (_lsu_io_core_lxcpt_bits_uop_mem_size),
.io_core_lxcpt_bits_uop_mem_signed (_lsu_io_core_lxcpt_bits_uop_mem_signed),
.io_core_lxcpt_bits_uop_is_fence (_lsu_io_core_lxcpt_bits_uop_is_fence),
.io_core_lxcpt_bits_uop_is_fencei (_lsu_io_core_lxcpt_bits_uop_is_fencei),
.io_core_lxcpt_bits_uop_is_amo (_lsu_io_core_lxcpt_bits_uop_is_amo),
.io_core_lxcpt_bits_uop_uses_ldq (_lsu_io_core_lxcpt_bits_uop_uses_ldq),
.io_core_lxcpt_bits_uop_uses_stq (_lsu_io_core_lxcpt_bits_uop_uses_stq),
.io_core_lxcpt_bits_uop_is_sys_pc2epc (_lsu_io_core_lxcpt_bits_uop_is_sys_pc2epc),
.io_core_lxcpt_bits_uop_is_unique (_lsu_io_core_lxcpt_bits_uop_is_unique),
.io_core_lxcpt_bits_uop_flush_on_commit (_lsu_io_core_lxcpt_bits_uop_flush_on_commit),
.io_core_lxcpt_bits_uop_ldst_is_rs1 (_lsu_io_core_lxcpt_bits_uop_ldst_is_rs1),
.io_core_lxcpt_bits_uop_ldst (_lsu_io_core_lxcpt_bits_uop_ldst),
.io_core_lxcpt_bits_uop_lrs1 (_lsu_io_core_lxcpt_bits_uop_lrs1),
.io_core_lxcpt_bits_uop_lrs2 (_lsu_io_core_lxcpt_bits_uop_lrs2),
.io_core_lxcpt_bits_uop_lrs3 (_lsu_io_core_lxcpt_bits_uop_lrs3),
.io_core_lxcpt_bits_uop_ldst_val (_lsu_io_core_lxcpt_bits_uop_ldst_val),
.io_core_lxcpt_bits_uop_dst_rtype (_lsu_io_core_lxcpt_bits_uop_dst_rtype),
.io_core_lxcpt_bits_uop_lrs1_rtype (_lsu_io_core_lxcpt_bits_uop_lrs1_rtype),
.io_core_lxcpt_bits_uop_lrs2_rtype (_lsu_io_core_lxcpt_bits_uop_lrs2_rtype),
.io_core_lxcpt_bits_uop_frs3_en (_lsu_io_core_lxcpt_bits_uop_frs3_en),
.io_core_lxcpt_bits_uop_fp_val (_lsu_io_core_lxcpt_bits_uop_fp_val),
.io_core_lxcpt_bits_uop_fp_single (_lsu_io_core_lxcpt_bits_uop_fp_single),
.io_core_lxcpt_bits_uop_xcpt_pf_if (_lsu_io_core_lxcpt_bits_uop_xcpt_pf_if),
.io_core_lxcpt_bits_uop_xcpt_ae_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ae_if),
.io_core_lxcpt_bits_uop_xcpt_ma_if (_lsu_io_core_lxcpt_bits_uop_xcpt_ma_if),
.io_core_lxcpt_bits_uop_bp_debug_if (_lsu_io_core_lxcpt_bits_uop_bp_debug_if),
.io_core_lxcpt_bits_uop_bp_xcpt_if (_lsu_io_core_lxcpt_bits_uop_bp_xcpt_if),
.io_core_lxcpt_bits_uop_debug_fsrc (_lsu_io_core_lxcpt_bits_uop_debug_fsrc),
.io_core_lxcpt_bits_uop_debug_tsrc (_lsu_io_core_lxcpt_bits_uop_debug_tsrc),
.io_core_lxcpt_bits_cause (_lsu_io_core_lxcpt_bits_cause),
.io_core_lxcpt_bits_badvaddr (_lsu_io_core_lxcpt_bits_badvaddr),
.io_core_tsc_reg (_core_io_lsu_tsc_reg), // @[tile.scala:159:20]
.io_core_perf_acquire (_lsu_io_core_perf_acquire),
.io_core_perf_release (_lsu_io_core_perf_release),
.io_core_perf_tlbMiss (_lsu_io_core_perf_tlbMiss),
.io_dmem_req_ready (_dcache_io_lsu_req_ready), // @[tile.scala:132:54]
.io_dmem_req_valid (_lsu_io_dmem_req_valid),
.io_dmem_req_bits_0_valid (_lsu_io_dmem_req_bits_0_valid),
.io_dmem_req_bits_0_bits_uop_uopc (_lsu_io_dmem_req_bits_0_bits_uop_uopc),
.io_dmem_req_bits_0_bits_uop_inst (_lsu_io_dmem_req_bits_0_bits_uop_inst),
.io_dmem_req_bits_0_bits_uop_debug_inst (_lsu_io_dmem_req_bits_0_bits_uop_debug_inst),
.io_dmem_req_bits_0_bits_uop_is_rvc (_lsu_io_dmem_req_bits_0_bits_uop_is_rvc),
.io_dmem_req_bits_0_bits_uop_debug_pc (_lsu_io_dmem_req_bits_0_bits_uop_debug_pc),
.io_dmem_req_bits_0_bits_uop_iq_type (_lsu_io_dmem_req_bits_0_bits_uop_iq_type),
.io_dmem_req_bits_0_bits_uop_fu_code (_lsu_io_dmem_req_bits_0_bits_uop_fu_code),
.io_dmem_req_bits_0_bits_uop_ctrl_br_type (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_br_type),
.io_dmem_req_bits_0_bits_uop_ctrl_op1_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op1_sel),
.io_dmem_req_bits_0_bits_uop_ctrl_op2_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op2_sel),
.io_dmem_req_bits_0_bits_uop_ctrl_imm_sel (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_imm_sel),
.io_dmem_req_bits_0_bits_uop_ctrl_op_fcn (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_op_fcn),
.io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_fcn_dw),
.io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_csr_cmd),
.io_dmem_req_bits_0_bits_uop_ctrl_is_load (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_load),
.io_dmem_req_bits_0_bits_uop_ctrl_is_sta (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_sta),
.io_dmem_req_bits_0_bits_uop_ctrl_is_std (_lsu_io_dmem_req_bits_0_bits_uop_ctrl_is_std),
.io_dmem_req_bits_0_bits_uop_iw_state (_lsu_io_dmem_req_bits_0_bits_uop_iw_state),
.io_dmem_req_bits_0_bits_uop_iw_p1_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p1_poisoned),
.io_dmem_req_bits_0_bits_uop_iw_p2_poisoned (_lsu_io_dmem_req_bits_0_bits_uop_iw_p2_poisoned),
.io_dmem_req_bits_0_bits_uop_is_br (_lsu_io_dmem_req_bits_0_bits_uop_is_br),
.io_dmem_req_bits_0_bits_uop_is_jalr (_lsu_io_dmem_req_bits_0_bits_uop_is_jalr),
.io_dmem_req_bits_0_bits_uop_is_jal (_lsu_io_dmem_req_bits_0_bits_uop_is_jal),
.io_dmem_req_bits_0_bits_uop_is_sfb (_lsu_io_dmem_req_bits_0_bits_uop_is_sfb),
.io_dmem_req_bits_0_bits_uop_br_mask (_lsu_io_dmem_req_bits_0_bits_uop_br_mask),
.io_dmem_req_bits_0_bits_uop_br_tag (_lsu_io_dmem_req_bits_0_bits_uop_br_tag),
.io_dmem_req_bits_0_bits_uop_ftq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ftq_idx),
.io_dmem_req_bits_0_bits_uop_edge_inst (_lsu_io_dmem_req_bits_0_bits_uop_edge_inst),
.io_dmem_req_bits_0_bits_uop_pc_lob (_lsu_io_dmem_req_bits_0_bits_uop_pc_lob),
.io_dmem_req_bits_0_bits_uop_taken (_lsu_io_dmem_req_bits_0_bits_uop_taken),
.io_dmem_req_bits_0_bits_uop_imm_packed (_lsu_io_dmem_req_bits_0_bits_uop_imm_packed),
.io_dmem_req_bits_0_bits_uop_csr_addr (_lsu_io_dmem_req_bits_0_bits_uop_csr_addr),
.io_dmem_req_bits_0_bits_uop_rob_idx (_lsu_io_dmem_req_bits_0_bits_uop_rob_idx),
.io_dmem_req_bits_0_bits_uop_ldq_idx (_lsu_io_dmem_req_bits_0_bits_uop_ldq_idx),
.io_dmem_req_bits_0_bits_uop_stq_idx (_lsu_io_dmem_req_bits_0_bits_uop_stq_idx),
.io_dmem_req_bits_0_bits_uop_rxq_idx (_lsu_io_dmem_req_bits_0_bits_uop_rxq_idx),
.io_dmem_req_bits_0_bits_uop_pdst (_lsu_io_dmem_req_bits_0_bits_uop_pdst),
.io_dmem_req_bits_0_bits_uop_prs1 (_lsu_io_dmem_req_bits_0_bits_uop_prs1),
.io_dmem_req_bits_0_bits_uop_prs2 (_lsu_io_dmem_req_bits_0_bits_uop_prs2),
.io_dmem_req_bits_0_bits_uop_prs3 (_lsu_io_dmem_req_bits_0_bits_uop_prs3),
.io_dmem_req_bits_0_bits_uop_ppred (_lsu_io_dmem_req_bits_0_bits_uop_ppred),
.io_dmem_req_bits_0_bits_uop_prs1_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs1_busy),
.io_dmem_req_bits_0_bits_uop_prs2_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs2_busy),
.io_dmem_req_bits_0_bits_uop_prs3_busy (_lsu_io_dmem_req_bits_0_bits_uop_prs3_busy),
.io_dmem_req_bits_0_bits_uop_ppred_busy (_lsu_io_dmem_req_bits_0_bits_uop_ppred_busy),
.io_dmem_req_bits_0_bits_uop_stale_pdst (_lsu_io_dmem_req_bits_0_bits_uop_stale_pdst),
.io_dmem_req_bits_0_bits_uop_exception (_lsu_io_dmem_req_bits_0_bits_uop_exception),
.io_dmem_req_bits_0_bits_uop_exc_cause (_lsu_io_dmem_req_bits_0_bits_uop_exc_cause),
.io_dmem_req_bits_0_bits_uop_bypassable (_lsu_io_dmem_req_bits_0_bits_uop_bypassable),
.io_dmem_req_bits_0_bits_uop_mem_cmd (_lsu_io_dmem_req_bits_0_bits_uop_mem_cmd),
.io_dmem_req_bits_0_bits_uop_mem_size (_lsu_io_dmem_req_bits_0_bits_uop_mem_size),
.io_dmem_req_bits_0_bits_uop_mem_signed (_lsu_io_dmem_req_bits_0_bits_uop_mem_signed),
.io_dmem_req_bits_0_bits_uop_is_fence (_lsu_io_dmem_req_bits_0_bits_uop_is_fence),
.io_dmem_req_bits_0_bits_uop_is_fencei (_lsu_io_dmem_req_bits_0_bits_uop_is_fencei),
.io_dmem_req_bits_0_bits_uop_is_amo (_lsu_io_dmem_req_bits_0_bits_uop_is_amo),
.io_dmem_req_bits_0_bits_uop_uses_ldq (_lsu_io_dmem_req_bits_0_bits_uop_uses_ldq),
.io_dmem_req_bits_0_bits_uop_uses_stq (_lsu_io_dmem_req_bits_0_bits_uop_uses_stq),
.io_dmem_req_bits_0_bits_uop_is_sys_pc2epc (_lsu_io_dmem_req_bits_0_bits_uop_is_sys_pc2epc),
.io_dmem_req_bits_0_bits_uop_is_unique (_lsu_io_dmem_req_bits_0_bits_uop_is_unique),
.io_dmem_req_bits_0_bits_uop_flush_on_commit (_lsu_io_dmem_req_bits_0_bits_uop_flush_on_commit),
.io_dmem_req_bits_0_bits_uop_ldst_is_rs1 (_lsu_io_dmem_req_bits_0_bits_uop_ldst_is_rs1),
.io_dmem_req_bits_0_bits_uop_ldst (_lsu_io_dmem_req_bits_0_bits_uop_ldst),
.io_dmem_req_bits_0_bits_uop_lrs1 (_lsu_io_dmem_req_bits_0_bits_uop_lrs1),
.io_dmem_req_bits_0_bits_uop_lrs2 (_lsu_io_dmem_req_bits_0_bits_uop_lrs2),
.io_dmem_req_bits_0_bits_uop_lrs3 (_lsu_io_dmem_req_bits_0_bits_uop_lrs3),
.io_dmem_req_bits_0_bits_uop_ldst_val (_lsu_io_dmem_req_bits_0_bits_uop_ldst_val),
.io_dmem_req_bits_0_bits_uop_dst_rtype (_lsu_io_dmem_req_bits_0_bits_uop_dst_rtype),
.io_dmem_req_bits_0_bits_uop_lrs1_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs1_rtype),
.io_dmem_req_bits_0_bits_uop_lrs2_rtype (_lsu_io_dmem_req_bits_0_bits_uop_lrs2_rtype),
.io_dmem_req_bits_0_bits_uop_frs3_en (_lsu_io_dmem_req_bits_0_bits_uop_frs3_en),
.io_dmem_req_bits_0_bits_uop_fp_val (_lsu_io_dmem_req_bits_0_bits_uop_fp_val),
.io_dmem_req_bits_0_bits_uop_fp_single (_lsu_io_dmem_req_bits_0_bits_uop_fp_single),
.io_dmem_req_bits_0_bits_uop_xcpt_pf_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_pf_if),
.io_dmem_req_bits_0_bits_uop_xcpt_ae_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ae_if),
.io_dmem_req_bits_0_bits_uop_xcpt_ma_if (_lsu_io_dmem_req_bits_0_bits_uop_xcpt_ma_if),
.io_dmem_req_bits_0_bits_uop_bp_debug_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_debug_if),
.io_dmem_req_bits_0_bits_uop_bp_xcpt_if (_lsu_io_dmem_req_bits_0_bits_uop_bp_xcpt_if),
.io_dmem_req_bits_0_bits_uop_debug_fsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_fsrc),
.io_dmem_req_bits_0_bits_uop_debug_tsrc (_lsu_io_dmem_req_bits_0_bits_uop_debug_tsrc),
.io_dmem_req_bits_0_bits_addr (_lsu_io_dmem_req_bits_0_bits_addr),
.io_dmem_req_bits_0_bits_data (_lsu_io_dmem_req_bits_0_bits_data),
.io_dmem_req_bits_0_bits_is_hella (_lsu_io_dmem_req_bits_0_bits_is_hella),
.io_dmem_s1_kill_0 (_lsu_io_dmem_s1_kill_0),
.io_dmem_resp_0_valid (_dcache_io_lsu_resp_0_valid), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_uopc (_dcache_io_lsu_resp_0_bits_uop_uopc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_inst (_dcache_io_lsu_resp_0_bits_uop_inst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_inst (_dcache_io_lsu_resp_0_bits_uop_debug_inst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_rvc (_dcache_io_lsu_resp_0_bits_uop_is_rvc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_pc (_dcache_io_lsu_resp_0_bits_uop_debug_pc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iq_type (_dcache_io_lsu_resp_0_bits_uop_iq_type), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_fu_code (_dcache_io_lsu_resp_0_bits_uop_fu_code), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_br_type (_dcache_io_lsu_resp_0_bits_uop_ctrl_br_type), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op1_sel), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_op2_sel), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_resp_0_bits_uop_ctrl_imm_sel), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_resp_0_bits_uop_ctrl_op_fcn), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_resp_0_bits_uop_ctrl_fcn_dw), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_resp_0_bits_uop_ctrl_csr_cmd), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_is_load (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_load), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_sta), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ctrl_is_std (_dcache_io_lsu_resp_0_bits_uop_ctrl_is_std), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iw_state (_dcache_io_lsu_resp_0_bits_uop_iw_state), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p1_poisoned), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_resp_0_bits_uop_iw_p2_poisoned), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_br (_dcache_io_lsu_resp_0_bits_uop_is_br), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_jalr (_dcache_io_lsu_resp_0_bits_uop_is_jalr), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_jal (_dcache_io_lsu_resp_0_bits_uop_is_jal), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_sfb (_dcache_io_lsu_resp_0_bits_uop_is_sfb), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_br_mask (_dcache_io_lsu_resp_0_bits_uop_br_mask), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_br_tag (_dcache_io_lsu_resp_0_bits_uop_br_tag), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ftq_idx (_dcache_io_lsu_resp_0_bits_uop_ftq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_edge_inst (_dcache_io_lsu_resp_0_bits_uop_edge_inst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_pc_lob (_dcache_io_lsu_resp_0_bits_uop_pc_lob), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_taken (_dcache_io_lsu_resp_0_bits_uop_taken), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_imm_packed (_dcache_io_lsu_resp_0_bits_uop_imm_packed), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_csr_addr (_dcache_io_lsu_resp_0_bits_uop_csr_addr), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_rob_idx (_dcache_io_lsu_resp_0_bits_uop_rob_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldq_idx (_dcache_io_lsu_resp_0_bits_uop_ldq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_stq_idx (_dcache_io_lsu_resp_0_bits_uop_stq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_rxq_idx (_dcache_io_lsu_resp_0_bits_uop_rxq_idx), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_pdst (_dcache_io_lsu_resp_0_bits_uop_pdst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs1 (_dcache_io_lsu_resp_0_bits_uop_prs1), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs2 (_dcache_io_lsu_resp_0_bits_uop_prs2), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs3 (_dcache_io_lsu_resp_0_bits_uop_prs3), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ppred (_dcache_io_lsu_resp_0_bits_uop_ppred), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs1_busy (_dcache_io_lsu_resp_0_bits_uop_prs1_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs2_busy (_dcache_io_lsu_resp_0_bits_uop_prs2_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_prs3_busy (_dcache_io_lsu_resp_0_bits_uop_prs3_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ppred_busy (_dcache_io_lsu_resp_0_bits_uop_ppred_busy), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_stale_pdst (_dcache_io_lsu_resp_0_bits_uop_stale_pdst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_exception (_dcache_io_lsu_resp_0_bits_uop_exception), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_exc_cause (_dcache_io_lsu_resp_0_bits_uop_exc_cause), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_bypassable (_dcache_io_lsu_resp_0_bits_uop_bypassable), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_mem_cmd (_dcache_io_lsu_resp_0_bits_uop_mem_cmd), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_mem_size (_dcache_io_lsu_resp_0_bits_uop_mem_size), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_mem_signed (_dcache_io_lsu_resp_0_bits_uop_mem_signed), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_fence (_dcache_io_lsu_resp_0_bits_uop_is_fence), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_fencei (_dcache_io_lsu_resp_0_bits_uop_is_fencei), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_amo (_dcache_io_lsu_resp_0_bits_uop_is_amo), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_uses_ldq (_dcache_io_lsu_resp_0_bits_uop_uses_ldq), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_uses_stq (_dcache_io_lsu_resp_0_bits_uop_uses_stq), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_resp_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_is_unique (_dcache_io_lsu_resp_0_bits_uop_is_unique), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_flush_on_commit (_dcache_io_lsu_resp_0_bits_uop_flush_on_commit), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_resp_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldst (_dcache_io_lsu_resp_0_bits_uop_ldst), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs1 (_dcache_io_lsu_resp_0_bits_uop_lrs1), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs2 (_dcache_io_lsu_resp_0_bits_uop_lrs2), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs3 (_dcache_io_lsu_resp_0_bits_uop_lrs3), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_ldst_val (_dcache_io_lsu_resp_0_bits_uop_ldst_val), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_dst_rtype (_dcache_io_lsu_resp_0_bits_uop_dst_rtype), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs1_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_lrs2_rtype (_dcache_io_lsu_resp_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_frs3_en (_dcache_io_lsu_resp_0_bits_uop_frs3_en), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_fp_val (_dcache_io_lsu_resp_0_bits_uop_fp_val), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_fp_single (_dcache_io_lsu_resp_0_bits_uop_fp_single), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_resp_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_bp_debug_if (_dcache_io_lsu_resp_0_bits_uop_bp_debug_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_resp_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_fsrc (_dcache_io_lsu_resp_0_bits_uop_debug_fsrc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_uop_debug_tsrc (_dcache_io_lsu_resp_0_bits_uop_debug_tsrc), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_data (_dcache_io_lsu_resp_0_bits_data), // @[tile.scala:132:54]
.io_dmem_resp_0_bits_is_hella (_dcache_io_lsu_resp_0_bits_is_hella), // @[tile.scala:132:54]
.io_dmem_nack_0_valid (_dcache_io_lsu_nack_0_valid), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_uopc (_dcache_io_lsu_nack_0_bits_uop_uopc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_inst (_dcache_io_lsu_nack_0_bits_uop_inst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_inst (_dcache_io_lsu_nack_0_bits_uop_debug_inst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_rvc (_dcache_io_lsu_nack_0_bits_uop_is_rvc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_pc (_dcache_io_lsu_nack_0_bits_uop_debug_pc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iq_type (_dcache_io_lsu_nack_0_bits_uop_iq_type), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_fu_code (_dcache_io_lsu_nack_0_bits_uop_fu_code), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_br_type (_dcache_io_lsu_nack_0_bits_uop_ctrl_br_type), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_op1_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op1_sel), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_op2_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_op2_sel), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_imm_sel (_dcache_io_lsu_nack_0_bits_uop_ctrl_imm_sel), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_op_fcn (_dcache_io_lsu_nack_0_bits_uop_ctrl_op_fcn), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_fcn_dw (_dcache_io_lsu_nack_0_bits_uop_ctrl_fcn_dw), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_csr_cmd (_dcache_io_lsu_nack_0_bits_uop_ctrl_csr_cmd), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_is_load (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_load), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_is_sta (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_sta), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ctrl_is_std (_dcache_io_lsu_nack_0_bits_uop_ctrl_is_std), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iw_state (_dcache_io_lsu_nack_0_bits_uop_iw_state), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iw_p1_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p1_poisoned), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_iw_p2_poisoned (_dcache_io_lsu_nack_0_bits_uop_iw_p2_poisoned), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_br (_dcache_io_lsu_nack_0_bits_uop_is_br), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_jalr (_dcache_io_lsu_nack_0_bits_uop_is_jalr), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_jal (_dcache_io_lsu_nack_0_bits_uop_is_jal), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_sfb (_dcache_io_lsu_nack_0_bits_uop_is_sfb), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_br_mask (_dcache_io_lsu_nack_0_bits_uop_br_mask), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_br_tag (_dcache_io_lsu_nack_0_bits_uop_br_tag), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ftq_idx (_dcache_io_lsu_nack_0_bits_uop_ftq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_edge_inst (_dcache_io_lsu_nack_0_bits_uop_edge_inst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_pc_lob (_dcache_io_lsu_nack_0_bits_uop_pc_lob), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_taken (_dcache_io_lsu_nack_0_bits_uop_taken), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_imm_packed (_dcache_io_lsu_nack_0_bits_uop_imm_packed), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_csr_addr (_dcache_io_lsu_nack_0_bits_uop_csr_addr), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_rob_idx (_dcache_io_lsu_nack_0_bits_uop_rob_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldq_idx (_dcache_io_lsu_nack_0_bits_uop_ldq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_stq_idx (_dcache_io_lsu_nack_0_bits_uop_stq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_rxq_idx (_dcache_io_lsu_nack_0_bits_uop_rxq_idx), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_pdst (_dcache_io_lsu_nack_0_bits_uop_pdst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs1 (_dcache_io_lsu_nack_0_bits_uop_prs1), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs2 (_dcache_io_lsu_nack_0_bits_uop_prs2), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs3 (_dcache_io_lsu_nack_0_bits_uop_prs3), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ppred (_dcache_io_lsu_nack_0_bits_uop_ppred), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs1_busy (_dcache_io_lsu_nack_0_bits_uop_prs1_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs2_busy (_dcache_io_lsu_nack_0_bits_uop_prs2_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_prs3_busy (_dcache_io_lsu_nack_0_bits_uop_prs3_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ppred_busy (_dcache_io_lsu_nack_0_bits_uop_ppred_busy), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_stale_pdst (_dcache_io_lsu_nack_0_bits_uop_stale_pdst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_exception (_dcache_io_lsu_nack_0_bits_uop_exception), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_exc_cause (_dcache_io_lsu_nack_0_bits_uop_exc_cause), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_bypassable (_dcache_io_lsu_nack_0_bits_uop_bypassable), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_mem_cmd (_dcache_io_lsu_nack_0_bits_uop_mem_cmd), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_mem_size (_dcache_io_lsu_nack_0_bits_uop_mem_size), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_mem_signed (_dcache_io_lsu_nack_0_bits_uop_mem_signed), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_fence (_dcache_io_lsu_nack_0_bits_uop_is_fence), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_fencei (_dcache_io_lsu_nack_0_bits_uop_is_fencei), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_amo (_dcache_io_lsu_nack_0_bits_uop_is_amo), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_uses_ldq (_dcache_io_lsu_nack_0_bits_uop_uses_ldq), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_uses_stq (_dcache_io_lsu_nack_0_bits_uop_uses_stq), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_sys_pc2epc (_dcache_io_lsu_nack_0_bits_uop_is_sys_pc2epc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_is_unique (_dcache_io_lsu_nack_0_bits_uop_is_unique), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_flush_on_commit (_dcache_io_lsu_nack_0_bits_uop_flush_on_commit), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldst_is_rs1 (_dcache_io_lsu_nack_0_bits_uop_ldst_is_rs1), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldst (_dcache_io_lsu_nack_0_bits_uop_ldst), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs1 (_dcache_io_lsu_nack_0_bits_uop_lrs1), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs2 (_dcache_io_lsu_nack_0_bits_uop_lrs2), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs3 (_dcache_io_lsu_nack_0_bits_uop_lrs3), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_ldst_val (_dcache_io_lsu_nack_0_bits_uop_ldst_val), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_dst_rtype (_dcache_io_lsu_nack_0_bits_uop_dst_rtype), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs1_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs1_rtype), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_lrs2_rtype (_dcache_io_lsu_nack_0_bits_uop_lrs2_rtype), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_frs3_en (_dcache_io_lsu_nack_0_bits_uop_frs3_en), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_fp_val (_dcache_io_lsu_nack_0_bits_uop_fp_val), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_fp_single (_dcache_io_lsu_nack_0_bits_uop_fp_single), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_xcpt_pf_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_pf_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_xcpt_ae_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ae_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_xcpt_ma_if (_dcache_io_lsu_nack_0_bits_uop_xcpt_ma_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_bp_debug_if (_dcache_io_lsu_nack_0_bits_uop_bp_debug_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_bp_xcpt_if (_dcache_io_lsu_nack_0_bits_uop_bp_xcpt_if), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_fsrc (_dcache_io_lsu_nack_0_bits_uop_debug_fsrc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_uop_debug_tsrc (_dcache_io_lsu_nack_0_bits_uop_debug_tsrc), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_addr (_dcache_io_lsu_nack_0_bits_addr), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_data (_dcache_io_lsu_nack_0_bits_data), // @[tile.scala:132:54]
.io_dmem_nack_0_bits_is_hella (_dcache_io_lsu_nack_0_bits_is_hella), // @[tile.scala:132:54]
.io_dmem_brupdate_b1_resolve_mask (_lsu_io_dmem_brupdate_b1_resolve_mask),
.io_dmem_brupdate_b1_mispredict_mask (_lsu_io_dmem_brupdate_b1_mispredict_mask),
.io_dmem_brupdate_b2_uop_uopc (_lsu_io_dmem_brupdate_b2_uop_uopc),
.io_dmem_brupdate_b2_uop_inst (_lsu_io_dmem_brupdate_b2_uop_inst),
.io_dmem_brupdate_b2_uop_debug_inst (_lsu_io_dmem_brupdate_b2_uop_debug_inst),
.io_dmem_brupdate_b2_uop_is_rvc (_lsu_io_dmem_brupdate_b2_uop_is_rvc),
.io_dmem_brupdate_b2_uop_debug_pc (_lsu_io_dmem_brupdate_b2_uop_debug_pc),
.io_dmem_brupdate_b2_uop_iq_type (_lsu_io_dmem_brupdate_b2_uop_iq_type),
.io_dmem_brupdate_b2_uop_fu_code (_lsu_io_dmem_brupdate_b2_uop_fu_code),
.io_dmem_brupdate_b2_uop_ctrl_br_type (_lsu_io_dmem_brupdate_b2_uop_ctrl_br_type),
.io_dmem_brupdate_b2_uop_ctrl_op1_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op1_sel),
.io_dmem_brupdate_b2_uop_ctrl_op2_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_op2_sel),
.io_dmem_brupdate_b2_uop_ctrl_imm_sel (_lsu_io_dmem_brupdate_b2_uop_ctrl_imm_sel),
.io_dmem_brupdate_b2_uop_ctrl_op_fcn (_lsu_io_dmem_brupdate_b2_uop_ctrl_op_fcn),
.io_dmem_brupdate_b2_uop_ctrl_fcn_dw (_lsu_io_dmem_brupdate_b2_uop_ctrl_fcn_dw),
.io_dmem_brupdate_b2_uop_ctrl_csr_cmd (_lsu_io_dmem_brupdate_b2_uop_ctrl_csr_cmd),
.io_dmem_brupdate_b2_uop_ctrl_is_load (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_load),
.io_dmem_brupdate_b2_uop_ctrl_is_sta (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_sta),
.io_dmem_brupdate_b2_uop_ctrl_is_std (_lsu_io_dmem_brupdate_b2_uop_ctrl_is_std),
.io_dmem_brupdate_b2_uop_iw_state (_lsu_io_dmem_brupdate_b2_uop_iw_state),
.io_dmem_brupdate_b2_uop_iw_p1_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p1_poisoned),
.io_dmem_brupdate_b2_uop_iw_p2_poisoned (_lsu_io_dmem_brupdate_b2_uop_iw_p2_poisoned),
.io_dmem_brupdate_b2_uop_is_br (_lsu_io_dmem_brupdate_b2_uop_is_br),
.io_dmem_brupdate_b2_uop_is_jalr (_lsu_io_dmem_brupdate_b2_uop_is_jalr),
.io_dmem_brupdate_b2_uop_is_jal (_lsu_io_dmem_brupdate_b2_uop_is_jal),
.io_dmem_brupdate_b2_uop_is_sfb (_lsu_io_dmem_brupdate_b2_uop_is_sfb),
.io_dmem_brupdate_b2_uop_br_mask (_lsu_io_dmem_brupdate_b2_uop_br_mask),
.io_dmem_brupdate_b2_uop_br_tag (_lsu_io_dmem_brupdate_b2_uop_br_tag),
.io_dmem_brupdate_b2_uop_ftq_idx (_lsu_io_dmem_brupdate_b2_uop_ftq_idx),
.io_dmem_brupdate_b2_uop_edge_inst (_lsu_io_dmem_brupdate_b2_uop_edge_inst),
.io_dmem_brupdate_b2_uop_pc_lob (_lsu_io_dmem_brupdate_b2_uop_pc_lob),
.io_dmem_brupdate_b2_uop_taken (_lsu_io_dmem_brupdate_b2_uop_taken),
.io_dmem_brupdate_b2_uop_imm_packed (_lsu_io_dmem_brupdate_b2_uop_imm_packed),
.io_dmem_brupdate_b2_uop_csr_addr (_lsu_io_dmem_brupdate_b2_uop_csr_addr),
.io_dmem_brupdate_b2_uop_rob_idx (_lsu_io_dmem_brupdate_b2_uop_rob_idx),
.io_dmem_brupdate_b2_uop_ldq_idx (_lsu_io_dmem_brupdate_b2_uop_ldq_idx),
.io_dmem_brupdate_b2_uop_stq_idx (_lsu_io_dmem_brupdate_b2_uop_stq_idx),
.io_dmem_brupdate_b2_uop_rxq_idx (_lsu_io_dmem_brupdate_b2_uop_rxq_idx),
.io_dmem_brupdate_b2_uop_pdst (_lsu_io_dmem_brupdate_b2_uop_pdst),
.io_dmem_brupdate_b2_uop_prs1 (_lsu_io_dmem_brupdate_b2_uop_prs1),
.io_dmem_brupdate_b2_uop_prs2 (_lsu_io_dmem_brupdate_b2_uop_prs2),
.io_dmem_brupdate_b2_uop_prs3 (_lsu_io_dmem_brupdate_b2_uop_prs3),
.io_dmem_brupdate_b2_uop_ppred (_lsu_io_dmem_brupdate_b2_uop_ppred),
.io_dmem_brupdate_b2_uop_prs1_busy (_lsu_io_dmem_brupdate_b2_uop_prs1_busy),
.io_dmem_brupdate_b2_uop_prs2_busy (_lsu_io_dmem_brupdate_b2_uop_prs2_busy),
.io_dmem_brupdate_b2_uop_prs3_busy (_lsu_io_dmem_brupdate_b2_uop_prs3_busy),
.io_dmem_brupdate_b2_uop_ppred_busy (_lsu_io_dmem_brupdate_b2_uop_ppred_busy),
.io_dmem_brupdate_b2_uop_stale_pdst (_lsu_io_dmem_brupdate_b2_uop_stale_pdst),
.io_dmem_brupdate_b2_uop_exception (_lsu_io_dmem_brupdate_b2_uop_exception),
.io_dmem_brupdate_b2_uop_exc_cause (_lsu_io_dmem_brupdate_b2_uop_exc_cause),
.io_dmem_brupdate_b2_uop_bypassable (_lsu_io_dmem_brupdate_b2_uop_bypassable),
.io_dmem_brupdate_b2_uop_mem_cmd (_lsu_io_dmem_brupdate_b2_uop_mem_cmd),
.io_dmem_brupdate_b2_uop_mem_size (_lsu_io_dmem_brupdate_b2_uop_mem_size),
.io_dmem_brupdate_b2_uop_mem_signed (_lsu_io_dmem_brupdate_b2_uop_mem_signed),
.io_dmem_brupdate_b2_uop_is_fence (_lsu_io_dmem_brupdate_b2_uop_is_fence),
.io_dmem_brupdate_b2_uop_is_fencei (_lsu_io_dmem_brupdate_b2_uop_is_fencei),
.io_dmem_brupdate_b2_uop_is_amo (_lsu_io_dmem_brupdate_b2_uop_is_amo),
.io_dmem_brupdate_b2_uop_uses_ldq (_lsu_io_dmem_brupdate_b2_uop_uses_ldq),
.io_dmem_brupdate_b2_uop_uses_stq (_lsu_io_dmem_brupdate_b2_uop_uses_stq),
.io_dmem_brupdate_b2_uop_is_sys_pc2epc (_lsu_io_dmem_brupdate_b2_uop_is_sys_pc2epc),
.io_dmem_brupdate_b2_uop_is_unique (_lsu_io_dmem_brupdate_b2_uop_is_unique),
.io_dmem_brupdate_b2_uop_flush_on_commit (_lsu_io_dmem_brupdate_b2_uop_flush_on_commit),
.io_dmem_brupdate_b2_uop_ldst_is_rs1 (_lsu_io_dmem_brupdate_b2_uop_ldst_is_rs1),
.io_dmem_brupdate_b2_uop_ldst (_lsu_io_dmem_brupdate_b2_uop_ldst),
.io_dmem_brupdate_b2_uop_lrs1 (_lsu_io_dmem_brupdate_b2_uop_lrs1),
.io_dmem_brupdate_b2_uop_lrs2 (_lsu_io_dmem_brupdate_b2_uop_lrs2),
.io_dmem_brupdate_b2_uop_lrs3 (_lsu_io_dmem_brupdate_b2_uop_lrs3),
.io_dmem_brupdate_b2_uop_ldst_val (_lsu_io_dmem_brupdate_b2_uop_ldst_val),
.io_dmem_brupdate_b2_uop_dst_rtype (_lsu_io_dmem_brupdate_b2_uop_dst_rtype),
.io_dmem_brupdate_b2_uop_lrs1_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs1_rtype),
.io_dmem_brupdate_b2_uop_lrs2_rtype (_lsu_io_dmem_brupdate_b2_uop_lrs2_rtype),
.io_dmem_brupdate_b2_uop_frs3_en (_lsu_io_dmem_brupdate_b2_uop_frs3_en),
.io_dmem_brupdate_b2_uop_fp_val (_lsu_io_dmem_brupdate_b2_uop_fp_val),
.io_dmem_brupdate_b2_uop_fp_single (_lsu_io_dmem_brupdate_b2_uop_fp_single),
.io_dmem_brupdate_b2_uop_xcpt_pf_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_pf_if),
.io_dmem_brupdate_b2_uop_xcpt_ae_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ae_if),
.io_dmem_brupdate_b2_uop_xcpt_ma_if (_lsu_io_dmem_brupdate_b2_uop_xcpt_ma_if),
.io_dmem_brupdate_b2_uop_bp_debug_if (_lsu_io_dmem_brupdate_b2_uop_bp_debug_if),
.io_dmem_brupdate_b2_uop_bp_xcpt_if (_lsu_io_dmem_brupdate_b2_uop_bp_xcpt_if),
.io_dmem_brupdate_b2_uop_debug_fsrc (_lsu_io_dmem_brupdate_b2_uop_debug_fsrc),
.io_dmem_brupdate_b2_uop_debug_tsrc (_lsu_io_dmem_brupdate_b2_uop_debug_tsrc),
.io_dmem_brupdate_b2_valid (_lsu_io_dmem_brupdate_b2_valid),
.io_dmem_brupdate_b2_mispredict (_lsu_io_dmem_brupdate_b2_mispredict),
.io_dmem_brupdate_b2_taken (_lsu_io_dmem_brupdate_b2_taken),
.io_dmem_brupdate_b2_cfi_type (_lsu_io_dmem_brupdate_b2_cfi_type),
.io_dmem_brupdate_b2_pc_sel (_lsu_io_dmem_brupdate_b2_pc_sel),
.io_dmem_brupdate_b2_jalr_target (_lsu_io_dmem_brupdate_b2_jalr_target),
.io_dmem_brupdate_b2_target_offset (_lsu_io_dmem_brupdate_b2_target_offset),
.io_dmem_exception (_lsu_io_dmem_exception),
.io_dmem_rob_pnr_idx (_lsu_io_dmem_rob_pnr_idx),
.io_dmem_rob_head_idx (_lsu_io_dmem_rob_head_idx),
.io_dmem_release_ready (_lsu_io_dmem_release_ready),
.io_dmem_release_valid (_dcache_io_lsu_release_valid), // @[tile.scala:132:54]
.io_dmem_release_bits_opcode (_dcache_io_lsu_release_bits_opcode), // @[tile.scala:132:54]
.io_dmem_release_bits_param (_dcache_io_lsu_release_bits_param), // @[tile.scala:132:54]
.io_dmem_release_bits_size (_dcache_io_lsu_release_bits_size), // @[tile.scala:132:54]
.io_dmem_release_bits_source (_dcache_io_lsu_release_bits_source), // @[tile.scala:132:54]
.io_dmem_release_bits_address (_dcache_io_lsu_release_bits_address), // @[tile.scala:132:54]
.io_dmem_release_bits_data (_dcache_io_lsu_release_bits_data), // @[tile.scala:132:54]
.io_dmem_force_order (_lsu_io_dmem_force_order),
.io_dmem_ordered (_dcache_io_lsu_ordered), // @[tile.scala:132:54]
.io_dmem_perf_acquire (_dcache_io_lsu_perf_acquire), // @[tile.scala:132:54]
.io_dmem_perf_release (_dcache_io_lsu_perf_release), // @[tile.scala:132:54]
.io_hellacache_req_ready (_lsu_io_hellacache_req_ready),
.io_hellacache_req_valid (_hellaCacheArb_io_mem_req_valid), // @[tile.scala:243:29]
.io_hellacache_req_bits_addr (_hellaCacheArb_io_mem_req_bits_addr), // @[tile.scala:243:29]
.io_hellacache_req_bits_dv (_hellaCacheArb_io_mem_req_bits_dv), // @[tile.scala:243:29]
.io_hellacache_s1_kill (_hellaCacheArb_io_mem_s1_kill), // @[tile.scala:243:29]
.io_hellacache_s2_nack (_lsu_io_hellacache_s2_nack),
.io_hellacache_resp_valid (_lsu_io_hellacache_resp_valid),
.io_hellacache_resp_bits_addr (_lsu_io_hellacache_resp_bits_addr),
.io_hellacache_resp_bits_data (_lsu_io_hellacache_resp_bits_data),
.io_hellacache_s2_xcpt_ma_ld (_lsu_io_hellacache_s2_xcpt_ma_ld),
.io_hellacache_s2_xcpt_ma_st (_lsu_io_hellacache_s2_xcpt_ma_st),
.io_hellacache_s2_xcpt_pf_ld (_lsu_io_hellacache_s2_xcpt_pf_ld),
.io_hellacache_s2_xcpt_pf_st (_lsu_io_hellacache_s2_xcpt_pf_st),
.io_hellacache_s2_xcpt_gf_ld (_lsu_io_hellacache_s2_xcpt_gf_ld),
.io_hellacache_s2_xcpt_gf_st (_lsu_io_hellacache_s2_xcpt_gf_st),
.io_hellacache_s2_xcpt_ae_ld (_lsu_io_hellacache_s2_xcpt_ae_ld),
.io_hellacache_s2_xcpt_ae_st (_lsu_io_hellacache_s2_xcpt_ae_st),
.io_hellacache_store_pending (_lsu_io_hellacache_store_pending)
); // @[tile.scala:160:20]
PTW_2 ptw ( // @[tile.scala:237:20]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_lsu_io_ptw_req_valid), // @[tile.scala:160:20]
.io_requestor_0_req_bits_valid (_lsu_io_ptw_req_bits_valid), // @[tile.scala:160:20]
.io_requestor_0_req_bits_bits_addr (_lsu_io_ptw_req_bits_bits_addr), // @[tile.scala:160:20]
.io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw),
.io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final),
.io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf),
.io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf),
.io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr),
.io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw),
.io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx),
.io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future),
.io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn),
.io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software),
.io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d),
.io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a),
.io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g),
.io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u),
.io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x),
.io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w),
.io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r),
.io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v),
.io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level),
.io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous),
.io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid),
.io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits),
.io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte),
.io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode),
.io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn),
.io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug),
.io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease),
.io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi),
.io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv),
.io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv),
.io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv),
.io_requestor_0_status_v (_ptw_io_requestor_0_status_v),
.io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd),
.io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv),
.io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva),
.io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr),
.io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw),
.io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm),
.io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr),
.io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum),
.io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv),
.io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs),
.io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp),
.io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp),
.io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie),
.io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie),
.io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie),
.io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie),
.io_requestor_0_pmp_0_cfg_l (_ptw_io_requestor_0_pmp_0_cfg_l),
.io_requestor_0_pmp_0_cfg_a (_ptw_io_requestor_0_pmp_0_cfg_a),
.io_requestor_0_pmp_0_cfg_x (_ptw_io_requestor_0_pmp_0_cfg_x),
.io_requestor_0_pmp_0_cfg_w (_ptw_io_requestor_0_pmp_0_cfg_w),
.io_requestor_0_pmp_0_cfg_r (_ptw_io_requestor_0_pmp_0_cfg_r),
.io_requestor_0_pmp_0_addr (_ptw_io_requestor_0_pmp_0_addr),
.io_requestor_0_pmp_0_mask (_ptw_io_requestor_0_pmp_0_mask),
.io_requestor_0_pmp_1_cfg_l (_ptw_io_requestor_0_pmp_1_cfg_l),
.io_requestor_0_pmp_1_cfg_a (_ptw_io_requestor_0_pmp_1_cfg_a),
.io_requestor_0_pmp_1_cfg_x (_ptw_io_requestor_0_pmp_1_cfg_x),
.io_requestor_0_pmp_1_cfg_w (_ptw_io_requestor_0_pmp_1_cfg_w),
.io_requestor_0_pmp_1_cfg_r (_ptw_io_requestor_0_pmp_1_cfg_r),
.io_requestor_0_pmp_1_addr (_ptw_io_requestor_0_pmp_1_addr),
.io_requestor_0_pmp_1_mask (_ptw_io_requestor_0_pmp_1_mask),
.io_requestor_0_pmp_2_cfg_l (_ptw_io_requestor_0_pmp_2_cfg_l),
.io_requestor_0_pmp_2_cfg_a (_ptw_io_requestor_0_pmp_2_cfg_a),
.io_requestor_0_pmp_2_cfg_x (_ptw_io_requestor_0_pmp_2_cfg_x),
.io_requestor_0_pmp_2_cfg_w (_ptw_io_requestor_0_pmp_2_cfg_w),
.io_requestor_0_pmp_2_cfg_r (_ptw_io_requestor_0_pmp_2_cfg_r),
.io_requestor_0_pmp_2_addr (_ptw_io_requestor_0_pmp_2_addr),
.io_requestor_0_pmp_2_mask (_ptw_io_requestor_0_pmp_2_mask),
.io_requestor_0_pmp_3_cfg_l (_ptw_io_requestor_0_pmp_3_cfg_l),
.io_requestor_0_pmp_3_cfg_a (_ptw_io_requestor_0_pmp_3_cfg_a),
.io_requestor_0_pmp_3_cfg_x (_ptw_io_requestor_0_pmp_3_cfg_x),
.io_requestor_0_pmp_3_cfg_w (_ptw_io_requestor_0_pmp_3_cfg_w),
.io_requestor_0_pmp_3_cfg_r (_ptw_io_requestor_0_pmp_3_cfg_r),
.io_requestor_0_pmp_3_addr (_ptw_io_requestor_0_pmp_3_addr),
.io_requestor_0_pmp_3_mask (_ptw_io_requestor_0_pmp_3_mask),
.io_requestor_0_pmp_4_cfg_l (_ptw_io_requestor_0_pmp_4_cfg_l),
.io_requestor_0_pmp_4_cfg_a (_ptw_io_requestor_0_pmp_4_cfg_a),
.io_requestor_0_pmp_4_cfg_x (_ptw_io_requestor_0_pmp_4_cfg_x),
.io_requestor_0_pmp_4_cfg_w (_ptw_io_requestor_0_pmp_4_cfg_w),
.io_requestor_0_pmp_4_cfg_r (_ptw_io_requestor_0_pmp_4_cfg_r),
.io_requestor_0_pmp_4_addr (_ptw_io_requestor_0_pmp_4_addr),
.io_requestor_0_pmp_4_mask (_ptw_io_requestor_0_pmp_4_mask),
.io_requestor_0_pmp_5_cfg_l (_ptw_io_requestor_0_pmp_5_cfg_l),
.io_requestor_0_pmp_5_cfg_a (_ptw_io_requestor_0_pmp_5_cfg_a),
.io_requestor_0_pmp_5_cfg_x (_ptw_io_requestor_0_pmp_5_cfg_x),
.io_requestor_0_pmp_5_cfg_w (_ptw_io_requestor_0_pmp_5_cfg_w),
.io_requestor_0_pmp_5_cfg_r (_ptw_io_requestor_0_pmp_5_cfg_r),
.io_requestor_0_pmp_5_addr (_ptw_io_requestor_0_pmp_5_addr),
.io_requestor_0_pmp_5_mask (_ptw_io_requestor_0_pmp_5_mask),
.io_requestor_0_pmp_6_cfg_l (_ptw_io_requestor_0_pmp_6_cfg_l),
.io_requestor_0_pmp_6_cfg_a (_ptw_io_requestor_0_pmp_6_cfg_a),
.io_requestor_0_pmp_6_cfg_x (_ptw_io_requestor_0_pmp_6_cfg_x),
.io_requestor_0_pmp_6_cfg_w (_ptw_io_requestor_0_pmp_6_cfg_w),
.io_requestor_0_pmp_6_cfg_r (_ptw_io_requestor_0_pmp_6_cfg_r),
.io_requestor_0_pmp_6_addr (_ptw_io_requestor_0_pmp_6_addr),
.io_requestor_0_pmp_6_mask (_ptw_io_requestor_0_pmp_6_mask),
.io_requestor_0_pmp_7_cfg_l (_ptw_io_requestor_0_pmp_7_cfg_l),
.io_requestor_0_pmp_7_cfg_a (_ptw_io_requestor_0_pmp_7_cfg_a),
.io_requestor_0_pmp_7_cfg_x (_ptw_io_requestor_0_pmp_7_cfg_x),
.io_requestor_0_pmp_7_cfg_w (_ptw_io_requestor_0_pmp_7_cfg_w),
.io_requestor_0_pmp_7_cfg_r (_ptw_io_requestor_0_pmp_7_cfg_r),
.io_requestor_0_pmp_7_addr (_ptw_io_requestor_0_pmp_7_addr),
.io_requestor_0_pmp_7_mask (_ptw_io_requestor_0_pmp_7_mask),
.io_requestor_1_req_ready (_ptw_io_requestor_1_req_ready),
.io_requestor_1_req_valid (_frontend_io_ptw_req_valid), // @[tile.scala:138:28]
.io_requestor_1_req_bits_bits_addr (_frontend_io_ptw_req_bits_bits_addr), // @[tile.scala:138:28]
.io_requestor_1_req_bits_bits_need_gpa (_frontend_io_ptw_req_bits_bits_need_gpa), // @[tile.scala:138:28]
.io_requestor_1_resp_valid (_ptw_io_requestor_1_resp_valid),
.io_requestor_1_resp_bits_ae_ptw (_ptw_io_requestor_1_resp_bits_ae_ptw),
.io_requestor_1_resp_bits_ae_final (_ptw_io_requestor_1_resp_bits_ae_final),
.io_requestor_1_resp_bits_pf (_ptw_io_requestor_1_resp_bits_pf),
.io_requestor_1_resp_bits_gf (_ptw_io_requestor_1_resp_bits_gf),
.io_requestor_1_resp_bits_hr (_ptw_io_requestor_1_resp_bits_hr),
.io_requestor_1_resp_bits_hw (_ptw_io_requestor_1_resp_bits_hw),
.io_requestor_1_resp_bits_hx (_ptw_io_requestor_1_resp_bits_hx),
.io_requestor_1_resp_bits_pte_reserved_for_future (_ptw_io_requestor_1_resp_bits_pte_reserved_for_future),
.io_requestor_1_resp_bits_pte_ppn (_ptw_io_requestor_1_resp_bits_pte_ppn),
.io_requestor_1_resp_bits_pte_reserved_for_software (_ptw_io_requestor_1_resp_bits_pte_reserved_for_software),
.io_requestor_1_resp_bits_pte_d (_ptw_io_requestor_1_resp_bits_pte_d),
.io_requestor_1_resp_bits_pte_a (_ptw_io_requestor_1_resp_bits_pte_a),
.io_requestor_1_resp_bits_pte_g (_ptw_io_requestor_1_resp_bits_pte_g),
.io_requestor_1_resp_bits_pte_u (_ptw_io_requestor_1_resp_bits_pte_u),
.io_requestor_1_resp_bits_pte_x (_ptw_io_requestor_1_resp_bits_pte_x),
.io_requestor_1_resp_bits_pte_w (_ptw_io_requestor_1_resp_bits_pte_w),
.io_requestor_1_resp_bits_pte_r (_ptw_io_requestor_1_resp_bits_pte_r),
.io_requestor_1_resp_bits_pte_v (_ptw_io_requestor_1_resp_bits_pte_v),
.io_requestor_1_resp_bits_level (_ptw_io_requestor_1_resp_bits_level),
.io_requestor_1_resp_bits_homogeneous (_ptw_io_requestor_1_resp_bits_homogeneous),
.io_requestor_1_resp_bits_gpa_valid (_ptw_io_requestor_1_resp_bits_gpa_valid),
.io_requestor_1_resp_bits_gpa_bits (_ptw_io_requestor_1_resp_bits_gpa_bits),
.io_requestor_1_resp_bits_gpa_is_pte (_ptw_io_requestor_1_resp_bits_gpa_is_pte),
.io_requestor_1_ptbr_mode (_ptw_io_requestor_1_ptbr_mode),
.io_requestor_1_ptbr_ppn (_ptw_io_requestor_1_ptbr_ppn),
.io_requestor_1_status_debug (_ptw_io_requestor_1_status_debug),
.io_requestor_1_status_cease (_ptw_io_requestor_1_status_cease),
.io_requestor_1_status_wfi (_ptw_io_requestor_1_status_wfi),
.io_requestor_1_status_dprv (_ptw_io_requestor_1_status_dprv),
.io_requestor_1_status_dv (_ptw_io_requestor_1_status_dv),
.io_requestor_1_status_prv (_ptw_io_requestor_1_status_prv),
.io_requestor_1_status_v (_ptw_io_requestor_1_status_v),
.io_requestor_1_status_sd (_ptw_io_requestor_1_status_sd),
.io_requestor_1_status_mpv (_ptw_io_requestor_1_status_mpv),
.io_requestor_1_status_gva (_ptw_io_requestor_1_status_gva),
.io_requestor_1_status_tsr (_ptw_io_requestor_1_status_tsr),
.io_requestor_1_status_tw (_ptw_io_requestor_1_status_tw),
.io_requestor_1_status_tvm (_ptw_io_requestor_1_status_tvm),
.io_requestor_1_status_mxr (_ptw_io_requestor_1_status_mxr),
.io_requestor_1_status_sum (_ptw_io_requestor_1_status_sum),
.io_requestor_1_status_mprv (_ptw_io_requestor_1_status_mprv),
.io_requestor_1_status_fs (_ptw_io_requestor_1_status_fs),
.io_requestor_1_status_mpp (_ptw_io_requestor_1_status_mpp),
.io_requestor_1_status_spp (_ptw_io_requestor_1_status_spp),
.io_requestor_1_status_mpie (_ptw_io_requestor_1_status_mpie),
.io_requestor_1_status_spie (_ptw_io_requestor_1_status_spie),
.io_requestor_1_status_mie (_ptw_io_requestor_1_status_mie),
.io_requestor_1_status_sie (_ptw_io_requestor_1_status_sie),
.io_requestor_1_pmp_0_cfg_l (_ptw_io_requestor_1_pmp_0_cfg_l),
.io_requestor_1_pmp_0_cfg_a (_ptw_io_requestor_1_pmp_0_cfg_a),
.io_requestor_1_pmp_0_cfg_x (_ptw_io_requestor_1_pmp_0_cfg_x),
.io_requestor_1_pmp_0_cfg_w (_ptw_io_requestor_1_pmp_0_cfg_w),
.io_requestor_1_pmp_0_cfg_r (_ptw_io_requestor_1_pmp_0_cfg_r),
.io_requestor_1_pmp_0_addr (_ptw_io_requestor_1_pmp_0_addr),
.io_requestor_1_pmp_0_mask (_ptw_io_requestor_1_pmp_0_mask),
.io_requestor_1_pmp_1_cfg_l (_ptw_io_requestor_1_pmp_1_cfg_l),
.io_requestor_1_pmp_1_cfg_a (_ptw_io_requestor_1_pmp_1_cfg_a),
.io_requestor_1_pmp_1_cfg_x (_ptw_io_requestor_1_pmp_1_cfg_x),
.io_requestor_1_pmp_1_cfg_w (_ptw_io_requestor_1_pmp_1_cfg_w),
.io_requestor_1_pmp_1_cfg_r (_ptw_io_requestor_1_pmp_1_cfg_r),
.io_requestor_1_pmp_1_addr (_ptw_io_requestor_1_pmp_1_addr),
.io_requestor_1_pmp_1_mask (_ptw_io_requestor_1_pmp_1_mask),
.io_requestor_1_pmp_2_cfg_l (_ptw_io_requestor_1_pmp_2_cfg_l),
.io_requestor_1_pmp_2_cfg_a (_ptw_io_requestor_1_pmp_2_cfg_a),
.io_requestor_1_pmp_2_cfg_x (_ptw_io_requestor_1_pmp_2_cfg_x),
.io_requestor_1_pmp_2_cfg_w (_ptw_io_requestor_1_pmp_2_cfg_w),
.io_requestor_1_pmp_2_cfg_r (_ptw_io_requestor_1_pmp_2_cfg_r),
.io_requestor_1_pmp_2_addr (_ptw_io_requestor_1_pmp_2_addr),
.io_requestor_1_pmp_2_mask (_ptw_io_requestor_1_pmp_2_mask),
.io_requestor_1_pmp_3_cfg_l (_ptw_io_requestor_1_pmp_3_cfg_l),
.io_requestor_1_pmp_3_cfg_a (_ptw_io_requestor_1_pmp_3_cfg_a),
.io_requestor_1_pmp_3_cfg_x (_ptw_io_requestor_1_pmp_3_cfg_x),
.io_requestor_1_pmp_3_cfg_w (_ptw_io_requestor_1_pmp_3_cfg_w),
.io_requestor_1_pmp_3_cfg_r (_ptw_io_requestor_1_pmp_3_cfg_r),
.io_requestor_1_pmp_3_addr (_ptw_io_requestor_1_pmp_3_addr),
.io_requestor_1_pmp_3_mask (_ptw_io_requestor_1_pmp_3_mask),
.io_requestor_1_pmp_4_cfg_l (_ptw_io_requestor_1_pmp_4_cfg_l),
.io_requestor_1_pmp_4_cfg_a (_ptw_io_requestor_1_pmp_4_cfg_a),
.io_requestor_1_pmp_4_cfg_x (_ptw_io_requestor_1_pmp_4_cfg_x),
.io_requestor_1_pmp_4_cfg_w (_ptw_io_requestor_1_pmp_4_cfg_w),
.io_requestor_1_pmp_4_cfg_r (_ptw_io_requestor_1_pmp_4_cfg_r),
.io_requestor_1_pmp_4_addr (_ptw_io_requestor_1_pmp_4_addr),
.io_requestor_1_pmp_4_mask (_ptw_io_requestor_1_pmp_4_mask),
.io_requestor_1_pmp_5_cfg_l (_ptw_io_requestor_1_pmp_5_cfg_l),
.io_requestor_1_pmp_5_cfg_a (_ptw_io_requestor_1_pmp_5_cfg_a),
.io_requestor_1_pmp_5_cfg_x (_ptw_io_requestor_1_pmp_5_cfg_x),
.io_requestor_1_pmp_5_cfg_w (_ptw_io_requestor_1_pmp_5_cfg_w),
.io_requestor_1_pmp_5_cfg_r (_ptw_io_requestor_1_pmp_5_cfg_r),
.io_requestor_1_pmp_5_addr (_ptw_io_requestor_1_pmp_5_addr),
.io_requestor_1_pmp_5_mask (_ptw_io_requestor_1_pmp_5_mask),
.io_requestor_1_pmp_6_cfg_l (_ptw_io_requestor_1_pmp_6_cfg_l),
.io_requestor_1_pmp_6_cfg_a (_ptw_io_requestor_1_pmp_6_cfg_a),
.io_requestor_1_pmp_6_cfg_x (_ptw_io_requestor_1_pmp_6_cfg_x),
.io_requestor_1_pmp_6_cfg_w (_ptw_io_requestor_1_pmp_6_cfg_w),
.io_requestor_1_pmp_6_cfg_r (_ptw_io_requestor_1_pmp_6_cfg_r),
.io_requestor_1_pmp_6_addr (_ptw_io_requestor_1_pmp_6_addr),
.io_requestor_1_pmp_6_mask (_ptw_io_requestor_1_pmp_6_mask),
.io_requestor_1_pmp_7_cfg_l (_ptw_io_requestor_1_pmp_7_cfg_l),
.io_requestor_1_pmp_7_cfg_a (_ptw_io_requestor_1_pmp_7_cfg_a),
.io_requestor_1_pmp_7_cfg_x (_ptw_io_requestor_1_pmp_7_cfg_x),
.io_requestor_1_pmp_7_cfg_w (_ptw_io_requestor_1_pmp_7_cfg_w),
.io_requestor_1_pmp_7_cfg_r (_ptw_io_requestor_1_pmp_7_cfg_r),
.io_requestor_1_pmp_7_addr (_ptw_io_requestor_1_pmp_7_addr),
.io_requestor_1_pmp_7_mask (_ptw_io_requestor_1_pmp_7_mask),
.io_requestor_2_req_ready (_ptw_io_requestor_2_req_ready),
.io_requestor_2_resp_valid (_ptw_io_requestor_2_resp_valid),
.io_requestor_2_resp_bits_ae_ptw (_ptw_io_requestor_2_resp_bits_ae_ptw),
.io_requestor_2_resp_bits_ae_final (_ptw_io_requestor_2_resp_bits_ae_final),
.io_requestor_2_resp_bits_pf (_ptw_io_requestor_2_resp_bits_pf),
.io_requestor_2_resp_bits_gf (_ptw_io_requestor_2_resp_bits_gf),
.io_requestor_2_resp_bits_hr (_ptw_io_requestor_2_resp_bits_hr),
.io_requestor_2_resp_bits_hw (_ptw_io_requestor_2_resp_bits_hw),
.io_requestor_2_resp_bits_hx (_ptw_io_requestor_2_resp_bits_hx),
.io_requestor_2_resp_bits_pte_reserved_for_future (_ptw_io_requestor_2_resp_bits_pte_reserved_for_future),
.io_requestor_2_resp_bits_pte_ppn (_ptw_io_requestor_2_resp_bits_pte_ppn),
.io_requestor_2_resp_bits_pte_reserved_for_software (_ptw_io_requestor_2_resp_bits_pte_reserved_for_software),
.io_requestor_2_resp_bits_pte_d (_ptw_io_requestor_2_resp_bits_pte_d),
.io_requestor_2_resp_bits_pte_a (_ptw_io_requestor_2_resp_bits_pte_a),
.io_requestor_2_resp_bits_pte_g (_ptw_io_requestor_2_resp_bits_pte_g),
.io_requestor_2_resp_bits_pte_u (_ptw_io_requestor_2_resp_bits_pte_u),
.io_requestor_2_resp_bits_pte_x (_ptw_io_requestor_2_resp_bits_pte_x),
.io_requestor_2_resp_bits_pte_w (_ptw_io_requestor_2_resp_bits_pte_w),
.io_requestor_2_resp_bits_pte_r (_ptw_io_requestor_2_resp_bits_pte_r),
.io_requestor_2_resp_bits_pte_v (_ptw_io_requestor_2_resp_bits_pte_v),
.io_requestor_2_resp_bits_level (_ptw_io_requestor_2_resp_bits_level),
.io_requestor_2_resp_bits_homogeneous (_ptw_io_requestor_2_resp_bits_homogeneous),
.io_requestor_2_resp_bits_gpa_valid (_ptw_io_requestor_2_resp_bits_gpa_valid),
.io_requestor_2_resp_bits_gpa_bits (_ptw_io_requestor_2_resp_bits_gpa_bits),
.io_requestor_2_resp_bits_gpa_is_pte (_ptw_io_requestor_2_resp_bits_gpa_is_pte),
.io_requestor_2_ptbr_mode (_ptw_io_requestor_2_ptbr_mode),
.io_requestor_2_ptbr_ppn (_ptw_io_requestor_2_ptbr_ppn),
.io_requestor_2_status_debug (_ptw_io_requestor_2_status_debug),
.io_requestor_2_status_cease (_ptw_io_requestor_2_status_cease),
.io_requestor_2_status_wfi (_ptw_io_requestor_2_status_wfi),
.io_requestor_2_status_dprv (_ptw_io_requestor_2_status_dprv),
.io_requestor_2_status_dv (_ptw_io_requestor_2_status_dv),
.io_requestor_2_status_prv (_ptw_io_requestor_2_status_prv),
.io_requestor_2_status_v (_ptw_io_requestor_2_status_v),
.io_requestor_2_status_sd (_ptw_io_requestor_2_status_sd),
.io_requestor_2_status_mpv (_ptw_io_requestor_2_status_mpv),
.io_requestor_2_status_gva (_ptw_io_requestor_2_status_gva),
.io_requestor_2_status_tsr (_ptw_io_requestor_2_status_tsr),
.io_requestor_2_status_tw (_ptw_io_requestor_2_status_tw),
.io_requestor_2_status_tvm (_ptw_io_requestor_2_status_tvm),
.io_requestor_2_status_mxr (_ptw_io_requestor_2_status_mxr),
.io_requestor_2_status_sum (_ptw_io_requestor_2_status_sum),
.io_requestor_2_status_mprv (_ptw_io_requestor_2_status_mprv),
.io_requestor_2_status_fs (_ptw_io_requestor_2_status_fs),
.io_requestor_2_status_mpp (_ptw_io_requestor_2_status_mpp),
.io_requestor_2_status_spp (_ptw_io_requestor_2_status_spp),
.io_requestor_2_status_mpie (_ptw_io_requestor_2_status_mpie),
.io_requestor_2_status_spie (_ptw_io_requestor_2_status_spie),
.io_requestor_2_status_mie (_ptw_io_requestor_2_status_mie),
.io_requestor_2_status_sie (_ptw_io_requestor_2_status_sie),
.io_requestor_2_pmp_0_cfg_l (_ptw_io_requestor_2_pmp_0_cfg_l),
.io_requestor_2_pmp_0_cfg_a (_ptw_io_requestor_2_pmp_0_cfg_a),
.io_requestor_2_pmp_0_cfg_x (_ptw_io_requestor_2_pmp_0_cfg_x),
.io_requestor_2_pmp_0_cfg_w (_ptw_io_requestor_2_pmp_0_cfg_w),
.io_requestor_2_pmp_0_cfg_r (_ptw_io_requestor_2_pmp_0_cfg_r),
.io_requestor_2_pmp_0_addr (_ptw_io_requestor_2_pmp_0_addr),
.io_requestor_2_pmp_0_mask (_ptw_io_requestor_2_pmp_0_mask),
.io_requestor_2_pmp_1_cfg_l (_ptw_io_requestor_2_pmp_1_cfg_l),
.io_requestor_2_pmp_1_cfg_a (_ptw_io_requestor_2_pmp_1_cfg_a),
.io_requestor_2_pmp_1_cfg_x (_ptw_io_requestor_2_pmp_1_cfg_x),
.io_requestor_2_pmp_1_cfg_w (_ptw_io_requestor_2_pmp_1_cfg_w),
.io_requestor_2_pmp_1_cfg_r (_ptw_io_requestor_2_pmp_1_cfg_r),
.io_requestor_2_pmp_1_addr (_ptw_io_requestor_2_pmp_1_addr),
.io_requestor_2_pmp_1_mask (_ptw_io_requestor_2_pmp_1_mask),
.io_requestor_2_pmp_2_cfg_l (_ptw_io_requestor_2_pmp_2_cfg_l),
.io_requestor_2_pmp_2_cfg_a (_ptw_io_requestor_2_pmp_2_cfg_a),
.io_requestor_2_pmp_2_cfg_x (_ptw_io_requestor_2_pmp_2_cfg_x),
.io_requestor_2_pmp_2_cfg_w (_ptw_io_requestor_2_pmp_2_cfg_w),
.io_requestor_2_pmp_2_cfg_r (_ptw_io_requestor_2_pmp_2_cfg_r),
.io_requestor_2_pmp_2_addr (_ptw_io_requestor_2_pmp_2_addr),
.io_requestor_2_pmp_2_mask (_ptw_io_requestor_2_pmp_2_mask),
.io_requestor_2_pmp_3_cfg_l (_ptw_io_requestor_2_pmp_3_cfg_l),
.io_requestor_2_pmp_3_cfg_a (_ptw_io_requestor_2_pmp_3_cfg_a),
.io_requestor_2_pmp_3_cfg_x (_ptw_io_requestor_2_pmp_3_cfg_x),
.io_requestor_2_pmp_3_cfg_w (_ptw_io_requestor_2_pmp_3_cfg_w),
.io_requestor_2_pmp_3_cfg_r (_ptw_io_requestor_2_pmp_3_cfg_r),
.io_requestor_2_pmp_3_addr (_ptw_io_requestor_2_pmp_3_addr),
.io_requestor_2_pmp_3_mask (_ptw_io_requestor_2_pmp_3_mask),
.io_requestor_2_pmp_4_cfg_l (_ptw_io_requestor_2_pmp_4_cfg_l),
.io_requestor_2_pmp_4_cfg_a (_ptw_io_requestor_2_pmp_4_cfg_a),
.io_requestor_2_pmp_4_cfg_x (_ptw_io_requestor_2_pmp_4_cfg_x),
.io_requestor_2_pmp_4_cfg_w (_ptw_io_requestor_2_pmp_4_cfg_w),
.io_requestor_2_pmp_4_cfg_r (_ptw_io_requestor_2_pmp_4_cfg_r),
.io_requestor_2_pmp_4_addr (_ptw_io_requestor_2_pmp_4_addr),
.io_requestor_2_pmp_4_mask (_ptw_io_requestor_2_pmp_4_mask),
.io_requestor_2_pmp_5_cfg_l (_ptw_io_requestor_2_pmp_5_cfg_l),
.io_requestor_2_pmp_5_cfg_a (_ptw_io_requestor_2_pmp_5_cfg_a),
.io_requestor_2_pmp_5_cfg_x (_ptw_io_requestor_2_pmp_5_cfg_x),
.io_requestor_2_pmp_5_cfg_w (_ptw_io_requestor_2_pmp_5_cfg_w),
.io_requestor_2_pmp_5_cfg_r (_ptw_io_requestor_2_pmp_5_cfg_r),
.io_requestor_2_pmp_5_addr (_ptw_io_requestor_2_pmp_5_addr),
.io_requestor_2_pmp_5_mask (_ptw_io_requestor_2_pmp_5_mask),
.io_requestor_2_pmp_6_cfg_l (_ptw_io_requestor_2_pmp_6_cfg_l),
.io_requestor_2_pmp_6_cfg_a (_ptw_io_requestor_2_pmp_6_cfg_a),
.io_requestor_2_pmp_6_cfg_x (_ptw_io_requestor_2_pmp_6_cfg_x),
.io_requestor_2_pmp_6_cfg_w (_ptw_io_requestor_2_pmp_6_cfg_w),
.io_requestor_2_pmp_6_cfg_r (_ptw_io_requestor_2_pmp_6_cfg_r),
.io_requestor_2_pmp_6_addr (_ptw_io_requestor_2_pmp_6_addr),
.io_requestor_2_pmp_6_mask (_ptw_io_requestor_2_pmp_6_mask),
.io_requestor_2_pmp_7_cfg_l (_ptw_io_requestor_2_pmp_7_cfg_l),
.io_requestor_2_pmp_7_cfg_a (_ptw_io_requestor_2_pmp_7_cfg_a),
.io_requestor_2_pmp_7_cfg_x (_ptw_io_requestor_2_pmp_7_cfg_x),
.io_requestor_2_pmp_7_cfg_w (_ptw_io_requestor_2_pmp_7_cfg_w),
.io_requestor_2_pmp_7_cfg_r (_ptw_io_requestor_2_pmp_7_cfg_r),
.io_requestor_2_pmp_7_addr (_ptw_io_requestor_2_pmp_7_addr),
.io_requestor_2_pmp_7_mask (_ptw_io_requestor_2_pmp_7_mask),
.io_mem_req_ready (_hellaCacheArb_io_requestor_0_req_ready), // @[tile.scala:243:29]
.io_mem_req_valid (_ptw_io_mem_req_valid),
.io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr),
.io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv),
.io_mem_s1_kill (_ptw_io_mem_s1_kill),
.io_mem_s2_nack (_hellaCacheArb_io_requestor_0_s2_nack), // @[tile.scala:243:29]
.io_mem_resp_valid (_hellaCacheArb_io_requestor_0_resp_valid), // @[tile.scala:243:29]
.io_mem_resp_bits_addr (_hellaCacheArb_io_requestor_0_resp_bits_addr), // @[tile.scala:243:29]
.io_mem_resp_bits_data (_hellaCacheArb_io_requestor_0_resp_bits_data), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ma_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ma_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_st), // @[tile.scala:243:29]
.io_mem_s2_xcpt_pf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_pf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_st), // @[tile.scala:243:29]
.io_mem_s2_xcpt_gf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_gf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_st), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ae_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[tile.scala:243:29]
.io_mem_s2_xcpt_ae_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_st), // @[tile.scala:243:29]
.io_mem_store_pending (_hellaCacheArb_io_requestor_0_store_pending), // @[tile.scala:243:29]
.io_dpath_ptbr_mode (_core_io_ptw_ptbr_mode), // @[tile.scala:159:20]
.io_dpath_ptbr_ppn (_core_io_ptw_ptbr_ppn), // @[tile.scala:159:20]
.io_dpath_sfence_valid (_core_io_ptw_sfence_valid), // @[tile.scala:159:20]
.io_dpath_sfence_bits_rs1 (_core_io_ptw_sfence_bits_rs1), // @[tile.scala:159:20]
.io_dpath_sfence_bits_rs2 (_core_io_ptw_sfence_bits_rs2), // @[tile.scala:159:20]
.io_dpath_sfence_bits_addr (_core_io_ptw_sfence_bits_addr), // @[tile.scala:159:20]
.io_dpath_sfence_bits_asid (_core_io_ptw_sfence_bits_asid), // @[tile.scala:159:20]
.io_dpath_status_debug (_core_io_ptw_status_debug), // @[tile.scala:159:20]
.io_dpath_status_cease (_core_io_ptw_status_cease), // @[tile.scala:159:20]
.io_dpath_status_wfi (_core_io_ptw_status_wfi), // @[tile.scala:159:20]
.io_dpath_status_dprv (_core_io_ptw_status_dprv), // @[tile.scala:159:20]
.io_dpath_status_dv (_core_io_ptw_status_dv), // @[tile.scala:159:20]
.io_dpath_status_prv (_core_io_ptw_status_prv), // @[tile.scala:159:20]
.io_dpath_status_v (_core_io_ptw_status_v), // @[tile.scala:159:20]
.io_dpath_status_sd (_core_io_ptw_status_sd), // @[tile.scala:159:20]
.io_dpath_status_mpv (_core_io_ptw_status_mpv), // @[tile.scala:159:20]
.io_dpath_status_gva (_core_io_ptw_status_gva), // @[tile.scala:159:20]
.io_dpath_status_tsr (_core_io_ptw_status_tsr), // @[tile.scala:159:20]
.io_dpath_status_tw (_core_io_ptw_status_tw), // @[tile.scala:159:20]
.io_dpath_status_tvm (_core_io_ptw_status_tvm), // @[tile.scala:159:20]
.io_dpath_status_mxr (_core_io_ptw_status_mxr), // @[tile.scala:159:20]
.io_dpath_status_sum (_core_io_ptw_status_sum), // @[tile.scala:159:20]
.io_dpath_status_mprv (_core_io_ptw_status_mprv), // @[tile.scala:159:20]
.io_dpath_status_fs (_core_io_ptw_status_fs), // @[tile.scala:159:20]
.io_dpath_status_mpp (_core_io_ptw_status_mpp), // @[tile.scala:159:20]
.io_dpath_status_spp (_core_io_ptw_status_spp), // @[tile.scala:159:20]
.io_dpath_status_mpie (_core_io_ptw_status_mpie), // @[tile.scala:159:20]
.io_dpath_status_spie (_core_io_ptw_status_spie), // @[tile.scala:159:20]
.io_dpath_status_mie (_core_io_ptw_status_mie), // @[tile.scala:159:20]
.io_dpath_status_sie (_core_io_ptw_status_sie), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_l (_core_io_ptw_pmp_0_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_a (_core_io_ptw_pmp_0_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_x (_core_io_ptw_pmp_0_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_w (_core_io_ptw_pmp_0_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_0_cfg_r (_core_io_ptw_pmp_0_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_0_addr (_core_io_ptw_pmp_0_addr), // @[tile.scala:159:20]
.io_dpath_pmp_0_mask (_core_io_ptw_pmp_0_mask), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_l (_core_io_ptw_pmp_1_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_a (_core_io_ptw_pmp_1_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_x (_core_io_ptw_pmp_1_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_w (_core_io_ptw_pmp_1_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_1_cfg_r (_core_io_ptw_pmp_1_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_1_addr (_core_io_ptw_pmp_1_addr), // @[tile.scala:159:20]
.io_dpath_pmp_1_mask (_core_io_ptw_pmp_1_mask), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_l (_core_io_ptw_pmp_2_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_a (_core_io_ptw_pmp_2_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_x (_core_io_ptw_pmp_2_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_w (_core_io_ptw_pmp_2_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_2_cfg_r (_core_io_ptw_pmp_2_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_2_addr (_core_io_ptw_pmp_2_addr), // @[tile.scala:159:20]
.io_dpath_pmp_2_mask (_core_io_ptw_pmp_2_mask), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_l (_core_io_ptw_pmp_3_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_a (_core_io_ptw_pmp_3_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_x (_core_io_ptw_pmp_3_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_w (_core_io_ptw_pmp_3_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_3_cfg_r (_core_io_ptw_pmp_3_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_3_addr (_core_io_ptw_pmp_3_addr), // @[tile.scala:159:20]
.io_dpath_pmp_3_mask (_core_io_ptw_pmp_3_mask), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_l (_core_io_ptw_pmp_4_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_a (_core_io_ptw_pmp_4_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_x (_core_io_ptw_pmp_4_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_w (_core_io_ptw_pmp_4_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_4_cfg_r (_core_io_ptw_pmp_4_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_4_addr (_core_io_ptw_pmp_4_addr), // @[tile.scala:159:20]
.io_dpath_pmp_4_mask (_core_io_ptw_pmp_4_mask), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_l (_core_io_ptw_pmp_5_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_a (_core_io_ptw_pmp_5_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_x (_core_io_ptw_pmp_5_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_w (_core_io_ptw_pmp_5_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_5_cfg_r (_core_io_ptw_pmp_5_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_5_addr (_core_io_ptw_pmp_5_addr), // @[tile.scala:159:20]
.io_dpath_pmp_5_mask (_core_io_ptw_pmp_5_mask), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_l (_core_io_ptw_pmp_6_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_a (_core_io_ptw_pmp_6_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_x (_core_io_ptw_pmp_6_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_w (_core_io_ptw_pmp_6_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_6_cfg_r (_core_io_ptw_pmp_6_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_6_addr (_core_io_ptw_pmp_6_addr), // @[tile.scala:159:20]
.io_dpath_pmp_6_mask (_core_io_ptw_pmp_6_mask), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_l (_core_io_ptw_pmp_7_cfg_l), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_a (_core_io_ptw_pmp_7_cfg_a), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_x (_core_io_ptw_pmp_7_cfg_x), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_w (_core_io_ptw_pmp_7_cfg_w), // @[tile.scala:159:20]
.io_dpath_pmp_7_cfg_r (_core_io_ptw_pmp_7_cfg_r), // @[tile.scala:159:20]
.io_dpath_pmp_7_addr (_core_io_ptw_pmp_7_addr), // @[tile.scala:159:20]
.io_dpath_pmp_7_mask (_core_io_ptw_pmp_7_mask), // @[tile.scala:159:20]
.io_dpath_perf_l2miss (_ptw_io_dpath_perf_l2miss),
.io_dpath_perf_l2hit (_ptw_io_dpath_perf_l2hit),
.io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss),
.io_dpath_perf_pte_hit (_ptw_io_dpath_perf_pte_hit),
.io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled)
); // @[tile.scala:237:20]
HellaCacheArbiter_2 hellaCacheArb ( // @[tile.scala:243:29]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_hellaCacheArb_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[tile.scala:237:20]
.io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[tile.scala:237:20]
.io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[tile.scala:237:20]
.io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[tile.scala:237:20]
.io_requestor_0_s2_nack (_hellaCacheArb_io_requestor_0_s2_nack),
.io_requestor_0_resp_valid (_hellaCacheArb_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_addr (_hellaCacheArb_io_requestor_0_resp_bits_addr),
.io_requestor_0_resp_bits_data (_hellaCacheArb_io_requestor_0_resp_bits_data),
.io_requestor_0_s2_xcpt_ma_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_ld),
.io_requestor_0_s2_xcpt_ma_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ma_st),
.io_requestor_0_s2_xcpt_pf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_ld),
.io_requestor_0_s2_xcpt_pf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_pf_st),
.io_requestor_0_s2_xcpt_gf_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_ld),
.io_requestor_0_s2_xcpt_gf_st (_hellaCacheArb_io_requestor_0_s2_xcpt_gf_st),
.io_requestor_0_s2_xcpt_ae_ld (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_ld),
.io_requestor_0_s2_xcpt_ae_st (_hellaCacheArb_io_requestor_0_s2_xcpt_ae_st),
.io_requestor_0_store_pending (_hellaCacheArb_io_requestor_0_store_pending),
.io_mem_req_ready (_lsu_io_hellacache_req_ready), // @[tile.scala:160:20]
.io_mem_req_valid (_hellaCacheArb_io_mem_req_valid),
.io_mem_req_bits_addr (_hellaCacheArb_io_mem_req_bits_addr),
.io_mem_req_bits_dv (_hellaCacheArb_io_mem_req_bits_dv),
.io_mem_s1_kill (_hellaCacheArb_io_mem_s1_kill),
.io_mem_s2_nack (_lsu_io_hellacache_s2_nack), // @[tile.scala:160:20]
.io_mem_resp_valid (_lsu_io_hellacache_resp_valid), // @[tile.scala:160:20]
.io_mem_resp_bits_addr (_lsu_io_hellacache_resp_bits_addr), // @[tile.scala:160:20]
.io_mem_resp_bits_data (_lsu_io_hellacache_resp_bits_data), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ma_ld (_lsu_io_hellacache_s2_xcpt_ma_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ma_st (_lsu_io_hellacache_s2_xcpt_ma_st), // @[tile.scala:160:20]
.io_mem_s2_xcpt_pf_ld (_lsu_io_hellacache_s2_xcpt_pf_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_pf_st (_lsu_io_hellacache_s2_xcpt_pf_st), // @[tile.scala:160:20]
.io_mem_s2_xcpt_gf_ld (_lsu_io_hellacache_s2_xcpt_gf_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_gf_st (_lsu_io_hellacache_s2_xcpt_gf_st), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ae_ld (_lsu_io_hellacache_s2_xcpt_ae_ld), // @[tile.scala:160:20]
.io_mem_s2_xcpt_ae_st (_lsu_io_hellacache_s2_xcpt_ae_st), // @[tile.scala:160:20]
.io_mem_store_pending (_lsu_io_hellacache_store_pending) // @[tile.scala:160:20]
); // @[tile.scala:243:29]
assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[tile.scala:155:7]
assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[tile.scala:155:7]
assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[tile.scala:155:7]
assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[tile.scala:155:7]
assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[tile.scala:155:7]
assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[tile.scala:155:7]
assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[tile.scala:155:7]
assign auto_trace_source_out_time = auto_trace_source_out_time_0; // @[tile.scala:155:7]
assign auto_trace_source_out_custom_rob_empty = auto_trace_source_out_custom_rob_empty_0; // @[tile.scala:155:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module PE_306( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_50 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
|
module OptimizationBarrier_TLBEntryData_50( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerShiftReg_w1_d3_i0_45( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_57 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File EgressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = Decoupled(new EgressFlit(cParam.payloadBits))
}
val io = IO(new EgressUnitIO)
val channel_empty = RegInit(true.B)
val flow = Reg(new FlowRoutingBundle)
val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true))
q.io.enq.valid := io.in(0).valid
q.io.enq.bits.head := io.in(0).bits.head
q.io.enq.bits.tail := io.in(0).bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
q.io.enq.bits.ingress_id := 0.U(1.W)
} else {
q.io.enq.bits.ingress_id := Mux1H(
flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node &&
f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)),
flows.map(f => f.ingressId.U(ingressIdBits.W))
)
}
q.io.enq.bits.payload := io.in(0).bits.payload
io.out <> q.io.deq
assert(!(q.io.enq.valid && !q.io.enq.ready))
io.credit_available(0) := q.io.count === 0.U
io.channel_status(0).occupied := !channel_empty
io.channel_status(0).flow := flow
when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) {
channel_empty := true.B
if (coupleSAVA) io.channel_status(0).occupied := false.B
}
when (io.allocs(0).alloc) {
channel_empty := false.B
flow := io.allocs(0).flow
}
}
|
module EgressUnit_12( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [144:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [144:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_10 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_19( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_18 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_25 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [103:0] c_opcodes_set = 104'h0; // @[Monitor.scala:740:34]
wire [103:0] c_sizes_set = 104'h0; // @[Monitor.scala:741:34]
wire [25:0] c_set = 26'h0; // @[Monitor.scala:738:34]
wire [25:0] c_set_wo_ready = 26'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_7 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_4 = source_ok_uncommonBits < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire _source_ok_T_6 = io_in_a_bits_source_0 == 5'h19; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = ~_source_ok_T_7; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_11 = source_ok_uncommonBits_1 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_12 = _source_ok_T_10 & _source_ok_T_11; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire _source_ok_T_13 = io_in_a_bits_source_0 == 5'h9; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_3 = _source_ok_T_13; // @[Parameters.scala:1138:31]
wire _source_ok_T_14 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_15 = _source_ok_T_14 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_15 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_18 = _uncommonBits_T_18[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_19 = _uncommonBits_T_19[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_20 = _uncommonBits_T_20[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] uncommonBits_21 = _uncommonBits_T_21[3:0]; // @[Parameters.scala:52:{29,56}]
wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_16 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_23 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7]
wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_19 = _source_ok_T_17; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_20 = source_ok_uncommonBits_2 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_21 = _source_ok_T_19 & _source_ok_T_20; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_21; // @[Parameters.scala:1138:31]
wire _source_ok_T_22 = io_in_d_bits_source_0 == 5'h19; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_1 = _source_ok_T_22; // @[Parameters.scala:1138:31]
wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_24 = ~_source_ok_T_23; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_26 = _source_ok_T_24; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_27 = source_ok_uncommonBits_3 < 4'h9; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_28 = _source_ok_T_26 & _source_ok_T_27; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_2 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_d_bits_source_0 == 5'h9; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_3 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_31 = _source_ok_T_30 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_31 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _T_831 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_831; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_831; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_899 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_899; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_899; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_899; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [25:0] inflight; // @[Monitor.scala:614:27]
reg [103:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [103:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [25:0] a_set; // @[Monitor.scala:626:34]
wire [25:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [103:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [103:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [103:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [103:0] _a_opcode_lookup_T_6 = {100'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [103:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [103:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [103:0] _a_size_lookup_T_6 = {100'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [103:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[103:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire _T_764 = _T_831 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_764 ? _a_set_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_764 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_764 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_764 ? _a_opcodes_set_T_1[103:0] : 104'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_764 ? _a_sizes_set_T_1[103:0] : 104'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [25:0] d_clr; // @[Monitor.scala:664:34]
wire [25:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [103:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [103:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_810 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_810 & ~d_release_ack ? _d_clr_wo_ready_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire _T_779 = _T_899 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_779 ? _d_clr_T[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_779 ? _d_opcodes_clr_T_5[103:0] : 104'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_779 ? _d_sizes_clr_T_5[103:0] : 104'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [25:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [25:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [25:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [103:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [103:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [103:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [103:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [103:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [103:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [25:0] inflight_1; // @[Monitor.scala:726:35]
wire [25:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [103:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [103:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [103:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [103:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [103:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [103:0] _c_opcode_lookup_T_6 = {100'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [103:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[103:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [103:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [103:0] _c_size_lookup_T_6 = {100'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [103:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[103:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [25:0] d_clr_1; // @[Monitor.scala:774:34]
wire [25:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [103:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [103:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_875 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_875 & d_release_ack_1 ? _d_clr_wo_ready_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire _T_857 = _T_899 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_857 ? _d_clr_T_1[25:0] : 26'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_857 ? _d_opcodes_clr_T_11[103:0] : 104'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_857 ? _d_sizes_clr_T_11[103:0] : 104'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [25:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [25:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [103:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [103:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [103:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [103:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module MacUnit_187( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
|
module BranchKillableQueue_14( // @[util.scala:448:7]
input clock, // @[util.scala:448:7]
input reset, // @[util.scala:448:7]
output io_enq_ready, // @[util.scala:453:14]
input io_enq_valid, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:453:14]
input [33:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14]
input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
input io_enq_bits_uop_is_br, // @[util.scala:453:14]
input io_enq_bits_uop_is_jalr, // @[util.scala:453:14]
input io_enq_bits_uop_is_jal, // @[util.scala:453:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14]
input io_enq_bits_uop_taken, // @[util.scala:453:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14]
input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14]
input [3:0] io_enq_bits_uop_ppred, // @[util.scala:453:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14]
input io_enq_bits_uop_exception, // @[util.scala:453:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14]
input io_enq_bits_uop_bypassable, // @[util.scala:453:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:453:14]
input io_enq_bits_uop_is_fence, // @[util.scala:453:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:453:14]
input io_enq_bits_uop_is_amo, // @[util.scala:453:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:453:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
input io_enq_bits_uop_is_unique, // @[util.scala:453:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14]
input io_enq_bits_uop_ldst_val, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:453:14]
input io_enq_bits_uop_fp_val, // @[util.scala:453:14]
input io_enq_bits_uop_fp_single, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14]
input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14]
input [33:0] io_enq_bits_addr, // @[util.scala:453:14]
input [63:0] io_enq_bits_data, // @[util.scala:453:14]
input io_enq_bits_is_hella, // @[util.scala:453:14]
input io_enq_bits_tag_match, // @[util.scala:453:14]
input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14]
input [21:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14]
input [1:0] io_enq_bits_way_en, // @[util.scala:453:14]
input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14]
input io_deq_ready, // @[util.scala:453:14]
output io_deq_valid, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:453:14]
output [33:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14]
output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14]
output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14]
output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14]
output io_deq_bits_uop_is_br, // @[util.scala:453:14]
output io_deq_bits_uop_is_jalr, // @[util.scala:453:14]
output io_deq_bits_uop_is_jal, // @[util.scala:453:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14]
output io_deq_bits_uop_taken, // @[util.scala:453:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14]
output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14]
output [3:0] io_deq_bits_uop_ppred, // @[util.scala:453:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14]
output io_deq_bits_uop_exception, // @[util.scala:453:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14]
output io_deq_bits_uop_bypassable, // @[util.scala:453:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:453:14]
output io_deq_bits_uop_is_fence, // @[util.scala:453:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:453:14]
output io_deq_bits_uop_is_amo, // @[util.scala:453:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:453:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14]
output io_deq_bits_uop_is_unique, // @[util.scala:453:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14]
output io_deq_bits_uop_ldst_val, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:453:14]
output io_deq_bits_uop_fp_val, // @[util.scala:453:14]
output io_deq_bits_uop_fp_single, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14]
output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14]
output [33:0] io_deq_bits_addr, // @[util.scala:453:14]
output [63:0] io_deq_bits_data, // @[util.scala:453:14]
output io_deq_bits_is_hella, // @[util.scala:453:14]
output io_deq_bits_tag_match, // @[util.scala:453:14]
output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14]
output [21:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14]
output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14]
output io_empty // @[util.scala:453:14]
);
wire [3:0] out_uop_br_mask; // @[util.scala:506:17]
wire [130:0] _ram_ext_R0_data; // @[util.scala:464:20]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7]
wire [33:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7]
wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7]
wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7]
wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7]
wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7]
wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7]
wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7]
wire [3:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7]
wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7]
wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7]
wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7]
wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7]
wire [33:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7]
wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7]
wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7]
wire [21:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7]
wire [1:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7]
wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7]
wire _valids_0_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_0_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_1_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_1_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_2_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_2_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_3_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_3_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_4_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_4_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_5_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_5_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_6_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_6_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_7_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_7_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_8_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_8_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_9_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_9_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_10_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_10_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_11_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_11_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_12_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_12_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_13_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_13_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_14_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_14_T_5 = 1'h1; // @[util.scala:481:72]
wire _valids_15_T_2 = 1'h1; // @[util.scala:481:32]
wire _valids_15_T_5 = 1'h1; // @[util.scala:481:72]
wire _io_deq_valid_T_4 = 1'h1; // @[util.scala:509:68]
wire _io_deq_valid_T_7 = 1'h1; // @[util.scala:509:111]
wire [3:0] _uops_0_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_1_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_2_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_3_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_4_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_5_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_6_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_7_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_8_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_9_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_10_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_11_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_12_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_13_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_14_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_15_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _uops_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [3:0] _io_deq_bits_uop_br_mask_T = 4'hF; // @[util.scala:85:27, :89:23]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[util.scala:448:7, :453:14]
wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[util.scala:448:7, :453:14]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[util.scala:448:7, :453:14]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[util.scala:448:7, :453:14]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[util.scala:448:7, :453:14]
wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[util.scala:448:7, :453:14]
wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[util.scala:448:7, :453:14]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[util.scala:448:7, :453:14]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[util.scala:448:7, :453:14]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[util.scala:448:7, :453:14]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_br = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_jal = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bypassable = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_fp_single = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_valid = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[util.scala:448:7]
wire io_brupdate_b2_taken = 1'h0; // @[util.scala:448:7]
wire io_flush = 1'h0; // @[util.scala:448:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32]
wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32]
wire _valids_0_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_0_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_1_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_1_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_2_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_2_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_3_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_3_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_4_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_4_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_5_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_5_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_6_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_6_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_7_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_7_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_8_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_8_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_9_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_9_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_10_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_10_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_11_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_11_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_12_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_12_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_13_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_13_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_14_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_14_T_4 = 1'h0; // @[util.scala:481:83]
wire _valids_15_T_1 = 1'h0; // @[util.scala:118:59]
wire _valids_15_T_4 = 1'h0; // @[util.scala:481:83]
wire _io_deq_valid_T_3 = 1'h0; // @[util.scala:118:59]
wire _io_deq_valid_T_6 = 1'h0; // @[util.scala:509:122]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[util.scala:448:7, :453:14]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[util.scala:448:7, :453:14]
wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[util.scala:448:7, :453:14]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[util.scala:448:7]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[util.scala:448:7]
wire [3:0] _valids_0_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_1_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_2_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_3_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_4_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_5_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_6_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_7_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_8_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_9_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_10_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_11_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_12_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_13_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_14_T = 4'h0; // @[util.scala:118:51]
wire [3:0] _valids_15_T = 4'h0; // @[util.scala:118:51]
wire _io_enq_ready_T; // @[util.scala:504:19]
wire [3:0] _io_deq_valid_T_2 = 4'h0; // @[util.scala:118:51]
wire [3:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0; // @[util.scala:85:25, :448:7]
wire _io_deq_valid_T_8; // @[util.scala:509:108]
wire [6:0] out_uop_uopc; // @[util.scala:506:17]
wire [31:0] out_uop_inst; // @[util.scala:506:17]
wire [31:0] out_uop_debug_inst; // @[util.scala:506:17]
wire out_uop_is_rvc; // @[util.scala:506:17]
wire [33:0] out_uop_debug_pc; // @[util.scala:506:17]
wire [2:0] out_uop_iq_type; // @[util.scala:506:17]
wire [9:0] out_uop_fu_code; // @[util.scala:506:17]
wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17]
wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17]
wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17]
wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17]
wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17]
wire out_uop_ctrl_is_load; // @[util.scala:506:17]
wire out_uop_ctrl_is_sta; // @[util.scala:506:17]
wire out_uop_ctrl_is_std; // @[util.scala:506:17]
wire [1:0] out_uop_iw_state; // @[util.scala:506:17]
wire out_uop_iw_p1_poisoned; // @[util.scala:506:17]
wire out_uop_iw_p2_poisoned; // @[util.scala:506:17]
wire out_uop_is_br; // @[util.scala:506:17]
wire out_uop_is_jalr; // @[util.scala:506:17]
wire out_uop_is_jal; // @[util.scala:506:17]
wire out_uop_is_sfb; // @[util.scala:506:17]
wire [3:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [1:0] out_uop_br_tag; // @[util.scala:506:17]
wire [3:0] out_uop_ftq_idx; // @[util.scala:506:17]
wire out_uop_edge_inst; // @[util.scala:506:17]
wire [5:0] out_uop_pc_lob; // @[util.scala:506:17]
wire out_uop_taken; // @[util.scala:506:17]
wire [19:0] out_uop_imm_packed; // @[util.scala:506:17]
wire [11:0] out_uop_csr_addr; // @[util.scala:506:17]
wire [5:0] out_uop_rob_idx; // @[util.scala:506:17]
wire [3:0] out_uop_ldq_idx; // @[util.scala:506:17]
wire [3:0] out_uop_stq_idx; // @[util.scala:506:17]
wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17]
wire [6:0] out_uop_pdst; // @[util.scala:506:17]
wire [6:0] out_uop_prs1; // @[util.scala:506:17]
wire [6:0] out_uop_prs2; // @[util.scala:506:17]
wire [6:0] out_uop_prs3; // @[util.scala:506:17]
wire [3:0] out_uop_ppred; // @[util.scala:506:17]
wire out_uop_prs1_busy; // @[util.scala:506:17]
wire out_uop_prs2_busy; // @[util.scala:506:17]
wire out_uop_prs3_busy; // @[util.scala:506:17]
wire out_uop_ppred_busy; // @[util.scala:506:17]
wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17]
wire out_uop_exception; // @[util.scala:506:17]
wire [63:0] out_uop_exc_cause; // @[util.scala:506:17]
wire out_uop_bypassable; // @[util.scala:506:17]
wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17]
wire [1:0] out_uop_mem_size; // @[util.scala:506:17]
wire out_uop_mem_signed; // @[util.scala:506:17]
wire out_uop_is_fence; // @[util.scala:506:17]
wire out_uop_is_fencei; // @[util.scala:506:17]
wire out_uop_is_amo; // @[util.scala:506:17]
wire out_uop_uses_ldq; // @[util.scala:506:17]
wire out_uop_uses_stq; // @[util.scala:506:17]
wire out_uop_is_sys_pc2epc; // @[util.scala:506:17]
wire out_uop_is_unique; // @[util.scala:506:17]
wire out_uop_flush_on_commit; // @[util.scala:506:17]
wire out_uop_ldst_is_rs1; // @[util.scala:506:17]
wire [5:0] out_uop_ldst; // @[util.scala:506:17]
wire [5:0] out_uop_lrs1; // @[util.scala:506:17]
wire [5:0] out_uop_lrs2; // @[util.scala:506:17]
wire [5:0] out_uop_lrs3; // @[util.scala:506:17]
wire out_uop_ldst_val; // @[util.scala:506:17]
wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17]
wire out_uop_frs3_en; // @[util.scala:506:17]
wire out_uop_fp_val; // @[util.scala:506:17]
wire out_uop_fp_single; // @[util.scala:506:17]
wire out_uop_xcpt_pf_if; // @[util.scala:506:17]
wire out_uop_xcpt_ae_if; // @[util.scala:506:17]
wire out_uop_xcpt_ma_if; // @[util.scala:506:17]
wire out_uop_bp_debug_if; // @[util.scala:506:17]
wire out_uop_bp_xcpt_if; // @[util.scala:506:17]
wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17]
wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17]
wire [33:0] out_addr; // @[util.scala:506:17]
wire [63:0] out_data; // @[util.scala:506:17]
wire out_is_hella; // @[util.scala:506:17]
wire out_tag_match; // @[util.scala:506:17]
wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17]
wire [21:0] out_old_meta_tag; // @[util.scala:506:17]
wire [1:0] out_way_en; // @[util.scala:506:17]
wire [4:0] out_sdq_id; // @[util.scala:506:17]
wire _io_empty_T_1; // @[util.scala:473:25]
wire io_enq_ready_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
wire [33:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:448:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
wire [3:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7]
wire [21:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7]
wire [33:0] io_deq_bits_addr_0; // @[util.scala:448:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7]
wire io_deq_bits_is_hella_0; // @[util.scala:448:7]
wire io_deq_bits_tag_match_0; // @[util.scala:448:7]
wire [1:0] io_deq_bits_way_en; // @[util.scala:448:7]
wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7]
wire io_deq_valid_0; // @[util.scala:448:7]
wire io_empty_0; // @[util.scala:448:7]
wire [3:0] io_count; // @[util.scala:448:7]
assign out_addr = _ram_ext_R0_data[33:0]; // @[util.scala:464:20, :506:17]
assign out_data = _ram_ext_R0_data[97:34]; // @[util.scala:464:20, :506:17]
assign out_is_hella = _ram_ext_R0_data[98]; // @[util.scala:464:20, :506:17]
assign out_tag_match = _ram_ext_R0_data[99]; // @[util.scala:464:20, :506:17]
assign out_old_meta_coh_state = _ram_ext_R0_data[101:100]; // @[util.scala:464:20, :506:17]
assign out_old_meta_tag = _ram_ext_R0_data[123:102]; // @[util.scala:464:20, :506:17]
assign out_way_en = _ram_ext_R0_data[125:124]; // @[util.scala:464:20, :506:17]
assign out_sdq_id = _ram_ext_R0_data[130:126]; // @[util.scala:464:20, :506:17]
reg valids_0; // @[util.scala:465:24]
wire _valids_0_T_3 = valids_0; // @[util.scala:465:24, :481:29]
reg valids_1; // @[util.scala:465:24]
wire _valids_1_T_3 = valids_1; // @[util.scala:465:24, :481:29]
reg valids_2; // @[util.scala:465:24]
wire _valids_2_T_3 = valids_2; // @[util.scala:465:24, :481:29]
reg valids_3; // @[util.scala:465:24]
wire _valids_3_T_3 = valids_3; // @[util.scala:465:24, :481:29]
reg valids_4; // @[util.scala:465:24]
wire _valids_4_T_3 = valids_4; // @[util.scala:465:24, :481:29]
reg valids_5; // @[util.scala:465:24]
wire _valids_5_T_3 = valids_5; // @[util.scala:465:24, :481:29]
reg valids_6; // @[util.scala:465:24]
wire _valids_6_T_3 = valids_6; // @[util.scala:465:24, :481:29]
reg valids_7; // @[util.scala:465:24]
wire _valids_7_T_3 = valids_7; // @[util.scala:465:24, :481:29]
reg valids_8; // @[util.scala:465:24]
wire _valids_8_T_3 = valids_8; // @[util.scala:465:24, :481:29]
reg valids_9; // @[util.scala:465:24]
wire _valids_9_T_3 = valids_9; // @[util.scala:465:24, :481:29]
reg valids_10; // @[util.scala:465:24]
wire _valids_10_T_3 = valids_10; // @[util.scala:465:24, :481:29]
reg valids_11; // @[util.scala:465:24]
wire _valids_11_T_3 = valids_11; // @[util.scala:465:24, :481:29]
reg valids_12; // @[util.scala:465:24]
wire _valids_12_T_3 = valids_12; // @[util.scala:465:24, :481:29]
reg valids_13; // @[util.scala:465:24]
wire _valids_13_T_3 = valids_13; // @[util.scala:465:24, :481:29]
reg valids_14; // @[util.scala:465:24]
wire _valids_14_T_3 = valids_14; // @[util.scala:465:24, :481:29]
reg valids_15; // @[util.scala:465:24]
wire _valids_15_T_3 = valids_15; // @[util.scala:465:24, :481:29]
reg [6:0] uops_0_uopc; // @[util.scala:466:20]
reg [31:0] uops_0_inst; // @[util.scala:466:20]
reg [31:0] uops_0_debug_inst; // @[util.scala:466:20]
reg uops_0_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_0_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_0_iq_type; // @[util.scala:466:20]
reg [9:0] uops_0_fu_code; // @[util.scala:466:20]
reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_0_ctrl_is_load; // @[util.scala:466:20]
reg uops_0_ctrl_is_sta; // @[util.scala:466:20]
reg uops_0_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_0_iw_state; // @[util.scala:466:20]
reg uops_0_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_0_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_0_is_br; // @[util.scala:466:20]
reg uops_0_is_jalr; // @[util.scala:466:20]
reg uops_0_is_jal; // @[util.scala:466:20]
reg uops_0_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_0_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_0_br_mask_T_1 = uops_0_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_0_br_tag; // @[util.scala:466:20]
reg [3:0] uops_0_ftq_idx; // @[util.scala:466:20]
reg uops_0_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_0_pc_lob; // @[util.scala:466:20]
reg uops_0_taken; // @[util.scala:466:20]
reg [19:0] uops_0_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_0_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_0_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_0_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_0_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_0_pdst; // @[util.scala:466:20]
reg [6:0] uops_0_prs1; // @[util.scala:466:20]
reg [6:0] uops_0_prs2; // @[util.scala:466:20]
reg [6:0] uops_0_prs3; // @[util.scala:466:20]
reg [3:0] uops_0_ppred; // @[util.scala:466:20]
reg uops_0_prs1_busy; // @[util.scala:466:20]
reg uops_0_prs2_busy; // @[util.scala:466:20]
reg uops_0_prs3_busy; // @[util.scala:466:20]
reg uops_0_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20]
reg uops_0_exception; // @[util.scala:466:20]
reg [63:0] uops_0_exc_cause; // @[util.scala:466:20]
reg uops_0_bypassable; // @[util.scala:466:20]
reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_0_mem_size; // @[util.scala:466:20]
reg uops_0_mem_signed; // @[util.scala:466:20]
reg uops_0_is_fence; // @[util.scala:466:20]
reg uops_0_is_fencei; // @[util.scala:466:20]
reg uops_0_is_amo; // @[util.scala:466:20]
reg uops_0_uses_ldq; // @[util.scala:466:20]
reg uops_0_uses_stq; // @[util.scala:466:20]
reg uops_0_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_0_is_unique; // @[util.scala:466:20]
reg uops_0_flush_on_commit; // @[util.scala:466:20]
reg uops_0_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_0_ldst; // @[util.scala:466:20]
reg [5:0] uops_0_lrs1; // @[util.scala:466:20]
reg [5:0] uops_0_lrs2; // @[util.scala:466:20]
reg [5:0] uops_0_lrs3; // @[util.scala:466:20]
reg uops_0_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20]
reg uops_0_frs3_en; // @[util.scala:466:20]
reg uops_0_fp_val; // @[util.scala:466:20]
reg uops_0_fp_single; // @[util.scala:466:20]
reg uops_0_xcpt_pf_if; // @[util.scala:466:20]
reg uops_0_xcpt_ae_if; // @[util.scala:466:20]
reg uops_0_xcpt_ma_if; // @[util.scala:466:20]
reg uops_0_bp_debug_if; // @[util.scala:466:20]
reg uops_0_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_1_uopc; // @[util.scala:466:20]
reg [31:0] uops_1_inst; // @[util.scala:466:20]
reg [31:0] uops_1_debug_inst; // @[util.scala:466:20]
reg uops_1_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_1_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_1_iq_type; // @[util.scala:466:20]
reg [9:0] uops_1_fu_code; // @[util.scala:466:20]
reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_1_ctrl_is_load; // @[util.scala:466:20]
reg uops_1_ctrl_is_sta; // @[util.scala:466:20]
reg uops_1_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_1_iw_state; // @[util.scala:466:20]
reg uops_1_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_1_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_1_is_br; // @[util.scala:466:20]
reg uops_1_is_jalr; // @[util.scala:466:20]
reg uops_1_is_jal; // @[util.scala:466:20]
reg uops_1_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_1_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_1_br_mask_T_1 = uops_1_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_1_br_tag; // @[util.scala:466:20]
reg [3:0] uops_1_ftq_idx; // @[util.scala:466:20]
reg uops_1_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_1_pc_lob; // @[util.scala:466:20]
reg uops_1_taken; // @[util.scala:466:20]
reg [19:0] uops_1_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_1_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_1_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_1_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_1_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_1_pdst; // @[util.scala:466:20]
reg [6:0] uops_1_prs1; // @[util.scala:466:20]
reg [6:0] uops_1_prs2; // @[util.scala:466:20]
reg [6:0] uops_1_prs3; // @[util.scala:466:20]
reg [3:0] uops_1_ppred; // @[util.scala:466:20]
reg uops_1_prs1_busy; // @[util.scala:466:20]
reg uops_1_prs2_busy; // @[util.scala:466:20]
reg uops_1_prs3_busy; // @[util.scala:466:20]
reg uops_1_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20]
reg uops_1_exception; // @[util.scala:466:20]
reg [63:0] uops_1_exc_cause; // @[util.scala:466:20]
reg uops_1_bypassable; // @[util.scala:466:20]
reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_1_mem_size; // @[util.scala:466:20]
reg uops_1_mem_signed; // @[util.scala:466:20]
reg uops_1_is_fence; // @[util.scala:466:20]
reg uops_1_is_fencei; // @[util.scala:466:20]
reg uops_1_is_amo; // @[util.scala:466:20]
reg uops_1_uses_ldq; // @[util.scala:466:20]
reg uops_1_uses_stq; // @[util.scala:466:20]
reg uops_1_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_1_is_unique; // @[util.scala:466:20]
reg uops_1_flush_on_commit; // @[util.scala:466:20]
reg uops_1_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_1_ldst; // @[util.scala:466:20]
reg [5:0] uops_1_lrs1; // @[util.scala:466:20]
reg [5:0] uops_1_lrs2; // @[util.scala:466:20]
reg [5:0] uops_1_lrs3; // @[util.scala:466:20]
reg uops_1_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20]
reg uops_1_frs3_en; // @[util.scala:466:20]
reg uops_1_fp_val; // @[util.scala:466:20]
reg uops_1_fp_single; // @[util.scala:466:20]
reg uops_1_xcpt_pf_if; // @[util.scala:466:20]
reg uops_1_xcpt_ae_if; // @[util.scala:466:20]
reg uops_1_xcpt_ma_if; // @[util.scala:466:20]
reg uops_1_bp_debug_if; // @[util.scala:466:20]
reg uops_1_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_2_uopc; // @[util.scala:466:20]
reg [31:0] uops_2_inst; // @[util.scala:466:20]
reg [31:0] uops_2_debug_inst; // @[util.scala:466:20]
reg uops_2_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_2_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_2_iq_type; // @[util.scala:466:20]
reg [9:0] uops_2_fu_code; // @[util.scala:466:20]
reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_2_ctrl_is_load; // @[util.scala:466:20]
reg uops_2_ctrl_is_sta; // @[util.scala:466:20]
reg uops_2_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_2_iw_state; // @[util.scala:466:20]
reg uops_2_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_2_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_2_is_br; // @[util.scala:466:20]
reg uops_2_is_jalr; // @[util.scala:466:20]
reg uops_2_is_jal; // @[util.scala:466:20]
reg uops_2_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_2_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_2_br_mask_T_1 = uops_2_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_2_br_tag; // @[util.scala:466:20]
reg [3:0] uops_2_ftq_idx; // @[util.scala:466:20]
reg uops_2_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_2_pc_lob; // @[util.scala:466:20]
reg uops_2_taken; // @[util.scala:466:20]
reg [19:0] uops_2_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_2_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_2_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_2_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_2_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_2_pdst; // @[util.scala:466:20]
reg [6:0] uops_2_prs1; // @[util.scala:466:20]
reg [6:0] uops_2_prs2; // @[util.scala:466:20]
reg [6:0] uops_2_prs3; // @[util.scala:466:20]
reg [3:0] uops_2_ppred; // @[util.scala:466:20]
reg uops_2_prs1_busy; // @[util.scala:466:20]
reg uops_2_prs2_busy; // @[util.scala:466:20]
reg uops_2_prs3_busy; // @[util.scala:466:20]
reg uops_2_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20]
reg uops_2_exception; // @[util.scala:466:20]
reg [63:0] uops_2_exc_cause; // @[util.scala:466:20]
reg uops_2_bypassable; // @[util.scala:466:20]
reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_2_mem_size; // @[util.scala:466:20]
reg uops_2_mem_signed; // @[util.scala:466:20]
reg uops_2_is_fence; // @[util.scala:466:20]
reg uops_2_is_fencei; // @[util.scala:466:20]
reg uops_2_is_amo; // @[util.scala:466:20]
reg uops_2_uses_ldq; // @[util.scala:466:20]
reg uops_2_uses_stq; // @[util.scala:466:20]
reg uops_2_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_2_is_unique; // @[util.scala:466:20]
reg uops_2_flush_on_commit; // @[util.scala:466:20]
reg uops_2_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_2_ldst; // @[util.scala:466:20]
reg [5:0] uops_2_lrs1; // @[util.scala:466:20]
reg [5:0] uops_2_lrs2; // @[util.scala:466:20]
reg [5:0] uops_2_lrs3; // @[util.scala:466:20]
reg uops_2_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20]
reg uops_2_frs3_en; // @[util.scala:466:20]
reg uops_2_fp_val; // @[util.scala:466:20]
reg uops_2_fp_single; // @[util.scala:466:20]
reg uops_2_xcpt_pf_if; // @[util.scala:466:20]
reg uops_2_xcpt_ae_if; // @[util.scala:466:20]
reg uops_2_xcpt_ma_if; // @[util.scala:466:20]
reg uops_2_bp_debug_if; // @[util.scala:466:20]
reg uops_2_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_3_uopc; // @[util.scala:466:20]
reg [31:0] uops_3_inst; // @[util.scala:466:20]
reg [31:0] uops_3_debug_inst; // @[util.scala:466:20]
reg uops_3_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_3_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_3_iq_type; // @[util.scala:466:20]
reg [9:0] uops_3_fu_code; // @[util.scala:466:20]
reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_3_ctrl_is_load; // @[util.scala:466:20]
reg uops_3_ctrl_is_sta; // @[util.scala:466:20]
reg uops_3_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_3_iw_state; // @[util.scala:466:20]
reg uops_3_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_3_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_3_is_br; // @[util.scala:466:20]
reg uops_3_is_jalr; // @[util.scala:466:20]
reg uops_3_is_jal; // @[util.scala:466:20]
reg uops_3_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_3_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_3_br_mask_T_1 = uops_3_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_3_br_tag; // @[util.scala:466:20]
reg [3:0] uops_3_ftq_idx; // @[util.scala:466:20]
reg uops_3_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_3_pc_lob; // @[util.scala:466:20]
reg uops_3_taken; // @[util.scala:466:20]
reg [19:0] uops_3_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_3_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_3_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_3_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_3_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_3_pdst; // @[util.scala:466:20]
reg [6:0] uops_3_prs1; // @[util.scala:466:20]
reg [6:0] uops_3_prs2; // @[util.scala:466:20]
reg [6:0] uops_3_prs3; // @[util.scala:466:20]
reg [3:0] uops_3_ppred; // @[util.scala:466:20]
reg uops_3_prs1_busy; // @[util.scala:466:20]
reg uops_3_prs2_busy; // @[util.scala:466:20]
reg uops_3_prs3_busy; // @[util.scala:466:20]
reg uops_3_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20]
reg uops_3_exception; // @[util.scala:466:20]
reg [63:0] uops_3_exc_cause; // @[util.scala:466:20]
reg uops_3_bypassable; // @[util.scala:466:20]
reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_3_mem_size; // @[util.scala:466:20]
reg uops_3_mem_signed; // @[util.scala:466:20]
reg uops_3_is_fence; // @[util.scala:466:20]
reg uops_3_is_fencei; // @[util.scala:466:20]
reg uops_3_is_amo; // @[util.scala:466:20]
reg uops_3_uses_ldq; // @[util.scala:466:20]
reg uops_3_uses_stq; // @[util.scala:466:20]
reg uops_3_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_3_is_unique; // @[util.scala:466:20]
reg uops_3_flush_on_commit; // @[util.scala:466:20]
reg uops_3_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_3_ldst; // @[util.scala:466:20]
reg [5:0] uops_3_lrs1; // @[util.scala:466:20]
reg [5:0] uops_3_lrs2; // @[util.scala:466:20]
reg [5:0] uops_3_lrs3; // @[util.scala:466:20]
reg uops_3_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20]
reg uops_3_frs3_en; // @[util.scala:466:20]
reg uops_3_fp_val; // @[util.scala:466:20]
reg uops_3_fp_single; // @[util.scala:466:20]
reg uops_3_xcpt_pf_if; // @[util.scala:466:20]
reg uops_3_xcpt_ae_if; // @[util.scala:466:20]
reg uops_3_xcpt_ma_if; // @[util.scala:466:20]
reg uops_3_bp_debug_if; // @[util.scala:466:20]
reg uops_3_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_4_uopc; // @[util.scala:466:20]
reg [31:0] uops_4_inst; // @[util.scala:466:20]
reg [31:0] uops_4_debug_inst; // @[util.scala:466:20]
reg uops_4_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_4_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_4_iq_type; // @[util.scala:466:20]
reg [9:0] uops_4_fu_code; // @[util.scala:466:20]
reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_4_ctrl_is_load; // @[util.scala:466:20]
reg uops_4_ctrl_is_sta; // @[util.scala:466:20]
reg uops_4_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_4_iw_state; // @[util.scala:466:20]
reg uops_4_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_4_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_4_is_br; // @[util.scala:466:20]
reg uops_4_is_jalr; // @[util.scala:466:20]
reg uops_4_is_jal; // @[util.scala:466:20]
reg uops_4_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_4_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_4_br_mask_T_1 = uops_4_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_4_br_tag; // @[util.scala:466:20]
reg [3:0] uops_4_ftq_idx; // @[util.scala:466:20]
reg uops_4_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_4_pc_lob; // @[util.scala:466:20]
reg uops_4_taken; // @[util.scala:466:20]
reg [19:0] uops_4_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_4_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_4_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_4_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_4_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_4_pdst; // @[util.scala:466:20]
reg [6:0] uops_4_prs1; // @[util.scala:466:20]
reg [6:0] uops_4_prs2; // @[util.scala:466:20]
reg [6:0] uops_4_prs3; // @[util.scala:466:20]
reg [3:0] uops_4_ppred; // @[util.scala:466:20]
reg uops_4_prs1_busy; // @[util.scala:466:20]
reg uops_4_prs2_busy; // @[util.scala:466:20]
reg uops_4_prs3_busy; // @[util.scala:466:20]
reg uops_4_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20]
reg uops_4_exception; // @[util.scala:466:20]
reg [63:0] uops_4_exc_cause; // @[util.scala:466:20]
reg uops_4_bypassable; // @[util.scala:466:20]
reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_4_mem_size; // @[util.scala:466:20]
reg uops_4_mem_signed; // @[util.scala:466:20]
reg uops_4_is_fence; // @[util.scala:466:20]
reg uops_4_is_fencei; // @[util.scala:466:20]
reg uops_4_is_amo; // @[util.scala:466:20]
reg uops_4_uses_ldq; // @[util.scala:466:20]
reg uops_4_uses_stq; // @[util.scala:466:20]
reg uops_4_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_4_is_unique; // @[util.scala:466:20]
reg uops_4_flush_on_commit; // @[util.scala:466:20]
reg uops_4_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_4_ldst; // @[util.scala:466:20]
reg [5:0] uops_4_lrs1; // @[util.scala:466:20]
reg [5:0] uops_4_lrs2; // @[util.scala:466:20]
reg [5:0] uops_4_lrs3; // @[util.scala:466:20]
reg uops_4_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20]
reg uops_4_frs3_en; // @[util.scala:466:20]
reg uops_4_fp_val; // @[util.scala:466:20]
reg uops_4_fp_single; // @[util.scala:466:20]
reg uops_4_xcpt_pf_if; // @[util.scala:466:20]
reg uops_4_xcpt_ae_if; // @[util.scala:466:20]
reg uops_4_xcpt_ma_if; // @[util.scala:466:20]
reg uops_4_bp_debug_if; // @[util.scala:466:20]
reg uops_4_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_5_uopc; // @[util.scala:466:20]
reg [31:0] uops_5_inst; // @[util.scala:466:20]
reg [31:0] uops_5_debug_inst; // @[util.scala:466:20]
reg uops_5_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_5_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_5_iq_type; // @[util.scala:466:20]
reg [9:0] uops_5_fu_code; // @[util.scala:466:20]
reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_5_ctrl_is_load; // @[util.scala:466:20]
reg uops_5_ctrl_is_sta; // @[util.scala:466:20]
reg uops_5_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_5_iw_state; // @[util.scala:466:20]
reg uops_5_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_5_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_5_is_br; // @[util.scala:466:20]
reg uops_5_is_jalr; // @[util.scala:466:20]
reg uops_5_is_jal; // @[util.scala:466:20]
reg uops_5_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_5_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_5_br_mask_T_1 = uops_5_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_5_br_tag; // @[util.scala:466:20]
reg [3:0] uops_5_ftq_idx; // @[util.scala:466:20]
reg uops_5_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_5_pc_lob; // @[util.scala:466:20]
reg uops_5_taken; // @[util.scala:466:20]
reg [19:0] uops_5_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_5_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_5_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_5_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_5_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_5_pdst; // @[util.scala:466:20]
reg [6:0] uops_5_prs1; // @[util.scala:466:20]
reg [6:0] uops_5_prs2; // @[util.scala:466:20]
reg [6:0] uops_5_prs3; // @[util.scala:466:20]
reg [3:0] uops_5_ppred; // @[util.scala:466:20]
reg uops_5_prs1_busy; // @[util.scala:466:20]
reg uops_5_prs2_busy; // @[util.scala:466:20]
reg uops_5_prs3_busy; // @[util.scala:466:20]
reg uops_5_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20]
reg uops_5_exception; // @[util.scala:466:20]
reg [63:0] uops_5_exc_cause; // @[util.scala:466:20]
reg uops_5_bypassable; // @[util.scala:466:20]
reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_5_mem_size; // @[util.scala:466:20]
reg uops_5_mem_signed; // @[util.scala:466:20]
reg uops_5_is_fence; // @[util.scala:466:20]
reg uops_5_is_fencei; // @[util.scala:466:20]
reg uops_5_is_amo; // @[util.scala:466:20]
reg uops_5_uses_ldq; // @[util.scala:466:20]
reg uops_5_uses_stq; // @[util.scala:466:20]
reg uops_5_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_5_is_unique; // @[util.scala:466:20]
reg uops_5_flush_on_commit; // @[util.scala:466:20]
reg uops_5_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_5_ldst; // @[util.scala:466:20]
reg [5:0] uops_5_lrs1; // @[util.scala:466:20]
reg [5:0] uops_5_lrs2; // @[util.scala:466:20]
reg [5:0] uops_5_lrs3; // @[util.scala:466:20]
reg uops_5_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20]
reg uops_5_frs3_en; // @[util.scala:466:20]
reg uops_5_fp_val; // @[util.scala:466:20]
reg uops_5_fp_single; // @[util.scala:466:20]
reg uops_5_xcpt_pf_if; // @[util.scala:466:20]
reg uops_5_xcpt_ae_if; // @[util.scala:466:20]
reg uops_5_xcpt_ma_if; // @[util.scala:466:20]
reg uops_5_bp_debug_if; // @[util.scala:466:20]
reg uops_5_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_6_uopc; // @[util.scala:466:20]
reg [31:0] uops_6_inst; // @[util.scala:466:20]
reg [31:0] uops_6_debug_inst; // @[util.scala:466:20]
reg uops_6_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_6_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_6_iq_type; // @[util.scala:466:20]
reg [9:0] uops_6_fu_code; // @[util.scala:466:20]
reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_6_ctrl_is_load; // @[util.scala:466:20]
reg uops_6_ctrl_is_sta; // @[util.scala:466:20]
reg uops_6_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_6_iw_state; // @[util.scala:466:20]
reg uops_6_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_6_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_6_is_br; // @[util.scala:466:20]
reg uops_6_is_jalr; // @[util.scala:466:20]
reg uops_6_is_jal; // @[util.scala:466:20]
reg uops_6_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_6_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_6_br_mask_T_1 = uops_6_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_6_br_tag; // @[util.scala:466:20]
reg [3:0] uops_6_ftq_idx; // @[util.scala:466:20]
reg uops_6_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_6_pc_lob; // @[util.scala:466:20]
reg uops_6_taken; // @[util.scala:466:20]
reg [19:0] uops_6_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_6_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_6_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_6_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_6_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_6_pdst; // @[util.scala:466:20]
reg [6:0] uops_6_prs1; // @[util.scala:466:20]
reg [6:0] uops_6_prs2; // @[util.scala:466:20]
reg [6:0] uops_6_prs3; // @[util.scala:466:20]
reg [3:0] uops_6_ppred; // @[util.scala:466:20]
reg uops_6_prs1_busy; // @[util.scala:466:20]
reg uops_6_prs2_busy; // @[util.scala:466:20]
reg uops_6_prs3_busy; // @[util.scala:466:20]
reg uops_6_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20]
reg uops_6_exception; // @[util.scala:466:20]
reg [63:0] uops_6_exc_cause; // @[util.scala:466:20]
reg uops_6_bypassable; // @[util.scala:466:20]
reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_6_mem_size; // @[util.scala:466:20]
reg uops_6_mem_signed; // @[util.scala:466:20]
reg uops_6_is_fence; // @[util.scala:466:20]
reg uops_6_is_fencei; // @[util.scala:466:20]
reg uops_6_is_amo; // @[util.scala:466:20]
reg uops_6_uses_ldq; // @[util.scala:466:20]
reg uops_6_uses_stq; // @[util.scala:466:20]
reg uops_6_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_6_is_unique; // @[util.scala:466:20]
reg uops_6_flush_on_commit; // @[util.scala:466:20]
reg uops_6_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_6_ldst; // @[util.scala:466:20]
reg [5:0] uops_6_lrs1; // @[util.scala:466:20]
reg [5:0] uops_6_lrs2; // @[util.scala:466:20]
reg [5:0] uops_6_lrs3; // @[util.scala:466:20]
reg uops_6_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20]
reg uops_6_frs3_en; // @[util.scala:466:20]
reg uops_6_fp_val; // @[util.scala:466:20]
reg uops_6_fp_single; // @[util.scala:466:20]
reg uops_6_xcpt_pf_if; // @[util.scala:466:20]
reg uops_6_xcpt_ae_if; // @[util.scala:466:20]
reg uops_6_xcpt_ma_if; // @[util.scala:466:20]
reg uops_6_bp_debug_if; // @[util.scala:466:20]
reg uops_6_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_7_uopc; // @[util.scala:466:20]
reg [31:0] uops_7_inst; // @[util.scala:466:20]
reg [31:0] uops_7_debug_inst; // @[util.scala:466:20]
reg uops_7_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_7_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_7_iq_type; // @[util.scala:466:20]
reg [9:0] uops_7_fu_code; // @[util.scala:466:20]
reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_7_ctrl_is_load; // @[util.scala:466:20]
reg uops_7_ctrl_is_sta; // @[util.scala:466:20]
reg uops_7_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_7_iw_state; // @[util.scala:466:20]
reg uops_7_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_7_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_7_is_br; // @[util.scala:466:20]
reg uops_7_is_jalr; // @[util.scala:466:20]
reg uops_7_is_jal; // @[util.scala:466:20]
reg uops_7_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_7_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_7_br_mask_T_1 = uops_7_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_7_br_tag; // @[util.scala:466:20]
reg [3:0] uops_7_ftq_idx; // @[util.scala:466:20]
reg uops_7_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_7_pc_lob; // @[util.scala:466:20]
reg uops_7_taken; // @[util.scala:466:20]
reg [19:0] uops_7_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_7_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_7_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_7_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_7_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_7_pdst; // @[util.scala:466:20]
reg [6:0] uops_7_prs1; // @[util.scala:466:20]
reg [6:0] uops_7_prs2; // @[util.scala:466:20]
reg [6:0] uops_7_prs3; // @[util.scala:466:20]
reg [3:0] uops_7_ppred; // @[util.scala:466:20]
reg uops_7_prs1_busy; // @[util.scala:466:20]
reg uops_7_prs2_busy; // @[util.scala:466:20]
reg uops_7_prs3_busy; // @[util.scala:466:20]
reg uops_7_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20]
reg uops_7_exception; // @[util.scala:466:20]
reg [63:0] uops_7_exc_cause; // @[util.scala:466:20]
reg uops_7_bypassable; // @[util.scala:466:20]
reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_7_mem_size; // @[util.scala:466:20]
reg uops_7_mem_signed; // @[util.scala:466:20]
reg uops_7_is_fence; // @[util.scala:466:20]
reg uops_7_is_fencei; // @[util.scala:466:20]
reg uops_7_is_amo; // @[util.scala:466:20]
reg uops_7_uses_ldq; // @[util.scala:466:20]
reg uops_7_uses_stq; // @[util.scala:466:20]
reg uops_7_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_7_is_unique; // @[util.scala:466:20]
reg uops_7_flush_on_commit; // @[util.scala:466:20]
reg uops_7_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_7_ldst; // @[util.scala:466:20]
reg [5:0] uops_7_lrs1; // @[util.scala:466:20]
reg [5:0] uops_7_lrs2; // @[util.scala:466:20]
reg [5:0] uops_7_lrs3; // @[util.scala:466:20]
reg uops_7_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20]
reg uops_7_frs3_en; // @[util.scala:466:20]
reg uops_7_fp_val; // @[util.scala:466:20]
reg uops_7_fp_single; // @[util.scala:466:20]
reg uops_7_xcpt_pf_if; // @[util.scala:466:20]
reg uops_7_xcpt_ae_if; // @[util.scala:466:20]
reg uops_7_xcpt_ma_if; // @[util.scala:466:20]
reg uops_7_bp_debug_if; // @[util.scala:466:20]
reg uops_7_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_8_uopc; // @[util.scala:466:20]
reg [31:0] uops_8_inst; // @[util.scala:466:20]
reg [31:0] uops_8_debug_inst; // @[util.scala:466:20]
reg uops_8_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_8_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_8_iq_type; // @[util.scala:466:20]
reg [9:0] uops_8_fu_code; // @[util.scala:466:20]
reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_8_ctrl_is_load; // @[util.scala:466:20]
reg uops_8_ctrl_is_sta; // @[util.scala:466:20]
reg uops_8_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_8_iw_state; // @[util.scala:466:20]
reg uops_8_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_8_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_8_is_br; // @[util.scala:466:20]
reg uops_8_is_jalr; // @[util.scala:466:20]
reg uops_8_is_jal; // @[util.scala:466:20]
reg uops_8_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_8_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_8_br_mask_T_1 = uops_8_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_8_br_tag; // @[util.scala:466:20]
reg [3:0] uops_8_ftq_idx; // @[util.scala:466:20]
reg uops_8_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_8_pc_lob; // @[util.scala:466:20]
reg uops_8_taken; // @[util.scala:466:20]
reg [19:0] uops_8_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_8_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_8_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_8_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_8_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_8_pdst; // @[util.scala:466:20]
reg [6:0] uops_8_prs1; // @[util.scala:466:20]
reg [6:0] uops_8_prs2; // @[util.scala:466:20]
reg [6:0] uops_8_prs3; // @[util.scala:466:20]
reg [3:0] uops_8_ppred; // @[util.scala:466:20]
reg uops_8_prs1_busy; // @[util.scala:466:20]
reg uops_8_prs2_busy; // @[util.scala:466:20]
reg uops_8_prs3_busy; // @[util.scala:466:20]
reg uops_8_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20]
reg uops_8_exception; // @[util.scala:466:20]
reg [63:0] uops_8_exc_cause; // @[util.scala:466:20]
reg uops_8_bypassable; // @[util.scala:466:20]
reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_8_mem_size; // @[util.scala:466:20]
reg uops_8_mem_signed; // @[util.scala:466:20]
reg uops_8_is_fence; // @[util.scala:466:20]
reg uops_8_is_fencei; // @[util.scala:466:20]
reg uops_8_is_amo; // @[util.scala:466:20]
reg uops_8_uses_ldq; // @[util.scala:466:20]
reg uops_8_uses_stq; // @[util.scala:466:20]
reg uops_8_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_8_is_unique; // @[util.scala:466:20]
reg uops_8_flush_on_commit; // @[util.scala:466:20]
reg uops_8_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_8_ldst; // @[util.scala:466:20]
reg [5:0] uops_8_lrs1; // @[util.scala:466:20]
reg [5:0] uops_8_lrs2; // @[util.scala:466:20]
reg [5:0] uops_8_lrs3; // @[util.scala:466:20]
reg uops_8_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20]
reg uops_8_frs3_en; // @[util.scala:466:20]
reg uops_8_fp_val; // @[util.scala:466:20]
reg uops_8_fp_single; // @[util.scala:466:20]
reg uops_8_xcpt_pf_if; // @[util.scala:466:20]
reg uops_8_xcpt_ae_if; // @[util.scala:466:20]
reg uops_8_xcpt_ma_if; // @[util.scala:466:20]
reg uops_8_bp_debug_if; // @[util.scala:466:20]
reg uops_8_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_9_uopc; // @[util.scala:466:20]
reg [31:0] uops_9_inst; // @[util.scala:466:20]
reg [31:0] uops_9_debug_inst; // @[util.scala:466:20]
reg uops_9_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_9_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_9_iq_type; // @[util.scala:466:20]
reg [9:0] uops_9_fu_code; // @[util.scala:466:20]
reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_9_ctrl_is_load; // @[util.scala:466:20]
reg uops_9_ctrl_is_sta; // @[util.scala:466:20]
reg uops_9_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_9_iw_state; // @[util.scala:466:20]
reg uops_9_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_9_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_9_is_br; // @[util.scala:466:20]
reg uops_9_is_jalr; // @[util.scala:466:20]
reg uops_9_is_jal; // @[util.scala:466:20]
reg uops_9_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_9_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_9_br_mask_T_1 = uops_9_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_9_br_tag; // @[util.scala:466:20]
reg [3:0] uops_9_ftq_idx; // @[util.scala:466:20]
reg uops_9_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_9_pc_lob; // @[util.scala:466:20]
reg uops_9_taken; // @[util.scala:466:20]
reg [19:0] uops_9_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_9_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_9_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_9_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_9_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_9_pdst; // @[util.scala:466:20]
reg [6:0] uops_9_prs1; // @[util.scala:466:20]
reg [6:0] uops_9_prs2; // @[util.scala:466:20]
reg [6:0] uops_9_prs3; // @[util.scala:466:20]
reg [3:0] uops_9_ppred; // @[util.scala:466:20]
reg uops_9_prs1_busy; // @[util.scala:466:20]
reg uops_9_prs2_busy; // @[util.scala:466:20]
reg uops_9_prs3_busy; // @[util.scala:466:20]
reg uops_9_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20]
reg uops_9_exception; // @[util.scala:466:20]
reg [63:0] uops_9_exc_cause; // @[util.scala:466:20]
reg uops_9_bypassable; // @[util.scala:466:20]
reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_9_mem_size; // @[util.scala:466:20]
reg uops_9_mem_signed; // @[util.scala:466:20]
reg uops_9_is_fence; // @[util.scala:466:20]
reg uops_9_is_fencei; // @[util.scala:466:20]
reg uops_9_is_amo; // @[util.scala:466:20]
reg uops_9_uses_ldq; // @[util.scala:466:20]
reg uops_9_uses_stq; // @[util.scala:466:20]
reg uops_9_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_9_is_unique; // @[util.scala:466:20]
reg uops_9_flush_on_commit; // @[util.scala:466:20]
reg uops_9_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_9_ldst; // @[util.scala:466:20]
reg [5:0] uops_9_lrs1; // @[util.scala:466:20]
reg [5:0] uops_9_lrs2; // @[util.scala:466:20]
reg [5:0] uops_9_lrs3; // @[util.scala:466:20]
reg uops_9_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20]
reg uops_9_frs3_en; // @[util.scala:466:20]
reg uops_9_fp_val; // @[util.scala:466:20]
reg uops_9_fp_single; // @[util.scala:466:20]
reg uops_9_xcpt_pf_if; // @[util.scala:466:20]
reg uops_9_xcpt_ae_if; // @[util.scala:466:20]
reg uops_9_xcpt_ma_if; // @[util.scala:466:20]
reg uops_9_bp_debug_if; // @[util.scala:466:20]
reg uops_9_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_10_uopc; // @[util.scala:466:20]
reg [31:0] uops_10_inst; // @[util.scala:466:20]
reg [31:0] uops_10_debug_inst; // @[util.scala:466:20]
reg uops_10_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_10_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_10_iq_type; // @[util.scala:466:20]
reg [9:0] uops_10_fu_code; // @[util.scala:466:20]
reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_10_ctrl_is_load; // @[util.scala:466:20]
reg uops_10_ctrl_is_sta; // @[util.scala:466:20]
reg uops_10_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_10_iw_state; // @[util.scala:466:20]
reg uops_10_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_10_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_10_is_br; // @[util.scala:466:20]
reg uops_10_is_jalr; // @[util.scala:466:20]
reg uops_10_is_jal; // @[util.scala:466:20]
reg uops_10_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_10_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_10_br_mask_T_1 = uops_10_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_10_br_tag; // @[util.scala:466:20]
reg [3:0] uops_10_ftq_idx; // @[util.scala:466:20]
reg uops_10_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_10_pc_lob; // @[util.scala:466:20]
reg uops_10_taken; // @[util.scala:466:20]
reg [19:0] uops_10_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_10_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_10_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_10_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_10_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_10_pdst; // @[util.scala:466:20]
reg [6:0] uops_10_prs1; // @[util.scala:466:20]
reg [6:0] uops_10_prs2; // @[util.scala:466:20]
reg [6:0] uops_10_prs3; // @[util.scala:466:20]
reg [3:0] uops_10_ppred; // @[util.scala:466:20]
reg uops_10_prs1_busy; // @[util.scala:466:20]
reg uops_10_prs2_busy; // @[util.scala:466:20]
reg uops_10_prs3_busy; // @[util.scala:466:20]
reg uops_10_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20]
reg uops_10_exception; // @[util.scala:466:20]
reg [63:0] uops_10_exc_cause; // @[util.scala:466:20]
reg uops_10_bypassable; // @[util.scala:466:20]
reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_10_mem_size; // @[util.scala:466:20]
reg uops_10_mem_signed; // @[util.scala:466:20]
reg uops_10_is_fence; // @[util.scala:466:20]
reg uops_10_is_fencei; // @[util.scala:466:20]
reg uops_10_is_amo; // @[util.scala:466:20]
reg uops_10_uses_ldq; // @[util.scala:466:20]
reg uops_10_uses_stq; // @[util.scala:466:20]
reg uops_10_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_10_is_unique; // @[util.scala:466:20]
reg uops_10_flush_on_commit; // @[util.scala:466:20]
reg uops_10_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_10_ldst; // @[util.scala:466:20]
reg [5:0] uops_10_lrs1; // @[util.scala:466:20]
reg [5:0] uops_10_lrs2; // @[util.scala:466:20]
reg [5:0] uops_10_lrs3; // @[util.scala:466:20]
reg uops_10_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20]
reg uops_10_frs3_en; // @[util.scala:466:20]
reg uops_10_fp_val; // @[util.scala:466:20]
reg uops_10_fp_single; // @[util.scala:466:20]
reg uops_10_xcpt_pf_if; // @[util.scala:466:20]
reg uops_10_xcpt_ae_if; // @[util.scala:466:20]
reg uops_10_xcpt_ma_if; // @[util.scala:466:20]
reg uops_10_bp_debug_if; // @[util.scala:466:20]
reg uops_10_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_11_uopc; // @[util.scala:466:20]
reg [31:0] uops_11_inst; // @[util.scala:466:20]
reg [31:0] uops_11_debug_inst; // @[util.scala:466:20]
reg uops_11_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_11_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_11_iq_type; // @[util.scala:466:20]
reg [9:0] uops_11_fu_code; // @[util.scala:466:20]
reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_11_ctrl_is_load; // @[util.scala:466:20]
reg uops_11_ctrl_is_sta; // @[util.scala:466:20]
reg uops_11_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_11_iw_state; // @[util.scala:466:20]
reg uops_11_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_11_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_11_is_br; // @[util.scala:466:20]
reg uops_11_is_jalr; // @[util.scala:466:20]
reg uops_11_is_jal; // @[util.scala:466:20]
reg uops_11_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_11_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_11_br_mask_T_1 = uops_11_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_11_br_tag; // @[util.scala:466:20]
reg [3:0] uops_11_ftq_idx; // @[util.scala:466:20]
reg uops_11_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_11_pc_lob; // @[util.scala:466:20]
reg uops_11_taken; // @[util.scala:466:20]
reg [19:0] uops_11_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_11_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_11_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_11_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_11_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_11_pdst; // @[util.scala:466:20]
reg [6:0] uops_11_prs1; // @[util.scala:466:20]
reg [6:0] uops_11_prs2; // @[util.scala:466:20]
reg [6:0] uops_11_prs3; // @[util.scala:466:20]
reg [3:0] uops_11_ppred; // @[util.scala:466:20]
reg uops_11_prs1_busy; // @[util.scala:466:20]
reg uops_11_prs2_busy; // @[util.scala:466:20]
reg uops_11_prs3_busy; // @[util.scala:466:20]
reg uops_11_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20]
reg uops_11_exception; // @[util.scala:466:20]
reg [63:0] uops_11_exc_cause; // @[util.scala:466:20]
reg uops_11_bypassable; // @[util.scala:466:20]
reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_11_mem_size; // @[util.scala:466:20]
reg uops_11_mem_signed; // @[util.scala:466:20]
reg uops_11_is_fence; // @[util.scala:466:20]
reg uops_11_is_fencei; // @[util.scala:466:20]
reg uops_11_is_amo; // @[util.scala:466:20]
reg uops_11_uses_ldq; // @[util.scala:466:20]
reg uops_11_uses_stq; // @[util.scala:466:20]
reg uops_11_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_11_is_unique; // @[util.scala:466:20]
reg uops_11_flush_on_commit; // @[util.scala:466:20]
reg uops_11_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_11_ldst; // @[util.scala:466:20]
reg [5:0] uops_11_lrs1; // @[util.scala:466:20]
reg [5:0] uops_11_lrs2; // @[util.scala:466:20]
reg [5:0] uops_11_lrs3; // @[util.scala:466:20]
reg uops_11_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20]
reg uops_11_frs3_en; // @[util.scala:466:20]
reg uops_11_fp_val; // @[util.scala:466:20]
reg uops_11_fp_single; // @[util.scala:466:20]
reg uops_11_xcpt_pf_if; // @[util.scala:466:20]
reg uops_11_xcpt_ae_if; // @[util.scala:466:20]
reg uops_11_xcpt_ma_if; // @[util.scala:466:20]
reg uops_11_bp_debug_if; // @[util.scala:466:20]
reg uops_11_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_12_uopc; // @[util.scala:466:20]
reg [31:0] uops_12_inst; // @[util.scala:466:20]
reg [31:0] uops_12_debug_inst; // @[util.scala:466:20]
reg uops_12_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_12_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_12_iq_type; // @[util.scala:466:20]
reg [9:0] uops_12_fu_code; // @[util.scala:466:20]
reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_12_ctrl_is_load; // @[util.scala:466:20]
reg uops_12_ctrl_is_sta; // @[util.scala:466:20]
reg uops_12_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_12_iw_state; // @[util.scala:466:20]
reg uops_12_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_12_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_12_is_br; // @[util.scala:466:20]
reg uops_12_is_jalr; // @[util.scala:466:20]
reg uops_12_is_jal; // @[util.scala:466:20]
reg uops_12_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_12_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_12_br_mask_T_1 = uops_12_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_12_br_tag; // @[util.scala:466:20]
reg [3:0] uops_12_ftq_idx; // @[util.scala:466:20]
reg uops_12_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_12_pc_lob; // @[util.scala:466:20]
reg uops_12_taken; // @[util.scala:466:20]
reg [19:0] uops_12_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_12_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_12_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_12_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_12_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_12_pdst; // @[util.scala:466:20]
reg [6:0] uops_12_prs1; // @[util.scala:466:20]
reg [6:0] uops_12_prs2; // @[util.scala:466:20]
reg [6:0] uops_12_prs3; // @[util.scala:466:20]
reg [3:0] uops_12_ppred; // @[util.scala:466:20]
reg uops_12_prs1_busy; // @[util.scala:466:20]
reg uops_12_prs2_busy; // @[util.scala:466:20]
reg uops_12_prs3_busy; // @[util.scala:466:20]
reg uops_12_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20]
reg uops_12_exception; // @[util.scala:466:20]
reg [63:0] uops_12_exc_cause; // @[util.scala:466:20]
reg uops_12_bypassable; // @[util.scala:466:20]
reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_12_mem_size; // @[util.scala:466:20]
reg uops_12_mem_signed; // @[util.scala:466:20]
reg uops_12_is_fence; // @[util.scala:466:20]
reg uops_12_is_fencei; // @[util.scala:466:20]
reg uops_12_is_amo; // @[util.scala:466:20]
reg uops_12_uses_ldq; // @[util.scala:466:20]
reg uops_12_uses_stq; // @[util.scala:466:20]
reg uops_12_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_12_is_unique; // @[util.scala:466:20]
reg uops_12_flush_on_commit; // @[util.scala:466:20]
reg uops_12_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_12_ldst; // @[util.scala:466:20]
reg [5:0] uops_12_lrs1; // @[util.scala:466:20]
reg [5:0] uops_12_lrs2; // @[util.scala:466:20]
reg [5:0] uops_12_lrs3; // @[util.scala:466:20]
reg uops_12_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20]
reg uops_12_frs3_en; // @[util.scala:466:20]
reg uops_12_fp_val; // @[util.scala:466:20]
reg uops_12_fp_single; // @[util.scala:466:20]
reg uops_12_xcpt_pf_if; // @[util.scala:466:20]
reg uops_12_xcpt_ae_if; // @[util.scala:466:20]
reg uops_12_xcpt_ma_if; // @[util.scala:466:20]
reg uops_12_bp_debug_if; // @[util.scala:466:20]
reg uops_12_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_13_uopc; // @[util.scala:466:20]
reg [31:0] uops_13_inst; // @[util.scala:466:20]
reg [31:0] uops_13_debug_inst; // @[util.scala:466:20]
reg uops_13_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_13_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_13_iq_type; // @[util.scala:466:20]
reg [9:0] uops_13_fu_code; // @[util.scala:466:20]
reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_13_ctrl_is_load; // @[util.scala:466:20]
reg uops_13_ctrl_is_sta; // @[util.scala:466:20]
reg uops_13_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_13_iw_state; // @[util.scala:466:20]
reg uops_13_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_13_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_13_is_br; // @[util.scala:466:20]
reg uops_13_is_jalr; // @[util.scala:466:20]
reg uops_13_is_jal; // @[util.scala:466:20]
reg uops_13_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_13_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_13_br_mask_T_1 = uops_13_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_13_br_tag; // @[util.scala:466:20]
reg [3:0] uops_13_ftq_idx; // @[util.scala:466:20]
reg uops_13_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_13_pc_lob; // @[util.scala:466:20]
reg uops_13_taken; // @[util.scala:466:20]
reg [19:0] uops_13_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_13_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_13_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_13_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_13_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_13_pdst; // @[util.scala:466:20]
reg [6:0] uops_13_prs1; // @[util.scala:466:20]
reg [6:0] uops_13_prs2; // @[util.scala:466:20]
reg [6:0] uops_13_prs3; // @[util.scala:466:20]
reg [3:0] uops_13_ppred; // @[util.scala:466:20]
reg uops_13_prs1_busy; // @[util.scala:466:20]
reg uops_13_prs2_busy; // @[util.scala:466:20]
reg uops_13_prs3_busy; // @[util.scala:466:20]
reg uops_13_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20]
reg uops_13_exception; // @[util.scala:466:20]
reg [63:0] uops_13_exc_cause; // @[util.scala:466:20]
reg uops_13_bypassable; // @[util.scala:466:20]
reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_13_mem_size; // @[util.scala:466:20]
reg uops_13_mem_signed; // @[util.scala:466:20]
reg uops_13_is_fence; // @[util.scala:466:20]
reg uops_13_is_fencei; // @[util.scala:466:20]
reg uops_13_is_amo; // @[util.scala:466:20]
reg uops_13_uses_ldq; // @[util.scala:466:20]
reg uops_13_uses_stq; // @[util.scala:466:20]
reg uops_13_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_13_is_unique; // @[util.scala:466:20]
reg uops_13_flush_on_commit; // @[util.scala:466:20]
reg uops_13_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_13_ldst; // @[util.scala:466:20]
reg [5:0] uops_13_lrs1; // @[util.scala:466:20]
reg [5:0] uops_13_lrs2; // @[util.scala:466:20]
reg [5:0] uops_13_lrs3; // @[util.scala:466:20]
reg uops_13_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20]
reg uops_13_frs3_en; // @[util.scala:466:20]
reg uops_13_fp_val; // @[util.scala:466:20]
reg uops_13_fp_single; // @[util.scala:466:20]
reg uops_13_xcpt_pf_if; // @[util.scala:466:20]
reg uops_13_xcpt_ae_if; // @[util.scala:466:20]
reg uops_13_xcpt_ma_if; // @[util.scala:466:20]
reg uops_13_bp_debug_if; // @[util.scala:466:20]
reg uops_13_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_14_uopc; // @[util.scala:466:20]
reg [31:0] uops_14_inst; // @[util.scala:466:20]
reg [31:0] uops_14_debug_inst; // @[util.scala:466:20]
reg uops_14_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_14_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_14_iq_type; // @[util.scala:466:20]
reg [9:0] uops_14_fu_code; // @[util.scala:466:20]
reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_14_ctrl_is_load; // @[util.scala:466:20]
reg uops_14_ctrl_is_sta; // @[util.scala:466:20]
reg uops_14_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_14_iw_state; // @[util.scala:466:20]
reg uops_14_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_14_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_14_is_br; // @[util.scala:466:20]
reg uops_14_is_jalr; // @[util.scala:466:20]
reg uops_14_is_jal; // @[util.scala:466:20]
reg uops_14_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_14_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_14_br_mask_T_1 = uops_14_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_14_br_tag; // @[util.scala:466:20]
reg [3:0] uops_14_ftq_idx; // @[util.scala:466:20]
reg uops_14_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_14_pc_lob; // @[util.scala:466:20]
reg uops_14_taken; // @[util.scala:466:20]
reg [19:0] uops_14_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_14_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_14_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_14_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_14_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_14_pdst; // @[util.scala:466:20]
reg [6:0] uops_14_prs1; // @[util.scala:466:20]
reg [6:0] uops_14_prs2; // @[util.scala:466:20]
reg [6:0] uops_14_prs3; // @[util.scala:466:20]
reg [3:0] uops_14_ppred; // @[util.scala:466:20]
reg uops_14_prs1_busy; // @[util.scala:466:20]
reg uops_14_prs2_busy; // @[util.scala:466:20]
reg uops_14_prs3_busy; // @[util.scala:466:20]
reg uops_14_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20]
reg uops_14_exception; // @[util.scala:466:20]
reg [63:0] uops_14_exc_cause; // @[util.scala:466:20]
reg uops_14_bypassable; // @[util.scala:466:20]
reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_14_mem_size; // @[util.scala:466:20]
reg uops_14_mem_signed; // @[util.scala:466:20]
reg uops_14_is_fence; // @[util.scala:466:20]
reg uops_14_is_fencei; // @[util.scala:466:20]
reg uops_14_is_amo; // @[util.scala:466:20]
reg uops_14_uses_ldq; // @[util.scala:466:20]
reg uops_14_uses_stq; // @[util.scala:466:20]
reg uops_14_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_14_is_unique; // @[util.scala:466:20]
reg uops_14_flush_on_commit; // @[util.scala:466:20]
reg uops_14_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_14_ldst; // @[util.scala:466:20]
reg [5:0] uops_14_lrs1; // @[util.scala:466:20]
reg [5:0] uops_14_lrs2; // @[util.scala:466:20]
reg [5:0] uops_14_lrs3; // @[util.scala:466:20]
reg uops_14_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20]
reg uops_14_frs3_en; // @[util.scala:466:20]
reg uops_14_fp_val; // @[util.scala:466:20]
reg uops_14_fp_single; // @[util.scala:466:20]
reg uops_14_xcpt_pf_if; // @[util.scala:466:20]
reg uops_14_xcpt_ae_if; // @[util.scala:466:20]
reg uops_14_xcpt_ma_if; // @[util.scala:466:20]
reg uops_14_bp_debug_if; // @[util.scala:466:20]
reg uops_14_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20]
reg [6:0] uops_15_uopc; // @[util.scala:466:20]
reg [31:0] uops_15_inst; // @[util.scala:466:20]
reg [31:0] uops_15_debug_inst; // @[util.scala:466:20]
reg uops_15_is_rvc; // @[util.scala:466:20]
reg [33:0] uops_15_debug_pc; // @[util.scala:466:20]
reg [2:0] uops_15_iq_type; // @[util.scala:466:20]
reg [9:0] uops_15_fu_code; // @[util.scala:466:20]
reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20]
reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20]
reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20]
reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20]
reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20]
reg uops_15_ctrl_is_load; // @[util.scala:466:20]
reg uops_15_ctrl_is_sta; // @[util.scala:466:20]
reg uops_15_ctrl_is_std; // @[util.scala:466:20]
reg [1:0] uops_15_iw_state; // @[util.scala:466:20]
reg uops_15_iw_p1_poisoned; // @[util.scala:466:20]
reg uops_15_iw_p2_poisoned; // @[util.scala:466:20]
reg uops_15_is_br; // @[util.scala:466:20]
reg uops_15_is_jalr; // @[util.scala:466:20]
reg uops_15_is_jal; // @[util.scala:466:20]
reg uops_15_is_sfb; // @[util.scala:466:20]
reg [3:0] uops_15_br_mask; // @[util.scala:466:20]
wire [3:0] _uops_15_br_mask_T_1 = uops_15_br_mask; // @[util.scala:89:21, :466:20]
reg [1:0] uops_15_br_tag; // @[util.scala:466:20]
reg [3:0] uops_15_ftq_idx; // @[util.scala:466:20]
reg uops_15_edge_inst; // @[util.scala:466:20]
reg [5:0] uops_15_pc_lob; // @[util.scala:466:20]
reg uops_15_taken; // @[util.scala:466:20]
reg [19:0] uops_15_imm_packed; // @[util.scala:466:20]
reg [11:0] uops_15_csr_addr; // @[util.scala:466:20]
reg [5:0] uops_15_rob_idx; // @[util.scala:466:20]
reg [3:0] uops_15_ldq_idx; // @[util.scala:466:20]
reg [3:0] uops_15_stq_idx; // @[util.scala:466:20]
reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20]
reg [6:0] uops_15_pdst; // @[util.scala:466:20]
reg [6:0] uops_15_prs1; // @[util.scala:466:20]
reg [6:0] uops_15_prs2; // @[util.scala:466:20]
reg [6:0] uops_15_prs3; // @[util.scala:466:20]
reg [3:0] uops_15_ppred; // @[util.scala:466:20]
reg uops_15_prs1_busy; // @[util.scala:466:20]
reg uops_15_prs2_busy; // @[util.scala:466:20]
reg uops_15_prs3_busy; // @[util.scala:466:20]
reg uops_15_ppred_busy; // @[util.scala:466:20]
reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20]
reg uops_15_exception; // @[util.scala:466:20]
reg [63:0] uops_15_exc_cause; // @[util.scala:466:20]
reg uops_15_bypassable; // @[util.scala:466:20]
reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20]
reg [1:0] uops_15_mem_size; // @[util.scala:466:20]
reg uops_15_mem_signed; // @[util.scala:466:20]
reg uops_15_is_fence; // @[util.scala:466:20]
reg uops_15_is_fencei; // @[util.scala:466:20]
reg uops_15_is_amo; // @[util.scala:466:20]
reg uops_15_uses_ldq; // @[util.scala:466:20]
reg uops_15_uses_stq; // @[util.scala:466:20]
reg uops_15_is_sys_pc2epc; // @[util.scala:466:20]
reg uops_15_is_unique; // @[util.scala:466:20]
reg uops_15_flush_on_commit; // @[util.scala:466:20]
reg uops_15_ldst_is_rs1; // @[util.scala:466:20]
reg [5:0] uops_15_ldst; // @[util.scala:466:20]
reg [5:0] uops_15_lrs1; // @[util.scala:466:20]
reg [5:0] uops_15_lrs2; // @[util.scala:466:20]
reg [5:0] uops_15_lrs3; // @[util.scala:466:20]
reg uops_15_ldst_val; // @[util.scala:466:20]
reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20]
reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20]
reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20]
reg uops_15_frs3_en; // @[util.scala:466:20]
reg uops_15_fp_val; // @[util.scala:466:20]
reg uops_15_fp_single; // @[util.scala:466:20]
reg uops_15_xcpt_pf_if; // @[util.scala:466:20]
reg uops_15_xcpt_ae_if; // @[util.scala:466:20]
reg uops_15_xcpt_ma_if; // @[util.scala:466:20]
reg uops_15_bp_debug_if; // @[util.scala:466:20]
reg uops_15_bp_xcpt_if; // @[util.scala:466:20]
reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20]
reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20]
reg [3:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [3:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:470:27]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}]
assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25]
wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24]
wire full; // @[util.scala:474:24]
assign full = _GEN; // @[util.scala:474:24]
wire _io_count_T; // @[util.scala:526:32]
assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35]
wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42]
wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}]
wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}]
wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}]
wire _valids_0_T_6 = _valids_0_T_3; // @[util.scala:481:{29,69}]
wire _valids_1_T_6 = _valids_1_T_3; // @[util.scala:481:{29,69}]
wire _valids_2_T_6 = _valids_2_T_3; // @[util.scala:481:{29,69}]
wire _valids_3_T_6 = _valids_3_T_3; // @[util.scala:481:{29,69}]
wire _valids_4_T_6 = _valids_4_T_3; // @[util.scala:481:{29,69}]
wire _valids_5_T_6 = _valids_5_T_3; // @[util.scala:481:{29,69}]
wire _valids_6_T_6 = _valids_6_T_3; // @[util.scala:481:{29,69}]
wire _valids_7_T_6 = _valids_7_T_3; // @[util.scala:481:{29,69}]
wire _valids_8_T_6 = _valids_8_T_3; // @[util.scala:481:{29,69}]
wire _valids_9_T_6 = _valids_9_T_3; // @[util.scala:481:{29,69}]
wire _valids_10_T_6 = _valids_10_T_3; // @[util.scala:481:{29,69}]
wire _valids_11_T_6 = _valids_11_T_3; // @[util.scala:481:{29,69}]
wire _valids_12_T_6 = _valids_12_T_3; // @[util.scala:481:{29,69}]
wire _valids_13_T_6 = _valids_13_T_3; // @[util.scala:481:{29,69}]
wire _valids_14_T_6 = _valids_14_T_3; // @[util.scala:481:{29,69}]
wire _valids_15_T_6 = _valids_15_T_3; // @[util.scala:481:{29,69}]
wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24]
wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24]
wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19]
assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17]
assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask; // @[util.scala:85:25, :506:17]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17]
assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17]
assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17]
assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17]
assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17]
assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17]
assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17]
assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17]
assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17]
wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19]
assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][33:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19]
assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19]
assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19]
assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19]
assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19]
assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19]
assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19]
assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19]
assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19]
assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19]
assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][3:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19]
assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19]
assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19]
assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19]
assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19]
assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19]
assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19]
assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19]
assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19]
assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19]
assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19]
assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19]
assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19]
assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19]
assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30]
wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}]
wire _io_deq_valid_T_5 = _io_deq_valid_T_1; // @[util.scala:509:{40,65}]
assign _io_deq_valid_T_8 = _io_deq_valid_T_5; // @[util.scala:509:{65,108}]
assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108]
assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7]
wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24]
wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40]
wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}]
assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}]
wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40]
wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40]
wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40]
wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40]
wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40]
wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40]
wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40]
wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40]
wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40]
wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40]
wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40]
wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40]
wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40]
wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40]
wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40]
wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33]
wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40]
always @(posedge clock) begin // @[util.scala:448:7]
if (reset) begin // @[util.scala:448:7]
valids_0 <= 1'h0; // @[util.scala:465:24]
valids_1 <= 1'h0; // @[util.scala:465:24]
valids_2 <= 1'h0; // @[util.scala:465:24]
valids_3 <= 1'h0; // @[util.scala:465:24]
valids_4 <= 1'h0; // @[util.scala:465:24]
valids_5 <= 1'h0; // @[util.scala:465:24]
valids_6 <= 1'h0; // @[util.scala:465:24]
valids_7 <= 1'h0; // @[util.scala:465:24]
valids_8 <= 1'h0; // @[util.scala:465:24]
valids_9 <= 1'h0; // @[util.scala:465:24]
valids_10 <= 1'h0; // @[util.scala:465:24]
valids_11 <= 1'h0; // @[util.scala:465:24]
valids_12 <= 1'h0; // @[util.scala:465:24]
valids_13 <= 1'h0; // @[util.scala:465:24]
valids_14 <= 1'h0; // @[util.scala:465:24]
valids_15 <= 1'h0; // @[util.scala:465:24]
enq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 4'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:470:27]
end
else begin // @[util.scala:448:7]
valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 | _valids_3_T_6); // @[Counter.scala:61:40]
valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 | _valids_4_T_6); // @[Counter.scala:61:40]
valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 | _valids_5_T_6); // @[Counter.scala:61:40]
valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 | _valids_6_T_6); // @[Counter.scala:61:40]
valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 | _valids_7_T_6); // @[Counter.scala:61:40]
valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 | _valids_8_T_6); // @[Counter.scala:61:40]
valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 | _valids_9_T_6); // @[Counter.scala:61:40]
valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 | _valids_10_T_6); // @[Counter.scala:61:40]
valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 | _valids_11_T_6); // @[Counter.scala:61:40]
valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 | _valids_12_T_6); // @[Counter.scala:61:40]
valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 | _valids_13_T_6); // @[Counter.scala:61:40]
valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 | _valids_14_T_6); // @[Counter.scala:61:40]
valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 | _valids_15_T_6); // @[Counter.scala:61:40]
if (do_enq) // @[util.scala:475:24]
enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24]
if (do_deq) // @[util.scala:476:24]
deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24]
if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16]
maybe_full <= do_enq; // @[util.scala:470:27, :475:24]
end
if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33]
uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_0) // @[util.scala:465:24]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33]
uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_1) // @[util.scala:465:24]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33]
uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_2) // @[util.scala:465:24]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33]
uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_3) // @[util.scala:465:24]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33]
uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_4) // @[util.scala:465:24]
uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33]
uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_5) // @[util.scala:465:24]
uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33]
uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_6) // @[util.scala:465:24]
uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33]
uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_7) // @[util.scala:465:24]
uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33]
uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_8) // @[util.scala:465:24]
uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33]
uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_9) // @[util.scala:465:24]
uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33]
uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_10) // @[util.scala:465:24]
uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33]
uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_11) // @[util.scala:465:24]
uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33]
uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_12) // @[util.scala:465:24]
uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33]
uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_13) // @[util.scala:465:24]
uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33]
uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33]
uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_14) // @[util.scala:465:24]
uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20]
if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33]
uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20]
uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20]
uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20]
uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20]
uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20]
uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20]
uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20]
uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20]
uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20]
uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20]
uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20]
uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20]
uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20]
uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20]
uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20]
uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20]
uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20]
uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20]
uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20]
uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20]
uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20]
uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20]
uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20]
uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20]
uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20]
uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20]
uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20]
uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20]
uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20]
uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20]
uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20]
uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20]
uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20]
uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20]
uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20]
uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20]
uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20]
uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20]
uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20]
uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20]
uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20]
uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20]
uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20]
uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20]
uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20]
uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20]
uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20]
uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20]
uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20]
uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20]
uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20]
uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20]
uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20]
uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20]
uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20]
uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20]
uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20]
uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20]
uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20]
uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20]
uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20]
uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20]
end
if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40]
uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20]
else if (valids_15) // @[util.scala:465:24]
uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20]
always @(posedge)
ram_16x131 ram_ext ( // @[util.scala:464:20]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:475:24]
.W0_clk (clock),
.W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20]
); // @[util.scala:464:20]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7]
assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7]
assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7]
assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7]
assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7]
assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7]
assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7]
assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7]
assign io_empty = io_empty_0; // @[util.scala:448:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v4.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val grant = Input(Bool())
val iss_uop = Output(new MicroOp())
val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val squash_grant = Input(Bool())
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup)))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val child_rebusys = Input(UInt(aluWidth.W))
}
class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters)
extends BoomModule
{
val io = IO(new IssueSlotIO(numWakeupPorts))
val slot_valid = RegInit(false.B)
val slot_uop = Reg(new MicroOp())
val next_valid = WireInit(slot_valid)
val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop))
val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop)
io.valid := slot_valid
io.out_uop := next_uop
io.will_be_valid := next_valid && !killed
when (io.kill) {
slot_valid := false.B
} .elsewhen (io.in_uop.valid) {
slot_valid := true.B
} .elsewhen (io.clear) {
slot_valid := false.B
} .otherwise {
slot_valid := next_valid && !killed
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (!slot_valid || io.clear || io.kill)
} .otherwise {
slot_uop := next_uop
}
// Wakeups
next_uop.iw_p1_bypass_hint := false.B
next_uop.iw_p2_bypass_hint := false.B
next_uop.iw_p3_bypass_hint := false.B
next_uop.iw_p1_speculative_child := 0.U
next_uop.iw_p2_speculative_child := 0.U
val rebusied_prs1 = WireInit(false.B)
val rebusied_prs2 = WireInit(false.B)
val rebusied = rebusied_prs1 || rebusied_prs2
val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 }
val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 }
val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 }
val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m }
val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m }
val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m }
val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m }
val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m }
val bypassables = io.wakeup_ports.map { w => w.bits.bypassable }
val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask }
when (prs1_wakeups.reduce(_||_)) {
next_uop.prs1_busy := false.B
next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks)
next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables)
}
when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) &&
slot_uop.lrs1_rtype === RT_FIX) {
next_uop.prs1_busy := true.B
rebusied_prs1 := true.B
}
when (prs2_wakeups.reduce(_||_)) {
next_uop.prs2_busy := false.B
next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks)
next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables)
}
when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) &&
slot_uop.lrs2_rtype === RT_FIX) {
next_uop.prs2_busy := true.B
rebusied_prs2 := true.B
}
when (prs3_wakeups.reduce(_||_)) {
next_uop.prs3_busy := false.B
next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables)
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) {
next_uop.ppred_busy := false.B
}
val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B)
val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
io.request := slot_valid && !slot_uop.iw_issued && (
iss_ready || agen_ready || dgen_ready
)
io.iss_uop := slot_uop
// Update state for current micro-op based on grant
next_uop.iw_issued := false.B
next_uop.iw_issued_partial_agen := false.B
next_uop.iw_issued_partial_dgen := false.B
when (io.grant && !io.squash_grant) {
next_uop.iw_issued := true.B
}
if (isMem) {
when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) {
when (agen_ready) {
// Issue the AGEN, next slot entry is a DGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_agen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := true.B
io.iss_uop.fu_code(FC_DGEN) := false.B
} .otherwise {
// Issue the DGEN, next slot entry is the AGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_dgen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := false.B
io.iss_uop.fu_code(FC_DGEN) := true.B
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
} .elsewhen (slot_uop.fu_code(FC_DGEN)) {
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
io.iss_uop.lrs2_rtype := RT_X
io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE
}
when (slot_valid && slot_uop.iw_issued) {
next_valid := rebusied
if (isMem) {
when (slot_uop.iw_issued_partial_agen) {
next_valid := true.B
when (!rebusied_prs1) {
next_uop.fu_code(FC_AGEN) := false.B
next_uop.fu_code(FC_DGEN) := true.B
}
} .elsewhen (slot_uop.iw_issued_partial_dgen) {
next_valid := true.B
when (!rebusied_prs2) {
next_uop.fu_code(FC_AGEN) := true.B
next_uop.fu_code(FC_DGEN) := false.B
}
}
}
}
}
|
module IssueSlot_88( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_bypassable, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_speculative_mask, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_rebusy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_2_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_2_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_2_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_2_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_2_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_2_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_2_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_2_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_2_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_2_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_2_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_3_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_3_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_3_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_3_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_3_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_3_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_3_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_3_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_3_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_3_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_3_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_4_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_4_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [15:0] io_wakeup_ports_4_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_4_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_4_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_4_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_4_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_4_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_4_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_4_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_4_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_pred_wakeup_port_valid, // @[issue-slot.scala:52:14]
input [4:0] io_pred_wakeup_port_bits, // @[issue-slot.scala:52:14]
input [2:0] io_child_rebusys // @[issue-slot.scala:52:14]
);
wire [15:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_bypassable_0 = io_wakeup_ports_0_bits_bypassable; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_speculative_mask_0 = io_wakeup_ports_0_bits_speculative_mask; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy_0 = io_wakeup_ports_0_bits_rebusy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_inst_0 = io_wakeup_ports_2_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_2_bits_uop_debug_inst_0 = io_wakeup_ports_2_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rvc_0 = io_wakeup_ports_2_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_2_bits_uop_debug_pc_0 = io_wakeup_ports_2_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_0_0 = io_wakeup_ports_2_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_1_0 = io_wakeup_ports_2_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_2_0 = io_wakeup_ports_2_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iq_type_3_0 = io_wakeup_ports_2_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_0_0 = io_wakeup_ports_2_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_1_0 = io_wakeup_ports_2_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_2_0 = io_wakeup_ports_2_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_3_0 = io_wakeup_ports_2_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_4_0 = io_wakeup_ports_2_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_5_0 = io_wakeup_ports_2_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_6_0 = io_wakeup_ports_2_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_7_0 = io_wakeup_ports_2_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_8_0 = io_wakeup_ports_2_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fu_code_9_0 = io_wakeup_ports_2_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_0 = io_wakeup_ports_2_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_2_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_2_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_dis_col_sel_0 = io_wakeup_ports_2_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_2_bits_uop_br_mask_0 = io_wakeup_ports_2_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_tag_0 = io_wakeup_ports_2_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_2_bits_uop_br_type_0 = io_wakeup_ports_2_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfb_0 = io_wakeup_ports_2_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fence_0 = io_wakeup_ports_2_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_fencei_0 = io_wakeup_ports_2_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sfence_0 = io_wakeup_ports_2_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_amo_0 = io_wakeup_ports_2_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_eret_0 = io_wakeup_ports_2_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_2_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_rocc_0 = io_wakeup_ports_2_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_mov_0 = io_wakeup_ports_2_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ftq_idx_0 = io_wakeup_ports_2_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_edge_inst_0 = io_wakeup_ports_2_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_pc_lob_0 = io_wakeup_ports_2_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_taken_0 = io_wakeup_ports_2_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_imm_rename_0 = io_wakeup_ports_2_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_imm_sel_0 = io_wakeup_ports_2_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_pimm_0 = io_wakeup_ports_2_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_2_bits_uop_imm_packed_0 = io_wakeup_ports_2_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_op1_sel_0 = io_wakeup_ports_2_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_op2_sel_0 = io_wakeup_ports_2_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_2_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_rob_idx_0 = io_wakeup_ports_2_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ldq_idx_0 = io_wakeup_ports_2_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_stq_idx_0 = io_wakeup_ports_2_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_rxq_idx_0 = io_wakeup_ports_2_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_pdst_0 = io_wakeup_ports_2_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs1_0 = io_wakeup_ports_2_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs2_0 = io_wakeup_ports_2_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_prs3_0 = io_wakeup_ports_2_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_ppred_0 = io_wakeup_ports_2_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs1_busy_0 = io_wakeup_ports_2_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs2_busy_0 = io_wakeup_ports_2_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_prs3_busy_0 = io_wakeup_ports_2_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ppred_busy_0 = io_wakeup_ports_2_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_2_bits_uop_stale_pdst_0 = io_wakeup_ports_2_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_exception_0 = io_wakeup_ports_2_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_2_bits_uop_exc_cause_0 = io_wakeup_ports_2_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_mem_cmd_0 = io_wakeup_ports_2_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_mem_size_0 = io_wakeup_ports_2_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_mem_signed_0 = io_wakeup_ports_2_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_ldq_0 = io_wakeup_ports_2_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_uses_stq_0 = io_wakeup_ports_2_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_is_unique_0 = io_wakeup_ports_2_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_flush_on_commit_0 = io_wakeup_ports_2_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_csr_cmd_0 = io_wakeup_ports_2_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_2_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_ldst_0 = io_wakeup_ports_2_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs1_0 = io_wakeup_ports_2_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs2_0 = io_wakeup_ports_2_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_2_bits_uop_lrs3_0 = io_wakeup_ports_2_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_dst_rtype_0 = io_wakeup_ports_2_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs1_rtype_0 = io_wakeup_ports_2_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_lrs2_rtype_0 = io_wakeup_ports_2_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_frs3_en_0 = io_wakeup_ports_2_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fcn_dw_0 = io_wakeup_ports_2_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_2_bits_uop_fcn_op_0 = io_wakeup_ports_2_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_fp_val_0 = io_wakeup_ports_2_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_fp_rm_0 = io_wakeup_ports_2_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_2_bits_uop_fp_typ_0 = io_wakeup_ports_2_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_2_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_2_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_debug_if_0 = io_wakeup_ports_2_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_2_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_fsrc_0 = io_wakeup_ports_2_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_2_bits_uop_debug_tsrc_0 = io_wakeup_ports_2_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_inst_0 = io_wakeup_ports_3_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_3_bits_uop_debug_inst_0 = io_wakeup_ports_3_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rvc_0 = io_wakeup_ports_3_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_3_bits_uop_debug_pc_0 = io_wakeup_ports_3_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_0_0 = io_wakeup_ports_3_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_1_0 = io_wakeup_ports_3_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_2_0 = io_wakeup_ports_3_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iq_type_3_0 = io_wakeup_ports_3_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_0_0 = io_wakeup_ports_3_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_1_0 = io_wakeup_ports_3_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_2_0 = io_wakeup_ports_3_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_3_0 = io_wakeup_ports_3_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_4_0 = io_wakeup_ports_3_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_5_0 = io_wakeup_ports_3_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_6_0 = io_wakeup_ports_3_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_7_0 = io_wakeup_ports_3_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_8_0 = io_wakeup_ports_3_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fu_code_9_0 = io_wakeup_ports_3_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_0 = io_wakeup_ports_3_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_3_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_3_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_dis_col_sel_0 = io_wakeup_ports_3_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_3_bits_uop_br_mask_0 = io_wakeup_ports_3_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_tag_0 = io_wakeup_ports_3_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_3_bits_uop_br_type_0 = io_wakeup_ports_3_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfb_0 = io_wakeup_ports_3_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fence_0 = io_wakeup_ports_3_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_fencei_0 = io_wakeup_ports_3_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sfence_0 = io_wakeup_ports_3_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_amo_0 = io_wakeup_ports_3_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_eret_0 = io_wakeup_ports_3_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_3_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_rocc_0 = io_wakeup_ports_3_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_mov_0 = io_wakeup_ports_3_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ftq_idx_0 = io_wakeup_ports_3_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_edge_inst_0 = io_wakeup_ports_3_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_pc_lob_0 = io_wakeup_ports_3_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_taken_0 = io_wakeup_ports_3_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_imm_rename_0 = io_wakeup_ports_3_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_imm_sel_0 = io_wakeup_ports_3_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_pimm_0 = io_wakeup_ports_3_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_3_bits_uop_imm_packed_0 = io_wakeup_ports_3_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_op1_sel_0 = io_wakeup_ports_3_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_op2_sel_0 = io_wakeup_ports_3_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_3_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_rob_idx_0 = io_wakeup_ports_3_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ldq_idx_0 = io_wakeup_ports_3_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_stq_idx_0 = io_wakeup_ports_3_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_rxq_idx_0 = io_wakeup_ports_3_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_pdst_0 = io_wakeup_ports_3_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs1_0 = io_wakeup_ports_3_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs2_0 = io_wakeup_ports_3_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_prs3_0 = io_wakeup_ports_3_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_ppred_0 = io_wakeup_ports_3_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs1_busy_0 = io_wakeup_ports_3_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs2_busy_0 = io_wakeup_ports_3_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_prs3_busy_0 = io_wakeup_ports_3_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ppred_busy_0 = io_wakeup_ports_3_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_3_bits_uop_stale_pdst_0 = io_wakeup_ports_3_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_exception_0 = io_wakeup_ports_3_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_3_bits_uop_exc_cause_0 = io_wakeup_ports_3_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_mem_cmd_0 = io_wakeup_ports_3_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_mem_size_0 = io_wakeup_ports_3_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_mem_signed_0 = io_wakeup_ports_3_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_ldq_0 = io_wakeup_ports_3_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_uses_stq_0 = io_wakeup_ports_3_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_is_unique_0 = io_wakeup_ports_3_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_flush_on_commit_0 = io_wakeup_ports_3_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_csr_cmd_0 = io_wakeup_ports_3_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_3_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_ldst_0 = io_wakeup_ports_3_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs1_0 = io_wakeup_ports_3_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs2_0 = io_wakeup_ports_3_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_3_bits_uop_lrs3_0 = io_wakeup_ports_3_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_dst_rtype_0 = io_wakeup_ports_3_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs1_rtype_0 = io_wakeup_ports_3_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_lrs2_rtype_0 = io_wakeup_ports_3_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_frs3_en_0 = io_wakeup_ports_3_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fcn_dw_0 = io_wakeup_ports_3_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_3_bits_uop_fcn_op_0 = io_wakeup_ports_3_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_fp_val_0 = io_wakeup_ports_3_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_fp_rm_0 = io_wakeup_ports_3_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_3_bits_uop_fp_typ_0 = io_wakeup_ports_3_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_3_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_3_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_debug_if_0 = io_wakeup_ports_3_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_3_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_fsrc_0 = io_wakeup_ports_3_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_uop_debug_tsrc_0 = io_wakeup_ports_3_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_inst_0 = io_wakeup_ports_4_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_4_bits_uop_debug_inst_0 = io_wakeup_ports_4_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rvc_0 = io_wakeup_ports_4_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_4_bits_uop_debug_pc_0 = io_wakeup_ports_4_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_0_0 = io_wakeup_ports_4_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_1_0 = io_wakeup_ports_4_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_2_0 = io_wakeup_ports_4_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iq_type_3_0 = io_wakeup_ports_4_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_0_0 = io_wakeup_ports_4_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_1_0 = io_wakeup_ports_4_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_2_0 = io_wakeup_ports_4_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_3_0 = io_wakeup_ports_4_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_4_0 = io_wakeup_ports_4_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_5_0 = io_wakeup_ports_4_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_6_0 = io_wakeup_ports_4_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_7_0 = io_wakeup_ports_4_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_8_0 = io_wakeup_ports_4_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fu_code_9_0 = io_wakeup_ports_4_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_0 = io_wakeup_ports_4_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_4_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_4_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_dis_col_sel_0 = io_wakeup_ports_4_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [15:0] io_wakeup_ports_4_bits_uop_br_mask_0 = io_wakeup_ports_4_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_tag_0 = io_wakeup_ports_4_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_4_bits_uop_br_type_0 = io_wakeup_ports_4_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfb_0 = io_wakeup_ports_4_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fence_0 = io_wakeup_ports_4_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_fencei_0 = io_wakeup_ports_4_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sfence_0 = io_wakeup_ports_4_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_amo_0 = io_wakeup_ports_4_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_eret_0 = io_wakeup_ports_4_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_4_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_rocc_0 = io_wakeup_ports_4_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_mov_0 = io_wakeup_ports_4_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ftq_idx_0 = io_wakeup_ports_4_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_edge_inst_0 = io_wakeup_ports_4_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_pc_lob_0 = io_wakeup_ports_4_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_taken_0 = io_wakeup_ports_4_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_imm_rename_0 = io_wakeup_ports_4_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_imm_sel_0 = io_wakeup_ports_4_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_pimm_0 = io_wakeup_ports_4_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_4_bits_uop_imm_packed_0 = io_wakeup_ports_4_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_op1_sel_0 = io_wakeup_ports_4_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_op2_sel_0 = io_wakeup_ports_4_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_4_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_rob_idx_0 = io_wakeup_ports_4_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ldq_idx_0 = io_wakeup_ports_4_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_stq_idx_0 = io_wakeup_ports_4_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_rxq_idx_0 = io_wakeup_ports_4_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_pdst_0 = io_wakeup_ports_4_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs1_0 = io_wakeup_ports_4_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs2_0 = io_wakeup_ports_4_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_prs3_0 = io_wakeup_ports_4_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_ppred_0 = io_wakeup_ports_4_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs1_busy_0 = io_wakeup_ports_4_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs2_busy_0 = io_wakeup_ports_4_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_prs3_busy_0 = io_wakeup_ports_4_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ppred_busy_0 = io_wakeup_ports_4_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_4_bits_uop_stale_pdst_0 = io_wakeup_ports_4_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_exception_0 = io_wakeup_ports_4_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_4_bits_uop_exc_cause_0 = io_wakeup_ports_4_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_mem_cmd_0 = io_wakeup_ports_4_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_mem_size_0 = io_wakeup_ports_4_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_mem_signed_0 = io_wakeup_ports_4_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_ldq_0 = io_wakeup_ports_4_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_uses_stq_0 = io_wakeup_ports_4_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_is_unique_0 = io_wakeup_ports_4_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_flush_on_commit_0 = io_wakeup_ports_4_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_csr_cmd_0 = io_wakeup_ports_4_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_4_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_ldst_0 = io_wakeup_ports_4_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs1_0 = io_wakeup_ports_4_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs2_0 = io_wakeup_ports_4_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_4_bits_uop_lrs3_0 = io_wakeup_ports_4_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_dst_rtype_0 = io_wakeup_ports_4_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs1_rtype_0 = io_wakeup_ports_4_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_lrs2_rtype_0 = io_wakeup_ports_4_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_frs3_en_0 = io_wakeup_ports_4_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fcn_dw_0 = io_wakeup_ports_4_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_4_bits_uop_fcn_op_0 = io_wakeup_ports_4_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_fp_val_0 = io_wakeup_ports_4_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_fp_rm_0 = io_wakeup_ports_4_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_4_bits_uop_fp_typ_0 = io_wakeup_ports_4_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_4_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_4_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_debug_if_0 = io_wakeup_ports_4_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_4_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_fsrc_0 = io_wakeup_ports_4_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_uop_debug_tsrc_0 = io_wakeup_ports_4_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid_0 = io_pred_wakeup_port_valid; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits_0 = io_pred_wakeup_port_bits; // @[issue-slot.scala:49:7]
wire [2:0] io_child_rebusys_0 = io_child_rebusys; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_clear = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_2_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_2 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_3 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_4 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_2 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_3 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_4 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _iss_ready_T_6 = 1'h0; // @[issue-slot.scala:136:131]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [2:0] io_wakeup_ports_1_bits_speculative_mask = 3'h0; // @[issue-slot.scala:49:7]
wire [2:0] _next_uop_iw_p1_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire [2:0] _next_uop_iw_p2_speculative_child_T_1 = 3'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_2_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_3_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_4_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire _iss_ready_T_7 = 1'h1; // @[issue-slot.scala:136:110]
wire [2:0] io_wakeup_ports_2_bits_speculative_mask = 3'h1; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_3_bits_speculative_mask = 3'h2; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_4_bits_speculative_mask = 3'h4; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p1_speculative_child; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_iw_p2_speculative_child; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [15:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [2:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [2:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [15:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_speculative_child_0 = next_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_speculative_child_0 = next_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [15:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_55( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_65 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
|
module dataMems_77( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File AsyncResetReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
/** This black-boxes an Async Reset
* (or Set)
* Register.
*
* Because Chisel doesn't support
* parameterized black boxes,
* we unfortunately have to
* instantiate a number of these.
*
* We also have to hard-code the set/
* reset behavior.
*
* Do not confuse an asynchronous
* reset signal with an asynchronously
* reset reg. You should still
* properly synchronize your reset
* deassertion.
*
* @param d Data input
* @param q Data Output
* @param clk Clock Input
* @param rst Reset Input
* @param en Write Enable Input
*
*/
class AsyncResetReg(resetValue: Int = 0) extends RawModule {
val io = IO(new Bundle {
val d = Input(Bool())
val q = Output(Bool())
val en = Input(Bool())
val clk = Input(Clock())
val rst = Input(Reset())
})
val reg = withClockAndReset(io.clk, io.rst.asAsyncReset)(RegInit(resetValue.U(1.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
class SimpleRegIO(val w: Int) extends Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
}
class AsyncResetRegVec(val w: Int, val init: BigInt) extends Module {
override def desiredName = s"AsyncResetRegVec_w${w}_i${init}"
val io = IO(new SimpleRegIO(w))
val reg = withReset(reset.asAsyncReset)(RegInit(init.U(w.W)))
when (io.en) {
reg := io.d
}
io.q := reg
}
object AsyncResetReg {
// Create Single Registers
def apply(d: Bool, clk: Clock, rst: Bool, init: Boolean, name: Option[String]): Bool = {
val reg = Module(new AsyncResetReg(if (init) 1 else 0))
reg.io.d := d
reg.io.clk := clk
reg.io.rst := rst
reg.io.en := true.B
name.foreach(reg.suggestName(_))
reg.io.q
}
def apply(d: Bool, clk: Clock, rst: Bool): Bool = apply(d, clk, rst, false, None)
def apply(d: Bool, clk: Clock, rst: Bool, name: String): Bool = apply(d, clk, rst, false, Some(name))
// Create Vectors of Registers
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: Option[String] = None): UInt = {
val w = updateData.getWidth max resetData.bitLength
val reg = Module(new AsyncResetRegVec(w, resetData))
name.foreach(reg.suggestName(_))
reg.io.d := updateData
reg.io.en := enable
reg.io.q
}
def apply(updateData: UInt, resetData: BigInt, enable: Bool, name: String): UInt = apply(updateData,
resetData, enable, Some(name))
def apply(updateData: UInt, resetData: BigInt): UInt = apply(updateData, resetData, enable = true.B)
def apply(updateData: UInt, resetData: BigInt, name: String): UInt = apply(updateData, resetData, enable = true.B, Some(name))
def apply(updateData: UInt, enable: Bool): UInt = apply(updateData, resetData=BigInt(0), enable)
def apply(updateData: UInt, enable: Bool, name: String): UInt = apply(updateData, resetData = BigInt(0), enable, Some(name))
def apply(updateData: UInt): UInt = apply(updateData, resetData = BigInt(0), enable = true.B)
def apply(updateData: UInt, name:String): UInt = apply(updateData, resetData = BigInt(0), enable = true.B, Some(name))
}
|
module AsyncResetRegVec_w1_i0_12( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset, // @[AsyncResetReg.scala:56:7]
input io_d, // @[AsyncResetReg.scala:59:14]
output io_q // @[AsyncResetReg.scala:59:14]
);
wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7]
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_q_0; // @[AsyncResetReg.scala:56:7]
reg reg_0; // @[AsyncResetReg.scala:61:50]
assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29]
if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29]
reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50]
else // @[AsyncResetReg.scala:56:7]
reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50]
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
|
module OptimizationBarrier_TLBEntryData_58( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Crossing.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.interrupts
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.{SynchronizerShiftReg, AsyncResetReg}
@deprecated("IntXing does not ensure interrupt source is glitch free. Use IntSyncSource and IntSyncSink", "rocket-chip 1.2")
class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val intnode = IntAdapterNode()
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(intnode.in zip intnode.out) foreach { case ((in, _), (out, _)) =>
out := SynchronizerShiftReg(in, sync)
}
}
}
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSourceNode(alreadyRegistered)
lazy val module = if (alreadyRegistered) (new ImplRegistered) else (new Impl)
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := AsyncResetReg(Cat(in.reverse)).asBools
}
}
class ImplRegistered extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.sync.size).getOrElse(0)
override def desiredName = s"IntSyncCrossingSource_n${node.out.size}x${outSize}_Registered"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.sync := in
}
}
}
object IntSyncCrossingSink
{
@deprecated("IntSyncCrossingSink which used the `sync` parameter to determine crossing type is deprecated. Use IntSyncAsyncCrossingSink, IntSyncRationalCrossingSink, or IntSyncSyncCrossingSink instead for > 1, 1, and 0 sync values respectively", "rocket-chip 1.2")
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncAsyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(sync)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = s"IntSyncAsyncCrossingSink_n${node.out.size}x${node.out.head._1.size}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := SynchronizerShiftReg(in.sync, sync)
}
}
}
object IntSyncAsyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncAsyncCrossingSink(sync))
intsink.node
}
}
class IntSyncSyncCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(0)
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncSyncCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := in.sync
}
}
}
object IntSyncSyncCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncSyncCrossingSink())
intsink.node
}
}
class IntSyncRationalCrossingSink()(implicit p: Parameters) extends LazyModule
{
val node = IntSyncSinkNode(1)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def outSize = node.out.headOption.map(_._1.size).getOrElse(0)
override def desiredName = s"IntSyncRationalCrossingSink_n${node.out.size}x${outSize}"
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out := RegNext(in.sync)
}
}
}
object IntSyncRationalCrossingSink
{
def apply()(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncRationalCrossingSink())
intsink.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
|
module IntSyncSyncCrossingSink_n1x1_13( // @[Crossing.scala:96:9]
input auto_in_sync_0, // @[LazyModuleImp.scala:107:25]
output auto_out_0 // @[LazyModuleImp.scala:107:25]
);
wire auto_in_sync_0_0 = auto_in_sync_0; // @[Crossing.scala:96:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire nodeIn_sync_0 = auto_in_sync_0_0; // @[Crossing.scala:96:9]
wire nodeOut_0; // @[MixedNode.scala:542:17]
wire auto_out_0_0; // @[Crossing.scala:96:9]
assign nodeOut_0 = nodeIn_sync_0; // @[MixedNode.scala:542:17, :551:17]
assign auto_out_0_0 = nodeOut_0; // @[Crossing.scala:96:9]
assign auto_out_0 = auto_out_0_0; // @[Crossing.scala:96:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File WidthWidget.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.AddressSet
import freechips.rocketchip.util.{Repeater, UIntToOH1}
// innBeatBytes => the new client-facing bus width
class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyModule
{
private def noChangeRequired(manager: TLManagerPortParameters) = manager.beatBytes == innerBeatBytes
val node = new TLAdapterNode(
clientFn = { case c => c },
managerFn = { case m => m.v1copy(beatBytes = innerBeatBytes) }){
override def circuitIdentity = edges.out.map(_.manager).forall(noChangeRequired)
}
override lazy val desiredName = s"TLWidthWidget$innerBeatBytes"
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def merge[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T]) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = outBytes / inBytes
val keepBits = log2Ceil(outBytes)
val dropBits = log2Ceil(inBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
val enable = Seq.tabulate(ratio) { i => !((count ^ i.U) & limit).orR }
val corrupt_reg = RegInit(false.B)
val corrupt_in = edgeIn.corrupt(in.bits)
val corrupt_out = corrupt_in || corrupt_reg
when (in.fire) {
count := count + 1.U
corrupt_reg := corrupt_out
when (last) {
count := 0.U
corrupt_reg := false.B
}
}
def helper(idata: UInt): UInt = {
// rdata is X until the first time a multi-beat write occurs.
// Prevent the X from leaking outside by jamming the mux control until
// the first time rdata is written (and hence no longer X).
val rdata_written_once = RegInit(false.B)
val masked_enable = enable.map(_ || !rdata_written_once)
val odata = Seq.fill(ratio) { WireInit(idata) }
val rdata = Reg(Vec(ratio-1, chiselTypeOf(idata)))
val pdata = rdata :+ idata
val mdata = (masked_enable zip (odata zip pdata)) map { case (e, (o, p)) => Mux(e, o, p) }
when (in.fire && !last) {
rdata_written_once := true.B
(rdata zip mdata) foreach { case (r, m) => r := m }
}
Cat(mdata.reverse)
}
in.ready := out.ready || !last
out.valid := in.valid && last
out.bits := in.bits
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits)))
edgeOut.corrupt(out.bits) := corrupt_out
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleB, i: TLBundleB) => o.mask := edgeOut.mask(o.address, o.size) & Mux(hasData, helper(i.mask), ~0.U(outBytes.W))
case (o: TLBundleC, i: TLBundleC) => ()
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossible bundle combination in WidthWidget")
}
}
def split[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
val inBytes = edgeIn.manager.beatBytes
val outBytes = edgeOut.manager.beatBytes
val ratio = inBytes / outBytes
val keepBits = log2Ceil(inBytes)
val dropBits = log2Ceil(outBytes)
val countBits = log2Ceil(ratio)
val size = edgeIn.size(in.bits)
val hasData = edgeIn.hasData(in.bits)
val limit = UIntToOH1(size, keepBits) >> dropBits
val count = RegInit(0.U(countBits.W))
val first = count === 0.U
val last = count === limit || !hasData
when (out.fire) {
count := count + 1.U
when (last) { count := 0.U }
}
// For sub-beat transfer, extract which part matters
val sel = in.bits match {
case a: TLBundleA => a.address(keepBits-1, dropBits)
case b: TLBundleB => b.address(keepBits-1, dropBits)
case c: TLBundleC => c.address(keepBits-1, dropBits)
case d: TLBundleD => {
val sel = sourceMap(d.source)
val hold = Mux(first, sel, RegEnable(sel, first)) // a_first is not for whole xfer
hold & ~limit // if more than one a_first/xfer, the address must be aligned anyway
}
}
val index = sel | count
def helper(idata: UInt, width: Int): UInt = {
val mux = VecInit.tabulate(ratio) { i => idata((i+1)*outBytes*width-1, i*outBytes*width) }
mux(index)
}
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
// Don't put down hardware if we never carry data
edgeOut.data(out.bits) := (if (edgeIn.staticHasData(in.bits) == Some(false)) 0.U else helper(edgeIn.data(in.bits), 8))
(out.bits, in.bits) match {
case (o: TLBundleA, i: TLBundleA) => o.mask := helper(i.mask, 1)
case (o: TLBundleB, i: TLBundleB) => o.mask := helper(i.mask, 1)
case (o: TLBundleC, i: TLBundleC) => () // replicating corrupt to all beats is ok
case (o: TLBundleD, i: TLBundleD) => ()
case _ => require(false, "Impossbile bundle combination in WidthWidget")
}
// Repeat the input if we're not last
!last
}
def splice[T <: TLDataChannel](edgeIn: TLEdge, in: DecoupledIO[T], edgeOut: TLEdge, out: DecoupledIO[T], sourceMap: UInt => UInt) = {
if (edgeIn.manager.beatBytes == edgeOut.manager.beatBytes) {
// nothing to do; pass it through
out.bits := in.bits
out.valid := in.valid
in.ready := out.ready
} else if (edgeIn.manager.beatBytes > edgeOut.manager.beatBytes) {
// split input to output
val repeat = Wire(Bool())
val repeated = Repeater(in, repeat)
val cated = Wire(chiselTypeOf(repeated))
cated <> repeated
edgeIn.data(cated.bits) := Cat(
edgeIn.data(repeated.bits)(edgeIn.manager.beatBytes*8-1, edgeOut.manager.beatBytes*8),
edgeIn.data(in.bits)(edgeOut.manager.beatBytes*8-1, 0))
repeat := split(edgeIn, cated, edgeOut, out, sourceMap)
} else {
// merge input to output
merge(edgeIn, in, edgeOut, out)
}
}
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// If the master is narrower than the slave, the D channel must be narrowed.
// This is tricky, because the D channel has no address data.
// Thus, you don't know which part of a sub-beat transfer to extract.
// To fix this, we record the relevant address bits for all sources.
// The assumption is that this sort of situation happens only where
// you connect a narrow master to the system bus, so there are few sources.
def sourceMap(source_bits: UInt) = {
val source = if (edgeIn.client.endSourceId == 1) 0.U(0.W) else source_bits
require (edgeOut.manager.beatBytes > edgeIn.manager.beatBytes)
val keepBits = log2Ceil(edgeOut.manager.beatBytes)
val dropBits = log2Ceil(edgeIn.manager.beatBytes)
val sources = Reg(Vec(edgeIn.client.endSourceId, UInt((keepBits-dropBits).W)))
val a_sel = in.a.bits.address(keepBits-1, dropBits)
when (in.a.fire) {
if (edgeIn.client.endSourceId == 1) { // avoid extraction-index-width warning
sources(0) := a_sel
} else {
sources(in.a.bits.source) := a_sel
}
}
// depopulate unused source registers:
edgeIn.client.unusedSources.foreach { id => sources(id) := 0.U }
val bypass = in.a.valid && in.a.bits.source === source
if (edgeIn.manager.minLatency > 0) sources(source)
else Mux(bypass, a_sel, sources(source))
}
splice(edgeIn, in.a, edgeOut, out.a, sourceMap)
splice(edgeOut, out.d, edgeIn, in.d, sourceMap)
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
splice(edgeOut, out.b, edgeIn, in.b, sourceMap)
splice(edgeIn, in.c, edgeOut, out.c, sourceMap)
out.e.valid := in.e.valid
out.e.bits := in.e.bits
in.e.ready := out.e.ready
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLWidthWidget
{
def apply(innerBeatBytes: Int)(implicit p: Parameters): TLNode =
{
val widget = LazyModule(new TLWidthWidget(innerBeatBytes))
widget.node
}
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper.beatBytes)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMWidthWidgetTest(little: Int, big: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMWidthWidget(little,big,txns)).module)
dut.io.start := DontCare
io.finished := dut.io.finished
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Repeater.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{Decoupled, DecoupledIO}
// A Repeater passes its input to its output, unless repeat is asserted.
// When repeat is asserted, the Repeater copies the input and repeats it next cycle.
class Repeater[T <: Data](gen: T) extends Module
{
override def desiredName = s"Repeater_${gen.typeName}"
val io = IO( new Bundle {
val repeat = Input(Bool())
val full = Output(Bool())
val enq = Flipped(Decoupled(gen.cloneType))
val deq = Decoupled(gen.cloneType)
} )
val full = RegInit(false.B)
val saved = Reg(gen.cloneType)
// When !full, a repeater is pass-through
io.deq.valid := io.enq.valid || full
io.enq.ready := io.deq.ready && !full
io.deq.bits := Mux(full, saved, io.enq.bits)
io.full := full
when (io.enq.fire && io.repeat) { full := true.B; saved := io.enq.bits }
when (io.deq.fire && !io.repeat) { full := false.B }
}
object Repeater
{
def apply[T <: Data](enq: DecoupledIO[T], repeat: Bool): DecoupledIO[T] = {
val repeater = Module(new Repeater(chiselTypeOf(enq.bits)))
repeater.io.repeat := repeat
repeater.io.enq <> enq
repeater.io.deq
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
|
module TLWidthWidget16( // @[WidthWidget.scala:27:9]
input clock, // @[WidthWidget.scala:27:9]
input reset, // @[WidthWidget.scala:27:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [127:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26]
wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [28:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [15:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [127:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [6:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [28:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [15:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [127:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [6:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [6:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [28:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [6:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [63:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
wire [6:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
wire [127:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
wire [6:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
wire [28:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
wire [7:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
wire [63:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9]
wire _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [127:0] _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
wire corrupt_out; // @[WidthWidget.scala:47:36]
assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire cated_ready = anonOut_a_ready; // @[WidthWidget.scala:161:25]
wire cated_valid; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] cated_bits_param; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
wire [6:0] cated_bits_source; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
wire [28:0] cated_bits_address; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
wire cated_bits_corrupt; // @[WidthWidget.scala:161:25]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9]
wire _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign anonIn_d_bits_opcode = anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_param = anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_size = anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_source = anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_sink = anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign anonIn_d_bits_denied = anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] anonIn_d_bits_data_odata_0 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire [63:0] anonIn_d_bits_data_odata_1 = anonOut_d_bits_data; // @[WidthWidget.scala:65:47]
wire _repeat_T_1; // @[WidthWidget.scala:148:7]
wire repeat_0; // @[WidthWidget.scala:159:26]
assign anonOut_a_valid = cated_valid; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25]
assign anonOut_a_bits_address = cated_bits_address; // @[WidthWidget.scala:161:25]
wire [127:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39]
assign anonOut_a_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25]
wire [15:0] cated_bits_mask; // @[WidthWidget.scala:161:25]
wire [127:0] cated_bits_data; // @[WidthWidget.scala:161:25]
wire [63:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[127:64]; // @[Repeater.scala:36:26]
wire [63:0] _cated_bits_data_T_1 = anonIn_a_bits_data[63:0]; // @[WidthWidget.scala:165:31]
assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31]
assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39]
wire _repeat_hasData_opdata_T = cated_bits_opcode[2]; // @[WidthWidget.scala:161:25]
wire repeat_hasData = ~_repeat_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire [18:0] _repeat_limit_T = 19'hF << cated_bits_size; // @[package.scala:243:71]
wire [3:0] _repeat_limit_T_1 = _repeat_limit_T[3:0]; // @[package.scala:243:{71,76}]
wire [3:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}]
wire repeat_limit = _repeat_limit_T_2[3]; // @[package.scala:243:46]
reg repeat_count; // @[WidthWidget.scala:105:26]
wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25]
wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25]
wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38]
wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}]
wire _repeat_T = anonOut_a_ready & anonOut_a_valid; // @[Decoupled.scala:51:35]
wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24]
wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24]
wire repeat_sel = cated_bits_address[3]; // @[WidthWidget.scala:116:39, :161:25]
wire repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :116:39, :126:24]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_0 = _repeat_anonOut_a_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [63:0] _repeat_anonOut_a_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25]
wire [63:0] repeat_anonOut_a_bits_data_mux_1 = _repeat_anonOut_a_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
assign anonOut_a_bits_data = repeat_index ? repeat_anonOut_a_bits_data_mux_1 : repeat_anonOut_a_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T = cated_bits_mask[7:0]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_0 = _repeat_anonOut_a_bits_mask_mux_T; // @[WidthWidget.scala:128:{43,55}]
wire [7:0] _repeat_anonOut_a_bits_mask_mux_T_1 = cated_bits_mask[15:8]; // @[WidthWidget.scala:128:55, :161:25]
wire [7:0] repeat_anonOut_a_bits_mask_mux_1 = _repeat_anonOut_a_bits_mask_mux_T_1; // @[WidthWidget.scala:128:{43,55}]
assign anonOut_a_bits_mask = repeat_index ? repeat_anonOut_a_bits_mask_mux_1 : repeat_anonOut_a_bits_mask_mux_0; // @[WidthWidget.scala:126:24, :128:43, :140:53]
assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7]
assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26]
wire hasData = anonOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [18:0] _limit_T = 19'hF << anonOut_d_bits_size; // @[package.scala:243:71]
wire [3:0] _limit_T_1 = _limit_T[3:0]; // @[package.scala:243:{71,76}]
wire [3:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}]
wire limit = _limit_T_2[3]; // @[package.scala:243:46]
reg count; // @[WidthWidget.scala:40:27]
wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56]
wire first = ~count; // @[WidthWidget.scala:40:27, :41:26]
wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26]
wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39]
wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}]
wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}]
wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}]
wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56]
wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}]
wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}]
wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}]
reg corrupt_reg; // @[WidthWidget.scala:45:32]
assign corrupt_out = anonOut_d_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36]
assign anonIn_d_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36]
wire _anonIn_d_bits_data_T = anonOut_d_ready & anonOut_d_valid; // @[Decoupled.scala:51:35]
wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24]
wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24]
wire _anonOut_d_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32]
assign _anonOut_d_ready_T_1 = anonIn_d_ready | _anonOut_d_ready_T; // @[WidthWidget.scala:76:{29,32}]
assign anonOut_d_ready = _anonOut_d_ready_T_1; // @[WidthWidget.scala:76:29]
assign _anonIn_d_valid_T = anonOut_d_valid & last; // @[WidthWidget.scala:42:36, :77:29]
assign anonIn_d_valid = _anonIn_d_valid_T; // @[WidthWidget.scala:77:29]
reg anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41]
wire _anonIn_d_bits_data_masked_enable_T = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_0 = enable_0 | _anonIn_d_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}]
wire _anonIn_d_bits_data_masked_enable_T_1 = ~anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45]
wire anonIn_d_bits_data_masked_enable_1 = enable_1 | _anonIn_d_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}]
reg [63:0] anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:66:24]
wire [63:0] anonIn_d_bits_data_mdata_0 = anonIn_d_bits_data_masked_enable_0 ? anonIn_d_bits_data_odata_0 : anonIn_d_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88]
wire [63:0] anonIn_d_bits_data_mdata_1 = anonIn_d_bits_data_masked_enable_1 ? anonIn_d_bits_data_odata_1 : anonOut_d_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88]
wire _anonIn_d_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32]
wire _anonIn_d_bits_data_T_2 = _anonIn_d_bits_data_T & _anonIn_d_bits_data_T_1; // @[Decoupled.scala:51:35]
assign _anonIn_d_bits_data_T_3 = {anonIn_d_bits_data_mdata_1, anonIn_d_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12]
assign anonIn_d_bits_data = _anonIn_d_bits_data_T_3; // @[WidthWidget.scala:73:12]
always @(posedge clock) begin // @[WidthWidget.scala:27:9]
if (reset) begin // @[WidthWidget.scala:27:9]
repeat_count <= 1'h0; // @[WidthWidget.scala:105:26]
count <= 1'h0; // @[WidthWidget.scala:40:27]
corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32]
anonIn_d_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41]
end
else begin // @[WidthWidget.scala:27:9]
if (_repeat_T) // @[Decoupled.scala:51:35]
repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}]
if (_anonIn_d_bits_data_T) begin // @[Decoupled.scala:51:35]
count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17]
corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23]
end
anonIn_d_bits_data_rdata_written_once <= _anonIn_d_bits_data_T_2 | anonIn_d_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30]
end
if (_anonIn_d_bits_data_T_2) // @[WidthWidget.scala:69:23]
anonIn_d_bits_data_rdata_0 <= anonIn_d_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88]
always @(posedge)
TLMonitor_3 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Repeater_TLBundleA_a29d128s7k1z4u repeated_repeater ( // @[Repeater.scala:36:26]
.clock (clock),
.reset (reset),
.io_repeat (repeat_0), // @[WidthWidget.scala:159:26]
.io_enq_ready (anonIn_a_ready),
.io_enq_valid (anonIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25]
.io_deq_valid (cated_valid),
.io_deq_bits_opcode (cated_bits_opcode),
.io_deq_bits_param (cated_bits_param),
.io_deq_bits_size (cated_bits_size),
.io_deq_bits_source (cated_bits_source),
.io_deq_bits_address (cated_bits_address),
.io_deq_bits_mask (cated_bits_mask),
.io_deq_bits_data (_repeated_repeater_io_deq_bits_data),
.io_deq_bits_corrupt (cated_bits_corrupt)
); // @[Repeater.scala:36:26]
assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9]
assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File InputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class AbstractInputUnitIO(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams],
)(implicit val p: Parameters) extends Bundle with HasRouterOutputParams {
val nodeId = cParam.destId
val router_req = Decoupled(new RouteComputerReq)
val router_resp = Input(new RouteComputerResp(outParams, egressParams))
val vcalloc_req = Decoupled(new VCAllocReq(cParam, outParams, egressParams))
val vcalloc_resp = Input(new VCAllocResp(outParams, egressParams))
val out_credit_available = Input(MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) }))
val salloc_req = Vec(cParam.destSpeedup, Decoupled(new SwitchAllocReq(outParams, egressParams)))
val out = Vec(cParam.destSpeedup, Valid(new SwitchBundle(outParams, egressParams)))
val debug = Output(new Bundle {
val va_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
val sa_stall = UInt(log2Ceil(cParam.nVirtualChannels).W)
})
val block = Input(Bool())
}
abstract class AbstractInputUnit(
val cParam: BaseChannelParams,
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module with HasRouterOutputParams with HasNoCParams {
val nodeId = cParam.destId
def io: AbstractInputUnitIO
}
class InputBuffer(cParam: ChannelParams)(implicit p: Parameters) extends Module {
val nVirtualChannels = cParam.nVirtualChannels
val io = IO(new Bundle {
val enq = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val deq = Vec(cParam.nVirtualChannels, Decoupled(new BaseFlit(cParam.payloadBits)))
})
val useOutputQueues = cParam.useOutputQueues
val delims = if (useOutputQueues) {
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize else 0).scanLeft(0)(_+_)
} else {
// If no queuing, have to add an additional slot since head == tail implies empty
// TODO this should be fixed, should use all slots available
cParam.virtualChannelParams.map(u => if (u.traversable) u.bufferSize + 1 else 0).scanLeft(0)(_+_)
}
val starts = delims.dropRight(1).zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val ends = delims.tail.zipWithIndex.map { case (s,i) =>
if (cParam.virtualChannelParams(i).traversable) s else 0
}
val fullSize = delims.last
// Ugly case. Use multiple queues
if ((cParam.srcSpeedup > 1 || cParam.destSpeedup > 1 || fullSize <= 1) || !cParam.unifiedBuffer) {
require(useOutputQueues)
val qs = cParam.virtualChannelParams.map(v => Module(new Queue(new BaseFlit(cParam.payloadBits), v.bufferSize)))
qs.zipWithIndex.foreach { case (q,i) =>
val sel = io.enq.map(f => f.valid && f.bits.virt_channel_id === i.U)
q.io.enq.valid := sel.orR
q.io.enq.bits.head := Mux1H(sel, io.enq.map(_.bits.head))
q.io.enq.bits.tail := Mux1H(sel, io.enq.map(_.bits.tail))
q.io.enq.bits.payload := Mux1H(sel, io.enq.map(_.bits.payload))
io.deq(i) <> q.io.deq
}
} else {
val mem = Mem(fullSize, new BaseFlit(cParam.payloadBits))
val heads = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val tails = RegInit(VecInit(starts.map(_.U(log2Ceil(fullSize).W))))
val empty = (heads zip tails).map(t => t._1 === t._2)
val qs = Seq.fill(nVirtualChannels) { Module(new Queue(new BaseFlit(cParam.payloadBits), 1, pipe=true)) }
qs.foreach(_.io.enq.valid := false.B)
qs.foreach(_.io.enq.bits := DontCare)
val vc_sel = UIntToOH(io.enq(0).bits.virt_channel_id)
val flit = Wire(new BaseFlit(cParam.payloadBits))
val direct_to_q = (Mux1H(vc_sel, qs.map(_.io.enq.ready)) && Mux1H(vc_sel, empty)) && useOutputQueues.B
flit.head := io.enq(0).bits.head
flit.tail := io.enq(0).bits.tail
flit.payload := io.enq(0).bits.payload
when (io.enq(0).valid && !direct_to_q) {
val tail = tails(io.enq(0).bits.virt_channel_id)
mem.write(tail, flit)
tails(io.enq(0).bits.virt_channel_id) := Mux(
tail === Mux1H(vc_sel, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(vc_sel, starts.map(_.U)),
tail + 1.U)
} .elsewhen (io.enq(0).valid && direct_to_q) {
for (i <- 0 until nVirtualChannels) {
when (io.enq(0).bits.virt_channel_id === i.U) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := flit
}
}
}
if (useOutputQueues) {
val can_to_q = (0 until nVirtualChannels).map { i => !empty(i) && qs(i).io.enq.ready }
val to_q_oh = PriorityEncoderOH(can_to_q)
val to_q = OHToUInt(to_q_oh)
when (can_to_q.orR) {
val head = Mux1H(to_q_oh, heads)
heads(to_q) := Mux(
head === Mux1H(to_q_oh, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(to_q_oh, starts.map(_.U)),
head + 1.U)
for (i <- 0 until nVirtualChannels) {
when (to_q_oh(i)) {
qs(i).io.enq.valid := true.B
qs(i).io.enq.bits := mem.read(head)
}
}
}
for (i <- 0 until nVirtualChannels) {
io.deq(i) <> qs(i).io.deq
}
} else {
qs.map(_.io.deq.ready := false.B)
val ready_sel = io.deq.map(_.ready)
val fire = io.deq.map(_.fire)
assert(PopCount(fire) <= 1.U)
val head = Mux1H(fire, heads)
when (fire.orR) {
val fire_idx = OHToUInt(fire)
heads(fire_idx) := Mux(
head === Mux1H(fire, ends.map(_ - 1).map(_ max 0).map(_.U)),
Mux1H(fire, starts.map(_.U)),
head + 1.U)
}
val read_flit = mem.read(head)
for (i <- 0 until nVirtualChannels) {
io.deq(i).valid := !empty(i)
io.deq(i).bits := read_flit
}
}
}
}
class InputUnit(cParam: ChannelParams, outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean, combineSAST: Boolean
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
val nVirtualChannels = cParam.nVirtualChannels
val virtualChannelParams = cParam.virtualChannelParams
class InputUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(new Channel(cParam.asInstanceOf[ChannelParams]))
}
val io = IO(new InputUnitIO)
val g_i :: g_r :: g_v :: g_a :: g_c :: Nil = Enum(5)
class InputState extends Bundle {
val g = UInt(3.W)
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
val flow = new FlowRoutingBundle
val fifo_deps = UInt(nVirtualChannels.W)
}
val input_buffer = Module(new InputBuffer(cParam))
for (i <- 0 until cParam.srcSpeedup) {
input_buffer.io.enq(i) := io.in.flit(i)
}
input_buffer.io.deq.foreach(_.ready := false.B)
val route_arbiter = Module(new Arbiter(
new RouteComputerReq, nVirtualChannels
))
io.router_req <> route_arbiter.io.out
val states = Reg(Vec(nVirtualChannels, new InputState))
val anyFifo = cParam.possibleFlows.map(_.fifo).reduce(_||_)
val allFifo = cParam.possibleFlows.map(_.fifo).reduce(_&&_)
if (anyFifo) {
val idle_mask = VecInit(states.map(_.g === g_i)).asUInt
for (s <- states)
for (i <- 0 until nVirtualChannels)
s.fifo_deps := s.fifo_deps & ~idle_mask
}
for (i <- 0 until cParam.srcSpeedup) {
when (io.in.flit(i).fire && io.in.flit(i).bits.head) {
val id = io.in.flit(i).bits.virt_channel_id
assert(id < nVirtualChannels.U)
assert(states(id).g === g_i)
val at_dest = io.in.flit(i).bits.flow.egress_node === nodeId.U
states(id).g := Mux(at_dest, g_v, g_r)
states(id).vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (o.U === io.in.flit(i).bits.flow.egress_node_id) {
states(id).vc_sel(o+nOutputs)(0) := true.B
}
}
states(id).flow := io.in.flit(i).bits.flow
if (anyFifo) {
val fifo = cParam.possibleFlows.filter(_.fifo).map(_.isFlow(io.in.flit(i).bits.flow)).toSeq.orR
states(id).fifo_deps := VecInit(states.zipWithIndex.map { case (s, j) =>
s.g =/= g_i && s.flow.asUInt === io.in.flit(i).bits.flow.asUInt && j.U =/= id
}).asUInt
}
}
}
(route_arbiter.io.in zip states).zipWithIndex.map { case ((i,s),idx) =>
if (virtualChannelParams(idx).traversable) {
i.valid := s.g === g_r
i.bits.flow := s.flow
i.bits.src_virt_id := idx.U
when (i.fire) { s.g := g_v }
} else {
i.valid := false.B
i.bits := DontCare
}
}
when (io.router_req.fire) {
val id = io.router_req.bits.src_virt_id
assert(states(id).g === g_r)
states(id).g := g_v
for (i <- 0 until nVirtualChannels) {
when (i.U === id) {
states(i).vc_sel := io.router_resp.vc_sel
}
}
}
val mask = RegInit(0.U(nVirtualChannels.W))
val vcalloc_reqs = Wire(Vec(nVirtualChannels, new VCAllocReq(cParam, outParams, egressParams)))
val vcalloc_vals = Wire(Vec(nVirtualChannels, Bool()))
val vcalloc_filter = PriorityEncoderOH(Cat(vcalloc_vals.asUInt, vcalloc_vals.asUInt & ~mask))
val vcalloc_sel = vcalloc_filter(nVirtualChannels-1,0) | (vcalloc_filter >> nVirtualChannels)
// Prioritize incoming packetes
when (io.router_req.fire) {
mask := (1.U << io.router_req.bits.src_virt_id) - 1.U
} .elsewhen (vcalloc_vals.orR) {
mask := Mux1H(vcalloc_sel, (0 until nVirtualChannels).map { w => ~(0.U((w+1).W)) })
}
io.vcalloc_req.valid := vcalloc_vals.orR
io.vcalloc_req.bits := Mux1H(vcalloc_sel, vcalloc_reqs)
states.zipWithIndex.map { case (s,idx) =>
if (virtualChannelParams(idx).traversable) {
vcalloc_vals(idx) := s.g === g_v && s.fifo_deps === 0.U
vcalloc_reqs(idx).in_vc := idx.U
vcalloc_reqs(idx).vc_sel := s.vc_sel
vcalloc_reqs(idx).flow := s.flow
when (vcalloc_vals(idx) && vcalloc_sel(idx) && io.vcalloc_req.ready) { s.g := g_a }
if (combineRCVA) {
when (route_arbiter.io.in(idx).fire) {
vcalloc_vals(idx) := true.B
vcalloc_reqs(idx).vc_sel := io.router_resp.vc_sel
}
}
} else {
vcalloc_vals(idx) := false.B
vcalloc_reqs(idx) := DontCare
}
}
io.debug.va_stall := PopCount(vcalloc_vals) - io.vcalloc_req.ready
when (io.vcalloc_req.fire) {
for (i <- 0 until nVirtualChannels) {
when (vcalloc_sel(i)) {
states(i).vc_sel := io.vcalloc_resp.vc_sel
states(i).g := g_a
if (!combineRCVA) {
assert(states(i).g === g_v)
}
}
}
}
val salloc_arb = Module(new SwitchArbiter(
nVirtualChannels,
cParam.destSpeedup,
outParams, egressParams
))
(states zip salloc_arb.io.in).zipWithIndex.map { case ((s,r),i) =>
if (virtualChannelParams(i).traversable) {
val credit_available = (s.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
r.valid := s.g === g_a && credit_available && input_buffer.io.deq(i).valid
r.bits.vc_sel := s.vc_sel
val deq_tail = input_buffer.io.deq(i).bits.tail
r.bits.tail := deq_tail
when (r.fire && deq_tail) {
s.g := g_i
}
input_buffer.io.deq(i).ready := r.ready
} else {
r.valid := false.B
r.bits := DontCare
}
}
io.debug.sa_stall := PopCount(salloc_arb.io.in.map(r => r.valid && !r.ready))
io.salloc_req <> salloc_arb.io.out
when (io.block) {
salloc_arb.io.out.foreach(_.ready := false.B)
io.salloc_req.foreach(_.valid := false.B)
}
class OutBundle extends Bundle {
val valid = Bool()
val vid = UInt(virtualChannelBits.W)
val out_vid = UInt(log2Up(allOutParams.map(_.nVirtualChannels).max).W)
val flit = new Flit(cParam.payloadBits)
}
val salloc_outs = if (combineSAST) {
Wire(Vec(cParam.destSpeedup, new OutBundle))
} else {
Reg(Vec(cParam.destSpeedup, new OutBundle))
}
io.in.credit_return := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire, salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
io.in.vc_free := salloc_arb.io.out.zipWithIndex.map { case (o, i) =>
Mux(o.fire && Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail)),
salloc_arb.io.chosen_oh(i), 0.U)
}.reduce(_|_)
for (i <- 0 until cParam.destSpeedup) {
val salloc_out = salloc_outs(i)
salloc_out.valid := salloc_arb.io.out(i).fire
salloc_out.vid := OHToUInt(salloc_arb.io.chosen_oh(i))
val vc_sel = Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.vc_sel))
val channel_oh = vc_sel.map(_.reduce(_||_)).toSeq
val virt_channel = Mux1H(channel_oh, vc_sel.map(v => OHToUInt(v)).toSeq)
when (salloc_arb.io.out(i).fire) {
salloc_out.out_vid := virt_channel
salloc_out.flit.payload := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.payload))
salloc_out.flit.head := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.head))
salloc_out.flit.tail := Mux1H(salloc_arb.io.chosen_oh(i), input_buffer.io.deq.map(_.bits.tail))
salloc_out.flit.flow := Mux1H(salloc_arb.io.chosen_oh(i), states.map(_.flow))
} .otherwise {
salloc_out.out_vid := DontCare
salloc_out.flit := DontCare
}
salloc_out.flit.virt_channel_id := DontCare // this gets set in the switch
io.out(i).valid := salloc_out.valid
io.out(i).bits.flit := salloc_out.flit
io.out(i).bits.out_virt_channel := salloc_out.out_vid
}
def filterVCSel(sel: MixedVec[Vec[Bool]], srcV: Int) = {
if (virtualChannelParams(srcV).traversable) {
outParams.zipWithIndex.map { case (oP, oI) =>
(0 until oP.nVirtualChannels).map { oV =>
var allow = false
virtualChannelParams(srcV).possibleFlows.foreach { pI =>
allow = allow || routingRelation(
cParam.channelRoutingInfos(srcV),
oP.channelRoutingInfos(oV),
pI
)
}
if (!allow)
sel(oI)(oV) := false.B
}
}
}
}
(0 until nVirtualChannels).map { i =>
if (!virtualChannelParams(i).traversable) states(i) := DontCare
filterVCSel(states(i).vc_sel, i)
}
when (reset.asBool) {
states.foreach(_.g := g_i)
}
}
|
module InputUnit_126( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [3:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_8, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_9, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_8, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_9, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_8, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_3, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_4, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_5, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_6, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_7, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_9, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_8, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_9, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [3:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [3:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [9:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [9:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire vcalloc_vals_9; // @[InputUnit.scala:266:32]
wire _salloc_arb_io_in_9_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [9:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_9_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [3:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_8_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_8_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_9_bits_tail; // @[InputUnit.scala:181:28]
wire [72:0] _input_buffer_io_deq_9_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_9_g; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_0_8; // @[InputUnit.scala:192:19]
reg states_9_vc_sel_0_9; // @[InputUnit.scala:192:19]
reg [2:0] states_9_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_9_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_9_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_9_flow_egress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_9_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_9_valid = states_9_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
reg [9:0] mask; // @[InputUnit.scala:250:21]
wire [9:0] _vcalloc_filter_T_3 = {vcalloc_vals_9, 9'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32]
wire [19:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 20'h1 : _vcalloc_filter_T_3[1] ? 20'h2 : _vcalloc_filter_T_3[2] ? 20'h4 : _vcalloc_filter_T_3[3] ? 20'h8 : _vcalloc_filter_T_3[4] ? 20'h10 : _vcalloc_filter_T_3[5] ? 20'h20 : _vcalloc_filter_T_3[6] ? 20'h40 : _vcalloc_filter_T_3[7] ? 20'h80 : _vcalloc_filter_T_3[8] ? 20'h100 : _vcalloc_filter_T_3[9] ? 20'h200 : {vcalloc_vals_9, 19'h0}; // @[OneHot.scala:85:71]
wire [9:0] vcalloc_sel = vcalloc_filter[9:0] | vcalloc_filter[19:10]; // @[Mux.scala:50:70]
assign vcalloc_vals_9 = states_9_g == 3'h2; // @[InputUnit.scala:192:19, :266:32]
wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_9; // @[Decoupled.scala:51:35]
wire _GEN_1 = _GEN_0 & vcalloc_sel[9]; // @[Mux.scala:32:36]
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_53( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_57 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_77 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_25 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_31 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_32 = _source_ok_T_31 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_6 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_18 = _uncommonBits_T_18[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_25 = _uncommonBits_T_25[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_30 = _uncommonBits_T_30[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_31 = _uncommonBits_T_31[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_36 = _uncommonBits_T_36[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_37 = _uncommonBits_T_37[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_42 = _uncommonBits_T_42[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_43 = _uncommonBits_T_43[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_48 = _uncommonBits_T_48[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_48 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_48; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_49 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_55 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_50 = _source_ok_T_49 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_54; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_56 = _source_ok_T_55 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_58 = _source_ok_T_56; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_60; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_61 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_67 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_73 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_79 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_62 = _source_ok_T_61 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_66; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_68 = _source_ok_T_67 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_74 = _source_ok_T_73 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_78 = _source_ok_T_76; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_5 = _source_ok_T_78; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_80 = _source_ok_T_79 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire _source_ok_T_85 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31]
wire _source_ok_T_86 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_89 = _source_ok_T_88 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_90 = _source_ok_T_89 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_91 = _source_ok_T_90 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_95 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1115 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1115; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1115; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1183 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1183; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1183; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1183; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1048 = _T_1115 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1048 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1048 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1048 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1048 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1048 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1094 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1094 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1063 = _T_1183 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1063 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1063 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1063 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1159 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1159 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1141 = _T_1183 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1141 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1141 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1141 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
|
module BranchKillableQueue_4( // @[util.scala:458:7]
input clock, // @[util.scala:458:7]
input reset, // @[util.scala:458:7]
output io_enq_ready, // @[util.scala:463:14]
input io_enq_valid, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_inst, // @[util.scala:463:14]
input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:463:14]
input io_enq_bits_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_0, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_1, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_2, // @[util.scala:463:14]
input io_enq_bits_uop_iq_type_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_0, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_1, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_2, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_3, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_4, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_5, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_6, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_7, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_8, // @[util.scala:463:14]
input io_enq_bits_uop_fu_code_9, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_enq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_enq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dis_col_sel, // @[util.scala:463:14]
input [11:0] io_enq_bits_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_br_type, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfb, // @[util.scala:463:14]
input io_enq_bits_uop_is_fence, // @[util.scala:463:14]
input io_enq_bits_uop_is_fencei, // @[util.scala:463:14]
input io_enq_bits_uop_is_sfence, // @[util.scala:463:14]
input io_enq_bits_uop_is_amo, // @[util.scala:463:14]
input io_enq_bits_uop_is_eret, // @[util.scala:463:14]
input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_enq_bits_uop_is_rocc, // @[util.scala:463:14]
input io_enq_bits_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:463:14]
input io_enq_bits_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:463:14]
input io_enq_bits_uop_taken, // @[util.scala:463:14]
input io_enq_bits_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_pimm, // @[util.scala:463:14]
input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_op2_sel, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_enq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_enq_bits_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_pdst, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs1, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs2, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_prs3, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_ppred, // @[util.scala:463:14]
input io_enq_bits_uop_prs1_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs2_busy, // @[util.scala:463:14]
input io_enq_bits_uop_prs3_busy, // @[util.scala:463:14]
input io_enq_bits_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:463:14]
input io_enq_bits_uop_exception, // @[util.scala:463:14]
input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:463:14]
input io_enq_bits_uop_mem_signed, // @[util.scala:463:14]
input io_enq_bits_uop_uses_ldq, // @[util.scala:463:14]
input io_enq_bits_uop_uses_stq, // @[util.scala:463:14]
input io_enq_bits_uop_is_unique, // @[util.scala:463:14]
input io_enq_bits_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_csr_cmd, // @[util.scala:463:14]
input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_ldst, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
input io_enq_bits_uop_frs3_en, // @[util.scala:463:14]
input io_enq_bits_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_enq_bits_uop_fcn_op, // @[util.scala:463:14]
input io_enq_bits_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_enq_bits_uop_fp_typ, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_debug_if, // @[util.scala:463:14]
input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:463:14]
input [63:0] io_enq_bits_data, // @[util.scala:463:14]
input io_enq_bits_is_hella, // @[util.scala:463:14]
input io_deq_ready, // @[util.scala:463:14]
output io_deq_valid, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_inst, // @[util.scala:463:14]
output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:463:14]
output io_deq_bits_uop_is_rvc, // @[util.scala:463:14]
output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_0, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_1, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_2, // @[util.scala:463:14]
output io_deq_bits_uop_iq_type_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_0, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_1, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_2, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_3, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_4, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_5, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_6, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_7, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_8, // @[util.scala:463:14]
output io_deq_bits_uop_fu_code_9, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_agen, // @[util.scala:463:14]
output io_deq_bits_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_iw_p1_speculative_child, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_iw_p2_speculative_child, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
output io_deq_bits_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dis_col_sel, // @[util.scala:463:14]
output [11:0] io_deq_bits_uop_br_mask, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_br_type, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfb, // @[util.scala:463:14]
output io_deq_bits_uop_is_fence, // @[util.scala:463:14]
output io_deq_bits_uop_is_fencei, // @[util.scala:463:14]
output io_deq_bits_uop_is_sfence, // @[util.scala:463:14]
output io_deq_bits_uop_is_amo, // @[util.scala:463:14]
output io_deq_bits_uop_is_eret, // @[util.scala:463:14]
output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:463:14]
output io_deq_bits_uop_is_rocc, // @[util.scala:463:14]
output io_deq_bits_uop_is_mov, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:463:14]
output io_deq_bits_uop_edge_inst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:463:14]
output io_deq_bits_uop_taken, // @[util.scala:463:14]
output io_deq_bits_uop_imm_rename, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_imm_sel, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_pimm, // @[util.scala:463:14]
output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_op1_sel, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_op2_sel, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ldst, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wen, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren1, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren2, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_ren3, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap12, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_swap23, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fromint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_toint, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_fma, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_div, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_wflags, // @[util.scala:463:14]
output io_deq_bits_uop_fp_ctrl_vec, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_rob_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_ldq_idx, // @[util.scala:463:14]
output [3:0] io_deq_bits_uop_stq_idx, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_pdst, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs1, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs2, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_prs3, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_ppred, // @[util.scala:463:14]
output io_deq_bits_uop_prs1_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs2_busy, // @[util.scala:463:14]
output io_deq_bits_uop_prs3_busy, // @[util.scala:463:14]
output io_deq_bits_uop_ppred_busy, // @[util.scala:463:14]
output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:463:14]
output io_deq_bits_uop_exception, // @[util.scala:463:14]
output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:463:14]
output io_deq_bits_uop_mem_signed, // @[util.scala:463:14]
output io_deq_bits_uop_uses_ldq, // @[util.scala:463:14]
output io_deq_bits_uop_uses_stq, // @[util.scala:463:14]
output io_deq_bits_uop_is_unique, // @[util.scala:463:14]
output io_deq_bits_uop_flush_on_commit, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_csr_cmd, // @[util.scala:463:14]
output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_ldst, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:463:14]
output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:463:14]
output io_deq_bits_uop_frs3_en, // @[util.scala:463:14]
output io_deq_bits_uop_fcn_dw, // @[util.scala:463:14]
output [4:0] io_deq_bits_uop_fcn_op, // @[util.scala:463:14]
output io_deq_bits_uop_fp_val, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_fp_rm, // @[util.scala:463:14]
output [1:0] io_deq_bits_uop_fp_typ, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:463:14]
output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_debug_if, // @[util.scala:463:14]
output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:463:14]
output [2:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:463:14]
output [63:0] io_deq_bits_data, // @[util.scala:463:14]
output io_deq_bits_is_hella, // @[util.scala:463:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[util.scala:463:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:463:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rvc, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_iq_type_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_0, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_4, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_5, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_6, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_7, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_8, // @[util.scala:463:14]
input io_brupdate_b2_uop_fu_code_9, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[util.scala:463:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[util.scala:463:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfb, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_fencei, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sfence, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_amo, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_eret, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_rocc, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_mov, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:463:14]
input io_brupdate_b2_uop_edge_inst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:463:14]
input io_brupdate_b2_uop_taken, // @[util.scala:463:14]
input io_brupdate_b2_uop_imm_rename, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[util.scala:463:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:463:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs1_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs2_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_prs3_busy, // @[util.scala:463:14]
input io_brupdate_b2_uop_ppred_busy, // @[util.scala:463:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:463:14]
input io_brupdate_b2_uop_exception, // @[util.scala:463:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:463:14]
input io_brupdate_b2_uop_mem_signed, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_ldq, // @[util.scala:463:14]
input io_brupdate_b2_uop_uses_stq, // @[util.scala:463:14]
input io_brupdate_b2_uop_is_unique, // @[util.scala:463:14]
input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[util.scala:463:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:463:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:463:14]
input io_brupdate_b2_uop_frs3_en, // @[util.scala:463:14]
input io_brupdate_b2_uop_fcn_dw, // @[util.scala:463:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[util.scala:463:14]
input io_brupdate_b2_uop_fp_val, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:463:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:463:14]
input io_brupdate_b2_mispredict, // @[util.scala:463:14]
input io_brupdate_b2_taken, // @[util.scala:463:14]
input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:463:14]
input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:463:14]
input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:463:14]
input [20:0] io_brupdate_b2_target_offset, // @[util.scala:463:14]
input io_flush // @[util.scala:463:14]
);
wire [64:0] _ram_ext_R0_data; // @[util.scala:503:22]
wire io_enq_valid_0 = io_enq_valid; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:458:7]
wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_0_0 = io_enq_bits_uop_iq_type_0; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_1_0 = io_enq_bits_uop_iq_type_1; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_2_0 = io_enq_bits_uop_iq_type_2; // @[util.scala:458:7]
wire io_enq_bits_uop_iq_type_3_0 = io_enq_bits_uop_iq_type_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_0_0 = io_enq_bits_uop_fu_code_0; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_1_0 = io_enq_bits_uop_fu_code_1; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_2_0 = io_enq_bits_uop_fu_code_2; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_3_0 = io_enq_bits_uop_fu_code_3; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_4_0 = io_enq_bits_uop_fu_code_4; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_5_0 = io_enq_bits_uop_fu_code_5; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_6_0 = io_enq_bits_uop_fu_code_6; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_7_0 = io_enq_bits_uop_fu_code_7; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_8_0 = io_enq_bits_uop_fu_code_8; // @[util.scala:458:7]
wire io_enq_bits_uop_fu_code_9_0 = io_enq_bits_uop_fu_code_9; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_0 = io_enq_bits_uop_iw_issued; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_agen_0 = io_enq_bits_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_issued_partial_dgen_0 = io_enq_bits_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_iw_p1_speculative_child_0 = io_enq_bits_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_iw_p2_speculative_child_0 = io_enq_bits_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p1_bypass_hint_0 = io_enq_bits_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p2_bypass_hint_0 = io_enq_bits_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_enq_bits_uop_iw_p3_bypass_hint_0 = io_enq_bits_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dis_col_sel_0 = io_enq_bits_uop_dis_col_sel; // @[util.scala:458:7]
wire [11:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_br_type_0 = io_enq_bits_uop_br_type; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sfence_0 = io_enq_bits_uop_is_sfence; // @[util.scala:458:7]
wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:458:7]
wire io_enq_bits_uop_is_eret_0 = io_enq_bits_uop_is_eret; // @[util.scala:458:7]
wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_rocc_0 = io_enq_bits_uop_is_rocc; // @[util.scala:458:7]
wire io_enq_bits_uop_is_mov_0 = io_enq_bits_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:458:7]
wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:458:7]
wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:458:7]
wire io_enq_bits_uop_imm_rename_0 = io_enq_bits_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_imm_sel_0 = io_enq_bits_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_pimm_0 = io_enq_bits_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_op1_sel_0 = io_enq_bits_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_op2_sel_0 = io_enq_bits_uop_op2_sel; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ldst_0 = io_enq_bits_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wen_0 = io_enq_bits_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren1_0 = io_enq_bits_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren2_0 = io_enq_bits_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_ren3_0 = io_enq_bits_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap12_0 = io_enq_bits_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_swap23_0 = io_enq_bits_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagIn_0 = io_enq_bits_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_ctrl_typeTagOut_0 = io_enq_bits_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fromint_0 = io_enq_bits_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_toint_0 = io_enq_bits_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fastpipe_0 = io_enq_bits_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_fma_0 = io_enq_bits_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_div_0 = io_enq_bits_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_sqrt_0 = io_enq_bits_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_wflags_0 = io_enq_bits_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_ctrl_vec_0 = io_enq_bits_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:458:7]
wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:458:7]
wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:458:7]
wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:458:7]
wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:458:7]
wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:458:7]
wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:458:7]
wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:458:7]
wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_csr_cmd_0 = io_enq_bits_uop_csr_cmd; // @[util.scala:458:7]
wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:458:7]
wire io_enq_bits_uop_fcn_dw_0 = io_enq_bits_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_enq_bits_uop_fcn_op_0 = io_enq_bits_uop_fcn_op; // @[util.scala:458:7]
wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_fp_rm_0 = io_enq_bits_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_enq_bits_uop_fp_typ_0 = io_enq_bits_uop_fp_typ; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:458:7]
wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:458:7]
wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:458:7]
wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:458:7]
wire io_deq_ready_0 = io_deq_ready; // @[util.scala:458:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:458:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:458:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[util.scala:458:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:458:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:458:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:458:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[util.scala:458:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:458:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:458:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:458:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:458:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:458:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:458:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:458:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[util.scala:458:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:458:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:458:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[util.scala:458:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[util.scala:458:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:458:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:458:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:458:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:458:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:458:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:458:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:458:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:458:7]
wire io_flush_0 = io_flush; // @[util.scala:458:7]
wire _valids_WIRE_0 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_1 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_2 = 1'h0; // @[util.scala:504:34]
wire _valids_WIRE_3 = 1'h0; // @[util.scala:504:34]
wire _io_enq_ready_T; // @[util.scala:543:21]
wire _io_deq_valid_T_1; // @[util.scala:548:42]
wire [31:0] out_uop_inst; // @[util.scala:545:19]
wire [31:0] out_uop_debug_inst; // @[util.scala:545:19]
wire out_uop_is_rvc; // @[util.scala:545:19]
wire [39:0] out_uop_debug_pc; // @[util.scala:545:19]
wire out_uop_iq_type_0; // @[util.scala:545:19]
wire out_uop_iq_type_1; // @[util.scala:545:19]
wire out_uop_iq_type_2; // @[util.scala:545:19]
wire out_uop_iq_type_3; // @[util.scala:545:19]
wire out_uop_fu_code_0; // @[util.scala:545:19]
wire out_uop_fu_code_1; // @[util.scala:545:19]
wire out_uop_fu_code_2; // @[util.scala:545:19]
wire out_uop_fu_code_3; // @[util.scala:545:19]
wire out_uop_fu_code_4; // @[util.scala:545:19]
wire out_uop_fu_code_5; // @[util.scala:545:19]
wire out_uop_fu_code_6; // @[util.scala:545:19]
wire out_uop_fu_code_7; // @[util.scala:545:19]
wire out_uop_fu_code_8; // @[util.scala:545:19]
wire out_uop_fu_code_9; // @[util.scala:545:19]
wire out_uop_iw_issued; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_agen; // @[util.scala:545:19]
wire out_uop_iw_issued_partial_dgen; // @[util.scala:545:19]
wire [1:0] out_uop_iw_p1_speculative_child; // @[util.scala:545:19]
wire [1:0] out_uop_iw_p2_speculative_child; // @[util.scala:545:19]
wire out_uop_iw_p1_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p2_bypass_hint; // @[util.scala:545:19]
wire out_uop_iw_p3_bypass_hint; // @[util.scala:545:19]
wire [1:0] out_uop_dis_col_sel; // @[util.scala:545:19]
wire [11:0] out_uop_br_mask; // @[util.scala:545:19]
wire [3:0] out_uop_br_tag; // @[util.scala:545:19]
wire [3:0] out_uop_br_type; // @[util.scala:545:19]
wire out_uop_is_sfb; // @[util.scala:545:19]
wire out_uop_is_fence; // @[util.scala:545:19]
wire out_uop_is_fencei; // @[util.scala:545:19]
wire out_uop_is_sfence; // @[util.scala:545:19]
wire out_uop_is_amo; // @[util.scala:545:19]
wire out_uop_is_eret; // @[util.scala:545:19]
wire out_uop_is_sys_pc2epc; // @[util.scala:545:19]
wire out_uop_is_rocc; // @[util.scala:545:19]
wire out_uop_is_mov; // @[util.scala:545:19]
wire [4:0] out_uop_ftq_idx; // @[util.scala:545:19]
wire out_uop_edge_inst; // @[util.scala:545:19]
wire [5:0] out_uop_pc_lob; // @[util.scala:545:19]
wire out_uop_taken; // @[util.scala:545:19]
wire out_uop_imm_rename; // @[util.scala:545:19]
wire [2:0] out_uop_imm_sel; // @[util.scala:545:19]
wire [4:0] out_uop_pimm; // @[util.scala:545:19]
wire [19:0] out_uop_imm_packed; // @[util.scala:545:19]
wire [1:0] out_uop_op1_sel; // @[util.scala:545:19]
wire [2:0] out_uop_op2_sel; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ldst; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wen; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren1; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren2; // @[util.scala:545:19]
wire out_uop_fp_ctrl_ren3; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap12; // @[util.scala:545:19]
wire out_uop_fp_ctrl_swap23; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagIn; // @[util.scala:545:19]
wire [1:0] out_uop_fp_ctrl_typeTagOut; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fromint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_toint; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fastpipe; // @[util.scala:545:19]
wire out_uop_fp_ctrl_fma; // @[util.scala:545:19]
wire out_uop_fp_ctrl_div; // @[util.scala:545:19]
wire out_uop_fp_ctrl_sqrt; // @[util.scala:545:19]
wire out_uop_fp_ctrl_wflags; // @[util.scala:545:19]
wire out_uop_fp_ctrl_vec; // @[util.scala:545:19]
wire [5:0] out_uop_rob_idx; // @[util.scala:545:19]
wire [3:0] out_uop_ldq_idx; // @[util.scala:545:19]
wire [3:0] out_uop_stq_idx; // @[util.scala:545:19]
wire [1:0] out_uop_rxq_idx; // @[util.scala:545:19]
wire [6:0] out_uop_pdst; // @[util.scala:545:19]
wire [6:0] out_uop_prs1; // @[util.scala:545:19]
wire [6:0] out_uop_prs2; // @[util.scala:545:19]
wire [6:0] out_uop_prs3; // @[util.scala:545:19]
wire [4:0] out_uop_ppred; // @[util.scala:545:19]
wire out_uop_prs1_busy; // @[util.scala:545:19]
wire out_uop_prs2_busy; // @[util.scala:545:19]
wire out_uop_prs3_busy; // @[util.scala:545:19]
wire out_uop_ppred_busy; // @[util.scala:545:19]
wire [6:0] out_uop_stale_pdst; // @[util.scala:545:19]
wire out_uop_exception; // @[util.scala:545:19]
wire [63:0] out_uop_exc_cause; // @[util.scala:545:19]
wire [4:0] out_uop_mem_cmd; // @[util.scala:545:19]
wire [1:0] out_uop_mem_size; // @[util.scala:545:19]
wire out_uop_mem_signed; // @[util.scala:545:19]
wire out_uop_uses_ldq; // @[util.scala:545:19]
wire out_uop_uses_stq; // @[util.scala:545:19]
wire out_uop_is_unique; // @[util.scala:545:19]
wire out_uop_flush_on_commit; // @[util.scala:545:19]
wire [2:0] out_uop_csr_cmd; // @[util.scala:545:19]
wire out_uop_ldst_is_rs1; // @[util.scala:545:19]
wire [5:0] out_uop_ldst; // @[util.scala:545:19]
wire [5:0] out_uop_lrs1; // @[util.scala:545:19]
wire [5:0] out_uop_lrs2; // @[util.scala:545:19]
wire [5:0] out_uop_lrs3; // @[util.scala:545:19]
wire [1:0] out_uop_dst_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs1_rtype; // @[util.scala:545:19]
wire [1:0] out_uop_lrs2_rtype; // @[util.scala:545:19]
wire out_uop_frs3_en; // @[util.scala:545:19]
wire out_uop_fcn_dw; // @[util.scala:545:19]
wire [4:0] out_uop_fcn_op; // @[util.scala:545:19]
wire out_uop_fp_val; // @[util.scala:545:19]
wire [2:0] out_uop_fp_rm; // @[util.scala:545:19]
wire [1:0] out_uop_fp_typ; // @[util.scala:545:19]
wire out_uop_xcpt_pf_if; // @[util.scala:545:19]
wire out_uop_xcpt_ae_if; // @[util.scala:545:19]
wire out_uop_xcpt_ma_if; // @[util.scala:545:19]
wire out_uop_bp_debug_if; // @[util.scala:545:19]
wire out_uop_bp_xcpt_if; // @[util.scala:545:19]
wire [2:0] out_uop_debug_fsrc; // @[util.scala:545:19]
wire [2:0] out_uop_debug_tsrc; // @[util.scala:545:19]
wire [63:0] out_data; // @[util.scala:545:19]
wire out_is_hella; // @[util.scala:545:19]
wire _io_empty_T_1; // @[util.scala:512:27]
wire io_enq_ready_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:458:7]
wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
wire io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
wire [11:0] io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
wire io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
wire io_deq_bits_uop_taken_0; // @[util.scala:458:7]
wire io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
wire [3:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
wire io_deq_bits_uop_exception_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
wire io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
wire io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
wire io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
wire [4:0] io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
wire io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
wire [1:0] io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
wire [2:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
wire [63:0] io_deq_bits_data_0; // @[util.scala:458:7]
wire io_deq_bits_is_hella_0; // @[util.scala:458:7]
wire io_deq_valid_0; // @[util.scala:458:7]
wire io_empty; // @[util.scala:458:7]
wire [1:0] io_count; // @[util.scala:458:7]
assign out_data = _ram_ext_R0_data[63:0]; // @[util.scala:503:22, :545:19]
assign out_is_hella = _ram_ext_R0_data[64]; // @[util.scala:503:22, :545:19]
reg valids_0; // @[util.scala:504:26]
reg valids_1; // @[util.scala:504:26]
reg valids_2; // @[util.scala:504:26]
reg valids_3; // @[util.scala:504:26]
reg [31:0] uops_0_inst; // @[util.scala:505:22]
reg [31:0] uops_0_debug_inst; // @[util.scala:505:22]
reg uops_0_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_0_debug_pc; // @[util.scala:505:22]
reg uops_0_iq_type_0; // @[util.scala:505:22]
reg uops_0_iq_type_1; // @[util.scala:505:22]
reg uops_0_iq_type_2; // @[util.scala:505:22]
reg uops_0_iq_type_3; // @[util.scala:505:22]
reg uops_0_fu_code_0; // @[util.scala:505:22]
reg uops_0_fu_code_1; // @[util.scala:505:22]
reg uops_0_fu_code_2; // @[util.scala:505:22]
reg uops_0_fu_code_3; // @[util.scala:505:22]
reg uops_0_fu_code_4; // @[util.scala:505:22]
reg uops_0_fu_code_5; // @[util.scala:505:22]
reg uops_0_fu_code_6; // @[util.scala:505:22]
reg uops_0_fu_code_7; // @[util.scala:505:22]
reg uops_0_fu_code_8; // @[util.scala:505:22]
reg uops_0_fu_code_9; // @[util.scala:505:22]
reg uops_0_iw_issued; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_0_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_0_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_0_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_0_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_0_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_0_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_0_br_mask; // @[util.scala:505:22]
reg [3:0] uops_0_br_tag; // @[util.scala:505:22]
reg [3:0] uops_0_br_type; // @[util.scala:505:22]
reg uops_0_is_sfb; // @[util.scala:505:22]
reg uops_0_is_fence; // @[util.scala:505:22]
reg uops_0_is_fencei; // @[util.scala:505:22]
reg uops_0_is_sfence; // @[util.scala:505:22]
reg uops_0_is_amo; // @[util.scala:505:22]
reg uops_0_is_eret; // @[util.scala:505:22]
reg uops_0_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_0_is_rocc; // @[util.scala:505:22]
reg uops_0_is_mov; // @[util.scala:505:22]
reg [4:0] uops_0_ftq_idx; // @[util.scala:505:22]
reg uops_0_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_0_pc_lob; // @[util.scala:505:22]
reg uops_0_taken; // @[util.scala:505:22]
reg uops_0_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_0_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_0_pimm; // @[util.scala:505:22]
reg [19:0] uops_0_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_0_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_0_op2_sel; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_0_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_0_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_0_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_0_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_0_fp_ctrl_div; // @[util.scala:505:22]
reg uops_0_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_0_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_0_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_0_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_0_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_0_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_0_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_0_pdst; // @[util.scala:505:22]
reg [6:0] uops_0_prs1; // @[util.scala:505:22]
reg [6:0] uops_0_prs2; // @[util.scala:505:22]
reg [6:0] uops_0_prs3; // @[util.scala:505:22]
reg [4:0] uops_0_ppred; // @[util.scala:505:22]
reg uops_0_prs1_busy; // @[util.scala:505:22]
reg uops_0_prs2_busy; // @[util.scala:505:22]
reg uops_0_prs3_busy; // @[util.scala:505:22]
reg uops_0_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_0_stale_pdst; // @[util.scala:505:22]
reg uops_0_exception; // @[util.scala:505:22]
reg [63:0] uops_0_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_0_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_0_mem_size; // @[util.scala:505:22]
reg uops_0_mem_signed; // @[util.scala:505:22]
reg uops_0_uses_ldq; // @[util.scala:505:22]
reg uops_0_uses_stq; // @[util.scala:505:22]
reg uops_0_is_unique; // @[util.scala:505:22]
reg uops_0_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_0_csr_cmd; // @[util.scala:505:22]
reg uops_0_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_0_ldst; // @[util.scala:505:22]
reg [5:0] uops_0_lrs1; // @[util.scala:505:22]
reg [5:0] uops_0_lrs2; // @[util.scala:505:22]
reg [5:0] uops_0_lrs3; // @[util.scala:505:22]
reg [1:0] uops_0_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_0_lrs2_rtype; // @[util.scala:505:22]
reg uops_0_frs3_en; // @[util.scala:505:22]
reg uops_0_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_0_fcn_op; // @[util.scala:505:22]
reg uops_0_fp_val; // @[util.scala:505:22]
reg [2:0] uops_0_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_0_fp_typ; // @[util.scala:505:22]
reg uops_0_xcpt_pf_if; // @[util.scala:505:22]
reg uops_0_xcpt_ae_if; // @[util.scala:505:22]
reg uops_0_xcpt_ma_if; // @[util.scala:505:22]
reg uops_0_bp_debug_if; // @[util.scala:505:22]
reg uops_0_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_0_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_0_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_1_inst; // @[util.scala:505:22]
reg [31:0] uops_1_debug_inst; // @[util.scala:505:22]
reg uops_1_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_1_debug_pc; // @[util.scala:505:22]
reg uops_1_iq_type_0; // @[util.scala:505:22]
reg uops_1_iq_type_1; // @[util.scala:505:22]
reg uops_1_iq_type_2; // @[util.scala:505:22]
reg uops_1_iq_type_3; // @[util.scala:505:22]
reg uops_1_fu_code_0; // @[util.scala:505:22]
reg uops_1_fu_code_1; // @[util.scala:505:22]
reg uops_1_fu_code_2; // @[util.scala:505:22]
reg uops_1_fu_code_3; // @[util.scala:505:22]
reg uops_1_fu_code_4; // @[util.scala:505:22]
reg uops_1_fu_code_5; // @[util.scala:505:22]
reg uops_1_fu_code_6; // @[util.scala:505:22]
reg uops_1_fu_code_7; // @[util.scala:505:22]
reg uops_1_fu_code_8; // @[util.scala:505:22]
reg uops_1_fu_code_9; // @[util.scala:505:22]
reg uops_1_iw_issued; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_1_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_1_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_1_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_1_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_1_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_1_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_1_br_mask; // @[util.scala:505:22]
reg [3:0] uops_1_br_tag; // @[util.scala:505:22]
reg [3:0] uops_1_br_type; // @[util.scala:505:22]
reg uops_1_is_sfb; // @[util.scala:505:22]
reg uops_1_is_fence; // @[util.scala:505:22]
reg uops_1_is_fencei; // @[util.scala:505:22]
reg uops_1_is_sfence; // @[util.scala:505:22]
reg uops_1_is_amo; // @[util.scala:505:22]
reg uops_1_is_eret; // @[util.scala:505:22]
reg uops_1_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_1_is_rocc; // @[util.scala:505:22]
reg uops_1_is_mov; // @[util.scala:505:22]
reg [4:0] uops_1_ftq_idx; // @[util.scala:505:22]
reg uops_1_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_1_pc_lob; // @[util.scala:505:22]
reg uops_1_taken; // @[util.scala:505:22]
reg uops_1_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_1_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_1_pimm; // @[util.scala:505:22]
reg [19:0] uops_1_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_1_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_1_op2_sel; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_1_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_1_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_1_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_1_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_1_fp_ctrl_div; // @[util.scala:505:22]
reg uops_1_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_1_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_1_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_1_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_1_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_1_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_1_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_1_pdst; // @[util.scala:505:22]
reg [6:0] uops_1_prs1; // @[util.scala:505:22]
reg [6:0] uops_1_prs2; // @[util.scala:505:22]
reg [6:0] uops_1_prs3; // @[util.scala:505:22]
reg [4:0] uops_1_ppred; // @[util.scala:505:22]
reg uops_1_prs1_busy; // @[util.scala:505:22]
reg uops_1_prs2_busy; // @[util.scala:505:22]
reg uops_1_prs3_busy; // @[util.scala:505:22]
reg uops_1_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_1_stale_pdst; // @[util.scala:505:22]
reg uops_1_exception; // @[util.scala:505:22]
reg [63:0] uops_1_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_1_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_1_mem_size; // @[util.scala:505:22]
reg uops_1_mem_signed; // @[util.scala:505:22]
reg uops_1_uses_ldq; // @[util.scala:505:22]
reg uops_1_uses_stq; // @[util.scala:505:22]
reg uops_1_is_unique; // @[util.scala:505:22]
reg uops_1_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_1_csr_cmd; // @[util.scala:505:22]
reg uops_1_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_1_ldst; // @[util.scala:505:22]
reg [5:0] uops_1_lrs1; // @[util.scala:505:22]
reg [5:0] uops_1_lrs2; // @[util.scala:505:22]
reg [5:0] uops_1_lrs3; // @[util.scala:505:22]
reg [1:0] uops_1_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_1_lrs2_rtype; // @[util.scala:505:22]
reg uops_1_frs3_en; // @[util.scala:505:22]
reg uops_1_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_1_fcn_op; // @[util.scala:505:22]
reg uops_1_fp_val; // @[util.scala:505:22]
reg [2:0] uops_1_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_1_fp_typ; // @[util.scala:505:22]
reg uops_1_xcpt_pf_if; // @[util.scala:505:22]
reg uops_1_xcpt_ae_if; // @[util.scala:505:22]
reg uops_1_xcpt_ma_if; // @[util.scala:505:22]
reg uops_1_bp_debug_if; // @[util.scala:505:22]
reg uops_1_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_1_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_1_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_2_inst; // @[util.scala:505:22]
reg [31:0] uops_2_debug_inst; // @[util.scala:505:22]
reg uops_2_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_2_debug_pc; // @[util.scala:505:22]
reg uops_2_iq_type_0; // @[util.scala:505:22]
reg uops_2_iq_type_1; // @[util.scala:505:22]
reg uops_2_iq_type_2; // @[util.scala:505:22]
reg uops_2_iq_type_3; // @[util.scala:505:22]
reg uops_2_fu_code_0; // @[util.scala:505:22]
reg uops_2_fu_code_1; // @[util.scala:505:22]
reg uops_2_fu_code_2; // @[util.scala:505:22]
reg uops_2_fu_code_3; // @[util.scala:505:22]
reg uops_2_fu_code_4; // @[util.scala:505:22]
reg uops_2_fu_code_5; // @[util.scala:505:22]
reg uops_2_fu_code_6; // @[util.scala:505:22]
reg uops_2_fu_code_7; // @[util.scala:505:22]
reg uops_2_fu_code_8; // @[util.scala:505:22]
reg uops_2_fu_code_9; // @[util.scala:505:22]
reg uops_2_iw_issued; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_2_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_2_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_2_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_2_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_2_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_2_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_2_br_mask; // @[util.scala:505:22]
reg [3:0] uops_2_br_tag; // @[util.scala:505:22]
reg [3:0] uops_2_br_type; // @[util.scala:505:22]
reg uops_2_is_sfb; // @[util.scala:505:22]
reg uops_2_is_fence; // @[util.scala:505:22]
reg uops_2_is_fencei; // @[util.scala:505:22]
reg uops_2_is_sfence; // @[util.scala:505:22]
reg uops_2_is_amo; // @[util.scala:505:22]
reg uops_2_is_eret; // @[util.scala:505:22]
reg uops_2_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_2_is_rocc; // @[util.scala:505:22]
reg uops_2_is_mov; // @[util.scala:505:22]
reg [4:0] uops_2_ftq_idx; // @[util.scala:505:22]
reg uops_2_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_2_pc_lob; // @[util.scala:505:22]
reg uops_2_taken; // @[util.scala:505:22]
reg uops_2_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_2_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_2_pimm; // @[util.scala:505:22]
reg [19:0] uops_2_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_2_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_2_op2_sel; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_2_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_2_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_2_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_2_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_2_fp_ctrl_div; // @[util.scala:505:22]
reg uops_2_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_2_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_2_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_2_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_2_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_2_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_2_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_2_pdst; // @[util.scala:505:22]
reg [6:0] uops_2_prs1; // @[util.scala:505:22]
reg [6:0] uops_2_prs2; // @[util.scala:505:22]
reg [6:0] uops_2_prs3; // @[util.scala:505:22]
reg [4:0] uops_2_ppred; // @[util.scala:505:22]
reg uops_2_prs1_busy; // @[util.scala:505:22]
reg uops_2_prs2_busy; // @[util.scala:505:22]
reg uops_2_prs3_busy; // @[util.scala:505:22]
reg uops_2_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_2_stale_pdst; // @[util.scala:505:22]
reg uops_2_exception; // @[util.scala:505:22]
reg [63:0] uops_2_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_2_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_2_mem_size; // @[util.scala:505:22]
reg uops_2_mem_signed; // @[util.scala:505:22]
reg uops_2_uses_ldq; // @[util.scala:505:22]
reg uops_2_uses_stq; // @[util.scala:505:22]
reg uops_2_is_unique; // @[util.scala:505:22]
reg uops_2_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_2_csr_cmd; // @[util.scala:505:22]
reg uops_2_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_2_ldst; // @[util.scala:505:22]
reg [5:0] uops_2_lrs1; // @[util.scala:505:22]
reg [5:0] uops_2_lrs2; // @[util.scala:505:22]
reg [5:0] uops_2_lrs3; // @[util.scala:505:22]
reg [1:0] uops_2_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_2_lrs2_rtype; // @[util.scala:505:22]
reg uops_2_frs3_en; // @[util.scala:505:22]
reg uops_2_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_2_fcn_op; // @[util.scala:505:22]
reg uops_2_fp_val; // @[util.scala:505:22]
reg [2:0] uops_2_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_2_fp_typ; // @[util.scala:505:22]
reg uops_2_xcpt_pf_if; // @[util.scala:505:22]
reg uops_2_xcpt_ae_if; // @[util.scala:505:22]
reg uops_2_xcpt_ma_if; // @[util.scala:505:22]
reg uops_2_bp_debug_if; // @[util.scala:505:22]
reg uops_2_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_2_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_2_debug_tsrc; // @[util.scala:505:22]
reg [31:0] uops_3_inst; // @[util.scala:505:22]
reg [31:0] uops_3_debug_inst; // @[util.scala:505:22]
reg uops_3_is_rvc; // @[util.scala:505:22]
reg [39:0] uops_3_debug_pc; // @[util.scala:505:22]
reg uops_3_iq_type_0; // @[util.scala:505:22]
reg uops_3_iq_type_1; // @[util.scala:505:22]
reg uops_3_iq_type_2; // @[util.scala:505:22]
reg uops_3_iq_type_3; // @[util.scala:505:22]
reg uops_3_fu_code_0; // @[util.scala:505:22]
reg uops_3_fu_code_1; // @[util.scala:505:22]
reg uops_3_fu_code_2; // @[util.scala:505:22]
reg uops_3_fu_code_3; // @[util.scala:505:22]
reg uops_3_fu_code_4; // @[util.scala:505:22]
reg uops_3_fu_code_5; // @[util.scala:505:22]
reg uops_3_fu_code_6; // @[util.scala:505:22]
reg uops_3_fu_code_7; // @[util.scala:505:22]
reg uops_3_fu_code_8; // @[util.scala:505:22]
reg uops_3_fu_code_9; // @[util.scala:505:22]
reg uops_3_iw_issued; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_agen; // @[util.scala:505:22]
reg uops_3_iw_issued_partial_dgen; // @[util.scala:505:22]
reg [1:0] uops_3_iw_p1_speculative_child; // @[util.scala:505:22]
reg [1:0] uops_3_iw_p2_speculative_child; // @[util.scala:505:22]
reg uops_3_iw_p1_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p2_bypass_hint; // @[util.scala:505:22]
reg uops_3_iw_p3_bypass_hint; // @[util.scala:505:22]
reg [1:0] uops_3_dis_col_sel; // @[util.scala:505:22]
reg [11:0] uops_3_br_mask; // @[util.scala:505:22]
reg [3:0] uops_3_br_tag; // @[util.scala:505:22]
reg [3:0] uops_3_br_type; // @[util.scala:505:22]
reg uops_3_is_sfb; // @[util.scala:505:22]
reg uops_3_is_fence; // @[util.scala:505:22]
reg uops_3_is_fencei; // @[util.scala:505:22]
reg uops_3_is_sfence; // @[util.scala:505:22]
reg uops_3_is_amo; // @[util.scala:505:22]
reg uops_3_is_eret; // @[util.scala:505:22]
reg uops_3_is_sys_pc2epc; // @[util.scala:505:22]
reg uops_3_is_rocc; // @[util.scala:505:22]
reg uops_3_is_mov; // @[util.scala:505:22]
reg [4:0] uops_3_ftq_idx; // @[util.scala:505:22]
reg uops_3_edge_inst; // @[util.scala:505:22]
reg [5:0] uops_3_pc_lob; // @[util.scala:505:22]
reg uops_3_taken; // @[util.scala:505:22]
reg uops_3_imm_rename; // @[util.scala:505:22]
reg [2:0] uops_3_imm_sel; // @[util.scala:505:22]
reg [4:0] uops_3_pimm; // @[util.scala:505:22]
reg [19:0] uops_3_imm_packed; // @[util.scala:505:22]
reg [1:0] uops_3_op1_sel; // @[util.scala:505:22]
reg [2:0] uops_3_op2_sel; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ldst; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wen; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren1; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren2; // @[util.scala:505:22]
reg uops_3_fp_ctrl_ren3; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap12; // @[util.scala:505:22]
reg uops_3_fp_ctrl_swap23; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagIn; // @[util.scala:505:22]
reg [1:0] uops_3_fp_ctrl_typeTagOut; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fromint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_toint; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fastpipe; // @[util.scala:505:22]
reg uops_3_fp_ctrl_fma; // @[util.scala:505:22]
reg uops_3_fp_ctrl_div; // @[util.scala:505:22]
reg uops_3_fp_ctrl_sqrt; // @[util.scala:505:22]
reg uops_3_fp_ctrl_wflags; // @[util.scala:505:22]
reg uops_3_fp_ctrl_vec; // @[util.scala:505:22]
reg [5:0] uops_3_rob_idx; // @[util.scala:505:22]
reg [3:0] uops_3_ldq_idx; // @[util.scala:505:22]
reg [3:0] uops_3_stq_idx; // @[util.scala:505:22]
reg [1:0] uops_3_rxq_idx; // @[util.scala:505:22]
reg [6:0] uops_3_pdst; // @[util.scala:505:22]
reg [6:0] uops_3_prs1; // @[util.scala:505:22]
reg [6:0] uops_3_prs2; // @[util.scala:505:22]
reg [6:0] uops_3_prs3; // @[util.scala:505:22]
reg [4:0] uops_3_ppred; // @[util.scala:505:22]
reg uops_3_prs1_busy; // @[util.scala:505:22]
reg uops_3_prs2_busy; // @[util.scala:505:22]
reg uops_3_prs3_busy; // @[util.scala:505:22]
reg uops_3_ppred_busy; // @[util.scala:505:22]
reg [6:0] uops_3_stale_pdst; // @[util.scala:505:22]
reg uops_3_exception; // @[util.scala:505:22]
reg [63:0] uops_3_exc_cause; // @[util.scala:505:22]
reg [4:0] uops_3_mem_cmd; // @[util.scala:505:22]
reg [1:0] uops_3_mem_size; // @[util.scala:505:22]
reg uops_3_mem_signed; // @[util.scala:505:22]
reg uops_3_uses_ldq; // @[util.scala:505:22]
reg uops_3_uses_stq; // @[util.scala:505:22]
reg uops_3_is_unique; // @[util.scala:505:22]
reg uops_3_flush_on_commit; // @[util.scala:505:22]
reg [2:0] uops_3_csr_cmd; // @[util.scala:505:22]
reg uops_3_ldst_is_rs1; // @[util.scala:505:22]
reg [5:0] uops_3_ldst; // @[util.scala:505:22]
reg [5:0] uops_3_lrs1; // @[util.scala:505:22]
reg [5:0] uops_3_lrs2; // @[util.scala:505:22]
reg [5:0] uops_3_lrs3; // @[util.scala:505:22]
reg [1:0] uops_3_dst_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs1_rtype; // @[util.scala:505:22]
reg [1:0] uops_3_lrs2_rtype; // @[util.scala:505:22]
reg uops_3_frs3_en; // @[util.scala:505:22]
reg uops_3_fcn_dw; // @[util.scala:505:22]
reg [4:0] uops_3_fcn_op; // @[util.scala:505:22]
reg uops_3_fp_val; // @[util.scala:505:22]
reg [2:0] uops_3_fp_rm; // @[util.scala:505:22]
reg [1:0] uops_3_fp_typ; // @[util.scala:505:22]
reg uops_3_xcpt_pf_if; // @[util.scala:505:22]
reg uops_3_xcpt_ae_if; // @[util.scala:505:22]
reg uops_3_xcpt_ma_if; // @[util.scala:505:22]
reg uops_3_bp_debug_if; // @[util.scala:505:22]
reg uops_3_bp_xcpt_if; // @[util.scala:505:22]
reg [2:0] uops_3_debug_fsrc; // @[util.scala:505:22]
reg [2:0] uops_3_debug_tsrc; // @[util.scala:505:22]
reg [1:0] enq_ptr_value; // @[Counter.scala:61:40]
reg [1:0] deq_ptr_value; // @[Counter.scala:61:40]
reg maybe_full; // @[util.scala:509:29]
wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40]
wire _io_empty_T = ~maybe_full; // @[util.scala:509:29, :512:30]
assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:511:35, :512:{27,30}]
assign io_empty = _io_empty_T_1; // @[util.scala:458:7, :512:27]
wire _GEN = ptr_match & maybe_full; // @[util.scala:509:29, :511:35, :513:26]
wire full; // @[util.scala:513:26]
assign full = _GEN; // @[util.scala:513:26]
wire _io_count_T; // @[util.scala:553:34]
assign _io_count_T = _GEN; // @[util.scala:513:26, :553:34]
wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35]
wire [11:0] _do_enq_T_1 = io_brupdate_b1_mispredict_mask_0 & io_enq_bits_uop_br_mask_0; // @[util.scala:126:51, :458:7]
wire _do_enq_T_2 = |_do_enq_T_1; // @[util.scala:126:{51,59}]
wire _do_enq_T_3 = _do_enq_T_2; // @[util.scala:61:61, :126:59]
wire _do_enq_T_4 = ~_do_enq_T_3; // @[util.scala:61:61, :514:42]
wire _do_enq_T_5 = _do_enq_T & _do_enq_T_4; // @[Decoupled.scala:51:35]
wire _do_enq_T_6 = io_flush_0 & io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :514:113]
wire _do_enq_T_7 = ~_do_enq_T_6; // @[util.scala:514:{102,113}]
wire _do_enq_T_8 = _do_enq_T_5 & _do_enq_T_7; // @[util.scala:514:{39,99,102}]
wire do_enq = _do_enq_T_8; // @[util.scala:514:{26,99}]
wire [3:0] _GEN_0 = {{valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:504:26, :515:44]
wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40]
wire _do_deq_T = ~_GEN_1; // @[util.scala:515:44]
wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:458:7, :515:{41,44}]
wire _do_deq_T_2 = ~io_empty; // @[util.scala:458:7, :515:71]
wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:515:{41,68,71}]
wire do_deq = _do_deq_T_3; // @[util.scala:515:{26,68}]
wire [11:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:126:{51,59}]
wire _valids_0_T_2 = _valids_0_T_1; // @[util.scala:61:61, :126:59]
wire _valids_0_T_3 = ~_valids_0_T_2; // @[util.scala:61:61, :520:34]
wire _valids_0_T_4 = valids_0 & _valids_0_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_0_T_5 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_0_T_6 = ~_valids_0_T_5; // @[util.scala:520:{83,94}]
wire _valids_0_T_7 = _valids_0_T_4 & _valids_0_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:126:{51,59}]
wire _valids_1_T_2 = _valids_1_T_1; // @[util.scala:61:61, :126:59]
wire _valids_1_T_3 = ~_valids_1_T_2; // @[util.scala:61:61, :520:34]
wire _valids_1_T_4 = valids_1 & _valids_1_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_1_T_5 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_1_T_6 = ~_valids_1_T_5; // @[util.scala:520:{83,94}]
wire _valids_1_T_7 = _valids_1_T_4 & _valids_1_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:126:{51,59}]
wire _valids_2_T_2 = _valids_2_T_1; // @[util.scala:61:61, :126:59]
wire _valids_2_T_3 = ~_valids_2_T_2; // @[util.scala:61:61, :520:34]
wire _valids_2_T_4 = valids_2 & _valids_2_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_2_T_5 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_2_T_6 = ~_valids_2_T_5; // @[util.scala:520:{83,94}]
wire _valids_2_T_7 = _valids_2_T_4 & _valids_2_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:126:51, :458:7, :505:22]
wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:126:{51,59}]
wire _valids_3_T_2 = _valids_3_T_1; // @[util.scala:61:61, :126:59]
wire _valids_3_T_3 = ~_valids_3_T_2; // @[util.scala:61:61, :520:34]
wire _valids_3_T_4 = valids_3 & _valids_3_T_3; // @[util.scala:504:26, :520:{31,34}]
wire _valids_3_T_5 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:458:7, :505:22, :520:94]
wire _valids_3_T_6 = ~_valids_3_T_5; // @[util.scala:520:{83,94}]
wire _valids_3_T_7 = _valids_3_T_4 & _valids_3_T_6; // @[util.scala:520:{31,80,83}]
wire [11:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:97:23, :458:7]
wire [11:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:97:{21,23}, :505:22]
wire [11:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27, :97:23, :458:7]
wire [11:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:93:{25,27}, :458:7]
wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [2:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [2:0] _value_T = _GEN_2 + 3'h1; // @[Counter.scala:77:24]
wire [1:0] _value_T_1 = _value_T[1:0]; // @[Counter.scala:77:24]
wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24]
wire [2:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24]
wire [2:0] _value_T_2 = _GEN_3 + 3'h1; // @[Counter.scala:77:24]
wire [1:0] _value_T_3 = _value_T_2[1:0]; // @[Counter.scala:77:24]
assign _io_enq_ready_T = ~full; // @[util.scala:513:26, :543:21]
assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:458:7, :543:21]
assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_0_0 = out_uop_iq_type_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_1_0 = out_uop_iq_type_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_2_0 = out_uop_iq_type_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iq_type_3_0 = out_uop_iq_type_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_0_0 = out_uop_fu_code_0; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_1_0 = out_uop_fu_code_1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_2_0 = out_uop_fu_code_2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_3_0 = out_uop_fu_code_3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_4_0 = out_uop_fu_code_4; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_5_0 = out_uop_fu_code_5; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_6_0 = out_uop_fu_code_6; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_7_0 = out_uop_fu_code_7; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_8_0 = out_uop_fu_code_8; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fu_code_9_0 = out_uop_fu_code_9; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_0 = out_uop_iw_issued; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_agen_0 = out_uop_iw_issued_partial_agen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_issued_partial_dgen_0 = out_uop_iw_issued_partial_dgen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_speculative_child_0 = out_uop_iw_p1_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_speculative_child_0 = out_uop_iw_p2_speculative_child; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p1_bypass_hint_0 = out_uop_iw_p1_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p2_bypass_hint_0 = out_uop_iw_p2_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_iw_p3_bypass_hint_0 = out_uop_iw_p3_bypass_hint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dis_col_sel_0 = out_uop_dis_col_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_mask_0 = out_uop_br_mask; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_br_type_0 = out_uop_br_type; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sfence_0 = out_uop_is_sfence; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_eret_0 = out_uop_is_eret; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_rocc_0 = out_uop_is_rocc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_mov_0 = out_uop_is_mov; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_rename_0 = out_uop_imm_rename; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_sel_0 = out_uop_imm_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pimm_0 = out_uop_pimm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op1_sel_0 = out_uop_op1_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_op2_sel_0 = out_uop_op2_sel; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ldst_0 = out_uop_fp_ctrl_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wen_0 = out_uop_fp_ctrl_wen; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren1_0 = out_uop_fp_ctrl_ren1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren2_0 = out_uop_fp_ctrl_ren2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_ren3_0 = out_uop_fp_ctrl_ren3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap12_0 = out_uop_fp_ctrl_swap12; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_swap23_0 = out_uop_fp_ctrl_swap23; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagIn_0 = out_uop_fp_ctrl_typeTagIn; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_typeTagOut_0 = out_uop_fp_ctrl_typeTagOut; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fromint_0 = out_uop_fp_ctrl_fromint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_toint_0 = out_uop_fp_ctrl_toint; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fastpipe_0 = out_uop_fp_ctrl_fastpipe; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_fma_0 = out_uop_fp_ctrl_fma; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_div_0 = out_uop_fp_ctrl_div; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_sqrt_0 = out_uop_fp_ctrl_sqrt; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_wflags_0 = out_uop_fp_ctrl_wflags; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_ctrl_vec_0 = out_uop_fp_ctrl_vec; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_csr_cmd_0 = out_uop_csr_cmd; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_dw_0 = out_uop_fcn_dw; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fcn_op_0 = out_uop_fcn_op; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_rm_0 = out_uop_fp_rm; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_fp_typ_0 = out_uop_fp_typ; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:458:7, :545:19]
assign io_deq_bits_data_0 = out_data; // @[util.scala:458:7, :545:19]
assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:458:7, :545:19]
wire [3:0][31:0] _GEN_4 = {{uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_inst = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][31:0] _GEN_5 = {{uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_6 = {{uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rvc = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][39:0] _GEN_7 = {{uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_pc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_8 = {{uops_3_iq_type_0}, {uops_2_iq_type_0}, {uops_1_iq_type_0}, {uops_0_iq_type_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_0 = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_9 = {{uops_3_iq_type_1}, {uops_2_iq_type_1}, {uops_1_iq_type_1}, {uops_0_iq_type_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_1 = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_10 = {{uops_3_iq_type_2}, {uops_2_iq_type_2}, {uops_1_iq_type_2}, {uops_0_iq_type_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_2 = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_11 = {{uops_3_iq_type_3}, {uops_2_iq_type_3}, {uops_1_iq_type_3}, {uops_0_iq_type_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_iq_type_3 = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_12 = {{uops_3_fu_code_0}, {uops_2_fu_code_0}, {uops_1_fu_code_0}, {uops_0_fu_code_0}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_0 = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_13 = {{uops_3_fu_code_1}, {uops_2_fu_code_1}, {uops_1_fu_code_1}, {uops_0_fu_code_1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_1 = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_14 = {{uops_3_fu_code_2}, {uops_2_fu_code_2}, {uops_1_fu_code_2}, {uops_0_fu_code_2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_2 = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_15 = {{uops_3_fu_code_3}, {uops_2_fu_code_3}, {uops_1_fu_code_3}, {uops_0_fu_code_3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_3 = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_16 = {{uops_3_fu_code_4}, {uops_2_fu_code_4}, {uops_1_fu_code_4}, {uops_0_fu_code_4}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_4 = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_17 = {{uops_3_fu_code_5}, {uops_2_fu_code_5}, {uops_1_fu_code_5}, {uops_0_fu_code_5}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_5 = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_18 = {{uops_3_fu_code_6}, {uops_2_fu_code_6}, {uops_1_fu_code_6}, {uops_0_fu_code_6}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_6 = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_19 = {{uops_3_fu_code_7}, {uops_2_fu_code_7}, {uops_1_fu_code_7}, {uops_0_fu_code_7}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_7 = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_20 = {{uops_3_fu_code_8}, {uops_2_fu_code_8}, {uops_1_fu_code_8}, {uops_0_fu_code_8}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_8 = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_21 = {{uops_3_fu_code_9}, {uops_2_fu_code_9}, {uops_1_fu_code_9}, {uops_0_fu_code_9}}; // @[util.scala:505:22, :547:21]
assign out_uop_fu_code_9 = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_22 = {{uops_3_iw_issued}, {uops_2_iw_issued}, {uops_1_iw_issued}, {uops_0_iw_issued}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_23 = {{uops_3_iw_issued_partial_agen}, {uops_2_iw_issued_partial_agen}, {uops_1_iw_issued_partial_agen}, {uops_0_iw_issued_partial_agen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_agen = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_24 = {{uops_3_iw_issued_partial_dgen}, {uops_2_iw_issued_partial_dgen}, {uops_1_iw_issued_partial_dgen}, {uops_0_iw_issued_partial_dgen}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_issued_partial_dgen = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_25 = {{uops_3_iw_p1_speculative_child}, {uops_2_iw_p1_speculative_child}, {uops_1_iw_p1_speculative_child}, {uops_0_iw_p1_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_speculative_child = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_26 = {{uops_3_iw_p2_speculative_child}, {uops_2_iw_p2_speculative_child}, {uops_1_iw_p2_speculative_child}, {uops_0_iw_p2_speculative_child}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_speculative_child = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_27 = {{uops_3_iw_p1_bypass_hint}, {uops_2_iw_p1_bypass_hint}, {uops_1_iw_p1_bypass_hint}, {uops_0_iw_p1_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p1_bypass_hint = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_28 = {{uops_3_iw_p2_bypass_hint}, {uops_2_iw_p2_bypass_hint}, {uops_1_iw_p2_bypass_hint}, {uops_0_iw_p2_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p2_bypass_hint = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_29 = {{uops_3_iw_p3_bypass_hint}, {uops_2_iw_p3_bypass_hint}, {uops_1_iw_p3_bypass_hint}, {uops_0_iw_p3_bypass_hint}}; // @[util.scala:505:22, :547:21]
assign out_uop_iw_p3_bypass_hint = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_30 = {{uops_3_dis_col_sel}, {uops_2_dis_col_sel}, {uops_1_dis_col_sel}, {uops_0_dis_col_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_dis_col_sel = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][11:0] _GEN_31 = {{uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_mask = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][3:0] _GEN_32 = {{uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_tag = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][3:0] _GEN_33 = {{uops_3_br_type}, {uops_2_br_type}, {uops_1_br_type}, {uops_0_br_type}}; // @[util.scala:505:22, :547:21]
assign out_uop_br_type = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_34 = {{uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfb = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_35 = {{uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fence = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_36 = {{uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_fencei = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_37 = {{uops_3_is_sfence}, {uops_2_is_sfence}, {uops_1_is_sfence}, {uops_0_is_sfence}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sfence = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_38 = {{uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_amo = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_39 = {{uops_3_is_eret}, {uops_2_is_eret}, {uops_1_is_eret}, {uops_0_is_eret}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_eret = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_40 = {{uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_sys_pc2epc = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_41 = {{uops_3_is_rocc}, {uops_2_is_rocc}, {uops_1_is_rocc}, {uops_0_is_rocc}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_rocc = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_42 = {{uops_3_is_mov}, {uops_2_is_mov}, {uops_1_is_mov}, {uops_0_is_mov}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_mov = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_43 = {{uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ftq_idx = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_44 = {{uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:505:22, :547:21]
assign out_uop_edge_inst = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_45 = {{uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:505:22, :547:21]
assign out_uop_pc_lob = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_46 = {{uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:505:22, :547:21]
assign out_uop_taken = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_47 = {{uops_3_imm_rename}, {uops_2_imm_rename}, {uops_1_imm_rename}, {uops_0_imm_rename}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_rename = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_48 = {{uops_3_imm_sel}, {uops_2_imm_sel}, {uops_1_imm_sel}, {uops_0_imm_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_sel = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_49 = {{uops_3_pimm}, {uops_2_pimm}, {uops_1_pimm}, {uops_0_pimm}}; // @[util.scala:505:22, :547:21]
assign out_uop_pimm = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][19:0] _GEN_50 = {{uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:505:22, :547:21]
assign out_uop_imm_packed = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_51 = {{uops_3_op1_sel}, {uops_2_op1_sel}, {uops_1_op1_sel}, {uops_0_op1_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op1_sel = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_52 = {{uops_3_op2_sel}, {uops_2_op2_sel}, {uops_1_op2_sel}, {uops_0_op2_sel}}; // @[util.scala:505:22, :547:21]
assign out_uop_op2_sel = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_53 = {{uops_3_fp_ctrl_ldst}, {uops_2_fp_ctrl_ldst}, {uops_1_fp_ctrl_ldst}, {uops_0_fp_ctrl_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ldst = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_54 = {{uops_3_fp_ctrl_wen}, {uops_2_fp_ctrl_wen}, {uops_1_fp_ctrl_wen}, {uops_0_fp_ctrl_wen}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wen = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_55 = {{uops_3_fp_ctrl_ren1}, {uops_2_fp_ctrl_ren1}, {uops_1_fp_ctrl_ren1}, {uops_0_fp_ctrl_ren1}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren1 = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_56 = {{uops_3_fp_ctrl_ren2}, {uops_2_fp_ctrl_ren2}, {uops_1_fp_ctrl_ren2}, {uops_0_fp_ctrl_ren2}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren2 = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_57 = {{uops_3_fp_ctrl_ren3}, {uops_2_fp_ctrl_ren3}, {uops_1_fp_ctrl_ren3}, {uops_0_fp_ctrl_ren3}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_ren3 = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_58 = {{uops_3_fp_ctrl_swap12}, {uops_2_fp_ctrl_swap12}, {uops_1_fp_ctrl_swap12}, {uops_0_fp_ctrl_swap12}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap12 = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_59 = {{uops_3_fp_ctrl_swap23}, {uops_2_fp_ctrl_swap23}, {uops_1_fp_ctrl_swap23}, {uops_0_fp_ctrl_swap23}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_swap23 = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_60 = {{uops_3_fp_ctrl_typeTagIn}, {uops_2_fp_ctrl_typeTagIn}, {uops_1_fp_ctrl_typeTagIn}, {uops_0_fp_ctrl_typeTagIn}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagIn = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_61 = {{uops_3_fp_ctrl_typeTagOut}, {uops_2_fp_ctrl_typeTagOut}, {uops_1_fp_ctrl_typeTagOut}, {uops_0_fp_ctrl_typeTagOut}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_typeTagOut = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_62 = {{uops_3_fp_ctrl_fromint}, {uops_2_fp_ctrl_fromint}, {uops_1_fp_ctrl_fromint}, {uops_0_fp_ctrl_fromint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fromint = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_63 = {{uops_3_fp_ctrl_toint}, {uops_2_fp_ctrl_toint}, {uops_1_fp_ctrl_toint}, {uops_0_fp_ctrl_toint}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_toint = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_64 = {{uops_3_fp_ctrl_fastpipe}, {uops_2_fp_ctrl_fastpipe}, {uops_1_fp_ctrl_fastpipe}, {uops_0_fp_ctrl_fastpipe}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fastpipe = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_65 = {{uops_3_fp_ctrl_fma}, {uops_2_fp_ctrl_fma}, {uops_1_fp_ctrl_fma}, {uops_0_fp_ctrl_fma}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_fma = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_66 = {{uops_3_fp_ctrl_div}, {uops_2_fp_ctrl_div}, {uops_1_fp_ctrl_div}, {uops_0_fp_ctrl_div}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_div = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_67 = {{uops_3_fp_ctrl_sqrt}, {uops_2_fp_ctrl_sqrt}, {uops_1_fp_ctrl_sqrt}, {uops_0_fp_ctrl_sqrt}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_sqrt = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_68 = {{uops_3_fp_ctrl_wflags}, {uops_2_fp_ctrl_wflags}, {uops_1_fp_ctrl_wflags}, {uops_0_fp_ctrl_wflags}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_wflags = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_69 = {{uops_3_fp_ctrl_vec}, {uops_2_fp_ctrl_vec}, {uops_1_fp_ctrl_vec}, {uops_0_fp_ctrl_vec}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_ctrl_vec = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_70 = {{uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rob_idx = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][3:0] _GEN_71 = {{uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldq_idx = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][3:0] _GEN_72 = {{uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_stq_idx = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_73 = {{uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:505:22, :547:21]
assign out_uop_rxq_idx = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_74 = {{uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_pdst = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_75 = {{uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1 = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_76 = {{uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2 = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_77 = {{uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3 = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_78 = {{uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_79 = {{uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs1_busy = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_80 = {{uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs2_busy = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_81 = {{uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_prs3_busy = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_82 = {{uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:505:22, :547:21]
assign out_uop_ppred_busy = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][6:0] _GEN_83 = {{uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:505:22, :547:21]
assign out_uop_stale_pdst = _GEN_83[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_84 = {{uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:505:22, :547:21]
assign out_uop_exception = _GEN_84[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][63:0] _GEN_85 = {{uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:505:22, :547:21]
assign out_uop_exc_cause = _GEN_85[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_86 = {{uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_cmd = _GEN_86[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_87 = {{uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_size = _GEN_87[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_88 = {{uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:505:22, :547:21]
assign out_uop_mem_signed = _GEN_88[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_89 = {{uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_ldq = _GEN_89[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_90 = {{uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:505:22, :547:21]
assign out_uop_uses_stq = _GEN_90[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_91 = {{uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:505:22, :547:21]
assign out_uop_is_unique = _GEN_91[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_92 = {{uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:505:22, :547:21]
assign out_uop_flush_on_commit = _GEN_92[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_93 = {{uops_3_csr_cmd}, {uops_2_csr_cmd}, {uops_1_csr_cmd}, {uops_0_csr_cmd}}; // @[util.scala:505:22, :547:21]
assign out_uop_csr_cmd = _GEN_93[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_94 = {{uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst_is_rs1 = _GEN_94[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_95 = {{uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:505:22, :547:21]
assign out_uop_ldst = _GEN_95[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_96 = {{uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1 = _GEN_96[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_97 = {{uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2 = _GEN_97[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][5:0] _GEN_98 = {{uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs3 = _GEN_98[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_99 = {{uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_dst_rtype = _GEN_99[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_100 = {{uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs1_rtype = _GEN_100[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_101 = {{uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:505:22, :547:21]
assign out_uop_lrs2_rtype = _GEN_101[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_102 = {{uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:505:22, :547:21]
assign out_uop_frs3_en = _GEN_102[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_103 = {{uops_3_fcn_dw}, {uops_2_fcn_dw}, {uops_1_fcn_dw}, {uops_0_fcn_dw}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_dw = _GEN_103[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][4:0] _GEN_104 = {{uops_3_fcn_op}, {uops_2_fcn_op}, {uops_1_fcn_op}, {uops_0_fcn_op}}; // @[util.scala:505:22, :547:21]
assign out_uop_fcn_op = _GEN_104[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_105 = {{uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_val = _GEN_105[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_106 = {{uops_3_fp_rm}, {uops_2_fp_rm}, {uops_1_fp_rm}, {uops_0_fp_rm}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_rm = _GEN_106[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][1:0] _GEN_107 = {{uops_3_fp_typ}, {uops_2_fp_typ}, {uops_1_fp_typ}, {uops_0_fp_typ}}; // @[util.scala:505:22, :547:21]
assign out_uop_fp_typ = _GEN_107[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_108 = {{uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_pf_if = _GEN_108[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_109 = {{uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ae_if = _GEN_109[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_110 = {{uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_xcpt_ma_if = _GEN_110[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_111 = {{uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_debug_if = _GEN_111[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0] _GEN_112 = {{uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:505:22, :547:21]
assign out_uop_bp_xcpt_if = _GEN_112[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_113 = {{uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_fsrc = _GEN_113[deq_ptr_value]; // @[Counter.scala:61:40]
wire [3:0][2:0] _GEN_114 = {{uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:505:22, :547:21]
assign out_uop_debug_tsrc = _GEN_114[deq_ptr_value]; // @[Counter.scala:61:40]
wire _io_deq_valid_T = ~io_empty; // @[util.scala:458:7, :515:71, :548:32]
assign _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:515:44, :548:{32,42}]
assign io_deq_valid_0 = _io_deq_valid_T_1; // @[util.scala:458:7, :548:42]
wire [2:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24]
wire [1:0] ptr_diff = _ptr_diff_T[1:0]; // @[util.scala:551:34]
wire [2:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:551:34, :553:{22,34}]
assign io_count = _io_count_T_1[1:0]; // @[util.scala:458:7, :553:{16,22}]
wire _GEN_115 = enq_ptr_value == 2'h0; // @[Counter.scala:61:40]
wire _GEN_116 = do_enq & _GEN_115; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_117 = enq_ptr_value == 2'h1; // @[Counter.scala:61:40]
wire _GEN_118 = do_enq & _GEN_117; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_119 = enq_ptr_value == 2'h2; // @[Counter.scala:61:40]
wire _GEN_120 = do_enq & _GEN_119; // @[util.scala:514:26, :520:18, :526:19, :528:35]
wire _GEN_121 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40]
always @(posedge clock) begin // @[util.scala:458:7]
if (reset) begin // @[util.scala:458:7]
valids_0 <= 1'h0; // @[util.scala:504:26]
valids_1 <= 1'h0; // @[util.scala:504:26]
valids_2 <= 1'h0; // @[util.scala:504:26]
valids_3 <= 1'h0; // @[util.scala:504:26]
enq_ptr_value <= 2'h0; // @[Counter.scala:61:40]
deq_ptr_value <= 2'h0; // @[Counter.scala:61:40]
maybe_full <= 1'h0; // @[util.scala:509:29]
end
else begin // @[util.scala:458:7]
valids_0 <= ~(do_deq & deq_ptr_value == 2'h0) & (_GEN_116 | _valids_0_T_7); // @[Counter.scala:61:40]
valids_1 <= ~(do_deq & deq_ptr_value == 2'h1) & (_GEN_118 | _valids_1_T_7); // @[Counter.scala:61:40]
valids_2 <= ~(do_deq & deq_ptr_value == 2'h2) & (_GEN_120 | _valids_2_T_7); // @[Counter.scala:61:40]
valids_3 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_121 | _valids_3_T_7); // @[Counter.scala:61:40]
if (do_enq) // @[util.scala:514:26]
enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24]
if (do_deq) // @[util.scala:515:26]
deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24]
if (~(do_enq == do_deq)) // @[util.scala:509:29, :514:26, :515:26, :539:{18,30}, :540:18]
maybe_full <= do_enq; // @[util.scala:509:29, :514:26]
end
if (_GEN_116) begin // @[util.scala:520:18, :526:19, :528:35]
uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_0_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_0_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_0_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_0_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_0_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_0_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_0_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_0_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_0_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_0_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_0_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_0_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_0_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_0_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_0_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_0_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_0_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_0_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_115) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_0) // @[util.scala:504:26]
uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_118) begin // @[util.scala:520:18, :526:19, :528:35]
uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_1_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_1_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_1_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_1_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_1_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_1_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_1_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_1_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_1_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_1_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_1_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_1_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_1_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_1_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_1_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_1_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_1_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_1_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_117) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_1) // @[util.scala:504:26]
uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_120) begin // @[util.scala:520:18, :526:19, :528:35]
uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_2_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_2_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_2_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_2_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_2_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_2_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_2_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_2_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_2_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_2_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_2_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_2_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_2_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_2_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_2_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_2_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_2_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_2_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & _GEN_119) // @[util.scala:514:26, :521:24, :526:19, :528:35, :530:35]
uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_2) // @[util.scala:504:26]
uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:97:21, :505:22]
if (_GEN_121) begin // @[util.scala:520:18, :526:19, :528:35]
uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:458:7, :505:22]
uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:458:7, :505:22]
uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_0 <= io_enq_bits_uop_iq_type_0_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_1 <= io_enq_bits_uop_iq_type_1_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_2 <= io_enq_bits_uop_iq_type_2_0; // @[util.scala:458:7, :505:22]
uops_3_iq_type_3 <= io_enq_bits_uop_iq_type_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_0 <= io_enq_bits_uop_fu_code_0_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_1 <= io_enq_bits_uop_fu_code_1_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_2 <= io_enq_bits_uop_fu_code_2_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_3 <= io_enq_bits_uop_fu_code_3_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_4 <= io_enq_bits_uop_fu_code_4_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_5 <= io_enq_bits_uop_fu_code_5_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_6 <= io_enq_bits_uop_fu_code_6_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_7 <= io_enq_bits_uop_fu_code_7_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_8 <= io_enq_bits_uop_fu_code_8_0; // @[util.scala:458:7, :505:22]
uops_3_fu_code_9 <= io_enq_bits_uop_fu_code_9_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued <= io_enq_bits_uop_iw_issued_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_agen <= io_enq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_issued_partial_dgen <= io_enq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_speculative_child <= io_enq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_speculative_child <= io_enq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p1_bypass_hint <= io_enq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p2_bypass_hint <= io_enq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_iw_p3_bypass_hint <= io_enq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7, :505:22]
uops_3_dis_col_sel <= io_enq_bits_uop_dis_col_sel_0; // @[util.scala:458:7, :505:22]
uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:458:7, :505:22]
uops_3_br_type <= io_enq_bits_uop_br_type_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:458:7, :505:22]
uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:458:7, :505:22]
uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:458:7, :505:22]
uops_3_is_sfence <= io_enq_bits_uop_is_sfence_0; // @[util.scala:458:7, :505:22]
uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:458:7, :505:22]
uops_3_is_eret <= io_enq_bits_uop_is_eret_0; // @[util.scala:458:7, :505:22]
uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7, :505:22]
uops_3_is_rocc <= io_enq_bits_uop_is_rocc_0; // @[util.scala:458:7, :505:22]
uops_3_is_mov <= io_enq_bits_uop_is_mov_0; // @[util.scala:458:7, :505:22]
uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:458:7, :505:22]
uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:458:7, :505:22]
uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:458:7, :505:22]
uops_3_imm_rename <= io_enq_bits_uop_imm_rename_0; // @[util.scala:458:7, :505:22]
uops_3_imm_sel <= io_enq_bits_uop_imm_sel_0; // @[util.scala:458:7, :505:22]
uops_3_pimm <= io_enq_bits_uop_pimm_0; // @[util.scala:458:7, :505:22]
uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:458:7, :505:22]
uops_3_op1_sel <= io_enq_bits_uop_op1_sel_0; // @[util.scala:458:7, :505:22]
uops_3_op2_sel <= io_enq_bits_uop_op2_sel_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ldst <= io_enq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wen <= io_enq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren1 <= io_enq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren2 <= io_enq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_ren3 <= io_enq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap12 <= io_enq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_swap23 <= io_enq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagIn <= io_enq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_typeTagOut <= io_enq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fromint <= io_enq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_toint <= io_enq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fastpipe <= io_enq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_fma <= io_enq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_div <= io_enq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_sqrt <= io_enq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_wflags <= io_enq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7, :505:22]
uops_3_fp_ctrl_vec <= io_enq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7, :505:22]
uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:458:7, :505:22]
uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:458:7, :505:22]
uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:458:7, :505:22]
uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:458:7, :505:22]
uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:458:7, :505:22]
uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:458:7, :505:22]
uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:458:7, :505:22]
uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:458:7, :505:22]
uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:458:7, :505:22]
uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:458:7, :505:22]
uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:458:7, :505:22]
uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:458:7, :505:22]
uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:458:7, :505:22]
uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:458:7, :505:22]
uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:458:7, :505:22]
uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:458:7, :505:22]
uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:458:7, :505:22]
uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:458:7, :505:22]
uops_3_csr_cmd <= io_enq_bits_uop_csr_cmd_0; // @[util.scala:458:7, :505:22]
uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7, :505:22]
uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:458:7, :505:22]
uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:458:7, :505:22]
uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7, :505:22]
uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_dw <= io_enq_bits_uop_fcn_dw_0; // @[util.scala:458:7, :505:22]
uops_3_fcn_op <= io_enq_bits_uop_fcn_op_0; // @[util.scala:458:7, :505:22]
uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:458:7, :505:22]
uops_3_fp_rm <= io_enq_bits_uop_fp_rm_0; // @[util.scala:458:7, :505:22]
uops_3_fp_typ <= io_enq_bits_uop_fp_typ_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7, :505:22]
uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:458:7, :505:22]
uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7, :505:22]
uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:458:7, :505:22]
uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:458:7, :505:22]
end
if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40]
uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:93:25, :505:22]
else if (valids_3) // @[util.scala:504:26]
uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:97:21, :505:22]
always @(posedge)
ram_4x65 ram_ext ( // @[util.scala:503:22]
.R0_addr (deq_ptr_value), // @[Counter.scala:61:40]
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_ram_ext_R0_data),
.W0_addr (enq_ptr_value), // @[Counter.scala:61:40]
.W0_en (do_enq), // @[util.scala:514:26]
.W0_clk (clock),
.W0_data ({io_enq_bits_is_hella_0, io_enq_bits_data_0}) // @[util.scala:458:7, :503:22]
); // @[util.scala:503:22]
assign io_enq_ready = io_enq_ready_0; // @[util.scala:458:7]
assign io_deq_valid = io_deq_valid_0; // @[util.scala:458:7]
assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_0 = io_deq_bits_uop_iq_type_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_1 = io_deq_bits_uop_iq_type_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_2 = io_deq_bits_uop_iq_type_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iq_type_3 = io_deq_bits_uop_iq_type_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_0 = io_deq_bits_uop_fu_code_0_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_1 = io_deq_bits_uop_fu_code_1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_2 = io_deq_bits_uop_fu_code_2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_3 = io_deq_bits_uop_fu_code_3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_4 = io_deq_bits_uop_fu_code_4_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_5 = io_deq_bits_uop_fu_code_5_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_6 = io_deq_bits_uop_fu_code_6_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_7 = io_deq_bits_uop_fu_code_7_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_8 = io_deq_bits_uop_fu_code_8_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fu_code_9 = io_deq_bits_uop_fu_code_9_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued = io_deq_bits_uop_iw_issued_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_agen = io_deq_bits_uop_iw_issued_partial_agen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_issued_partial_dgen = io_deq_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_speculative_child = io_deq_bits_uop_iw_p1_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_speculative_child = io_deq_bits_uop_iw_p2_speculative_child_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p1_bypass_hint = io_deq_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p2_bypass_hint = io_deq_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_iw_p3_bypass_hint = io_deq_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dis_col_sel = io_deq_bits_uop_dis_col_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:458:7]
assign io_deq_bits_uop_br_type = io_deq_bits_uop_br_type_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sfence = io_deq_bits_uop_is_sfence_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_eret = io_deq_bits_uop_is_eret_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_rocc = io_deq_bits_uop_is_rocc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_mov = io_deq_bits_uop_is_mov_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:458:7]
assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_rename = io_deq_bits_uop_imm_rename_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_sel = io_deq_bits_uop_imm_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pimm = io_deq_bits_uop_pimm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op1_sel = io_deq_bits_uop_op1_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_op2_sel = io_deq_bits_uop_op2_sel_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ldst = io_deq_bits_uop_fp_ctrl_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wen = io_deq_bits_uop_fp_ctrl_wen_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren1 = io_deq_bits_uop_fp_ctrl_ren1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren2 = io_deq_bits_uop_fp_ctrl_ren2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_ren3 = io_deq_bits_uop_fp_ctrl_ren3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap12 = io_deq_bits_uop_fp_ctrl_swap12_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_swap23 = io_deq_bits_uop_fp_ctrl_swap23_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagIn = io_deq_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_typeTagOut = io_deq_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fromint = io_deq_bits_uop_fp_ctrl_fromint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_toint = io_deq_bits_uop_fp_ctrl_toint_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fastpipe = io_deq_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_fma = io_deq_bits_uop_fp_ctrl_fma_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_div = io_deq_bits_uop_fp_ctrl_div_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_sqrt = io_deq_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_wflags = io_deq_bits_uop_fp_ctrl_wflags_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_ctrl_vec = io_deq_bits_uop_fp_ctrl_vec_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:458:7]
assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:458:7]
assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:458:7]
assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:458:7]
assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:458:7]
assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:458:7]
assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:458:7]
assign io_deq_bits_uop_csr_cmd = io_deq_bits_uop_csr_cmd_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:458:7]
assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:458:7]
assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_dw = io_deq_bits_uop_fcn_dw_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fcn_op = io_deq_bits_uop_fcn_op_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_rm = io_deq_bits_uop_fp_rm_0; // @[util.scala:458:7]
assign io_deq_bits_uop_fp_typ = io_deq_bits_uop_fp_typ_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:458:7]
assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:458:7]
assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:458:7]
assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:458:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
|
module RecFNToRecFN( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [64:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire rawIn_isNaN = (&(io_in[31:30])) & io_in[29]; // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:{33,41}]
RoundAnyRawFNToRecFN_ie8_is24_oe11_os53 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19]
.io_invalidExc (rawIn_isNaN & ~(io_in[22])), // @[rawFloatFromRecFN.scala:56:33]
.io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:56:33]
.io_in_isInf ((&(io_in[31:30])) & ~(io_in[29])), // @[rawFloatFromRecFN.scala:51:21, :53:{28,53}, :56:41, :57:{33,36}]
.io_in_isZero (~(|(io_in[31:29]))), // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}]
.io_in_sign (io_in[32]), // @[rawFloatFromRecFN.scala:59:25]
.io_in_sExp ({1'h0, io_in[31:23]}), // @[rawFloatFromRecFN.scala:51:21, :60:27]
.io_in_sig ({1'h0, |(io_in[31:29]), io_in[22:0]}), // @[rawFloatFromRecFN.scala:51:21, :52:{28,53}, :61:{44,49}]
.io_out (io_out)
); // @[RecFNToRecFN.scala:72:19]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module PE_388( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_132 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module PE_256( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_44( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_b_ready, // @[Monitor.scala:20:14]
input io_in_b_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_b_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14]
input io_in_b_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_c_ready, // @[Monitor.scala:20:14]
input io_in_c_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_c_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [5:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_e_ready, // @[Monitor.scala:20:14]
input io_in_e_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire [26:0] _GEN_0 = {23'h0, io_in_c_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [5:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _d_first_T_3 = io_in_d_ready & io_in_d_valid; // @[Decoupled.scala:51:35]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [5:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [8:0] b_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_2; // @[Monitor.scala:410:22]
reg [1:0] param_2; // @[Monitor.scala:411:22]
reg [3:0] size_2; // @[Monitor.scala:412:22]
reg [5:0] source_2; // @[Monitor.scala:413:22]
reg [31:0] address_1; // @[Monitor.scala:414:22]
wire _c_first_T_1 = io_in_c_ready & io_in_c_valid; // @[Decoupled.scala:51:35]
reg [8:0] c_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_3; // @[Monitor.scala:515:22]
reg [2:0] param_3; // @[Monitor.scala:516:22]
reg [3:0] size_3; // @[Monitor.scala:517:22]
reg [5:0] source_3; // @[Monitor.scala:518:22]
reg [31:0] address_2; // @[Monitor.scala:519:22]
reg [34:0] inflight; // @[Monitor.scala:614:27]
reg [139:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [279:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire [63:0] _GEN_1 = {58'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_2 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_3 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [63:0] _GEN_4 = {58'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [34:0] inflight_1; // @[Monitor.scala:726:35]
reg [279:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] c_first_counter_1; // @[Edges.scala:229:27]
wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_5 = io_in_c_bits_opcode[2] & io_in_c_bits_opcode[1]; // @[Edges.scala:68:{36,40,51}]
wire [63:0] _GEN_6 = {58'h0, io_in_c_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_7 = _c_first_T_1 & c_first_1 & _GEN_5; // @[Decoupled.scala:51:35]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
reg [7:0] inflight_2; // @[Monitor.scala:828:27]
reg [8:0] d_first_counter_3; // @[Edges.scala:229:27]
wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_8 = _d_first_T_3 & d_first_3 & io_in_d_bits_opcode[2] & ~(io_in_d_bits_opcode[1]); // @[Decoupled.scala:51:35]
wire [7:0] _GEN_9 = {5'h0, io_in_d_bits_sink}; // @[OneHot.scala:58:35]
wire [7:0] d_set = _GEN_8 ? 8'h1 << _GEN_9 : 8'h0; // @[OneHot.scala:58:35]
wire _GEN_10 = io_in_e_ready & io_in_e_valid; // @[Decoupled.scala:51:35]
wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink}; // @[OneHot.scala:58:35]
|
Generate the Verilog code corresponding to the following Chisel files.
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
|
module rockettile_dcache_tag_array_4( // @[DescribedSRAM.scala:17:26]
input [5:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [175:0] RW0_wdata,
output [175:0] RW0_rdata,
input [7:0] RW0_wmask
);
rockettile_dcache_tag_array_ext rockettile_dcache_tag_array_ext ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
); // @[DescribedSRAM.scala:17:26]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module PE_420( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_164 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_76( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [258:0] _c_sizes_set_T_1 = 259'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [79:0] c_opcodes_set = 80'h0; // @[Monitor.scala:740:34]
wire [79:0] c_sizes_set = 80'h0; // @[Monitor.scala:741:34]
wire [19:0] c_set = 20'h0; // @[Monitor.scala:738:34]
wire [19:0] c_set_wo_ready = 20'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 5'h14; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_732 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_732; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_732; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_805 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_805; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_805; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [19:0] inflight; // @[Monitor.scala:614:27]
reg [79:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [79:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [19:0] a_set; // @[Monitor.scala:626:34]
wire [19:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [79:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [79:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [79:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [79:0] _a_opcode_lookup_T_6 = {76'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [79:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [79:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [79:0] _a_size_lookup_T_6 = {76'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [79:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[79:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_2 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_658 = _T_732 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_658 ? _a_set_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_658 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_658 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [7:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [7:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_658 ? _a_opcodes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [258:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_658 ? _a_sizes_set_T_1[79:0] : 80'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [19:0] d_clr; // @[Monitor.scala:664:34]
wire [19:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [79:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [79:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_704 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_704 & ~d_release_ack ? _d_clr_wo_ready_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_673 = _T_805 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_673 ? _d_clr_T[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_673 ? _d_opcodes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_673 ? _d_sizes_clr_T_5[79:0] : 80'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [19:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [19:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [19:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [79:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [79:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [79:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [79:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [79:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [79:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [19:0] inflight_1; // @[Monitor.scala:726:35]
wire [19:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [79:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [79:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [79:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [79:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [79:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [79:0] _c_opcode_lookup_T_6 = {76'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [79:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[79:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [79:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [79:0] _c_size_lookup_T_6 = {76'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [79:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[79:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [19:0] d_clr_1; // @[Monitor.scala:774:34]
wire [19:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [79:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [79:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_776 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_776 & d_release_ack_1 ? _d_clr_wo_ready_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire _T_758 = _T_805 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_758 ? _d_clr_T_1[19:0] : 20'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_758 ? _d_opcodes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_758 ? _d_sizes_clr_T_11[79:0] : 80'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [19:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [19:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [79:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [79:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [79:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [79:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerShiftReg_w1_d3_i0_200( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_360 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerShiftReg_w1_d3_i0_147( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_255 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File RoundAnyRawFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util.Fill
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundAnyRawFNToRecFN(
inExpWidth: Int,
inSigWidth: Int,
outExpWidth: Int,
outSigWidth: Int,
options: Int
)
extends RawModule
{
override def desiredName = s"RoundAnyRawFNToRecFN_ie${inExpWidth}_is${inSigWidth}_oe${outExpWidth}_os${outSigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(inExpWidth, inSigWidth))
// (allowed exponent range has limits)
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sigMSBitAlwaysZero = ((options & flRoundOpt_sigMSBitAlwaysZero) != 0)
val effectiveInSigWidth =
if (sigMSBitAlwaysZero) inSigWidth else inSigWidth + 1
val neverUnderflows =
((options &
(flRoundOpt_neverUnderflows | flRoundOpt_subnormsAlwaysExact)
) != 0) ||
(inExpWidth < outExpWidth)
val neverOverflows =
((options & flRoundOpt_neverOverflows) != 0) ||
(inExpWidth < outExpWidth)
val outNaNExp = BigInt(7)<<(outExpWidth - 2)
val outInfExp = BigInt(6)<<(outExpWidth - 2)
val outMaxFiniteExp = outInfExp - 1
val outMinNormExp = (BigInt(1)<<(outExpWidth - 1)) + 2
val outMinNonzeroExp = outMinNormExp - outSigWidth + 1
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundingMode_near_even = (io.roundingMode === round_near_even)
val roundingMode_minMag = (io.roundingMode === round_minMag)
val roundingMode_min = (io.roundingMode === round_min)
val roundingMode_max = (io.roundingMode === round_max)
val roundingMode_near_maxMag = (io.roundingMode === round_near_maxMag)
val roundingMode_odd = (io.roundingMode === round_odd)
val roundMagUp =
(roundingMode_min && io.in.sign) || (roundingMode_max && ! io.in.sign)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val sAdjustedExp =
if (inExpWidth < outExpWidth)
(io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
)(outExpWidth, 0).zext
else if (inExpWidth == outExpWidth)
io.in.sExp
else
io.in.sExp +&
((BigInt(1)<<outExpWidth) - (BigInt(1)<<inExpWidth)).S
val adjustedSig =
if (inSigWidth <= outSigWidth + 2)
io.in.sig<<(outSigWidth - inSigWidth + 2)
else
(io.in.sig(inSigWidth, inSigWidth - outSigWidth - 1) ##
io.in.sig(inSigWidth - outSigWidth - 2, 0).orR
)
val doShiftSigDown1 =
if (sigMSBitAlwaysZero) false.B else adjustedSig(outSigWidth + 2)
val common_expOut = Wire(UInt((outExpWidth + 1).W))
val common_fractOut = Wire(UInt((outSigWidth - 1).W))
val common_overflow = Wire(Bool())
val common_totalUnderflow = Wire(Bool())
val common_underflow = Wire(Bool())
val common_inexact = Wire(Bool())
if (
neverOverflows && neverUnderflows
&& (effectiveInSigWidth <= outSigWidth)
) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
common_expOut := sAdjustedExp(outExpWidth, 0) + doShiftSigDown1
common_fractOut :=
Mux(doShiftSigDown1,
adjustedSig(outSigWidth + 1, 3),
adjustedSig(outSigWidth, 2)
)
common_overflow := false.B
common_totalUnderflow := false.B
common_underflow := false.B
common_inexact := false.B
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundMask =
if (neverUnderflows)
0.U(outSigWidth.W) ## doShiftSigDown1 ## 3.U(2.W)
else
(lowMask(
sAdjustedExp(outExpWidth, 0),
outMinNormExp - outSigWidth - 1,
outMinNormExp
) | doShiftSigDown1) ##
3.U(2.W)
val shiftedRoundMask = 0.U(1.W) ## roundMask>>1
val roundPosMask = ~shiftedRoundMask & roundMask
val roundPosBit = (adjustedSig & roundPosMask).orR
val anyRoundExtra = (adjustedSig & shiftedRoundMask).orR
val anyRound = roundPosBit || anyRoundExtra
val roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
roundPosBit) ||
(roundMagUp && anyRound)
val roundedSig: Bits =
Mux(roundIncr,
(((adjustedSig | roundMask)>>2) +& 1.U) &
~Mux(roundingMode_near_even && roundPosBit &&
! anyRoundExtra,
roundMask>>1,
0.U((outSigWidth + 2).W)
),
(adjustedSig & ~roundMask)>>2 |
Mux(roundingMode_odd && anyRound, roundPosMask>>1, 0.U)
)
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
val sRoundedExp = sAdjustedExp +& (roundedSig>>outSigWidth).asUInt.zext
common_expOut := sRoundedExp(outExpWidth, 0)
common_fractOut :=
Mux(doShiftSigDown1,
roundedSig(outSigWidth - 1, 1),
roundedSig(outSigWidth - 2, 0)
)
common_overflow :=
(if (neverOverflows) false.B else
//*** REWRITE BASED ON BEFORE-ROUNDING EXPONENT?:
(sRoundedExp>>(outExpWidth - 1) >= 3.S))
common_totalUnderflow :=
(if (neverUnderflows) false.B else
//*** WOULD BE GOOD ENOUGH TO USE EXPONENT BEFORE ROUNDING?:
(sRoundedExp < outMinNonzeroExp.S))
val unboundedRange_roundPosBit =
Mux(doShiftSigDown1, adjustedSig(2), adjustedSig(1))
val unboundedRange_anyRound =
(doShiftSigDown1 && adjustedSig(2)) || adjustedSig(1, 0).orR
val unboundedRange_roundIncr =
((roundingMode_near_even || roundingMode_near_maxMag) &&
unboundedRange_roundPosBit) ||
(roundMagUp && unboundedRange_anyRound)
val roundCarry =
Mux(doShiftSigDown1,
roundedSig(outSigWidth + 1),
roundedSig(outSigWidth)
)
common_underflow :=
(if (neverUnderflows) false.B else
common_totalUnderflow ||
//*** IF SIG WIDTH IS VERY NARROW, NEED TO ACCOUNT FOR ROUND-EVEN ZEROING
//*** M.S. BIT OF SUBNORMAL SIG?
(anyRound && ((sAdjustedExp>>outExpWidth) <= 0.S) &&
Mux(doShiftSigDown1, roundMask(3), roundMask(2)) &&
! ((io.detectTininess === tininess_afterRounding) &&
! Mux(doShiftSigDown1,
roundMask(4),
roundMask(3)
) &&
roundCarry && roundPosBit &&
unboundedRange_roundIncr)))
common_inexact := common_totalUnderflow || anyRound
}
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val isNaNOut = io.invalidExc || io.in.isNaN
val notNaN_isSpecialInfOut = io.infiniteExc || io.in.isInf
val commonCase = ! isNaNOut && ! notNaN_isSpecialInfOut && ! io.in.isZero
val overflow = commonCase && common_overflow
val underflow = commonCase && common_underflow
val inexact = overflow || (commonCase && common_inexact)
val overflow_roundMagUp =
roundingMode_near_even || roundingMode_near_maxMag || roundMagUp
val pegMinNonzeroMagOut =
commonCase && common_totalUnderflow && (roundMagUp || roundingMode_odd)
val pegMaxFiniteMagOut = overflow && ! overflow_roundMagUp
val notNaN_isInfOut =
notNaN_isSpecialInfOut || (overflow && overflow_roundMagUp)
val signOut = Mux(isNaNOut, false.B, io.in.sign)
val expOut =
(common_expOut &
~Mux(io.in.isZero || common_totalUnderflow,
(BigInt(7)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMinNonzeroMagOut,
~outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) &
~Mux(pegMaxFiniteMagOut,
(BigInt(1)<<(outExpWidth - 1)).U((outExpWidth + 1).W),
0.U
) &
~Mux(notNaN_isInfOut,
(BigInt(1)<<(outExpWidth - 2)).U((outExpWidth + 1).W),
0.U
)) |
Mux(pegMinNonzeroMagOut,
outMinNonzeroExp.U((outExpWidth + 1).W),
0.U
) |
Mux(pegMaxFiniteMagOut,
outMaxFiniteExp.U((outExpWidth + 1).W),
0.U
) |
Mux(notNaN_isInfOut, outInfExp.U((outExpWidth + 1).W), 0.U) |
Mux(isNaNOut, outNaNExp.U((outExpWidth + 1).W), 0.U)
val fractOut =
Mux(isNaNOut || io.in.isZero || common_totalUnderflow,
Mux(isNaNOut, (BigInt(1)<<(outSigWidth - 2)).U, 0.U),
common_fractOut
) |
Fill(outSigWidth - 1, pegMaxFiniteMagOut)
io.out := signOut ## expOut ## fractOut
io.exceptionFlags :=
io.invalidExc ## io.infiniteExc ## overflow ## underflow ## inexact
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class
RoundRawFNToRecFN(expWidth: Int, sigWidth: Int, options: Int)
extends RawModule
{
override def desiredName = s"RoundRawFNToRecFN_e${expWidth}_s${sigWidth}"
val io = IO(new Bundle {
val invalidExc = Input(Bool()) // overrides 'infiniteExc' and 'in'
val infiniteExc = Input(Bool()) // overrides 'in' except for 'in.sign'
val in = Input(new RawFloat(expWidth, sigWidth + 2))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
expWidth, sigWidth + 2, expWidth, sigWidth, options))
roundAnyRawFNToRecFN.io.invalidExc := io.invalidExc
roundAnyRawFNToRecFN.io.infiniteExc := io.infiniteExc
roundAnyRawFNToRecFN.io.in := io.in
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
|
module RoundRawFNToRecFN_e8_s24_58( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_58 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File RouteComputer.scala:
package constellation.router
import chisel3._
import chisel3.util._
import chisel3.util.experimental.decode.{TruthTable, decoder}
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import freechips.rocketchip.rocket.DecodeLogic
import constellation.channel._
import constellation.routing.{FlowRoutingBundle, FlowRoutingInfo}
import constellation.noc.{HasNoCParams}
class RouteComputerReq(implicit val p: Parameters) extends Bundle with HasNoCParams {
val src_virt_id = UInt(virtualChannelBits.W)
val flow = new FlowRoutingBundle
}
class RouteComputerResp(
val outParams: Seq[ChannelParams],
val egressParams: Seq[EgressChannelParams])(implicit val p: Parameters) extends Bundle
with HasRouterOutputParams {
val vc_sel = MixedVec(allOutParams.map { u => Vec(u.nVirtualChannels, Bool()) })
}
class RouteComputer(
val routerParams: RouterParams,
val inParams: Seq[ChannelParams],
val outParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val egressParams: Seq[EgressChannelParams]
)(implicit val p: Parameters) extends Module
with HasRouterParams
with HasRouterInputParams
with HasRouterOutputParams
with HasNoCParams {
val io = IO(new Bundle {
val req = MixedVec(allInParams.map { u => Flipped(Decoupled(new RouteComputerReq)) })
val resp = MixedVec(allInParams.map { u => Output(new RouteComputerResp(outParams, egressParams)) })
})
(io.req zip io.resp).zipWithIndex.map { case ((req, resp), i) =>
req.ready := true.B
if (outParams.size == 0) {
assert(!req.valid)
resp.vc_sel := DontCare
} else {
def toUInt(t: (Int, FlowRoutingInfo)): UInt = {
val l2 = (BigInt(t._1) << req.bits.flow.vnet_id .getWidth) | t._2.vNetId
val l3 = ( l2 << req.bits.flow.ingress_node .getWidth) | t._2.ingressNode
val l4 = ( l3 << req.bits.flow.ingress_node_id.getWidth) | t._2.ingressNodeId
val l5 = ( l4 << req.bits.flow.egress_node .getWidth) | t._2.egressNode
val l6 = ( l5 << req.bits.flow.egress_node_id .getWidth) | t._2.egressNodeId
l6.U(req.bits.getWidth.W)
}
val flow = req.bits.flow
val table = allInParams(i).possibleFlows.toSeq.distinct.map { pI =>
allInParams(i).channelRoutingInfos.map { cI =>
var row: String = "b"
(0 until nOutputs).foreach { o =>
(0 until outParams(o).nVirtualChannels).foreach { outVId =>
row = row + (if (routingRelation(cI, outParams(o).channelRoutingInfos(outVId), pI)) "1" else "0")
}
}
((cI.vc, pI), row)
}
}.flatten
val addr = req.bits.asUInt
val width = outParams.map(_.nVirtualChannels).reduce(_+_)
val decoded = if (table.size > 0) {
val truthTable = TruthTable(
table.map { e => (BitPat(toUInt(e._1)), BitPat(e._2)) },
BitPat("b" + "?" * width)
)
Reverse(decoder(addr, truthTable))
} else {
0.U(width.W)
}
var idx = 0
(0 until nAllOutputs).foreach { o =>
if (o < nOutputs) {
(0 until outParams(o).nVirtualChannels).foreach { outVId =>
resp.vc_sel(o)(outVId) := decoded(idx)
idx += 1
}
} else {
resp.vc_sel(o)(0) := false.B
}
}
}
}
}
|
module RouteComputer_8( // @[RouteComputer.scala:29:7]
input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [2:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [3:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14]
input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14]
input [2:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14]
input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14]
input [2:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_3, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_8, // @[RouteComputer.scala:40:14]
output io_resp_2_vc_sel_0_9, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_1, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_8, // @[RouteComputer.scala:40:14]
output io_resp_1_vc_sel_0_9, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_0_2, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_0_4, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_0_6, // @[RouteComputer.scala:40:14]
output io_resp_0_vc_sel_0_8 // @[RouteComputer.scala:40:14]
);
wire [20:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id, io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21]
wire [1:0] _GEN = ~(io_req_1_bits_flow_egress_node[3:2]); // @[pla.scala:78:21]
assign io_resp_2_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_0_3 = &{io_req_2_bits_flow_egress_node_id[0], ~(io_req_2_bits_flow_egress_node[3])}; // @[pla.scala:78:21, :90:45, :98:{53,70}]
assign io_resp_2_vc_sel_0_4 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_0_5 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_0_6 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_0_7 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_0_8 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_2_vc_sel_0_9 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_0 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_1 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_2 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_3 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_4 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_5 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_6 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_7 = &{_GEN[0], _GEN[1]}; // @[pla.scala:78:21, :91:29, :98:{53,70}]
assign io_resp_1_vc_sel_0_8 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_1_vc_sel_0_9 = 1'h0; // @[RouteComputer.scala:29:7]
assign io_resp_0_vc_sel_0_0 = |{&{decoded_invInputs[0], io_req_0_bits_flow_egress_node_id[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node_id[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_0_2 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_0_4 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[4], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_0_6 = |{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[5], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
assign io_resp_0_vc_sel_0_8 = |{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Arbiter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
object TLArbiter
{
// (valids, select) => readys
type Policy = (Integer, UInt, Bool) => UInt
val lowestIndexFirst: Policy = (width, valids, select) => ~(leftOR(valids) << 1)(width-1, 0)
val highestIndexFirst: Policy = (width, valids, select) => ~((rightOR(valids) >> 1).pad(width))
val roundRobin: Policy = (width, valids, select) => if (width == 1) 1.U(1.W) else {
val valid = valids(width-1, 0)
assert (valid === valids)
val mask = RegInit(((BigInt(1) << width)-1).U(width-1,0))
val filter = Cat(valid & ~mask, valid)
val unready = (rightOR(filter, width*2, width) >> 1) | (mask << width)
val readys = ~((unready >> width) & unready(width-1, 0))
when (select && valid.orR) {
mask := leftOR(readys & valid, width)
}
readys(width-1, 0)
}
def lowestFromSeq[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: Seq[DecoupledIO[T]]): Unit = {
apply(lowestIndexFirst)(sink, sources.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def lowest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(lowestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def highest[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(highestIndexFirst)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def robin[T <: TLChannel](edge: TLEdge, sink: DecoupledIO[T], sources: DecoupledIO[T]*): Unit = {
apply(roundRobin)(sink, sources.toList.map(s => (edge.numBeats1(s.bits), s)):_*)
}
def apply[T <: Data](policy: Policy)(sink: DecoupledIO[T], sources: (UInt, DecoupledIO[T])*): Unit = {
if (sources.isEmpty) {
sink.bits := DontCare
} else if (sources.size == 1) {
sink :<>= sources.head._2
} else {
val pairs = sources.toList
val beatsIn = pairs.map(_._1)
val sourcesIn = pairs.map(_._2)
// The number of beats which remain to be sent
val beatsLeft = RegInit(0.U)
val idle = beatsLeft === 0.U
val latch = idle && sink.ready // winner (if any) claims sink
// Who wants access to the sink?
val valids = sourcesIn.map(_.valid)
// Arbitrate amongst the requests
val readys = VecInit(policy(valids.size, Cat(valids.reverse), latch).asBools)
// Which request wins arbitration?
val winner = VecInit((readys zip valids) map { case (r,v) => r&&v })
// Confirm the policy works properly
require (readys.size == valids.size)
// Never two winners
val prefixOR = winner.scanLeft(false.B)(_||_).init
assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})
// If there was any request, there is a winner
assert (!valids.reduce(_||_) || winner.reduce(_||_))
// Track remaining beats
val maskedBeats = (winner zip beatsIn) map { case (w,b) => Mux(w, b, 0.U) }
val initBeats = maskedBeats.reduce(_ | _) // no winner => 0 beats
beatsLeft := Mux(latch, initBeats, beatsLeft - sink.fire)
// The one-hot source granted access in the previous cycle
val state = RegInit(VecInit(Seq.fill(sources.size)(false.B)))
val muxState = Mux(idle, winner, state)
state := muxState
val allowed = Mux(idle, readys, state)
(sourcesIn zip allowed) foreach { case (s, r) =>
s.ready := sink.ready && r
}
sink.valid := Mux(idle, valids.reduce(_||_), Mux1H(state, valids))
sink.bits :<= Mux1H(muxState, sourcesIn.map(_.bits))
}
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
abstract class DecoupledArbiterTest(
policy: TLArbiter.Policy,
txns: Int,
timeout: Int,
val numSources: Int,
beatsLeftFromIdx: Int => UInt)
(implicit p: Parameters) extends UnitTest(timeout)
{
val sources = Wire(Vec(numSources, DecoupledIO(UInt(log2Ceil(numSources).W))))
dontTouch(sources.suggestName("sources"))
val sink = Wire(DecoupledIO(UInt(log2Ceil(numSources).W)))
dontTouch(sink.suggestName("sink"))
val count = RegInit(0.U(log2Ceil(txns).W))
val lfsr = LFSR(16, true.B)
sources.zipWithIndex.map { case (z, i) => z.bits := i.U }
TLArbiter(policy)(sink, sources.zipWithIndex.map {
case (z, i) => (beatsLeftFromIdx(i), z)
}:_*)
count := count + 1.U
io.finished := count >= txns.U
}
/** This tests that when a specific pattern of source valids are driven,
* a new index from amongst that pattern is always selected,
* unless one of those sources takes multiple beats,
* in which case the same index should be selected until the arbiter goes idle.
*/
class TLDecoupledArbiterRobinTest(txns: Int = 128, timeout: Int = 500000, print: Boolean = false)
(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.roundRobin, txns, timeout, 6, i => i.U)
{
val lastWinner = RegInit((numSources+1).U)
val beatsLeft = RegInit(0.U(log2Ceil(numSources).W))
val first = lastWinner > numSources.U
val valid = lfsr(0)
val ready = lfsr(15)
sink.ready := ready
sources.zipWithIndex.map { // pattern: every even-indexed valid is driven the same random way
case (s, i) => s.valid := (if (i % 2 == 1) false.B else valid)
}
when (sink.fire) {
if (print) { printf("TestRobin: %d\n", sink.bits) }
when (beatsLeft === 0.U) {
assert(lastWinner =/= sink.bits, "Round robin did not pick a new idx despite one being valid.")
lastWinner := sink.bits
beatsLeft := sink.bits
} .otherwise {
assert(lastWinner === sink.bits, "Round robin did not pick the same index over multiple beats")
beatsLeft := beatsLeft - 1.U
}
}
if (print) {
when (!sink.fire) { printf("TestRobin: idle (%d %d)\n", valid, ready) }
}
}
/** This tests that the lowest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterLowestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.lowestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertLowest(id: Int): Unit = {
when (sources(id).valid) {
assert((numSources-1 until id by -1).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a higher valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertLowest(_)) }
}
/** This tests that the highest index is always selected across random single cycle transactions. */
class TLDecoupledArbiterHighestTest(txns: Int = 128, timeout: Int = 500000)(implicit p: Parameters)
extends DecoupledArbiterTest(TLArbiter.highestIndexFirst, txns, timeout, 15, _ => 0.U)
{
def assertHighest(id: Int): Unit = {
when (sources(id).valid) {
assert((0 until id).map(!sources(_).fire).foldLeft(true.B)(_&&_), s"$id was valid but a lower valid source was granted ready.")
}
}
sources.zipWithIndex.map { case (s, i) => s.valid := lfsr(i) }
sink.ready := lfsr(15)
when (sink.fire) { (0 until numSources).foreach(assertHighest(_)) }
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
|
module TLXbar_cbus_out_i1_o8_a29d64s10k1z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [28:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_7_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_anon_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_7_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_6_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [16:0] auto_anon_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_6_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_6_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_5_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [11:0] auto_anon_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_5_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_5_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_4_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_anon_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_4_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_4_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_3_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_anon_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_3_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_3_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [28:0] auto_anon_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_secure, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_user_amba_prot_fetch, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_2_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [25:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [13:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire requestAIO_0_0 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], ~(auto_anon_in_a_bits_address[13:12])} == 7'h0; // @[Xbar.scala:222:41]
wire [9:0] _GEN = auto_anon_in_a_bits_address[25:16] ^ 10'h201; // @[Xbar.scala:222:41]
wire requestAIO_0_1 = {auto_anon_in_a_bits_address[28:27], _GEN[9], auto_anon_in_a_bits_address[20], _GEN[0], auto_anon_in_a_bits_address[13:12]} == 7'h0; // @[Xbar.scala:222:41]
wire [1:0] _requestAIO_T_20 = auto_anon_in_a_bits_address[28:27] ^ 2'h2; // @[Parameters.scala:137:31]
wire requestAIO_0_2 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13], ~(auto_anon_in_a_bits_address[12])} == 7'h0 | {_requestAIO_T_20, auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20]} == 4'h0 | {_requestAIO_T_20, auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13:12]} == 7'h0; // @[Xbar.scala:222:41, :291:92]
wire requestAIO_0_3 = {auto_anon_in_a_bits_address[28:27], ~(auto_anon_in_a_bits_address[25]), auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16]} == 5'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire requestAIO_0_4 = {auto_anon_in_a_bits_address[28], ~(auto_anon_in_a_bits_address[27])} == 2'h0; // @[Xbar.scala:222:41]
wire requestAIO_0_5 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], auto_anon_in_a_bits_address[16], auto_anon_in_a_bits_address[13:12]} == 7'h0; // @[Xbar.scala:222:41]
wire requestAIO_0_6 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], auto_anon_in_a_bits_address[20], ~(auto_anon_in_a_bits_address[16])} == 5'h0; // @[Parameters.scala:137:{31,41,46,59}]
wire requestAIO_0_7 = {auto_anon_in_a_bits_address[28:27], auto_anon_in_a_bits_address[25], ~(auto_anon_in_a_bits_address[20]), auto_anon_in_a_bits_address[13:12]} == 6'h0; // @[Xbar.scala:222:41]
wire _portsAOI_in_0_a_ready_T_14 = requestAIO_0_0 & auto_anon_out_0_a_ready | requestAIO_0_1 & auto_anon_out_1_a_ready | requestAIO_0_2 & auto_anon_out_2_a_ready | requestAIO_0_3 & auto_anon_out_3_a_ready | requestAIO_0_4 & auto_anon_out_4_a_ready | requestAIO_0_5 & auto_anon_out_5_a_ready | requestAIO_0_6 & auto_anon_out_6_a_ready | requestAIO_0_7 & auto_anon_out_7_a_ready; // @[Mux.scala:30:73]
reg [8:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 9'h0; // @[Arbiter.scala:60:30, :61:28]
wire [7:0] readys_valid = {auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid, auto_anon_out_1_d_valid, auto_anon_out_0_d_valid}; // @[Arbiter.scala:68:51]
reg [7:0] readys_mask; // @[Arbiter.scala:23:23]
wire [7:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [13:0] _GEN_0 = {_readys_filter_T_1[6:0], auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid, auto_anon_out_1_d_valid} | {_readys_filter_T_1, auto_anon_out_7_d_valid, auto_anon_out_6_d_valid, auto_anon_out_5_d_valid, auto_anon_out_4_d_valid, auto_anon_out_3_d_valid, auto_anon_out_2_d_valid}; // @[package.scala:262:{43,48}]
wire [12:0] _GEN_1 = _GEN_0[12:0] | {_readys_filter_T_1[7], _GEN_0[13:2]}; // @[package.scala:262:{43,48}]
wire [10:0] _GEN_2 = _GEN_1[10:0] | {_readys_filter_T_1[7], _GEN_0[13], _GEN_1[12:4]}; // @[package.scala:262:{43,48}]
wire [7:0] readys_readys = ~({readys_mask[7], _readys_filter_T_1[7] | readys_mask[6], _GEN_0[13] | readys_mask[5], _GEN_1[12:11] | readys_mask[4:3], _GEN_2[10:8] | readys_mask[2:0]} & _GEN_2[7:0]); // @[package.scala:262:43]
wire winner_0 = readys_readys[0] & auto_anon_out_0_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_1 = readys_readys[1] & auto_anon_out_1_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_2 = readys_readys[2] & auto_anon_out_2_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_3 = readys_readys[3] & auto_anon_out_3_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_4 = readys_readys[4] & auto_anon_out_4_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_5 = readys_readys[5] & auto_anon_out_5_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_6 = readys_readys[6] & auto_anon_out_6_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire winner_7 = readys_readys[7] & auto_anon_out_7_d_valid; // @[Arbiter.scala:26:18, :68:76, :71:69]
wire _in_0_d_valid_T = auto_anon_out_0_d_valid | auto_anon_out_1_d_valid; // @[Arbiter.scala:79:31]
|
Generate the Verilog code corresponding to the following Chisel files.
File MSHR.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import freechips.rocketchip.tilelink._
import TLPermissions._
import TLMessages._
import MetaData._
import chisel3.PrintableHelper
import chisel3.experimental.dataview._
class ScheduleRequest(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val a = Valid(new SourceARequest(params))
val b = Valid(new SourceBRequest(params))
val c = Valid(new SourceCRequest(params))
val d = Valid(new SourceDRequest(params))
val e = Valid(new SourceERequest(params))
val x = Valid(new SourceXRequest(params))
val dir = Valid(new DirectoryWrite(params))
val reload = Bool() // get next request via allocate (if any)
}
class MSHRStatus(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val way = UInt(params.wayBits.W)
val blockB = Bool()
val nestB = Bool()
val blockC = Bool()
val nestC = Bool()
}
class NestedWriteback(params: InclusiveCacheParameters) extends InclusiveCacheBundle(params)
{
val set = UInt(params.setBits.W)
val tag = UInt(params.tagBits.W)
val b_toN = Bool() // nested Probes may unhit us
val b_toB = Bool() // nested Probes may demote us
val b_clr_dirty = Bool() // nested Probes clear dirty
val c_set_dirty = Bool() // nested Releases MAY set dirty
}
sealed trait CacheState
{
val code = CacheState.index.U
CacheState.index = CacheState.index + 1
}
object CacheState
{
var index = 0
}
case object S_INVALID extends CacheState
case object S_BRANCH extends CacheState
case object S_BRANCH_C extends CacheState
case object S_TIP extends CacheState
case object S_TIP_C extends CacheState
case object S_TIP_CD extends CacheState
case object S_TIP_D extends CacheState
case object S_TRUNK_C extends CacheState
case object S_TRUNK_CD extends CacheState
class MSHR(params: InclusiveCacheParameters) extends Module
{
val io = IO(new Bundle {
val allocate = Flipped(Valid(new AllocateRequest(params))) // refills MSHR for next cycle
val directory = Flipped(Valid(new DirectoryResult(params))) // triggers schedule setup
val status = Valid(new MSHRStatus(params))
val schedule = Decoupled(new ScheduleRequest(params))
val sinkc = Flipped(Valid(new SinkCResponse(params)))
val sinkd = Flipped(Valid(new SinkDResponse(params)))
val sinke = Flipped(Valid(new SinkEResponse(params)))
val nestedwb = Flipped(new NestedWriteback(params))
})
val request_valid = RegInit(false.B)
val request = Reg(new FullRequest(params))
val meta_valid = RegInit(false.B)
val meta = Reg(new DirectoryResult(params))
// Define which states are valid
when (meta_valid) {
when (meta.state === INVALID) {
assert (!meta.clients.orR)
assert (!meta.dirty)
}
when (meta.state === BRANCH) {
assert (!meta.dirty)
}
when (meta.state === TRUNK) {
assert (meta.clients.orR)
assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one
}
when (meta.state === TIP) {
// noop
}
}
// Completed transitions (s_ = scheduled), (w_ = waiting)
val s_rprobe = RegInit(true.B) // B
val w_rprobeackfirst = RegInit(true.B)
val w_rprobeacklast = RegInit(true.B)
val s_release = RegInit(true.B) // CW w_rprobeackfirst
val w_releaseack = RegInit(true.B)
val s_pprobe = RegInit(true.B) // B
val s_acquire = RegInit(true.B) // A s_release, s_pprobe [1]
val s_flush = RegInit(true.B) // X w_releaseack
val w_grantfirst = RegInit(true.B)
val w_grantlast = RegInit(true.B)
val w_grant = RegInit(true.B) // first | last depending on wormhole
val w_pprobeackfirst = RegInit(true.B)
val w_pprobeacklast = RegInit(true.B)
val w_pprobeack = RegInit(true.B) // first | last depending on wormhole
val s_probeack = RegInit(true.B) // C w_pprobeackfirst (mutually exclusive with next two s_*)
val s_grantack = RegInit(true.B) // E w_grantfirst ... CAN require both outE&inD to service outD
val s_execute = RegInit(true.B) // D w_pprobeack, w_grant
val w_grantack = RegInit(true.B)
val s_writeback = RegInit(true.B) // W w_*
// [1]: We cannot issue outer Acquire while holding blockB (=> outA can stall)
// However, inB and outC are higher priority than outB, so s_release and s_pprobe
// may be safely issued while blockB. Thus we must NOT try to schedule the
// potentially stuck s_acquire with either of them (scheduler is all or none).
// Meta-data that we discover underway
val sink = Reg(UInt(params.outer.bundle.sinkBits.W))
val gotT = Reg(Bool())
val bad_grant = Reg(Bool())
val probes_done = Reg(UInt(params.clientBits.W))
val probes_toN = Reg(UInt(params.clientBits.W))
val probes_noT = Reg(Bool())
// When a nested transaction completes, update our meta data
when (meta_valid && meta.state =/= INVALID &&
io.nestedwb.set === request.set && io.nestedwb.tag === meta.tag) {
when (io.nestedwb.b_clr_dirty) { meta.dirty := false.B }
when (io.nestedwb.c_set_dirty) { meta.dirty := true.B }
when (io.nestedwb.b_toB) { meta.state := BRANCH }
when (io.nestedwb.b_toN) { meta.hit := false.B }
}
// Scheduler status
io.status.valid := request_valid
io.status.bits.set := request.set
io.status.bits.tag := request.tag
io.status.bits.way := meta.way
io.status.bits.blockB := !meta_valid || ((!w_releaseack || !w_rprobeacklast || !w_pprobeacklast) && !w_grantfirst)
io.status.bits.nestB := meta_valid && w_releaseack && w_rprobeacklast && w_pprobeacklast && !w_grantfirst
// The above rules ensure we will block and not nest an outer probe while still doing our
// own inner probes. Thus every probe wakes exactly one MSHR.
io.status.bits.blockC := !meta_valid
io.status.bits.nestC := meta_valid && (!w_rprobeackfirst || !w_pprobeackfirst || !w_grantfirst)
// The w_grantfirst in nestC is necessary to deal with:
// acquire waiting for grant, inner release gets queued, outer probe -> inner probe -> deadlock
// ... this is possible because the release+probe can be for same set, but different tag
// We can only demand: block, nest, or queue
assert (!io.status.bits.nestB || !io.status.bits.blockB)
assert (!io.status.bits.nestC || !io.status.bits.blockC)
// Scheduler requests
val no_wait = w_rprobeacklast && w_releaseack && w_grantlast && w_pprobeacklast && w_grantack
io.schedule.bits.a.valid := !s_acquire && s_release && s_pprobe
io.schedule.bits.b.valid := !s_rprobe || !s_pprobe
io.schedule.bits.c.valid := (!s_release && w_rprobeackfirst) || (!s_probeack && w_pprobeackfirst)
io.schedule.bits.d.valid := !s_execute && w_pprobeack && w_grant
io.schedule.bits.e.valid := !s_grantack && w_grantfirst
io.schedule.bits.x.valid := !s_flush && w_releaseack
io.schedule.bits.dir.valid := (!s_release && w_rprobeackfirst) || (!s_writeback && no_wait)
io.schedule.bits.reload := no_wait
io.schedule.valid := io.schedule.bits.a.valid || io.schedule.bits.b.valid || io.schedule.bits.c.valid ||
io.schedule.bits.d.valid || io.schedule.bits.e.valid || io.schedule.bits.x.valid ||
io.schedule.bits.dir.valid
// Schedule completions
when (io.schedule.ready) {
s_rprobe := true.B
when (w_rprobeackfirst) { s_release := true.B }
s_pprobe := true.B
when (s_release && s_pprobe) { s_acquire := true.B }
when (w_releaseack) { s_flush := true.B }
when (w_pprobeackfirst) { s_probeack := true.B }
when (w_grantfirst) { s_grantack := true.B }
when (w_pprobeack && w_grant) { s_execute := true.B }
when (no_wait) { s_writeback := true.B }
// Await the next operation
when (no_wait) {
request_valid := false.B
meta_valid := false.B
}
}
// Resulting meta-data
val final_meta_writeback = WireInit(meta)
val req_clientBit = params.clientBit(request.source)
val req_needT = needT(request.opcode, request.param)
val req_acquire = request.opcode === AcquireBlock || request.opcode === AcquirePerm
val meta_no_clients = !meta.clients.orR
val req_promoteT = req_acquire && Mux(meta.hit, meta_no_clients && meta.state === TIP, gotT)
when (request.prio(2) && (!params.firstLevel).B) { // always a hit
final_meta_writeback.dirty := meta.dirty || request.opcode(0)
final_meta_writeback.state := Mux(request.param =/= TtoT && meta.state === TRUNK, TIP, meta.state)
final_meta_writeback.clients := meta.clients & ~Mux(isToN(request.param), req_clientBit, 0.U)
final_meta_writeback.hit := true.B // chained requests are hits
} .elsewhen (request.control && params.control.B) { // request.prio(0)
when (meta.hit) {
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := meta.clients & ~probes_toN
}
final_meta_writeback.hit := false.B
} .otherwise {
final_meta_writeback.dirty := (meta.hit && meta.dirty) || !request.opcode(2)
final_meta_writeback.state := Mux(req_needT,
Mux(req_acquire, TRUNK, TIP),
Mux(!meta.hit, Mux(gotT, Mux(req_acquire, TRUNK, TIP), BRANCH),
MuxLookup(meta.state, 0.U(2.W))(Seq(
INVALID -> BRANCH,
BRANCH -> BRANCH,
TRUNK -> TIP,
TIP -> Mux(meta_no_clients && req_acquire, TRUNK, TIP)))))
final_meta_writeback.clients := Mux(meta.hit, meta.clients & ~probes_toN, 0.U) |
Mux(req_acquire, req_clientBit, 0.U)
final_meta_writeback.tag := request.tag
final_meta_writeback.hit := true.B
}
when (bad_grant) {
when (meta.hit) {
// upgrade failed (B -> T)
assert (!meta_valid || meta.state === BRANCH)
final_meta_writeback.hit := true.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := BRANCH
final_meta_writeback.clients := meta.clients & ~probes_toN
} .otherwise {
// failed N -> (T or B)
final_meta_writeback.hit := false.B
final_meta_writeback.dirty := false.B
final_meta_writeback.state := INVALID
final_meta_writeback.clients := 0.U
}
}
val invalid = Wire(new DirectoryEntry(params))
invalid.dirty := false.B
invalid.state := INVALID
invalid.clients := 0.U
invalid.tag := 0.U
// Just because a client says BtoT, by the time we process the request he may be N.
// Therefore, we must consult our own meta-data state to confirm he owns the line still.
val honour_BtoT = meta.hit && (meta.clients & req_clientBit).orR
// The client asking us to act is proof they don't have permissions.
val excluded_client = Mux(meta.hit && request.prio(0) && skipProbeN(request.opcode, params.cache.hintsSkipProbe), req_clientBit, 0.U)
io.schedule.bits.a.bits.tag := request.tag
io.schedule.bits.a.bits.set := request.set
io.schedule.bits.a.bits.param := Mux(req_needT, Mux(meta.hit, BtoT, NtoT), NtoB)
io.schedule.bits.a.bits.block := request.size =/= log2Ceil(params.cache.blockBytes).U ||
!(request.opcode === PutFullData || request.opcode === AcquirePerm)
io.schedule.bits.a.bits.source := 0.U
io.schedule.bits.b.bits.param := Mux(!s_rprobe, toN, Mux(request.prio(1), request.param, Mux(req_needT, toN, toB)))
io.schedule.bits.b.bits.tag := Mux(!s_rprobe, meta.tag, request.tag)
io.schedule.bits.b.bits.set := request.set
io.schedule.bits.b.bits.clients := meta.clients & ~excluded_client
io.schedule.bits.c.bits.opcode := Mux(meta.dirty, ReleaseData, Release)
io.schedule.bits.c.bits.param := Mux(meta.state === BRANCH, BtoN, TtoN)
io.schedule.bits.c.bits.source := 0.U
io.schedule.bits.c.bits.tag := meta.tag
io.schedule.bits.c.bits.set := request.set
io.schedule.bits.c.bits.way := meta.way
io.schedule.bits.c.bits.dirty := meta.dirty
io.schedule.bits.d.bits.viewAsSupertype(chiselTypeOf(request)) := request
io.schedule.bits.d.bits.param := Mux(!req_acquire, request.param,
MuxLookup(request.param, request.param)(Seq(
NtoB -> Mux(req_promoteT, NtoT, NtoB),
BtoT -> Mux(honour_BtoT, BtoT, NtoT),
NtoT -> NtoT)))
io.schedule.bits.d.bits.sink := 0.U
io.schedule.bits.d.bits.way := meta.way
io.schedule.bits.d.bits.bad := bad_grant
io.schedule.bits.e.bits.sink := sink
io.schedule.bits.x.bits.fail := false.B
io.schedule.bits.dir.bits.set := request.set
io.schedule.bits.dir.bits.way := meta.way
io.schedule.bits.dir.bits.data := Mux(!s_release, invalid, WireInit(new DirectoryEntry(params), init = final_meta_writeback))
// Coverage of state transitions
def cacheState(entry: DirectoryEntry, hit: Bool) = {
val out = WireDefault(0.U)
val c = entry.clients.orR
val d = entry.dirty
switch (entry.state) {
is (BRANCH) { out := Mux(c, S_BRANCH_C.code, S_BRANCH.code) }
is (TRUNK) { out := Mux(d, S_TRUNK_CD.code, S_TRUNK_C.code) }
is (TIP) { out := Mux(c, Mux(d, S_TIP_CD.code, S_TIP_C.code), Mux(d, S_TIP_D.code, S_TIP.code)) }
is (INVALID) { out := S_INVALID.code }
}
when (!hit) { out := S_INVALID.code }
out
}
val p = !params.lastLevel // can be probed
val c = !params.firstLevel // can be acquired
val m = params.inner.client.clients.exists(!_.supports.probe) // can be written (or read)
val r = params.outer.manager.managers.exists(!_.alwaysGrantsT) // read-only devices exist
val f = params.control // flush control register exists
val cfg = (p, c, m, r, f)
val b = r || p // can reach branch state (via probe downgrade or read-only device)
// The cache must be used for something or we would not be here
require(c || m)
val evict = cacheState(meta, !meta.hit)
val before = cacheState(meta, meta.hit)
val after = cacheState(final_meta_writeback, true.B)
def eviction(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(evict === from.code, s"MSHR_${from}_EVICT", s"State transition from ${from} to evicted ${cfg}")
} else {
assert(!(evict === from.code), cf"State transition from ${from} to evicted should be impossible ${cfg}")
}
if (cover && f) {
params.ccover(before === from.code, s"MSHR_${from}_FLUSH", s"State transition from ${from} to flushed ${cfg}")
} else {
assert(!(before === from.code), cf"State transition from ${from} to flushed should be impossible ${cfg}")
}
}
def transition(from: CacheState, to: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(before === from.code && after === to.code, s"MSHR_${from}_${to}", s"State transition from ${from} to ${to} ${cfg}")
} else {
assert(!(before === from.code && after === to.code), cf"State transition from ${from} to ${to} should be impossible ${cfg}")
}
}
when ((!s_release && w_rprobeackfirst) && io.schedule.ready) {
eviction(S_BRANCH, b) // MMIO read to read-only device
eviction(S_BRANCH_C, b && c) // you need children to become C
eviction(S_TIP, true) // MMIO read || clean release can lead to this state
eviction(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
eviction(S_TIP_D, true) // MMIO write || dirty release lead here
eviction(S_TRUNK_C, c) // acquire for write
eviction(S_TRUNK_CD, c) // dirty release then reacquire
}
when ((!s_writeback && no_wait) && io.schedule.ready) {
transition(S_INVALID, S_BRANCH, b && m) // only MMIO can bring us to BRANCH state
transition(S_INVALID, S_BRANCH_C, b && c) // C state is only possible if there are inner caches
transition(S_INVALID, S_TIP, m) // MMIO read
transition(S_INVALID, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_INVALID, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_INVALID, S_TIP_D, m) // MMIO write
transition(S_INVALID, S_TRUNK_C, c) // acquire
transition(S_INVALID, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_INVALID, b && p) // probe can do this (flushes run as evictions)
transition(S_BRANCH, S_BRANCH_C, b && c) // acquire
transition(S_BRANCH, S_TIP, b && m) // prefetch write
transition(S_BRANCH, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH, S_TIP_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH, S_TIP_D, b && m) // MMIO write
transition(S_BRANCH, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_BRANCH_C, S_INVALID, b && c && p)
transition(S_BRANCH_C, S_BRANCH, b && c) // clean release (optional)
transition(S_BRANCH_C, S_TIP, b && c && m) // prefetch write
transition(S_BRANCH_C, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_BRANCH_C, S_TIP_D, b && c && m) // MMIO write
transition(S_BRANCH_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_BRANCH_C, S_TRUNK_C, b && c) // acquire
transition(S_BRANCH_C, S_TRUNK_CD, false) // acquire does not cause dirty immediately
transition(S_TIP, S_INVALID, p)
transition(S_TIP, S_BRANCH, p) // losing TIP only possible via probe
transition(S_TIP, S_BRANCH_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP, S_TIP_D, m) // direct dirty only via MMIO write
transition(S_TIP, S_TIP_CD, false) // acquire does not make us dirty immediately
transition(S_TIP, S_TRUNK_C, c) // acquire
transition(S_TIP, S_TRUNK_CD, false) // acquire does not make us dirty immediately
transition(S_TIP_C, S_INVALID, c && p)
transition(S_TIP_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TIP_C, S_TIP, c) // probed while MMIO read || clean release (optional)
transition(S_TIP_C, S_TIP_D, c && m) // direct dirty only via MMIO write
transition(S_TIP_C, S_TIP_CD, false) // going dirty means we must shoot down clients
transition(S_TIP_C, S_TRUNK_C, c) // acquire
transition(S_TIP_C, S_TRUNK_CD, false) // acquire does not make us immediately dirty
transition(S_TIP_D, S_INVALID, p)
transition(S_TIP_D, S_BRANCH, p) // losing D is only possible via probe
transition(S_TIP_D, S_BRANCH_C, p && c) // probed while acquire shared
transition(S_TIP_D, S_TIP, p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_D, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_D, S_TIP_CD, false) // we would go S_TRUNK_CD instead
transition(S_TIP_D, S_TRUNK_C, p && c) // probed while acquired
transition(S_TIP_D, S_TRUNK_CD, c) // acquire
transition(S_TIP_CD, S_INVALID, c && p)
transition(S_TIP_CD, S_BRANCH, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_BRANCH_C, c && p) // losing D is only possible via probe
transition(S_TIP_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TIP_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TIP_CD, S_TIP_D, c) // MMIO write || clean release (optional)
transition(S_TIP_CD, S_TRUNK_C, c && p) // probed while acquire
transition(S_TIP_CD, S_TRUNK_CD, c) // acquire
transition(S_TRUNK_C, S_INVALID, c && p)
transition(S_TRUNK_C, S_BRANCH, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_BRANCH_C, c && p) // losing TIP only possible via probe
transition(S_TRUNK_C, S_TIP, c) // MMIO read || clean release (optional)
transition(S_TRUNK_C, S_TIP_C, c) // bounce shared
transition(S_TRUNK_C, S_TIP_D, c) // dirty release
transition(S_TRUNK_C, S_TIP_CD, c) // dirty bounce shared
transition(S_TRUNK_C, S_TRUNK_CD, c) // dirty bounce
transition(S_TRUNK_CD, S_INVALID, c && p)
transition(S_TRUNK_CD, S_BRANCH, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_BRANCH_C, c && p) // losing D only possible via probe
transition(S_TRUNK_CD, S_TIP, c && p) // probed while MMIO read || outer probe.toT (optional)
transition(S_TRUNK_CD, S_TIP_C, false) // we would go S_TRUNK_C instead
transition(S_TRUNK_CD, S_TIP_D, c) // dirty release
transition(S_TRUNK_CD, S_TIP_CD, c) // bounce shared
transition(S_TRUNK_CD, S_TRUNK_C, c && p) // probed while acquire
}
// Handle response messages
val probe_bit = params.clientBit(io.sinkc.bits.source)
val last_probe = (probes_done | probe_bit) === (meta.clients & ~excluded_client)
val probe_toN = isToN(io.sinkc.bits.param)
if (!params.firstLevel) when (io.sinkc.valid) {
params.ccover( probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_FULL", "Client downgraded to N when asked only to do B")
params.ccover(!probe_toN && io.schedule.bits.b.bits.param === toB, "MSHR_PROBE_HALF", "Client downgraded to B when asked only to do B")
// Caution: the probe matches us only in set.
// We would never allow an outer probe to nest until both w_[rp]probeack complete, so
// it is safe to just unguardedly update the probe FSM.
probes_done := probes_done | probe_bit
probes_toN := probes_toN | Mux(probe_toN, probe_bit, 0.U)
probes_noT := probes_noT || io.sinkc.bits.param =/= TtoT
w_rprobeackfirst := w_rprobeackfirst || last_probe
w_rprobeacklast := w_rprobeacklast || (last_probe && io.sinkc.bits.last)
w_pprobeackfirst := w_pprobeackfirst || last_probe
w_pprobeacklast := w_pprobeacklast || (last_probe && io.sinkc.bits.last)
// Allow wormhole routing from sinkC if the first request beat has offset 0
val set_pprobeack = last_probe && (io.sinkc.bits.last || request.offset === 0.U)
w_pprobeack := w_pprobeack || set_pprobeack
params.ccover(!set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_SERIAL", "Sequential routing of probe response data")
params.ccover( set_pprobeack && w_rprobeackfirst, "MSHR_PROBE_WORMHOLE", "Wormhole routing of probe response data")
// However, meta-data updates need to be done more cautiously
when (meta.state =/= INVALID && io.sinkc.bits.tag === meta.tag && io.sinkc.bits.data) { meta.dirty := true.B } // !!!
}
when (io.sinkd.valid) {
when (io.sinkd.bits.opcode === Grant || io.sinkd.bits.opcode === GrantData) {
sink := io.sinkd.bits.sink
w_grantfirst := true.B
w_grantlast := io.sinkd.bits.last
// Record if we need to prevent taking ownership
bad_grant := io.sinkd.bits.denied
// Allow wormhole routing for requests whose first beat has offset 0
w_grant := request.offset === 0.U || io.sinkd.bits.last
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset === 0.U, "MSHR_GRANT_WORMHOLE", "Wormhole routing of grant response data")
params.ccover(io.sinkd.bits.opcode === GrantData && request.offset =/= 0.U, "MSHR_GRANT_SERIAL", "Sequential routing of grant response data")
gotT := io.sinkd.bits.param === toT
}
.elsewhen (io.sinkd.bits.opcode === ReleaseAck) {
w_releaseack := true.B
}
}
when (io.sinke.valid) {
w_grantack := true.B
}
// Bootstrap new requests
val allocate_as_full = WireInit(new FullRequest(params), init = io.allocate.bits)
val new_meta = Mux(io.allocate.valid && io.allocate.bits.repeat, final_meta_writeback, io.directory.bits)
val new_request = Mux(io.allocate.valid, allocate_as_full, request)
val new_needT = needT(new_request.opcode, new_request.param)
val new_clientBit = params.clientBit(new_request.source)
val new_skipProbe = Mux(skipProbeN(new_request.opcode, params.cache.hintsSkipProbe), new_clientBit, 0.U)
val prior = cacheState(final_meta_writeback, true.B)
def bypass(from: CacheState, cover: Boolean)(implicit sourceInfo: SourceInfo) {
if (cover) {
params.ccover(prior === from.code, s"MSHR_${from}_BYPASS", s"State bypass transition from ${from} ${cfg}")
} else {
assert(!(prior === from.code), cf"State bypass from ${from} should be impossible ${cfg}")
}
}
when (io.allocate.valid && io.allocate.bits.repeat) {
bypass(S_INVALID, f || p) // Can lose permissions (probe/flush)
bypass(S_BRANCH, b) // MMIO read to read-only device
bypass(S_BRANCH_C, b && c) // you need children to become C
bypass(S_TIP, true) // MMIO read || clean release can lead to this state
bypass(S_TIP_C, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_CD, c) // needs two clients || client + mmio || downgrading client
bypass(S_TIP_D, true) // MMIO write || dirty release lead here
bypass(S_TRUNK_C, c) // acquire for write
bypass(S_TRUNK_CD, c) // dirty release then reacquire
}
when (io.allocate.valid) {
assert (!request_valid || (no_wait && io.schedule.fire))
request_valid := true.B
request := io.allocate.bits
}
// Create execution plan
when (io.directory.valid || (io.allocate.valid && io.allocate.bits.repeat)) {
meta_valid := true.B
meta := new_meta
probes_done := 0.U
probes_toN := 0.U
probes_noT := false.B
gotT := false.B
bad_grant := false.B
// These should already be either true or turning true
// We clear them here explicitly to simplify the mux tree
s_rprobe := true.B
w_rprobeackfirst := true.B
w_rprobeacklast := true.B
s_release := true.B
w_releaseack := true.B
s_pprobe := true.B
s_acquire := true.B
s_flush := true.B
w_grantfirst := true.B
w_grantlast := true.B
w_grant := true.B
w_pprobeackfirst := true.B
w_pprobeacklast := true.B
w_pprobeack := true.B
s_probeack := true.B
s_grantack := true.B
s_execute := true.B
w_grantack := true.B
s_writeback := true.B
// For C channel requests (ie: Release[Data])
when (new_request.prio(2) && (!params.firstLevel).B) {
s_execute := false.B
// Do we need to go dirty?
when (new_request.opcode(0) && !new_meta.dirty) {
s_writeback := false.B
}
// Does our state change?
when (isToB(new_request.param) && new_meta.state === TRUNK) {
s_writeback := false.B
}
// Do our clients change?
when (isToN(new_request.param) && (new_meta.clients & new_clientBit) =/= 0.U) {
s_writeback := false.B
}
assert (new_meta.hit)
}
// For X channel requests (ie: flush)
.elsewhen (new_request.control && params.control.B) { // new_request.prio(0)
s_flush := false.B
// Do we need to actually do something?
when (new_meta.hit) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B && (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
}
// For A channel requests
.otherwise { // new_request.prio(0) && !new_request.control
s_execute := false.B
// Do we need an eviction?
when (!new_meta.hit && new_meta.state =/= INVALID) {
s_release := false.B
w_releaseack := false.B
// Do we need to shoot-down inner caches?
when ((!params.firstLevel).B & (new_meta.clients =/= 0.U)) {
s_rprobe := false.B
w_rprobeackfirst := false.B
w_rprobeacklast := false.B
}
}
// Do we need an acquire?
when (!new_meta.hit || (new_meta.state === BRANCH && new_needT)) {
s_acquire := false.B
w_grantfirst := false.B
w_grantlast := false.B
w_grant := false.B
s_grantack := false.B
s_writeback := false.B
}
// Do we need a probe?
when ((!params.firstLevel).B && (new_meta.hit &&
(new_needT || new_meta.state === TRUNK) &&
(new_meta.clients & ~new_skipProbe) =/= 0.U)) {
s_pprobe := false.B
w_pprobeackfirst := false.B
w_pprobeacklast := false.B
w_pprobeack := false.B
s_writeback := false.B
}
// Do we need a grantack?
when (new_request.opcode === AcquireBlock || new_request.opcode === AcquirePerm) {
w_grantack := false.B
s_writeback := false.B
}
// Becomes dirty?
when (!new_request.opcode(2) && new_meta.hit && !new_meta.dirty) {
s_writeback := false.B
}
}
}
}
File Parameters.scala:
/*
* Copyright 2019 SiFive, Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You should have received a copy of LICENSE.Apache2 along with
* this software. If not, you may obtain a copy at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
package sifive.blocks.inclusivecache
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property.cover
import scala.math.{min,max}
case class CacheParameters(
level: Int,
ways: Int,
sets: Int,
blockBytes: Int,
beatBytes: Int, // inner
hintsSkipProbe: Boolean)
{
require (ways > 0)
require (sets > 0)
require (blockBytes > 0 && isPow2(blockBytes))
require (beatBytes > 0 && isPow2(beatBytes))
require (blockBytes >= beatBytes)
val blocks = ways * sets
val sizeBytes = blocks * blockBytes
val blockBeats = blockBytes/beatBytes
}
case class InclusiveCachePortParameters(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)
{
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new TLBuffer(a, b, c, d, e))
}
object InclusiveCachePortParameters
{
val none = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.none)
val full = InclusiveCachePortParameters(
a = BufferParams.default,
b = BufferParams.default,
c = BufferParams.default,
d = BufferParams.default,
e = BufferParams.default)
// This removes feed-through paths from C=>A and A=>C
val fullC = InclusiveCachePortParameters(
a = BufferParams.none,
b = BufferParams.none,
c = BufferParams.default,
d = BufferParams.none,
e = BufferParams.none)
val flowAD = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.flow,
e = BufferParams.none)
val flowAE = InclusiveCachePortParameters(
a = BufferParams.flow,
b = BufferParams.none,
c = BufferParams.none,
d = BufferParams.none,
e = BufferParams.flow)
// For innerBuf:
// SinkA: no restrictions, flows into scheduler+putbuffer
// SourceB: no restrictions, flows out of scheduler
// sinkC: no restrictions, flows into scheduler+putbuffer & buffered to bankedStore
// SourceD: no restrictions, flows out of bankedStore/regout
// SinkE: no restrictions, flows into scheduler
//
// ... so while none is possible, you probably want at least flowAC to cut ready
// from the scheduler delay and flowD to ease SourceD back-pressure
// For outerBufer:
// SourceA: must not be pipe, flows out of scheduler
// SinkB: no restrictions, flows into scheduler
// SourceC: pipe is useless, flows out of bankedStore/regout, parameter depth ignored
// SinkD: no restrictions, flows into scheduler & bankedStore
// SourceE: must not be pipe, flows out of scheduler
//
// ... AE take the channel ready into the scheduler, so you need at least flowAE
}
case class InclusiveCacheMicroParameters(
writeBytes: Int, // backing store update granularity
memCycles: Int = 40, // # of L2 clock cycles for a memory round-trip (50ns @ 800MHz)
portFactor: Int = 4, // numSubBanks = (widest TL port * portFactor) / writeBytes
dirReg: Boolean = false,
innerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.fullC, // or none
outerBuf: InclusiveCachePortParameters = InclusiveCachePortParameters.full) // or flowAE
{
require (writeBytes > 0 && isPow2(writeBytes))
require (memCycles > 0)
require (portFactor >= 2) // for inner RMW and concurrent outer Relase + Grant
}
case class InclusiveCacheControlParameters(
address: BigInt,
beatBytes: Int,
bankedControl: Boolean)
case class InclusiveCacheParameters(
cache: CacheParameters,
micro: InclusiveCacheMicroParameters,
control: Boolean,
inner: TLEdgeIn,
outer: TLEdgeOut)(implicit val p: Parameters)
{
require (cache.ways > 1)
require (cache.sets > 1 && isPow2(cache.sets))
require (micro.writeBytes <= inner.manager.beatBytes)
require (micro.writeBytes <= outer.manager.beatBytes)
require (inner.manager.beatBytes <= cache.blockBytes)
require (outer.manager.beatBytes <= cache.blockBytes)
// Require that all cached address ranges have contiguous blocks
outer.manager.managers.flatMap(_.address).foreach { a =>
require (a.alignment >= cache.blockBytes)
}
// If we are the first level cache, we do not need to support inner-BCE
val firstLevel = !inner.client.clients.exists(_.supports.probe)
// If we are the last level cache, we do not need to support outer-B
val lastLevel = !outer.manager.managers.exists(_.regionType > RegionType.UNCACHED)
require (lastLevel)
// Provision enough resources to achieve full throughput with missing single-beat accesses
val mshrs = InclusiveCacheParameters.all_mshrs(cache, micro)
val secondary = max(mshrs, micro.memCycles - mshrs)
val putLists = micro.memCycles // allow every request to be single beat
val putBeats = max(2*cache.blockBeats, micro.memCycles)
val relLists = 2
val relBeats = relLists*cache.blockBeats
val flatAddresses = AddressSet.unify(outer.manager.managers.flatMap(_.address))
val pickMask = AddressDecoder(flatAddresses.map(Seq(_)), flatAddresses.map(_.mask).reduce(_|_))
def bitOffsets(x: BigInt, offset: Int = 0, tail: List[Int] = List.empty[Int]): List[Int] =
if (x == 0) tail.reverse else bitOffsets(x >> 1, offset + 1, if ((x & 1) == 1) offset :: tail else tail)
val addressMapping = bitOffsets(pickMask)
val addressBits = addressMapping.size
// println(s"addresses: ${flatAddresses} => ${pickMask} => ${addressBits}")
val allClients = inner.client.clients.size
val clientBitsRaw = inner.client.clients.filter(_.supports.probe).size
val clientBits = max(1, clientBitsRaw)
val stateBits = 2
val wayBits = log2Ceil(cache.ways)
val setBits = log2Ceil(cache.sets)
val offsetBits = log2Ceil(cache.blockBytes)
val tagBits = addressBits - setBits - offsetBits
val putBits = log2Ceil(max(putLists, relLists))
require (tagBits > 0)
require (offsetBits > 0)
val innerBeatBits = (offsetBits - log2Ceil(inner.manager.beatBytes)) max 1
val outerBeatBits = (offsetBits - log2Ceil(outer.manager.beatBytes)) max 1
val innerMaskBits = inner.manager.beatBytes / micro.writeBytes
val outerMaskBits = outer.manager.beatBytes / micro.writeBytes
def clientBit(source: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Cat(inner.client.clients.filter(_.supports.probe).map(_.sourceId.contains(source)).reverse)
}
}
def clientSource(bit: UInt): UInt = {
if (clientBitsRaw == 0) {
0.U
} else {
Mux1H(bit, inner.client.clients.filter(_.supports.probe).map(c => c.sourceId.start.U))
}
}
def parseAddress(x: UInt): (UInt, UInt, UInt) = {
val offset = Cat(addressMapping.map(o => x(o,o)).reverse)
val set = offset >> offsetBits
val tag = set >> setBits
(tag(tagBits-1, 0), set(setBits-1, 0), offset(offsetBits-1, 0))
}
def widen(x: UInt, width: Int): UInt = {
val y = x | 0.U(width.W)
assert (y >> width === 0.U)
y(width-1, 0)
}
def expandAddress(tag: UInt, set: UInt, offset: UInt): UInt = {
val base = Cat(widen(tag, tagBits), widen(set, setBits), widen(offset, offsetBits))
val bits = Array.fill(outer.bundle.addressBits) { 0.U(1.W) }
addressMapping.zipWithIndex.foreach { case (a, i) => bits(a) = base(i,i) }
Cat(bits.reverse)
}
def restoreAddress(expanded: UInt): UInt = {
val missingBits = flatAddresses
.map { a => (a.widen(pickMask).base, a.widen(~pickMask)) } // key is the bits to restore on match
.groupBy(_._1)
.view
.mapValues(_.map(_._2))
val muxMask = AddressDecoder(missingBits.values.toList)
val mux = missingBits.toList.map { case (bits, addrs) =>
val widen = addrs.map(_.widen(~muxMask))
val matches = AddressSet
.unify(widen.distinct)
.map(_.contains(expanded))
.reduce(_ || _)
(matches, bits.U)
}
expanded | Mux1H(mux)
}
def dirReg[T <: Data](x: T, en: Bool = true.B): T = {
if (micro.dirReg) RegEnable(x, en) else x
}
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
cover(cond, "CCACHE_L" + cache.level + "_" + label, "MemorySystem;;" + desc)
}
object MetaData
{
val stateBits = 2
def INVALID: UInt = 0.U(stateBits.W) // way is empty
def BRANCH: UInt = 1.U(stateBits.W) // outer slave cache is trunk
def TRUNK: UInt = 2.U(stateBits.W) // unique inner master cache is trunk
def TIP: UInt = 3.U(stateBits.W) // we are trunk, inner masters are branch
// Does a request need trunk?
def needT(opcode: UInt, param: UInt): Bool = {
!opcode(2) ||
(opcode === TLMessages.Hint && param === TLHints.PREFETCH_WRITE) ||
((opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm) && param =/= TLPermissions.NtoB)
}
// Does a request prove the client need not be probed?
def skipProbeN(opcode: UInt, hintsSkipProbe: Boolean): Bool = {
// Acquire(toB) and Get => is N, so no probe
// Acquire(*toT) => is N or B, but need T, so no probe
// Hint => could be anything, so probe IS needed, if hintsSkipProbe is enabled, skip probe the same client
// Put* => is N or B, so probe IS needed
opcode === TLMessages.AcquireBlock || opcode === TLMessages.AcquirePerm || opcode === TLMessages.Get || (opcode === TLMessages.Hint && hintsSkipProbe.B)
}
def isToN(param: UInt): Bool = {
param === TLPermissions.TtoN || param === TLPermissions.BtoN || param === TLPermissions.NtoN
}
def isToB(param: UInt): Bool = {
param === TLPermissions.TtoB || param === TLPermissions.BtoB
}
}
object InclusiveCacheParameters
{
val lfsrBits = 10
val L2ControlAddress = 0x2010000
val L2ControlSize = 0x1000
def out_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int = {
// We need 2-3 normal MSHRs to cover the Directory latency
// To fully exploit memory bandwidth-delay-product, we need memCyles/blockBeats MSHRs
max(if (micro.dirReg) 3 else 2, (micro.memCycles + cache.blockBeats - 1) / cache.blockBeats)
}
def all_mshrs(cache: CacheParameters, micro: InclusiveCacheMicroParameters): Int =
// We need a dedicated MSHR for B+C each
2 + out_mshrs(cache, micro)
}
class InclusiveCacheBundle(params: InclusiveCacheParameters) extends Bundle
|
module MSHR_3( // @[MSHR.scala:84:7]
input clock, // @[MSHR.scala:84:7]
input reset, // @[MSHR.scala:84:7]
input io_allocate_valid, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_0, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_1, // @[MSHR.scala:86:14]
input io_allocate_bits_prio_2, // @[MSHR.scala:86:14]
input io_allocate_bits_control, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14]
input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14]
input [7:0] io_allocate_bits_source, // @[MSHR.scala:86:14]
input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14]
input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14]
input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14]
input io_allocate_bits_repeat, // @[MSHR.scala:86:14]
input io_directory_valid, // @[MSHR.scala:86:14]
input io_directory_bits_dirty, // @[MSHR.scala:86:14]
input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14]
input io_directory_bits_clients, // @[MSHR.scala:86:14]
input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14]
input io_directory_bits_hit, // @[MSHR.scala:86:14]
input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14]
output io_status_valid, // @[MSHR.scala:86:14]
output [9:0] io_status_bits_set, // @[MSHR.scala:86:14]
output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14]
output [2:0] io_status_bits_way, // @[MSHR.scala:86:14]
output io_status_bits_blockB, // @[MSHR.scala:86:14]
output io_status_bits_nestB, // @[MSHR.scala:86:14]
output io_status_bits_blockC, // @[MSHR.scala:86:14]
output io_status_bits_nestC, // @[MSHR.scala:86:14]
input io_schedule_ready, // @[MSHR.scala:86:14]
output io_schedule_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_a_valid, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14]
output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14]
output io_schedule_bits_b_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14]
output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14]
output io_schedule_bits_c_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14]
output io_schedule_bits_d_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14]
output [7:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14]
output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14]
output io_schedule_bits_e_valid, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14]
output io_schedule_bits_x_valid, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14]
output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14]
output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14]
output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14]
output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14]
output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14]
output io_schedule_bits_reload, // @[MSHR.scala:86:14]
input io_sinkc_valid, // @[MSHR.scala:86:14]
input io_sinkc_bits_last, // @[MSHR.scala:86:14]
input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14]
input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14]
input [7:0] io_sinkc_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14]
input io_sinkc_bits_data, // @[MSHR.scala:86:14]
input io_sinkd_valid, // @[MSHR.scala:86:14]
input io_sinkd_bits_last, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14]
input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14]
input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14]
input io_sinkd_bits_denied, // @[MSHR.scala:86:14]
input io_sinke_valid, // @[MSHR.scala:86:14]
input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14]
input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14]
input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14]
input io_nestedwb_b_toN, // @[MSHR.scala:86:14]
input io_nestedwb_b_toB, // @[MSHR.scala:86:14]
input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14]
input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14]
);
wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38]
wire final_meta_writeback_clients; // @[MSHR.scala:215:38]
wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38]
wire final_meta_writeback_dirty; // @[MSHR.scala:215:38]
wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7]
wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7]
wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7]
wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7]
wire [7:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7]
wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7]
wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7]
wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7]
wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7]
wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7]
wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7]
wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7]
wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7]
wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7]
wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7]
wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7]
wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7]
wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7]
wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7]
wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7]
wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7]
wire [7:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7]
wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7]
wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7]
wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7]
wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7]
wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7]
wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7]
wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7]
wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7]
wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7]
wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7]
wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7]
wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7]
wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7]
wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7]
wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68]
wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80]
wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21]
wire invalid_clients = 1'h0; // @[MSHR.scala:268:21]
wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137]
wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137]
wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11]
wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21]
wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21]
wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70]
wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34]
wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34]
wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34]
wire [7:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34]
wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34]
wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34]
wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34]
wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40]
wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93]
wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28]
wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39]
wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105]
wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55]
wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91]
wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41]
wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41]
wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41]
wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51]
wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64]
wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41]
wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41]
wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57]
wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41]
wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43]
wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40]
wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66]
wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41]
wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41]
wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41]
wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41]
wire no_wait; // @[MSHR.scala:183:83]
wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7]
wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7]
wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockB_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestB_0; // @[MSHR.scala:84:7]
wire io_status_bits_blockC_0; // @[MSHR.scala:84:7]
wire io_status_bits_nestC_0; // @[MSHR.scala:84:7]
wire io_status_valid_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7]
wire [7:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7]
wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7]
wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7]
wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7]
wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7]
wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7]
wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7]
wire io_schedule_valid_0; // @[MSHR.scala:84:7]
reg request_valid; // @[MSHR.scala:97:30]
assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30]
reg request_prio_0; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20]
reg request_prio_1; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20]
reg request_prio_2; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20]
reg request_control; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_opcode; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20]
reg [2:0] request_param; // @[MSHR.scala:98:20]
reg [2:0] request_size; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20]
reg [7:0] request_source; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20]
reg [12:0] request_tag; // @[MSHR.scala:98:20]
assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_offset; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20]
reg [5:0] request_put; // @[MSHR.scala:98:20]
assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20]
reg [9:0] request_set; // @[MSHR.scala:98:20]
assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20]
reg meta_valid; // @[MSHR.scala:99:27]
reg meta_dirty; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17]
reg [1:0] meta_state; // @[MSHR.scala:100:17]
reg meta_clients; // @[MSHR.scala:100:17]
wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39]
wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27]
reg [12:0] meta_tag; // @[MSHR.scala:100:17]
assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17]
reg meta_hit; // @[MSHR.scala:100:17]
reg [2:0] meta_way; // @[MSHR.scala:100:17]
assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17]
wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38]
reg s_rprobe; // @[MSHR.scala:121:33]
reg w_rprobeackfirst; // @[MSHR.scala:122:33]
reg w_rprobeacklast; // @[MSHR.scala:123:33]
reg s_release; // @[MSHR.scala:124:33]
reg w_releaseack; // @[MSHR.scala:125:33]
reg s_pprobe; // @[MSHR.scala:126:33]
reg s_acquire; // @[MSHR.scala:127:33]
reg s_flush; // @[MSHR.scala:128:33]
reg w_grantfirst; // @[MSHR.scala:129:33]
reg w_grantlast; // @[MSHR.scala:130:33]
reg w_grant; // @[MSHR.scala:131:33]
reg w_pprobeackfirst; // @[MSHR.scala:132:33]
reg w_pprobeacklast; // @[MSHR.scala:133:33]
reg w_pprobeack; // @[MSHR.scala:134:33]
reg s_grantack; // @[MSHR.scala:136:33]
reg s_execute; // @[MSHR.scala:137:33]
reg w_grantack; // @[MSHR.scala:138:33]
reg s_writeback; // @[MSHR.scala:139:33]
reg [2:0] sink; // @[MSHR.scala:147:17]
assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17]
reg gotT; // @[MSHR.scala:148:17]
reg bad_grant; // @[MSHR.scala:149:22]
assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22]
reg probes_done; // @[MSHR.scala:150:24]
reg probes_toN; // @[MSHR.scala:151:23]
reg probes_noT; // @[MSHR.scala:152:23]
wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28]
wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45]
wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62]
wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}]
wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82]
wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}]
wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103]
wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}]
assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}]
assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40]
wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39]
wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}]
wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}]
wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96]
assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}]
assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93]
assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28]
assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28]
wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43]
wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64]
wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}]
wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85]
wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}]
assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}]
assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39]
wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33]
wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}]
wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}]
assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}]
assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83]
wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31]
wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}]
assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}]
assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55]
wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31]
wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44]
assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}]
assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41]
wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32]
wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}]
assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}]
assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64]
wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31]
wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}]
assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}]
assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57]
wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31]
assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}]
assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43]
wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31]
assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}]
assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40]
wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34]
wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}]
wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70]
wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}]
assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}]
assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66]
wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49]
wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}]
wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}]
wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49]
wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}]
assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}]
assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105]
wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71]
wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71]
wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71]
wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27]
wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71]
wire final_meta_writeback_hit; // @[MSHR.scala:215:38]
wire req_clientBit = request_source == 8'hA0; // @[Parameters.scala:46:9]
wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12]
wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12]
wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _req_needT_T_2; // @[Parameters.scala:270:13]
assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13]
wire _excluded_client_T_6; // @[Parameters.scala:279:117]
assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117]
wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42]
wire _req_needT_T_3; // @[Parameters.scala:270:42]
assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42]
wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11]
assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11]
wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42]
wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _req_needT_T_6; // @[Parameters.scala:271:14]
assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14]
wire _req_acquire_T; // @[MSHR.scala:219:36]
assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14]
wire _excluded_client_T_1; // @[Parameters.scala:279:12]
assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12]
wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52]
wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89]
wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52]
wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}]
wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}]
wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81]
wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}]
wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}]
wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}]
wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65]
wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}]
wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55]
wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78]
wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78]
assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78]
wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70]
wire _evict_T_2; // @[MSHR.scala:317:26]
assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _before_T_1; // @[MSHR.scala:317:26]
assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26]
wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}]
wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}]
wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43]
assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43]
wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43]
wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75]
wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}]
wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}]
wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54]
wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}]
wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45]
wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}]
wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}]
wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40]
wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40]
assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40]
wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65]
assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65]
wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41]
wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}]
wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72]
wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}]
wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70]
wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70]
assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70]
wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53]
assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53]
wire _evict_T_1; // @[MSHR.scala:317:26]
assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire _before_T; // @[MSHR.scala:317:26]
assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26]
wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70]
wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70]
wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55]
wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70]
wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70]
wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66]
wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}]
wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}]
wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9]
wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40]
assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30]
wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54]
wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}]
assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21]
assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21]
assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36]
assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36]
wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9]
wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}]
wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}]
wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38]
wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}]
wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}]
wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}]
wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106]
wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9]
wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56]
wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70]
assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}]
wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51]
wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55]
wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52]
wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}]
wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}]
assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38]
assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91]
wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42]
wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70]
wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}]
assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}]
assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41]
wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42]
assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}]
assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41]
wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53]
assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}]
assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51]
assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41]
assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41]
assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}]
assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41]
wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42]
wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53]
wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53]
wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89]
wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53]
wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79]
assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79]
assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41]
wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42]
assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}]
assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}]
assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41]
assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41]
wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32]
wire [3:0] evict; // @[MSHR.scala:314:26]
wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32]
wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32]
wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32]
assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32]
assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32]
wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39]
wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39]
assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39]
assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39]
wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76]
wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76]
assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76]
assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76]
wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32]
assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] before_0; // @[MSHR.scala:314:26]
wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32]
wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26]
wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26]
wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11]
assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}]
wire [3:0] after; // @[MSHR.scala:314:26]
wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26]
wire _after_T; // @[MSHR.scala:317:26]
assign _after_T = _GEN_9; // @[MSHR.scala:317:26]
wire _prior_T; // @[MSHR.scala:317:26]
assign _prior_T = _GEN_9; // @[MSHR.scala:317:26]
wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32]
wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26]
wire _after_T_1; // @[MSHR.scala:317:26]
assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire _prior_T_1; // @[MSHR.scala:317:26]
assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26]
wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32]
wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32]
assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32]
assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32]
wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39]
wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39]
assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39]
assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39]
wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76]
wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76]
assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76]
assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76]
wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26]
wire _after_T_3; // @[MSHR.scala:317:26]
assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26]
wire _prior_T_3; // @[MSHR.scala:317:26]
assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26]
assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire probe_bit = io_sinkc_bits_source_0 == 8'hA0; // @[Parameters.scala:46:9]
wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9]
wire _last_probe_T; // @[MSHR.scala:459:33]
assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33]
wire _probes_done_T; // @[MSHR.scala:467:32]
assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32]
wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66]
wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}]
wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}]
wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11]
wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43]
wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}]
wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75]
wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}]
wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9]
wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}]
wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53]
wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}]
wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42]
wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55]
wire _w_rprobeacklast_T; // @[MSHR.scala:471:55]
assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55]
wire _w_pprobeacklast_T; // @[MSHR.scala:473:55]
assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55]
wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}]
wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42]
wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}]
wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77]
wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}]
wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}]
wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32]
wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33]
wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}]
wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35]
wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40]
wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}]
wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [7:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24]
wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12]
wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}]
wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13]
wire _new_needT_T_2; // @[Parameters.scala:270:13]
assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13]
wire _new_skipProbe_T_5; // @[Parameters.scala:279:117]
assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117]
wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42]
wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}]
wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33]
wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14]
wire _new_needT_T_6; // @[Parameters.scala:271:14]
assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14]
wire _new_skipProbe_T; // @[Parameters.scala:279:12]
assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12]
wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52]
wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}]
wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89]
wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}]
wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80]
wire new_clientBit = new_request_source == 8'hA0; // @[Parameters.scala:46:9]
wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50]
wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}]
wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87]
wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}]
wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}]
wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9]
wire [3:0] prior; // @[MSHR.scala:314:26]
wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32]
wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26]
wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}]
assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26]
wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
|
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
|
module TLBuffer_6( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset // @[Buffer.scala:40:9]
);
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File IdIndexer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.amba.axi4
import chisel3._
import chisel3.util.{log2Ceil, Cat}
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.lazymodule.{LazyModule, LazyModuleImp}
import freechips.rocketchip.diplomacy.IdRange
import freechips.rocketchip.util.{ControlKey, SimpleBundleField}
case object AXI4ExtraId extends ControlKey[UInt]("extra_id")
case class AXI4ExtraIdField(width: Int) extends SimpleBundleField(AXI4ExtraId)(Output(UInt(width.W)), 0.U)
/** This adapter limits the set of FIFO domain ids used by outbound transactions.
*
* Extra AWID and ARID bits from upstream transactions are stored in a User Bits field called AXI4ExtraId,
* which values are expected to be echoed back to this adapter alongside any downstream response messages,
* and are then prepended to the RID and BID field to restore the original identifier.
*
* @param idBits is the desired number of A[W|R]ID bits to be used
*/
class AXI4IdIndexer(idBits: Int)(implicit p: Parameters) extends LazyModule
{
require (idBits >= 0, s"AXI4IdIndexer: idBits must be > 0, not $idBits")
val node = AXI4AdapterNode(
masterFn = { mp =>
// Create one new "master" per ID
val masters = Array.tabulate(1 << idBits) { i => AXI4MasterParameters(
name = "",
id = IdRange(i, i+1),
aligned = true,
maxFlight = Some(0))
}
// Accumulate the names of masters we squish
val names = Array.fill(1 << idBits) { new scala.collection.mutable.HashSet[String]() }
// Squash the information from original masters into new ID masters
mp.masters.foreach { m =>
for (i <- m.id.start until m.id.end) {
val j = i % (1 << idBits)
val accumulated = masters(j)
names(j) += m.name
masters(j) = accumulated.copy(
aligned = accumulated.aligned && m.aligned,
maxFlight = accumulated.maxFlight.flatMap { o => m.maxFlight.map { n => o+n } })
}
}
val finalNameStrings = names.map { n => if (n.isEmpty) "(unused)" else n.toList.mkString(", ") }
val bits = log2Ceil(mp.endId) - idBits
val field = if (bits > 0) Seq(AXI4ExtraIdField(bits)) else Nil
mp.copy(
echoFields = field ++ mp.echoFields,
masters = masters.zip(finalNameStrings).map { case (m, n) => m.copy(name = n) })
},
slaveFn = { sp => sp
})
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
// Leave everything mostly untouched
Connectable.waiveUnmatched(out.ar, in.ar) match {
case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
}
Connectable.waiveUnmatched(out.aw, in.aw) match {
case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
}
Connectable.waiveUnmatched(out.w, in.w) match {
case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
}
Connectable.waiveUnmatched(in.b, out.b) match {
case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
}
Connectable.waiveUnmatched(in.r, out.r) match {
case (lhs, rhs) => lhs.squeezeAll :<>= rhs.squeezeAll
}
val bits = log2Ceil(edgeIn.master.endId) - idBits
if (bits > 0) {
// (in.aX.bits.id >> idBits).width = bits > 0
out.ar.bits.echo(AXI4ExtraId) := in.ar.bits.id >> idBits
out.aw.bits.echo(AXI4ExtraId) := in.aw.bits.id >> idBits
// Special care is needed in case of 0 idBits, b/c .id has width 1 still
if (idBits == 0) {
out.ar.bits.id := 0.U
out.aw.bits.id := 0.U
in.r.bits.id := out.r.bits.echo(AXI4ExtraId)
in.b.bits.id := out.b.bits.echo(AXI4ExtraId)
} else {
in.r.bits.id := Cat(out.r.bits.echo(AXI4ExtraId), out.r.bits.id)
in.b.bits.id := Cat(out.b.bits.echo(AXI4ExtraId), out.b.bits.id)
}
}
}
}
}
object AXI4IdIndexer
{
def apply(idBits: Int)(implicit p: Parameters): AXI4Node =
{
val axi4index = LazyModule(new AXI4IdIndexer(idBits))
axi4index.node
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
|
module AXI4IdIndexer_1( // @[IdIndexer.scala:63:9]
output auto_in_aw_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_valid, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_aw_bits_id, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_aw_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
output auto_in_w_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_w_valid, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_w_bits_data, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_w_bits_strb, // @[LazyModuleImp.scala:107:25]
input auto_in_w_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_id, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_ar_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_valid, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_ar_bits_id, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_ar_bits_len, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
input auto_in_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
input auto_in_r_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_r_valid, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_r_bits_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_r_bits_data, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_r_bits_resp, // @[LazyModuleImp.scala:107:25]
output auto_in_r_bits_last, // @[LazyModuleImp.scala:107:25]
input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_aw_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
input auto_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_b_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_out_ar_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
output auto_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_out_r_bits_echo_extra_id, // @[LazyModuleImp.scala:107:25]
input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25]
);
assign auto_in_aw_ready = auto_out_aw_ready; // @[IdIndexer.scala:63:9]
assign auto_in_w_ready = auto_out_w_ready; // @[IdIndexer.scala:63:9]
assign auto_in_b_valid = auto_out_b_valid; // @[IdIndexer.scala:63:9]
assign auto_in_b_bits_id = {auto_out_b_bits_echo_extra_id, auto_out_b_bits_id}; // @[IdIndexer.scala:63:9, :97:30]
assign auto_in_b_bits_resp = auto_out_b_bits_resp; // @[IdIndexer.scala:63:9]
assign auto_in_ar_ready = auto_out_ar_ready; // @[IdIndexer.scala:63:9]
assign auto_in_r_valid = auto_out_r_valid; // @[IdIndexer.scala:63:9]
assign auto_in_r_bits_id = {auto_out_r_bits_echo_extra_id, auto_out_r_bits_id}; // @[IdIndexer.scala:63:9, :96:30]
assign auto_in_r_bits_data = auto_out_r_bits_data; // @[IdIndexer.scala:63:9]
assign auto_in_r_bits_resp = auto_out_r_bits_resp; // @[IdIndexer.scala:63:9]
assign auto_in_r_bits_last = auto_out_r_bits_last; // @[IdIndexer.scala:63:9]
assign auto_out_aw_valid = auto_in_aw_valid; // @[IdIndexer.scala:63:9]
assign auto_out_aw_bits_id = auto_in_aw_bits_id[2:0]; // @[IdIndexer.scala:63:9, :72:43]
assign auto_out_aw_bits_addr = auto_in_aw_bits_addr; // @[IdIndexer.scala:63:9]
assign auto_out_aw_bits_len = auto_in_aw_bits_len; // @[IdIndexer.scala:63:9]
assign auto_out_aw_bits_size = auto_in_aw_bits_size; // @[IdIndexer.scala:63:9]
assign auto_out_aw_bits_burst = auto_in_aw_bits_burst; // @[IdIndexer.scala:63:9]
assign auto_out_aw_bits_lock = auto_in_aw_bits_lock; // @[IdIndexer.scala:63:9]
assign auto_out_aw_bits_cache = auto_in_aw_bits_cache; // @[IdIndexer.scala:63:9]
assign auto_out_aw_bits_prot = auto_in_aw_bits_prot; // @[IdIndexer.scala:63:9]
assign auto_out_aw_bits_qos = auto_in_aw_bits_qos; // @[IdIndexer.scala:63:9]
assign auto_out_aw_bits_echo_extra_id = auto_in_aw_bits_id[7:3]; // @[IdIndexer.scala:63:9, :88:56]
assign auto_out_w_valid = auto_in_w_valid; // @[IdIndexer.scala:63:9]
assign auto_out_w_bits_data = auto_in_w_bits_data; // @[IdIndexer.scala:63:9]
assign auto_out_w_bits_strb = auto_in_w_bits_strb; // @[IdIndexer.scala:63:9]
assign auto_out_w_bits_last = auto_in_w_bits_last; // @[IdIndexer.scala:63:9]
assign auto_out_b_ready = auto_in_b_ready; // @[IdIndexer.scala:63:9]
assign auto_out_ar_valid = auto_in_ar_valid; // @[IdIndexer.scala:63:9]
assign auto_out_ar_bits_id = auto_in_ar_bits_id[2:0]; // @[IdIndexer.scala:63:9, :69:43]
assign auto_out_ar_bits_addr = auto_in_ar_bits_addr; // @[IdIndexer.scala:63:9]
assign auto_out_ar_bits_len = auto_in_ar_bits_len; // @[IdIndexer.scala:63:9]
assign auto_out_ar_bits_size = auto_in_ar_bits_size; // @[IdIndexer.scala:63:9]
assign auto_out_ar_bits_burst = auto_in_ar_bits_burst; // @[IdIndexer.scala:63:9]
assign auto_out_ar_bits_lock = auto_in_ar_bits_lock; // @[IdIndexer.scala:63:9]
assign auto_out_ar_bits_cache = auto_in_ar_bits_cache; // @[IdIndexer.scala:63:9]
assign auto_out_ar_bits_prot = auto_in_ar_bits_prot; // @[IdIndexer.scala:63:9]
assign auto_out_ar_bits_qos = auto_in_ar_bits_qos; // @[IdIndexer.scala:63:9]
assign auto_out_ar_bits_echo_extra_id = auto_in_ar_bits_id[7:3]; // @[IdIndexer.scala:63:9, :87:56]
assign auto_out_r_ready = auto_in_r_ready; // @[IdIndexer.scala:63:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File RecFNToRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import consts._
class
RecFNToRecFN(
inExpWidth: Int, inSigWidth: Int, outExpWidth: Int, outSigWidth: Int)
extends chisel3.RawModule
{
val io = IO(new Bundle {
val in = Input(Bits((inExpWidth + inSigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(UInt(1.W))
val out = Output(Bits((outExpWidth + outSigWidth + 1).W))
val exceptionFlags = Output(Bits(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val rawIn = rawFloatFromRecFN(inExpWidth, inSigWidth, io.in);
if ((inExpWidth == outExpWidth) && (inSigWidth <= outSigWidth)) {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
io.out := io.in<<(outSigWidth - inSigWidth)
io.exceptionFlags := isSigNaNRawFloat(rawIn) ## 0.U(4.W)
} else {
//--------------------------------------------------------------------
//--------------------------------------------------------------------
val roundAnyRawFNToRecFN =
Module(
new RoundAnyRawFNToRecFN(
inExpWidth,
inSigWidth,
outExpWidth,
outSigWidth,
flRoundOpt_sigMSBitAlwaysZero
))
roundAnyRawFNToRecFN.io.invalidExc := isSigNaNRawFloat(rawIn)
roundAnyRawFNToRecFN.io.infiniteExc := false.B
roundAnyRawFNToRecFN.io.in := rawIn
roundAnyRawFNToRecFN.io.roundingMode := io.roundingMode
roundAnyRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundAnyRawFNToRecFN.io.out
io.exceptionFlags := roundAnyRawFNToRecFN.io.exceptionFlags
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
File common.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017, 2018 The Regents of
the University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object consts {
/*------------------------------------------------------------------------
| For rounding to integer values, rounding mode 'odd' rounds to minimum
| magnitude instead, same as 'minMag'.
*------------------------------------------------------------------------*/
def round_near_even = "b000".U(3.W)
def round_minMag = "b001".U(3.W)
def round_min = "b010".U(3.W)
def round_max = "b011".U(3.W)
def round_near_maxMag = "b100".U(3.W)
def round_odd = "b110".U(3.W)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def tininess_beforeRounding = 0.U
def tininess_afterRounding = 1.U
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def flRoundOpt_sigMSBitAlwaysZero = 1
def flRoundOpt_subnormsAlwaysExact = 2
def flRoundOpt_neverUnderflows = 4
def flRoundOpt_neverOverflows = 8
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
def divSqrtOpt_twoBitsPerCycle = 16
}
class RawFloat(val expWidth: Int, val sigWidth: Int) extends Bundle
{
val isNaN: Bool = Bool() // overrides all other fields
val isInf: Bool = Bool() // overrides 'isZero', 'sExp', and 'sig'
val isZero: Bool = Bool() // overrides 'sExp' and 'sig'
val sign: Bool = Bool()
val sExp: SInt = SInt((expWidth + 2).W)
val sig: UInt = UInt((sigWidth + 1).W) // 2 m.s. bits cannot both be 0
}
//*** CHANGE THIS INTO A '.isSigNaN' METHOD OF THE 'RawFloat' CLASS:
object isSigNaNRawFloat
{
def apply(in: RawFloat): Bool = in.isNaN && !in.sig(in.sigWidth - 2)
}
|
module RecFNToRecFN_6( // @[RecFNToRecFN.scala:44:5]
input [64:0] io_in, // @[RecFNToRecFN.scala:48:16]
input [2:0] io_roundingMode, // @[RecFNToRecFN.scala:48:16]
output [16:0] io_out, // @[RecFNToRecFN.scala:48:16]
output [4:0] io_exceptionFlags // @[RecFNToRecFN.scala:48:16]
);
wire [64:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19]
wire [16:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5]
wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[51]; // @[rawFloatFromRecFN.scala:55:23]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23]
RoundAnyRawFNToRecFN_ie11_is53_oe5_os11_3 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19]
.io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46]
.io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_roundingMode (io_roundingMode_0), // @[RecFNToRecFN.scala:44:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RecFNToRecFN.scala:72:19]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RecFNToRecFN.scala:44:5]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File UnsafeAXI4ToTL.scala:
package ara
import chisel3._
import chisel3.util._
import freechips.rocketchip.amba._
import freechips.rocketchip.amba.axi4._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
class ReorderData(val dataWidth: Int, val respWidth: Int, val userFields: Seq[BundleFieldBase]) extends Bundle {
val data = UInt(dataWidth.W)
val resp = UInt(respWidth.W)
val last = Bool()
val user = BundleMap(userFields)
}
/** Parameters for [[BaseReservableListBuffer]] and all child classes.
*
* @param numEntries Total number of elements that can be stored in the 'data' RAM
* @param numLists Maximum number of linked lists
* @param numBeats Maximum number of beats per entry
*/
case class ReservableListBufferParameters(numEntries: Int, numLists: Int, numBeats: Int) {
// Avoid zero-width wires when we call 'log2Ceil'
val entryBits = if (numEntries == 1) 1 else log2Ceil(numEntries)
val listBits = if (numLists == 1) 1 else log2Ceil(numLists)
val beatBits = if (numBeats == 1) 1 else log2Ceil(numBeats)
}
case class UnsafeAXI4ToTLNode(numTlTxns: Int, wcorrupt: Boolean)(implicit valName: ValName)
extends MixedAdapterNode(AXI4Imp, TLImp)(
dFn = { case mp =>
TLMasterPortParameters.v2(
masters = mp.masters.zipWithIndex.map { case (m, i) =>
// Support 'numTlTxns' read requests and 'numTlTxns' write requests at once.
val numSourceIds = numTlTxns * 2
TLMasterParameters.v2(
name = m.name,
sourceId = IdRange(i * numSourceIds, (i + 1) * numSourceIds),
nodePath = m.nodePath
)
},
echoFields = mp.echoFields,
requestFields = AMBAProtField() +: mp.requestFields,
responseKeys = mp.responseKeys
)
},
uFn = { mp =>
AXI4SlavePortParameters(
slaves = mp.managers.map { m =>
val maxXfer = TransferSizes(1, mp.beatBytes * (1 << AXI4Parameters.lenBits))
AXI4SlaveParameters(
address = m.address,
resources = m.resources,
regionType = m.regionType,
executable = m.executable,
nodePath = m.nodePath,
supportsWrite = m.supportsPutPartial.intersect(maxXfer),
supportsRead = m.supportsGet.intersect(maxXfer),
interleavedId = Some(0) // TL2 never interleaves D beats
)
},
beatBytes = mp.beatBytes,
minLatency = mp.minLatency,
responseFields = mp.responseFields,
requestKeys = (if (wcorrupt) Seq(AMBACorrupt) else Seq()) ++ mp.requestKeys.filter(_ != AMBAProt)
)
}
)
class UnsafeAXI4ToTL(numTlTxns: Int, wcorrupt: Boolean)(implicit p: Parameters) extends LazyModule {
require(numTlTxns >= 1)
require(isPow2(numTlTxns), s"Number of TileLink transactions ($numTlTxns) must be a power of 2")
val node = UnsafeAXI4ToTLNode(numTlTxns, wcorrupt)
lazy val module = new LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
edgeIn.master.masters.foreach { m =>
require(m.aligned, "AXI4ToTL requires aligned requests")
}
val numIds = edgeIn.master.endId
val beatBytes = edgeOut.slave.beatBytes
val maxTransfer = edgeOut.slave.maxTransfer
val maxBeats = maxTransfer / beatBytes
// Look for an Error device to redirect bad requests
val errorDevs = edgeOut.slave.managers.filter(_.nodePath.last.lazyModule.className == "TLError")
require(!errorDevs.isEmpty, "There is no TLError reachable from AXI4ToTL. One must be instantiated.")
val errorDev = errorDevs.maxBy(_.maxTransfer)
val errorDevAddr = errorDev.address.head.base
require(
errorDev.supportsPutPartial.contains(maxTransfer),
s"Error device supports ${errorDev.supportsPutPartial} PutPartial but must support $maxTransfer"
)
require(
errorDev.supportsGet.contains(maxTransfer),
s"Error device supports ${errorDev.supportsGet} Get but must support $maxTransfer"
)
// All of the read-response reordering logic.
val listBufData = new ReorderData(beatBytes * 8, edgeIn.bundle.respBits, out.d.bits.user.fields)
val listBufParams = ReservableListBufferParameters(numTlTxns, numIds, maxBeats)
val listBuffer = if (numTlTxns > 1) {
Module(new ReservableListBuffer(listBufData, listBufParams))
} else {
Module(new PassthroughListBuffer(listBufData, listBufParams))
}
// To differentiate between read and write transaction IDs, we will set the MSB of the TileLink 'source' field to
// 0 for read requests and 1 for write requests.
val isReadSourceBit = 0.U(1.W)
val isWriteSourceBit = 1.U(1.W)
/* Read request logic */
val rOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val rBytes1 = in.ar.bits.bytes1()
val rSize = OH1ToUInt(rBytes1)
val rOk = edgeOut.slave.supportsGetSafe(in.ar.bits.addr, rSize)
val rId = if (numTlTxns > 1) {
Cat(isReadSourceBit, listBuffer.ioReservedIndex)
} else {
isReadSourceBit
}
val rAddr = Mux(rOk, in.ar.bits.addr, errorDevAddr.U | in.ar.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Indicates if there are still valid TileLink source IDs left to use.
val canIssueR = listBuffer.ioReserve.ready
listBuffer.ioReserve.bits := in.ar.bits.id
listBuffer.ioReserve.valid := in.ar.valid && rOut.ready
in.ar.ready := rOut.ready && canIssueR
rOut.valid := in.ar.valid && canIssueR
rOut.bits :<= edgeOut.Get(rId, rAddr, rSize)._2
rOut.bits.user :<= in.ar.bits.user
rOut.bits.user.lift(AMBAProt).foreach { rProt =>
rProt.privileged := in.ar.bits.prot(0)
rProt.secure := !in.ar.bits.prot(1)
rProt.fetch := in.ar.bits.prot(2)
rProt.bufferable := in.ar.bits.cache(0)
rProt.modifiable := in.ar.bits.cache(1)
rProt.readalloc := in.ar.bits.cache(2)
rProt.writealloc := in.ar.bits.cache(3)
}
/* Write request logic */
// Strip off the MSB, which identifies the transaction as read vs write.
val strippedResponseSourceId = if (numTlTxns > 1) {
out.d.bits.source((out.d.bits.source).getWidth - 2, 0)
} else {
// When there's only 1 TileLink transaction allowed for read/write, then this field is always 0.
0.U(1.W)
}
// Track when a write request burst is in progress.
val writeBurstBusy = RegInit(false.B)
when(in.w.fire) {
writeBurstBusy := !in.w.bits.last
}
val usedWriteIds = RegInit(0.U(numTlTxns.W))
val canIssueW = !usedWriteIds.andR
val usedWriteIdsSet = WireDefault(0.U(numTlTxns.W))
val usedWriteIdsClr = WireDefault(0.U(numTlTxns.W))
usedWriteIds := (usedWriteIds & ~usedWriteIdsClr) | usedWriteIdsSet
// Since write responses can show up in the middle of a write burst, we need to ensure the write burst ID doesn't
// change mid-burst.
val freeWriteIdOHRaw = Wire(UInt(numTlTxns.W))
val freeWriteIdOH = freeWriteIdOHRaw holdUnless !writeBurstBusy
val freeWriteIdIndex = OHToUInt(freeWriteIdOH)
freeWriteIdOHRaw := ~(leftOR(~usedWriteIds) << 1) & ~usedWriteIds
val wOut = Wire(Decoupled(new TLBundleA(edgeOut.bundle)))
val wBytes1 = in.aw.bits.bytes1()
val wSize = OH1ToUInt(wBytes1)
val wOk = edgeOut.slave.supportsPutPartialSafe(in.aw.bits.addr, wSize)
val wId = if (numTlTxns > 1) {
Cat(isWriteSourceBit, freeWriteIdIndex)
} else {
isWriteSourceBit
}
val wAddr = Mux(wOk, in.aw.bits.addr, errorDevAddr.U | in.aw.bits.addr(log2Ceil(beatBytes) - 1, 0))
// Here, we're taking advantage of the Irrevocable behavior of AXI4 (once 'valid' is asserted it must remain
// asserted until the handshake occurs). We will only accept W-channel beats when we have a valid AW beat, but
// the AW-channel beat won't fire until the final W-channel beat fires. So, we have stable address/size/strb
// bits during a W-channel burst.
in.aw.ready := wOut.ready && in.w.valid && in.w.bits.last && canIssueW
in.w.ready := wOut.ready && in.aw.valid && canIssueW
wOut.valid := in.aw.valid && in.w.valid && canIssueW
wOut.bits :<= edgeOut.Put(wId, wAddr, wSize, in.w.bits.data, in.w.bits.strb)._2
in.w.bits.user.lift(AMBACorrupt).foreach { wOut.bits.corrupt := _ }
wOut.bits.user :<= in.aw.bits.user
wOut.bits.user.lift(AMBAProt).foreach { wProt =>
wProt.privileged := in.aw.bits.prot(0)
wProt.secure := !in.aw.bits.prot(1)
wProt.fetch := in.aw.bits.prot(2)
wProt.bufferable := in.aw.bits.cache(0)
wProt.modifiable := in.aw.bits.cache(1)
wProt.readalloc := in.aw.bits.cache(2)
wProt.writealloc := in.aw.bits.cache(3)
}
// Merge the AXI4 read/write requests into the TL-A channel.
TLArbiter(TLArbiter.roundRobin)(out.a, (0.U, rOut), (in.aw.bits.len, wOut))
/* Read/write response logic */
val okB = Wire(Irrevocable(new AXI4BundleB(edgeIn.bundle)))
val okR = Wire(Irrevocable(new AXI4BundleR(edgeIn.bundle)))
val dResp = Mux(out.d.bits.denied || out.d.bits.corrupt, AXI4Parameters.RESP_SLVERR, AXI4Parameters.RESP_OKAY)
val dHasData = edgeOut.hasData(out.d.bits)
val (_dFirst, dLast, _dDone, dCount) = edgeOut.count(out.d)
val dNumBeats1 = edgeOut.numBeats1(out.d.bits)
// Handle cases where writeack arrives before write is done
val writeEarlyAck = (UIntToOH(strippedResponseSourceId) & usedWriteIds) === 0.U
out.d.ready := Mux(dHasData, listBuffer.ioResponse.ready, okB.ready && !writeEarlyAck)
listBuffer.ioDataOut.ready := okR.ready
okR.valid := listBuffer.ioDataOut.valid
okB.valid := out.d.valid && !dHasData && !writeEarlyAck
listBuffer.ioResponse.valid := out.d.valid && dHasData
listBuffer.ioResponse.bits.index := strippedResponseSourceId
listBuffer.ioResponse.bits.data.data := out.d.bits.data
listBuffer.ioResponse.bits.data.resp := dResp
listBuffer.ioResponse.bits.data.last := dLast
listBuffer.ioResponse.bits.data.user :<= out.d.bits.user
listBuffer.ioResponse.bits.count := dCount
listBuffer.ioResponse.bits.numBeats1 := dNumBeats1
okR.bits.id := listBuffer.ioDataOut.bits.listIndex
okR.bits.data := listBuffer.ioDataOut.bits.payload.data
okR.bits.resp := listBuffer.ioDataOut.bits.payload.resp
okR.bits.last := listBuffer.ioDataOut.bits.payload.last
okR.bits.user :<= listBuffer.ioDataOut.bits.payload.user
// Upon the final beat in a write request, record a mapping from TileLink source ID to AXI write ID. Upon a write
// response, mark the write transaction as complete.
val writeIdMap = Mem(numTlTxns, UInt(log2Ceil(numIds).W))
val writeResponseId = writeIdMap.read(strippedResponseSourceId)
when(wOut.fire) {
writeIdMap.write(freeWriteIdIndex, in.aw.bits.id)
}
when(edgeOut.done(wOut)) {
usedWriteIdsSet := freeWriteIdOH
}
when(okB.fire) {
usedWriteIdsClr := UIntToOH(strippedResponseSourceId, numTlTxns)
}
okB.bits.id := writeResponseId
okB.bits.resp := dResp
okB.bits.user :<= out.d.bits.user
// AXI4 needs irrevocable behaviour
in.r <> Queue.irrevocable(okR, 1, flow = true)
in.b <> Queue.irrevocable(okB, 1, flow = true)
// Unused channels
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
/* Alignment constraints. The AXI4Fragmenter should guarantee all of these constraints. */
def checkRequest[T <: AXI4BundleA](a: IrrevocableIO[T], reqType: String): Unit = {
val lReqType = reqType.toLowerCase
when(a.valid) {
assert(a.bits.len < maxBeats.U, s"$reqType burst length (%d) must be less than $maxBeats", a.bits.len + 1.U)
// Narrow transfers and FIXED bursts must be single-beat bursts.
when(a.bits.len =/= 0.U) {
assert(
a.bits.size === log2Ceil(beatBytes).U,
s"Narrow $lReqType transfers (%d < $beatBytes bytes) can't be multi-beat bursts (%d beats)",
1.U << a.bits.size,
a.bits.len + 1.U
)
assert(
a.bits.burst =/= AXI4Parameters.BURST_FIXED,
s"Fixed $lReqType bursts can't be multi-beat bursts (%d beats)",
a.bits.len + 1.U
)
}
// Furthermore, the transfer size (a.bits.bytes1() + 1.U) must be naturally-aligned to the address (in
// particular, during both WRAP and INCR bursts), but this constraint is already checked by TileLink
// Monitors. Note that this alignment requirement means that WRAP bursts are identical to INCR bursts.
}
}
checkRequest(in.ar, "Read")
checkRequest(in.aw, "Write")
}
}
}
object UnsafeAXI4ToTL {
def apply(numTlTxns: Int = 1, wcorrupt: Boolean = true)(implicit p: Parameters) = {
val axi42tl = LazyModule(new UnsafeAXI4ToTL(numTlTxns, wcorrupt))
axi42tl.node
}
}
/* ReservableListBuffer logic, and associated classes. */
class ResponsePayload[T <: Data](val data: T, val params: ReservableListBufferParameters) extends Bundle {
val index = UInt(params.entryBits.W)
val count = UInt(params.beatBits.W)
val numBeats1 = UInt(params.beatBits.W)
}
class DataOutPayload[T <: Data](val payload: T, val params: ReservableListBufferParameters) extends Bundle {
val listIndex = UInt(params.listBits.W)
}
/** Abstract base class to unify [[ReservableListBuffer]] and [[PassthroughListBuffer]]. */
abstract class BaseReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends Module {
require(params.numEntries > 0)
require(params.numLists > 0)
val ioReserve = IO(Flipped(Decoupled(UInt(params.listBits.W))))
val ioReservedIndex = IO(Output(UInt(params.entryBits.W)))
val ioResponse = IO(Flipped(Decoupled(new ResponsePayload(gen, params))))
val ioDataOut = IO(Decoupled(new DataOutPayload(gen, params)))
}
/** A modified version of 'ListBuffer' from 'sifive/block-inclusivecache-sifive'. This module forces users to reserve
* linked list entries (through the 'ioReserve' port) before writing data into those linked lists (through the
* 'ioResponse' port). Each response is tagged to indicate which linked list it is written into. The responses for a
* given linked list can come back out-of-order, but they will be read out through the 'ioDataOut' port in-order.
*
* ==Constructor==
* @param gen Chisel type of linked list data element
* @param params Other parameters
*
* ==Module IO==
* @param ioReserve Index of list to reserve a new element in
* @param ioReservedIndex Index of the entry that was reserved in the linked list, valid when 'ioReserve.fire'
* @param ioResponse Payload containing response data and linked-list-entry index
* @param ioDataOut Payload containing data read from response linked list and linked list index
*/
class ReservableListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
val valid = RegInit(0.U(params.numLists.W))
val head = Mem(params.numLists, UInt(params.entryBits.W))
val tail = Mem(params.numLists, UInt(params.entryBits.W))
val used = RegInit(0.U(params.numEntries.W))
val next = Mem(params.numEntries, UInt(params.entryBits.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val dataMems = Seq.fill(params.numBeats) { SyncReadMem(params.numEntries, gen) }
val dataIsPresent = RegInit(0.U(params.numEntries.W))
val beats = Mem(params.numEntries, UInt(params.beatBits.W))
// The 'data' SRAM should be single-ported (read-or-write), since dual-ported SRAMs are significantly slower.
val dataMemReadEnable = WireDefault(false.B)
val dataMemWriteEnable = WireDefault(false.B)
assert(!(dataMemReadEnable && dataMemWriteEnable))
// 'freeOH' has a single bit set, which is the least-significant bit that is cleared in 'used'. So, it's the
// lowest-index entry in the 'data' RAM which is free.
val freeOH = Wire(UInt(params.numEntries.W))
val freeIndex = OHToUInt(freeOH)
freeOH := ~(leftOR(~used) << 1) & ~used
ioReservedIndex := freeIndex
val validSet = WireDefault(0.U(params.numLists.W))
val validClr = WireDefault(0.U(params.numLists.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
val dataIsPresentSet = WireDefault(0.U(params.numEntries.W))
val dataIsPresentClr = WireDefault(0.U(params.numEntries.W))
valid := (valid & ~validClr) | validSet
used := (used & ~usedClr) | usedSet
dataIsPresent := (dataIsPresent & ~dataIsPresentClr) | dataIsPresentSet
/* Reservation logic signals */
val reserveTail = Wire(UInt(params.entryBits.W))
val reserveIsValid = Wire(Bool())
/* Response logic signals */
val responseIndex = Wire(UInt(params.entryBits.W))
val responseListIndex = Wire(UInt(params.listBits.W))
val responseHead = Wire(UInt(params.entryBits.W))
val responseTail = Wire(UInt(params.entryBits.W))
val nextResponseHead = Wire(UInt(params.entryBits.W))
val nextDataIsPresent = Wire(Bool())
val isResponseInOrder = Wire(Bool())
val isEndOfList = Wire(Bool())
val isLastBeat = Wire(Bool())
val isLastResponseBeat = Wire(Bool())
val isLastUnwindBeat = Wire(Bool())
/* Reservation logic */
reserveTail := tail.read(ioReserve.bits)
reserveIsValid := valid(ioReserve.bits)
ioReserve.ready := !used.andR
// When we want to append-to and destroy the same linked list on the same cycle, we need to take special care that we
// actually start a new list, rather than appending to a list that's about to disappear.
val reserveResponseSameList = ioReserve.bits === responseListIndex
val appendToAndDestroyList =
ioReserve.fire && ioDataOut.fire && reserveResponseSameList && isEndOfList && isLastBeat
when(ioReserve.fire) {
validSet := UIntToOH(ioReserve.bits, params.numLists)
usedSet := freeOH
when(reserveIsValid && !appendToAndDestroyList) {
next.write(reserveTail, freeIndex)
}.otherwise {
head.write(ioReserve.bits, freeIndex)
}
tail.write(ioReserve.bits, freeIndex)
map.write(freeIndex, ioReserve.bits)
}
/* Response logic */
// The majority of the response logic (reading from and writing to the various RAMs) is common between the
// response-from-IO case (ioResponse.fire) and the response-from-unwind case (unwindDataIsValid).
// The read from the 'next' RAM should be performed at the address given by 'responseHead'. However, we only use the
// 'nextResponseHead' signal when 'isResponseInOrder' is asserted (both in the response-from-IO and
// response-from-unwind cases), which implies that 'responseHead' equals 'responseIndex'. 'responseHead' comes after
// two back-to-back RAM reads, so indexing into the 'next' RAM with 'responseIndex' is much quicker.
responseHead := head.read(responseListIndex)
responseTail := tail.read(responseListIndex)
nextResponseHead := next.read(responseIndex)
nextDataIsPresent := dataIsPresent(nextResponseHead)
// Note that when 'isEndOfList' is asserted, 'nextResponseHead' (and therefore 'nextDataIsPresent') is invalid, since
// there isn't a next element in the linked list.
isResponseInOrder := responseHead === responseIndex
isEndOfList := responseHead === responseTail
isLastResponseBeat := ioResponse.bits.count === ioResponse.bits.numBeats1
// When a response's last beat is sent to the output channel, mark it as completed. This can happen in two
// situations:
// 1. We receive an in-order response, which travels straight from 'ioResponse' to 'ioDataOut'. The 'data' SRAM
// reservation was never needed.
// 2. An entry is read out of the 'data' SRAM (within the unwind FSM).
when(ioDataOut.fire && isLastBeat) {
// Mark the reservation as no-longer-used.
usedClr := UIntToOH(responseIndex, params.numEntries)
// If the response is in-order, then we're popping an element from this linked list.
when(isEndOfList) {
// Once we pop the last element from a linked list, mark it as no-longer-present.
validClr := UIntToOH(responseListIndex, params.numLists)
}.otherwise {
// Move the linked list's head pointer to the new head pointer.
head.write(responseListIndex, nextResponseHead)
}
}
// If we get an out-of-order response, then stash it in the 'data' SRAM for later unwinding.
when(ioResponse.fire && !isResponseInOrder) {
dataMemWriteEnable := true.B
when(isLastResponseBeat) {
dataIsPresentSet := UIntToOH(ioResponse.bits.index, params.numEntries)
beats.write(ioResponse.bits.index, ioResponse.bits.numBeats1)
}
}
// Use the 'ioResponse.bits.count' index (AKA the beat number) to select which 'data' SRAM to write to.
val responseCountOH = UIntToOH(ioResponse.bits.count, params.numBeats)
(responseCountOH.asBools zip dataMems) foreach { case (select, seqMem) =>
when(select && dataMemWriteEnable) {
seqMem.write(ioResponse.bits.index, ioResponse.bits.data)
}
}
/* Response unwind logic */
// Unwind FSM state definitions
val sIdle :: sUnwinding :: Nil = Enum(2)
val unwindState = RegInit(sIdle)
val busyUnwinding = unwindState === sUnwinding
val startUnwind = Wire(Bool())
val stopUnwind = Wire(Bool())
when(startUnwind) {
unwindState := sUnwinding
}.elsewhen(stopUnwind) {
unwindState := sIdle
}
assert(!(startUnwind && stopUnwind))
// Start the unwind FSM when there is an old out-of-order response stored in the 'data' SRAM that is now about to
// become the next in-order response. As noted previously, when 'isEndOfList' is asserted, 'nextDataIsPresent' is
// invalid.
//
// Note that since an in-order response from 'ioResponse' to 'ioDataOut' starts the unwind FSM, we don't have to
// worry about overwriting the 'data' SRAM's output when we start the unwind FSM.
startUnwind := ioResponse.fire && isResponseInOrder && isLastResponseBeat && !isEndOfList && nextDataIsPresent
// Stop the unwind FSM when the output channel consumes the final beat of an element from the unwind FSM, and one of
// two things happens:
// 1. We're still waiting for the next in-order response for this list (!nextDataIsPresent)
// 2. There are no more outstanding responses in this list (isEndOfList)
//
// Including 'busyUnwinding' ensures this is a single-cycle pulse, and it never fires while in-order transactions are
// passing from 'ioResponse' to 'ioDataOut'.
stopUnwind := busyUnwinding && ioDataOut.fire && isLastUnwindBeat && (!nextDataIsPresent || isEndOfList)
val isUnwindBurstOver = Wire(Bool())
val startNewBurst = startUnwind || (isUnwindBurstOver && dataMemReadEnable)
// Track the number of beats left to unwind for each list entry. At the start of a new burst, we flop the number of
// beats in this burst (minus 1) into 'unwindBeats1', and we reset the 'beatCounter' counter. With each beat, we
// increment 'beatCounter' until it reaches 'unwindBeats1'.
val unwindBeats1 = Reg(UInt(params.beatBits.W))
val nextBeatCounter = Wire(UInt(params.beatBits.W))
val beatCounter = RegNext(nextBeatCounter)
isUnwindBurstOver := beatCounter === unwindBeats1
when(startNewBurst) {
unwindBeats1 := beats.read(nextResponseHead)
nextBeatCounter := 0.U
}.elsewhen(dataMemReadEnable) {
nextBeatCounter := beatCounter + 1.U
}.otherwise {
nextBeatCounter := beatCounter
}
// When unwinding, feed the next linked-list head pointer (read out of the 'next' RAM) back so we can unwind the next
// entry in this linked list. Only update the pointer when we're actually moving to the next 'data' SRAM entry (which
// happens at the start of reading a new stored burst).
val unwindResponseIndex = RegEnable(nextResponseHead, startNewBurst)
responseIndex := Mux(busyUnwinding, unwindResponseIndex, ioResponse.bits.index)
// Hold 'nextResponseHead' static while we're in the middle of unwinding a multi-beat burst entry. We don't want the
// SRAM read address to shift while reading beats from a burst. Note that this is identical to 'nextResponseHead
// holdUnless startNewBurst', but 'unwindResponseIndex' already implements the 'RegEnable' signal in 'holdUnless'.
val unwindReadAddress = Mux(startNewBurst, nextResponseHead, unwindResponseIndex)
// The 'data' SRAM's output is valid if we read from the SRAM on the previous cycle. The SRAM's output stays valid
// until it is consumed by the output channel (and if we don't read from the SRAM again on that same cycle).
val unwindDataIsValid = RegInit(false.B)
when(dataMemReadEnable) {
unwindDataIsValid := true.B
}.elsewhen(ioDataOut.fire) {
unwindDataIsValid := false.B
}
isLastUnwindBeat := isUnwindBurstOver && unwindDataIsValid
// Indicates if this is the last beat for both 'ioResponse'-to-'ioDataOut' and unwind-to-'ioDataOut' beats.
isLastBeat := Mux(busyUnwinding, isLastUnwindBeat, isLastResponseBeat)
// Select which SRAM to read from based on the beat counter.
val dataOutputVec = Wire(Vec(params.numBeats, gen))
val nextBeatCounterOH = UIntToOH(nextBeatCounter, params.numBeats)
(nextBeatCounterOH.asBools zip dataMems).zipWithIndex foreach { case ((select, seqMem), i) =>
dataOutputVec(i) := seqMem.read(unwindReadAddress, select && dataMemReadEnable)
}
// Select the current 'data' SRAM output beat, and save the output in a register in case we're being back-pressured
// by 'ioDataOut'. This implements the functionality of 'readAndHold', but only on the single SRAM we're reading
// from.
val dataOutput = dataOutputVec(beatCounter) holdUnless RegNext(dataMemReadEnable)
// Mark 'data' burst entries as no-longer-present as they get read out of the SRAM.
when(dataMemReadEnable) {
dataIsPresentClr := UIntToOH(unwindReadAddress, params.numEntries)
}
// As noted above, when starting the unwind FSM, we know the 'data' SRAM's output isn't valid, so it's safe to issue
// a read command. Otherwise, only issue an SRAM read when the next 'unwindState' is 'sUnwinding', and if we know
// we're not going to overwrite the SRAM's current output (the SRAM output is already valid, and it's not going to be
// consumed by the output channel).
val dontReadFromDataMem = unwindDataIsValid && !ioDataOut.ready
dataMemReadEnable := startUnwind || (busyUnwinding && !stopUnwind && !dontReadFromDataMem)
// While unwinding, prevent new reservations from overwriting the current 'map' entry that we're using. We need
// 'responseListIndex' to be coherent for the entire unwind process.
val rawResponseListIndex = map.read(responseIndex)
val unwindResponseListIndex = RegEnable(rawResponseListIndex, startNewBurst)
responseListIndex := Mux(busyUnwinding, unwindResponseListIndex, rawResponseListIndex)
// Accept responses either when they can be passed through to the output channel, or if they're out-of-order and are
// just going to be stashed in the 'data' SRAM. Never accept a response payload when we're busy unwinding, since that
// could result in reading from and writing to the 'data' SRAM in the same cycle, and we want that SRAM to be
// single-ported.
ioResponse.ready := (ioDataOut.ready || !isResponseInOrder) && !busyUnwinding
// Either pass an in-order response to the output channel, or data read from the unwind FSM.
ioDataOut.valid := Mux(busyUnwinding, unwindDataIsValid, ioResponse.valid && isResponseInOrder)
ioDataOut.bits.listIndex := responseListIndex
ioDataOut.bits.payload := Mux(busyUnwinding, dataOutput, ioResponse.bits.data)
// It's an error to get a response that isn't associated with a valid linked list.
when(ioResponse.fire || unwindDataIsValid) {
assert(
valid(responseListIndex),
"No linked list exists at index %d, mapped from %d",
responseListIndex,
responseIndex
)
}
when(busyUnwinding && dataMemReadEnable) {
assert(isResponseInOrder, "Unwind FSM must read entries from SRAM in order")
}
}
/** Specialized version of [[ReservableListBuffer]] for the case of numEntries == 1.
*
* Much of the complex logic in [[ReservableListBuffer]] can disappear in this case. For instance, we don't have to
* reorder any responses, or store any linked lists.
*/
class PassthroughListBuffer[T <: Data](gen: T, params: ReservableListBufferParameters)
extends BaseReservableListBuffer(gen, params) {
require(params.numEntries == 1, s"PassthroughListBuffer is only valid when 'numEntries' (${params.numEntries}) is 1")
val used = RegInit(0.U(params.numEntries.W))
val map = Mem(params.numEntries, UInt(params.listBits.W))
val usedSet = WireDefault(0.U(params.numEntries.W))
val usedClr = WireDefault(0.U(params.numEntries.W))
used := (used & ~usedClr) | usedSet
ioReserve.ready := used === 0.U
// Store which list index was reserved, we need to return this value when we get a response.
when(ioReserve.fire) {
usedSet := 1.U
map.write(0.U, ioReserve.bits)
}
// There's only one valid linked list entry, which is at index 0.
ioReservedIndex := 0.U
val isLastResponseBeat = ioResponse.bits.count === ioResponse.bits.numBeats1
// Mark the linked list as empty when we get the last beat in a response.
// Note that 'ioResponse.fire === ioDataOut.fire'.
when(ioResponse.fire && isLastResponseBeat) {
usedClr := 1.U
}
// Always pass the response data straight through, since we never need to reorder the response data.
ioDataOut.bits.listIndex := map.read(0.U)
ioDataOut.bits.payload := ioResponse.bits.data
ioDataOut.valid := ioResponse.valid
ioResponse.ready := ioDataOut.ready
}
|
module dataMems_89( // @[UnsafeAXI4ToTL.scala:365:62]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [66:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [66:0] W0_data
);
dataMems_0_ext dataMems_0_ext ( // @[UnsafeAXI4ToTL.scala:365:62]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[UnsafeAXI4ToTL.scala:365:62]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Tile.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
import Util._
/**
* A Tile is a purely combinational 2D array of passThrough PEs.
* a, b, s, and in_propag are broadcast across the entire array and are passed through to the Tile's outputs
* @param width The data width of each PE in bits
* @param rows Number of PEs on each row
* @param columns Number of PEs on each column
*/
class Tile[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, tree_reduction: Boolean, max_simultaneous_matmuls: Int, val rows: Int, val columns: Int)(implicit ev: Arithmetic[T]) extends Module {
val io = IO(new Bundle {
val in_a = Input(Vec(rows, inputType))
val in_b = Input(Vec(columns, outputType)) // This is the output of the tile next to it
val in_d = Input(Vec(columns, outputType))
val in_control = Input(Vec(columns, new PEControl(accType)))
val in_id = Input(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val in_last = Input(Vec(columns, Bool()))
val out_a = Output(Vec(rows, inputType))
val out_c = Output(Vec(columns, outputType))
val out_b = Output(Vec(columns, outputType))
val out_control = Output(Vec(columns, new PEControl(accType)))
val out_id = Output(Vec(columns, UInt(log2Up(max_simultaneous_matmuls).W)))
val out_last = Output(Vec(columns, Bool()))
val in_valid = Input(Vec(columns, Bool()))
val out_valid = Output(Vec(columns, Bool()))
val bad_dataflow = Output(Bool())
})
import ev._
val tile = Seq.fill(rows, columns)(Module(new PE(inputType, outputType, accType, df, max_simultaneous_matmuls)))
val tileT = tile.transpose
// TODO: abstract hori/vert broadcast, all these connections look the same
// Broadcast 'a' horizontally across the Tile
for (r <- 0 until rows) {
tile(r).foldLeft(io.in_a(r)) {
case (in_a, pe) =>
pe.io.in_a := in_a
pe.io.out_a
}
}
// Broadcast 'b' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_b(c)) {
case (in_b, pe) =>
pe.io.in_b := (if (tree_reduction) in_b.zero else in_b)
pe.io.out_b
}
}
// Broadcast 'd' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_d(c)) {
case (in_d, pe) =>
pe.io.in_d := in_d
pe.io.out_c
}
}
// Broadcast 'control' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_control(c)) {
case (in_ctrl, pe) =>
pe.io.in_control := in_ctrl
pe.io.out_control
}
}
// Broadcast 'garbage' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_valid(c)) {
case (v, pe) =>
pe.io.in_valid := v
pe.io.out_valid
}
}
// Broadcast 'id' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_id(c)) {
case (id, pe) =>
pe.io.in_id := id
pe.io.out_id
}
}
// Broadcast 'last' vertically across the Tile
for (c <- 0 until columns) {
tileT(c).foldLeft(io.in_last(c)) {
case (last, pe) =>
pe.io.in_last := last
pe.io.out_last
}
}
// Drive the Tile's bottom IO
for (c <- 0 until columns) {
io.out_c(c) := tile(rows-1)(c).io.out_c
io.out_control(c) := tile(rows-1)(c).io.out_control
io.out_id(c) := tile(rows-1)(c).io.out_id
io.out_last(c) := tile(rows-1)(c).io.out_last
io.out_valid(c) := tile(rows-1)(c).io.out_valid
io.out_b(c) := {
if (tree_reduction) {
val prods = tileT(c).map(_.io.out_b)
accumulateTree(prods :+ io.in_b(c))
} else {
tile(rows - 1)(c).io.out_b
}
}
}
io.bad_dataflow := tile.map(_.map(_.io.bad_dataflow).reduce(_||_)).reduce(_||_)
// Drive the Tile's right IO
for (r <- 0 until rows) {
io.out_a(r) := tile(r)(columns-1).io.out_a
}
}
|
module Tile_132( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_388 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File ToAXI4.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.amba.{AMBACorrupt, AMBACorruptField, AMBAProt, AMBAProtField}
import freechips.rocketchip.amba.axi4.{AXI4BundleARW, AXI4MasterParameters, AXI4MasterPortParameters, AXI4Parameters, AXI4Imp}
import freechips.rocketchip.diplomacy.{IdMap, IdMapEntry, IdRange}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, UIntToOH1}
import freechips.rocketchip.util.DataToAugmentedData
class AXI4TLStateBundle(val sourceBits: Int) extends Bundle {
val size = UInt(4.W)
val source = UInt((sourceBits max 1).W)
}
case object AXI4TLState extends ControlKey[AXI4TLStateBundle]("tl_state")
case class AXI4TLStateField(sourceBits: Int) extends BundleField[AXI4TLStateBundle](AXI4TLState, Output(new AXI4TLStateBundle(sourceBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLtoAXI4IdMap serves as a record for the translation performed between id spaces.
*
* Its member [axi4Masters] is used as the new AXI4MasterParameters in diplomacy.
* Its member [mapping] is used as the template for the circuit generated in TLToAXI4Node.module.
*/
class TLtoAXI4IdMap(tlPort: TLMasterPortParameters) extends IdMap[TLToAXI4IdMapEntry]
{
val tlMasters = tlPort.masters.sortBy(_.sourceId).sortWith(TLToAXI4.sortByType)
private val axi4IdSize = tlMasters.map { tl => if (tl.requestFifo) 1 else tl.sourceId.size }
private val axi4IdStart = axi4IdSize.scanLeft(0)(_+_).init
val axi4Masters = axi4IdStart.zip(axi4IdSize).zip(tlMasters).map { case ((start, size), tl) =>
AXI4MasterParameters(
name = tl.name,
id = IdRange(start, start+size),
aligned = true,
maxFlight = Some(if (tl.requestFifo) tl.sourceId.size else 1),
nodePath = tl.nodePath)
}
private val axi4IdEnd = axi4Masters.map(_.id.end).max
private val axiDigits = String.valueOf(axi4IdEnd-1).length()
private val tlDigits = String.valueOf(tlPort.endSourceId-1).length()
protected val fmt = s"\t[%${axiDigits}d, %${axiDigits}d) <= [%${tlDigits}d, %${tlDigits}d) %s%s%s"
val mapping: Seq[TLToAXI4IdMapEntry] = tlMasters.zip(axi4Masters).map { case (tl, axi) =>
TLToAXI4IdMapEntry(axi.id, tl.sourceId, tl.name, tl.supports.probe, tl.requestFifo)
}
}
case class TLToAXI4IdMapEntry(axi4Id: IdRange, tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = axi4Id
val maxTransactionsInFlight = Some(tlId.size)
}
case class TLToAXI4Node(wcorrupt: Boolean = true)(implicit valName: ValName) extends MixedAdapterNode(TLImp, AXI4Imp)(
dFn = { p =>
AXI4MasterPortParameters(
masters = (new TLtoAXI4IdMap(p)).axi4Masters,
requestFields = (if (wcorrupt) Seq(AMBACorruptField()) else Seq()) ++ p.requestFields.filter(!_.isInstanceOf[AMBAProtField]),
echoFields = AXI4TLStateField(log2Ceil(p.endSourceId)) +: p.echoFields,
responseKeys = p.responseKeys)
},
uFn = { p => TLSlavePortParameters.v1(
managers = p.slaves.map { case s =>
TLSlaveParameters.v1(
address = s.address,
resources = s.resources,
regionType = s.regionType,
executable = s.executable,
nodePath = s.nodePath,
supportsGet = s.supportsRead,
supportsPutFull = s.supportsWrite,
supportsPutPartial = s.supportsWrite,
fifoId = Some(0),
mayDenyPut = true,
mayDenyGet = true)},
beatBytes = p.beatBytes,
minLatency = p.minLatency,
responseFields = p.responseFields,
requestKeys = AMBAProt +: p.requestKeys)
})
// wcorrupt alone is not enough; a slave must include AMBACorrupt in the slave port's requestKeys
class TLToAXI4(val combinational: Boolean = true, val adapterName: Option[String] = None, val stripBits: Int = 0, val wcorrupt: Boolean = true)(implicit p: Parameters) extends LazyModule
{
require(stripBits == 0, "stripBits > 0 is no longer supported on TLToAXI4")
val node = TLToAXI4Node(wcorrupt)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
val slaves = edgeOut.slave.slaves
// All pairs of slaves must promise that they will never interleave data
require (slaves(0).interleavedId.isDefined)
slaves.foreach { s => require (s.interleavedId == slaves(0).interleavedId) }
// Construct the source=>ID mapping table
val map = new TLtoAXI4IdMap(edgeIn.client)
val sourceStall = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(false.B))
val sourceTable = WireDefault(VecInit.fill(edgeIn.client.endSourceId)(0.U.asTypeOf(out.aw.bits.id)))
val idStall = WireDefault(VecInit.fill(edgeOut.master.endId)(false.B))
var idCount = Array.fill(edgeOut.master.endId) { None:Option[Int] }
map.mapping.foreach { case TLToAXI4IdMapEntry(axi4Id, tlId, _, _, fifo) =>
for (i <- 0 until tlId.size) {
val id = axi4Id.start + (if (fifo) 0 else i)
sourceStall(tlId.start + i) := idStall(id)
sourceTable(tlId.start + i) := id.U
}
if (fifo) { idCount(axi4Id.start) = Some(tlId.size) }
}
adapterName.foreach { n =>
println(s"$n AXI4-ID <= TL-Source mapping:\n${map.pretty}\n")
ElaborationArtefacts.add(s"$n.axi4.json", s"""{"mapping":[${map.mapping.mkString(",")}]}""")
}
// We need to keep the following state from A => D: (size, source)
// All of those fields could potentially require 0 bits (argh. Chisel.)
// We will pack all of that extra information into the echo bits.
require (log2Ceil(edgeIn.maxLgSize+1) <= 4)
val a_address = edgeIn.address(in.a.bits)
val a_source = in.a.bits.source
val a_size = edgeIn.size(in.a.bits)
val a_isPut = edgeIn.hasData(in.a.bits)
val (a_first, a_last, _) = edgeIn.firstlast(in.a)
val r_state = out.r.bits.echo(AXI4TLState)
val r_source = r_state.source
val r_size = r_state.size
val b_state = out.b.bits.echo(AXI4TLState)
val b_source = b_state.source
val b_size = b_state.size
// We need these Queues because AXI4 queues are irrevocable
val depth = if (combinational) 1 else 2
val out_arw = Wire(Decoupled(new AXI4BundleARW(out.params)))
val out_w = Wire(chiselTypeOf(out.w))
out.w :<>= Queue.irrevocable(out_w, entries=depth, flow=combinational)
val queue_arw = Queue.irrevocable(out_arw, entries=depth, flow=combinational)
// Fan out the ARW channel to AR and AW
out.ar.bits := queue_arw.bits
out.aw.bits := queue_arw.bits
out.ar.valid := queue_arw.valid && !queue_arw.bits.wen
out.aw.valid := queue_arw.valid && queue_arw.bits.wen
queue_arw.ready := Mux(queue_arw.bits.wen, out.aw.ready, out.ar.ready)
val beatBytes = edgeIn.manager.beatBytes
val maxSize = log2Ceil(beatBytes).U
val doneAW = RegInit(false.B)
when (in.a.fire) { doneAW := !a_last }
val arw = out_arw.bits
arw.wen := a_isPut
arw.id := sourceTable(a_source)
arw.addr := a_address
arw.len := UIntToOH1(a_size, AXI4Parameters.lenBits + log2Ceil(beatBytes)) >> log2Ceil(beatBytes)
arw.size := Mux(a_size >= maxSize, maxSize, a_size)
arw.burst := AXI4Parameters.BURST_INCR
arw.lock := 0.U // not exclusive (LR/SC unsupported b/c no forward progress guarantee)
arw.cache := 0.U // do not allow AXI to modify our transactions
arw.prot := AXI4Parameters.PROT_PRIVILEGED
arw.qos := 0.U // no QoS
Connectable.waiveUnmatched(arw.user, in.a.bits.user) match {
case (lhs, rhs) => lhs :<= rhs
}
Connectable.waiveUnmatched(arw.echo, in.a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = arw.echo(AXI4TLState)
a_extra.source := a_source
a_extra.size := a_size
in.a.bits.user.lift(AMBAProt).foreach { x =>
val prot = Wire(Vec(3, Bool()))
val cache = Wire(Vec(4, Bool()))
prot(0) := x.privileged
prot(1) := !x.secure
prot(2) := x.fetch
cache(0) := x.bufferable
cache(1) := x.modifiable
cache(2) := x.readalloc
cache(3) := x.writealloc
arw.prot := Cat(prot.reverse)
arw.cache := Cat(cache.reverse)
}
val stall = sourceStall(in.a.bits.source) && a_first
in.a.ready := !stall && Mux(a_isPut, (doneAW || out_arw.ready) && out_w.ready, out_arw.ready)
out_arw.valid := !stall && in.a.valid && Mux(a_isPut, !doneAW && out_w.ready, true.B)
out_w.valid := !stall && in.a.valid && a_isPut && (doneAW || out_arw.ready)
out_w.bits.data := in.a.bits.data
out_w.bits.strb := in.a.bits.mask
out_w.bits.last := a_last
out_w.bits.user.lift(AMBACorrupt).foreach { _ := in.a.bits.corrupt }
// R and B => D arbitration
val r_holds_d = RegInit(false.B)
when (out.r.fire) { r_holds_d := !out.r.bits.last }
// Give R higher priority than B, unless B has been delayed for 8 cycles
val b_delay = Reg(UInt(3.W))
when (out.b.valid && !out.b.ready) {
b_delay := b_delay + 1.U
} .otherwise {
b_delay := 0.U
}
val r_wins = (out.r.valid && b_delay =/= 7.U) || r_holds_d
out.r.ready := in.d.ready && r_wins
out.b.ready := in.d.ready && !r_wins
in.d.valid := Mux(r_wins, out.r.valid, out.b.valid)
// If the first beat of the AXI RRESP is RESP_DECERR, treat this as a denied
// request. We must pulse extend this value as AXI is allowed to change the
// value of RRESP on every beat, and ChipLink may not.
val r_first = RegInit(true.B)
when (out.r.fire) { r_first := out.r.bits.last }
val r_denied = out.r.bits.resp === AXI4Parameters.RESP_DECERR holdUnless r_first
val r_corrupt = out.r.bits.resp =/= AXI4Parameters.RESP_OKAY
val b_denied = out.b.bits.resp =/= AXI4Parameters.RESP_OKAY
val r_d = edgeIn.AccessAck(r_source, r_size, 0.U, denied = r_denied, corrupt = r_corrupt || r_denied)
val b_d = edgeIn.AccessAck(b_source, b_size, denied = b_denied)
Connectable.waiveUnmatched(r_d.user, out.r.bits.user) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(r_d.echo, out.r.bits.echo) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(b_d.user, out.b.bits.user) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
Connectable.waiveUnmatched(b_d.echo, out.b.bits.echo) match {
case (lhs, rhs) => lhs.squeezeAll :<= rhs.squeezeAll
}
in.d.bits := Mux(r_wins, r_d, b_d)
in.d.bits.data := out.r.bits.data // avoid a costly Mux
// We need to track if any reads or writes are inflight for a given ID.
// If the opposite type arrives, we must stall until it completes.
val a_sel = UIntToOH(arw.id, edgeOut.master.endId).asBools
val d_sel = UIntToOH(Mux(r_wins, out.r.bits.id, out.b.bits.id), edgeOut.master.endId).asBools
val d_last = Mux(r_wins, out.r.bits.last, true.B)
// If FIFO was requested, ensure that R+W ordering is preserved
(a_sel zip d_sel zip idStall zip idCount) foreach { case (((as, ds), s), n) =>
// AXI does not guarantee read vs. write ordering. In particular, if we
// are in the middle of receiving a read burst and then issue a write,
// the write might affect the read burst. This violates FIFO behaviour.
// To solve this, we must wait until the last beat of a burst, but this
// means that a TileLink master which performs early source reuse can
// have one more transaction inflight than we promised AXI; stall it too.
val maxCount = n.getOrElse(1)
val count = RegInit(0.U(log2Ceil(maxCount + 1).W))
val write = Reg(Bool())
val idle = count === 0.U
val inc = as && out_arw.fire
val dec = ds && d_last && in.d.fire
count := count + inc.asUInt - dec.asUInt
assert (!dec || count =/= 0.U) // underflow
assert (!inc || count =/= maxCount.U) // overflow
when (inc) { write := arw.wen }
// If only one transaction can be inflight, it can't mismatch
val mismatch = if (maxCount > 1) { write =/= arw.wen } else { false.B }
s := (!idle && mismatch) || (count === maxCount.U)
}
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
}
}
}
object TLToAXI4
{
def apply(combinational: Boolean = true, adapterName: Option[String] = None, stripBits: Int = 0, wcorrupt: Boolean = true)(implicit p: Parameters) =
{
val tl2axi4 = LazyModule(new TLToAXI4(combinational, adapterName, stripBits, wcorrupt))
tl2axi4.node
}
def sortByType(a: TLMasterParameters, b: TLMasterParameters): Boolean = {
if ( a.supports.probe && !b.supports.probe) return false
if (!a.supports.probe && b.supports.probe) return true
if ( a.requestFifo && !b.requestFifo ) return false
if (!a.requestFifo && b.requestFifo ) return true
return false
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLToAXI4_1( // @[ToAXI4.scala:103:9]
input clock, // @[ToAXI4.scala:103:9]
input reset, // @[ToAXI4.scala:103:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_aw_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_valid, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_aw_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_aw_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_aw_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_aw_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_aw_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_aw_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_qos, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_aw_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_aw_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_out_w_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_w_valid, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_w_bits_data, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_w_bits_strb, // @[LazyModuleImp.scala:107:25]
output auto_out_w_bits_last, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_b_bits_id, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_resp, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_b_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_out_ar_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_valid, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_ar_bits_id, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_ar_bits_addr, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_ar_bits_len, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_ar_bits_burst, // @[LazyModuleImp.scala:107:25]
output auto_out_ar_bits_lock, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_cache, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_ar_bits_prot, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_qos, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_ar_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_out_ar_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
output auto_out_r_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_r_valid, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_r_bits_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_r_bits_data, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_r_bits_resp, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_r_bits_echo_tl_state_size, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_out_r_bits_echo_tl_state_source, // @[LazyModuleImp.scala:107:25]
input auto_out_r_bits_last // @[LazyModuleImp.scala:107:25]
);
reg count_57; // @[ToAXI4.scala:272:28]
reg count_56; // @[ToAXI4.scala:272:28]
reg count_55; // @[ToAXI4.scala:272:28]
reg count_54; // @[ToAXI4.scala:272:28]
reg count_53; // @[ToAXI4.scala:272:28]
reg count_52; // @[ToAXI4.scala:272:28]
reg count_51; // @[ToAXI4.scala:272:28]
reg count_50; // @[ToAXI4.scala:272:28]
reg count_49; // @[ToAXI4.scala:272:28]
reg count_48; // @[ToAXI4.scala:272:28]
reg count_47; // @[ToAXI4.scala:272:28]
reg count_46; // @[ToAXI4.scala:272:28]
reg count_45; // @[ToAXI4.scala:272:28]
reg count_44; // @[ToAXI4.scala:272:28]
reg count_43; // @[ToAXI4.scala:272:28]
reg count_42; // @[ToAXI4.scala:272:28]
reg count_41; // @[ToAXI4.scala:272:28]
reg count_40; // @[ToAXI4.scala:272:28]
reg count_39; // @[ToAXI4.scala:272:28]
reg count_38; // @[ToAXI4.scala:272:28]
reg count_37; // @[ToAXI4.scala:272:28]
reg count_36; // @[ToAXI4.scala:272:28]
reg count_35; // @[ToAXI4.scala:272:28]
reg count_34; // @[ToAXI4.scala:272:28]
reg count_33; // @[ToAXI4.scala:272:28]
reg count_32; // @[ToAXI4.scala:272:28]
reg count_31; // @[ToAXI4.scala:272:28]
reg count_30; // @[ToAXI4.scala:272:28]
reg count_29; // @[ToAXI4.scala:272:28]
reg count_28; // @[ToAXI4.scala:272:28]
reg count_27; // @[ToAXI4.scala:272:28]
reg count_26; // @[ToAXI4.scala:272:28]
reg count_25; // @[ToAXI4.scala:272:28]
reg count_24; // @[ToAXI4.scala:272:28]
reg count_23; // @[ToAXI4.scala:272:28]
reg count_22; // @[ToAXI4.scala:272:28]
reg count_21; // @[ToAXI4.scala:272:28]
reg count_20; // @[ToAXI4.scala:272:28]
reg count_19; // @[ToAXI4.scala:272:28]
reg count_18; // @[ToAXI4.scala:272:28]
reg count_17; // @[ToAXI4.scala:272:28]
reg count_16; // @[ToAXI4.scala:272:28]
reg count_15; // @[ToAXI4.scala:272:28]
reg count_14; // @[ToAXI4.scala:272:28]
reg count_13; // @[ToAXI4.scala:272:28]
reg count_12; // @[ToAXI4.scala:272:28]
reg count_11; // @[ToAXI4.scala:272:28]
reg count_10; // @[ToAXI4.scala:272:28]
reg count_9; // @[ToAXI4.scala:272:28]
reg count_8; // @[ToAXI4.scala:272:28]
reg count_7; // @[ToAXI4.scala:272:28]
reg count_6; // @[ToAXI4.scala:272:28]
reg count_5; // @[ToAXI4.scala:272:28]
reg count_4; // @[ToAXI4.scala:272:28]
reg count_3; // @[ToAXI4.scala:272:28]
reg count_2; // @[ToAXI4.scala:272:28]
reg count_1; // @[ToAXI4.scala:272:28]
reg count; // @[ToAXI4.scala:272:28]
wire _queue_arw_deq_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _queue_arw_deq_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [5:0] _queue_arw_deq_q_io_deq_bits_id; // @[Decoupled.scala:362:21]
wire [31:0] _queue_arw_deq_q_io_deq_bits_addr; // @[Decoupled.scala:362:21]
wire [7:0] _queue_arw_deq_q_io_deq_bits_len; // @[Decoupled.scala:362:21]
wire [2:0] _queue_arw_deq_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [1:0] _queue_arw_deq_q_io_deq_bits_burst; // @[Decoupled.scala:362:21]
wire _queue_arw_deq_q_io_deq_bits_lock; // @[Decoupled.scala:362:21]
wire [3:0] _queue_arw_deq_q_io_deq_bits_cache; // @[Decoupled.scala:362:21]
wire [2:0] _queue_arw_deq_q_io_deq_bits_prot; // @[Decoupled.scala:362:21]
wire [3:0] _queue_arw_deq_q_io_deq_bits_qos; // @[Decoupled.scala:362:21]
wire [3:0] _queue_arw_deq_q_io_deq_bits_echo_tl_state_size; // @[Decoupled.scala:362:21]
wire [5:0] _queue_arw_deq_q_io_deq_bits_echo_tl_state_source; // @[Decoupled.scala:362:21]
wire _queue_arw_deq_q_io_deq_bits_wen; // @[Decoupled.scala:362:21]
wire _nodeOut_w_deq_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire [63:0][5:0] _GEN = '{6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h0, 6'h39, 6'h38, 6'h37, 6'h36, 6'h35, 6'h34, 6'h33, 6'h32, 6'h31, 6'h30, 6'h2F, 6'h2E, 6'h2D, 6'h2C, 6'h2B, 6'h2A, 6'h29, 6'h28, 6'h27, 6'h26, 6'h25, 6'h24, 6'h23, 6'h22, 6'h21, 6'h20, 6'h1F, 6'h1E, 6'h1D, 6'h1C, 6'h1B, 6'h1A, 6'h19, 6'h18, 6'h17, 6'h16, 6'h15, 6'h14, 6'h13, 6'h12, 6'h11, 6'h10, 6'hF, 6'hE, 6'hD, 6'hC, 6'hB, 6'hA, 6'h9, 6'h8, 6'h7, 6'h6, 6'h5, 6'h4, 6'h3, 6'h2, 6'h1, 6'h0};
wire [12:0] _r_beats1_decode_T = 13'h3F << auto_in_a_bits_size; // @[package.scala:243:71]
wire [2:0] r_beats1 = auto_in_a_bits_opcode[2] ? 3'h0 : ~(_r_beats1_decode_T[5:3]); // @[package.scala:243:{46,71,76}]
reg [2:0] r_counter; // @[Edges.scala:229:27]
wire a_first = r_counter == 3'h0; // @[ToAXI4.scala:103:9]
wire a_last = r_counter == 3'h1 | r_beats1 == 3'h0; // @[ToAXI4.scala:103:9]
reg doneAW; // @[ToAXI4.scala:167:30]
wire [17:0] _out_arw_bits_len_T = 18'h7FF << auto_in_a_bits_size; // @[package.scala:243:71]
wire [63:0] _GEN_0 = {{count}, {count}, {count}, {count}, {count}, {count}, {count_57}, {count_56}, {count_55}, {count_54}, {count_53}, {count_52}, {count_51}, {count_50}, {count_49}, {count_48}, {count_47}, {count_46}, {count_45}, {count_44}, {count_43}, {count_42}, {count_41}, {count_40}, {count_39}, {count_38}, {count_37}, {count_36}, {count_35}, {count_34}, {count_33}, {count_32}, {count_31}, {count_30}, {count_29}, {count_28}, {count_27}, {count_26}, {count_25}, {count_24}, {count_23}, {count_22}, {count_21}, {count_20}, {count_19}, {count_18}, {count_17}, {count_16}, {count_15}, {count_14}, {count_13}, {count_12}, {count_11}, {count_10}, {count_9}, {count_8}, {count_7}, {count_6}, {count_5}, {count_4}, {count_3}, {count_2}, {count_1}, {count}}; // @[ToAXI4.scala:205:49, :272:28]
wire stall = _GEN_0[auto_in_a_bits_source] & a_first; // @[ToAXI4.scala:205:49]
wire _out_w_valid_T_3 = doneAW | _queue_arw_deq_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready = ~stall & (auto_in_a_bits_opcode[2] ? _queue_arw_deq_q_io_enq_ready : _out_w_valid_T_3 & _nodeOut_w_deq_q_io_enq_ready); // @[Decoupled.scala:362:21]
wire out_arw_valid = ~stall & auto_in_a_valid & (auto_in_a_bits_opcode[2] | ~doneAW & _nodeOut_w_deq_q_io_enq_ready); // @[Decoupled.scala:362:21]
reg r_holds_d; // @[ToAXI4.scala:216:30]
reg [2:0] b_delay; // @[ToAXI4.scala:219:24]
wire r_wins = auto_out_r_valid & b_delay != 3'h7 | r_holds_d; // @[ToAXI4.scala:216:30, :219:24, :225:{33,44,53}]
wire nodeOut_r_ready = auto_in_d_ready & r_wins; // @[ToAXI4.scala:225:53, :227:33]
wire nodeOut_b_ready = auto_in_d_ready & ~r_wins; // @[ToAXI4.scala:225:53, :228:{33,36}]
wire nodeIn_d_valid = r_wins ? auto_out_r_valid : auto_out_b_valid; // @[ToAXI4.scala:225:53, :229:24]
reg r_first; // @[ToAXI4.scala:234:28]
reg r_denied_r; // @[package.scala:88:63]
wire r_denied = r_first ? (&auto_out_r_bits_resp) : r_denied_r; // @[package.scala:88:{42,63}]
wire [2:0] nodeIn_d_bits_opcode = {2'h0, r_wins}; // @[ToAXI4.scala:103:9, :225:53, :255:23]
wire [2:0] nodeIn_d_bits_size = r_wins ? auto_out_r_bits_echo_tl_state_size[2:0] : auto_out_b_bits_echo_tl_state_size[2:0]; // @[ToAXI4.scala:225:53, :255:23]
wire [5:0] nodeIn_d_bits_source = r_wins ? auto_out_r_bits_echo_tl_state_source : auto_out_b_bits_echo_tl_state_source; // @[ToAXI4.scala:225:53, :255:23]
wire nodeIn_d_bits_denied = r_wins ? r_denied : (|auto_out_b_bits_resp); // @[package.scala:88:42]
wire nodeIn_d_bits_corrupt = r_wins & ((|auto_out_r_bits_resp) | r_denied); // @[package.scala:88:42]
wire [5:0] d_sel_shiftAmount = r_wins ? auto_out_r_bits_id : auto_out_b_bits_id; // @[ToAXI4.scala:225:53, :261:31]
wire d_last = ~r_wins | auto_out_r_bits_last; // @[ToAXI4.scala:225:53, :262:23]
wire _inc_T_57 = _queue_arw_deq_q_io_enq_ready & out_arw_valid; // @[Decoupled.scala:51:35, :362:21]
wire inc = _GEN[auto_in_a_bits_source] == 6'h0 & _inc_T_57; // @[OneHot.scala:65:27]
wire _dec_T_115 = auto_in_d_ready & nodeIn_d_valid; // @[Decoupled.scala:51:35]
wire dec = d_sel_shiftAmount == 6'h0 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_1 = _GEN[auto_in_a_bits_source] == 6'h1 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_1 = d_sel_shiftAmount == 6'h1 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_2 = _GEN[auto_in_a_bits_source] == 6'h2 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_2 = d_sel_shiftAmount == 6'h2 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_3 = _GEN[auto_in_a_bits_source] == 6'h3 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_3 = d_sel_shiftAmount == 6'h3 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_4 = _GEN[auto_in_a_bits_source] == 6'h4 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_4 = d_sel_shiftAmount == 6'h4 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_5 = _GEN[auto_in_a_bits_source] == 6'h5 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_5 = d_sel_shiftAmount == 6'h5 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_6 = _GEN[auto_in_a_bits_source] == 6'h6 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_6 = d_sel_shiftAmount == 6'h6 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_7 = _GEN[auto_in_a_bits_source] == 6'h7 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_7 = d_sel_shiftAmount == 6'h7 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_8 = _GEN[auto_in_a_bits_source] == 6'h8 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_8 = d_sel_shiftAmount == 6'h8 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_9 = _GEN[auto_in_a_bits_source] == 6'h9 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_9 = d_sel_shiftAmount == 6'h9 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_10 = _GEN[auto_in_a_bits_source] == 6'hA & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_10 = d_sel_shiftAmount == 6'hA & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_11 = _GEN[auto_in_a_bits_source] == 6'hB & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_11 = d_sel_shiftAmount == 6'hB & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_12 = _GEN[auto_in_a_bits_source] == 6'hC & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_12 = d_sel_shiftAmount == 6'hC & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_13 = _GEN[auto_in_a_bits_source] == 6'hD & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_13 = d_sel_shiftAmount == 6'hD & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_14 = _GEN[auto_in_a_bits_source] == 6'hE & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_14 = d_sel_shiftAmount == 6'hE & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_15 = _GEN[auto_in_a_bits_source] == 6'hF & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_15 = d_sel_shiftAmount == 6'hF & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_16 = _GEN[auto_in_a_bits_source] == 6'h10 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_16 = d_sel_shiftAmount == 6'h10 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_17 = _GEN[auto_in_a_bits_source] == 6'h11 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_17 = d_sel_shiftAmount == 6'h11 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_18 = _GEN[auto_in_a_bits_source] == 6'h12 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_18 = d_sel_shiftAmount == 6'h12 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_19 = _GEN[auto_in_a_bits_source] == 6'h13 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_19 = d_sel_shiftAmount == 6'h13 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_20 = _GEN[auto_in_a_bits_source] == 6'h14 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_20 = d_sel_shiftAmount == 6'h14 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_21 = _GEN[auto_in_a_bits_source] == 6'h15 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_21 = d_sel_shiftAmount == 6'h15 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_22 = _GEN[auto_in_a_bits_source] == 6'h16 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_22 = d_sel_shiftAmount == 6'h16 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_23 = _GEN[auto_in_a_bits_source] == 6'h17 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_23 = d_sel_shiftAmount == 6'h17 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_24 = _GEN[auto_in_a_bits_source] == 6'h18 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_24 = d_sel_shiftAmount == 6'h18 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_25 = _GEN[auto_in_a_bits_source] == 6'h19 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_25 = d_sel_shiftAmount == 6'h19 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_26 = _GEN[auto_in_a_bits_source] == 6'h1A & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_26 = d_sel_shiftAmount == 6'h1A & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_27 = _GEN[auto_in_a_bits_source] == 6'h1B & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_27 = d_sel_shiftAmount == 6'h1B & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_28 = _GEN[auto_in_a_bits_source] == 6'h1C & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_28 = d_sel_shiftAmount == 6'h1C & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_29 = _GEN[auto_in_a_bits_source] == 6'h1D & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_29 = d_sel_shiftAmount == 6'h1D & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_30 = _GEN[auto_in_a_bits_source] == 6'h1E & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_30 = d_sel_shiftAmount == 6'h1E & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_31 = _GEN[auto_in_a_bits_source] == 6'h1F & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_31 = d_sel_shiftAmount == 6'h1F & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_32 = _GEN[auto_in_a_bits_source] == 6'h20 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_32 = d_sel_shiftAmount == 6'h20 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_33 = _GEN[auto_in_a_bits_source] == 6'h21 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_33 = d_sel_shiftAmount == 6'h21 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_34 = _GEN[auto_in_a_bits_source] == 6'h22 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_34 = d_sel_shiftAmount == 6'h22 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_35 = _GEN[auto_in_a_bits_source] == 6'h23 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_35 = d_sel_shiftAmount == 6'h23 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_36 = _GEN[auto_in_a_bits_source] == 6'h24 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_36 = d_sel_shiftAmount == 6'h24 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_37 = _GEN[auto_in_a_bits_source] == 6'h25 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_37 = d_sel_shiftAmount == 6'h25 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_38 = _GEN[auto_in_a_bits_source] == 6'h26 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_38 = d_sel_shiftAmount == 6'h26 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_39 = _GEN[auto_in_a_bits_source] == 6'h27 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_39 = d_sel_shiftAmount == 6'h27 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_40 = _GEN[auto_in_a_bits_source] == 6'h28 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_40 = d_sel_shiftAmount == 6'h28 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_41 = _GEN[auto_in_a_bits_source] == 6'h29 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_41 = d_sel_shiftAmount == 6'h29 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_42 = _GEN[auto_in_a_bits_source] == 6'h2A & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_42 = d_sel_shiftAmount == 6'h2A & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_43 = _GEN[auto_in_a_bits_source] == 6'h2B & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_43 = d_sel_shiftAmount == 6'h2B & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_44 = _GEN[auto_in_a_bits_source] == 6'h2C & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_44 = d_sel_shiftAmount == 6'h2C & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_45 = _GEN[auto_in_a_bits_source] == 6'h2D & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_45 = d_sel_shiftAmount == 6'h2D & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_46 = _GEN[auto_in_a_bits_source] == 6'h2E & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_46 = d_sel_shiftAmount == 6'h2E & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_47 = _GEN[auto_in_a_bits_source] == 6'h2F & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_47 = d_sel_shiftAmount == 6'h2F & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_48 = _GEN[auto_in_a_bits_source] == 6'h30 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_48 = d_sel_shiftAmount == 6'h30 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_49 = _GEN[auto_in_a_bits_source] == 6'h31 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_49 = d_sel_shiftAmount == 6'h31 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_50 = _GEN[auto_in_a_bits_source] == 6'h32 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_50 = d_sel_shiftAmount == 6'h32 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_51 = _GEN[auto_in_a_bits_source] == 6'h33 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_51 = d_sel_shiftAmount == 6'h33 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_52 = _GEN[auto_in_a_bits_source] == 6'h34 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_52 = d_sel_shiftAmount == 6'h34 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_53 = _GEN[auto_in_a_bits_source] == 6'h35 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_53 = d_sel_shiftAmount == 6'h35 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_54 = _GEN[auto_in_a_bits_source] == 6'h36 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_54 = d_sel_shiftAmount == 6'h36 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_55 = _GEN[auto_in_a_bits_source] == 6'h37 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_55 = d_sel_shiftAmount == 6'h37 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_56 = _GEN[auto_in_a_bits_source] == 6'h38 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_56 = d_sel_shiftAmount == 6'h38 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
wire inc_57 = _GEN[auto_in_a_bits_source] == 6'h39 & _inc_T_57; // @[OneHot.scala:65:27]
wire dec_57 = d_sel_shiftAmount == 6'h39 & d_last & _dec_T_115; // @[OneHot.scala:65:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File IngressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
class IngressUnit(
ingressNodeId: Int,
cParam: IngressChannelParams,
outParams: Seq[ChannelParams],
egressParams: Seq[EgressChannelParams],
combineRCVA: Boolean,
combineSAST: Boolean,
)
(implicit p: Parameters) extends AbstractInputUnit(cParam, outParams, egressParams)(p) {
class IngressUnitIO extends AbstractInputUnitIO(cParam, outParams, egressParams) {
val in = Flipped(Decoupled(new IngressFlit(cParam.payloadBits)))
}
val io = IO(new IngressUnitIO)
val route_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val route_q = Module(new Queue(new RouteComputerResp(outParams, egressParams), 2,
flow=combineRCVA))
assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))
route_buffer.io.enq.bits.head := io.in.bits.head
route_buffer.io.enq.bits.tail := io.in.bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
route_buffer.io.enq.bits.flow := DontCare
} else {
route_buffer.io.enq.bits.flow.ingress_node := cParam.destId.U
route_buffer.io.enq.bits.flow.ingress_node_id := ingressNodeId.U
route_buffer.io.enq.bits.flow.vnet_id := cParam.vNetId.U
route_buffer.io.enq.bits.flow.egress_node := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNode.U)
)
route_buffer.io.enq.bits.flow.egress_node_id := Mux1H(
flows.map(_.egressId.U === io.in.bits.egress_id),
flows.map(_.egressNodeId.U)
)
}
route_buffer.io.enq.bits.payload := io.in.bits.payload
route_buffer.io.enq.bits.virt_channel_id := DontCare
io.router_req.bits.src_virt_id := 0.U
io.router_req.bits.flow := route_buffer.io.enq.bits.flow
val at_dest = route_buffer.io.enq.bits.flow.egress_node === nodeId.U
route_buffer.io.enq.valid := io.in.valid && (
io.router_req.ready || !io.in.bits.head || at_dest)
io.router_req.valid := io.in.valid && route_buffer.io.enq.ready && io.in.bits.head && !at_dest
io.in.ready := route_buffer.io.enq.ready && (
io.router_req.ready || !io.in.bits.head || at_dest)
route_q.io.enq.valid := io.router_req.fire
route_q.io.enq.bits := io.router_resp
when (io.in.fire && io.in.bits.head && at_dest) {
route_q.io.enq.valid := true.B
route_q.io.enq.bits.vc_sel.foreach(_.foreach(_ := false.B))
for (o <- 0 until nEgress) {
when (egressParams(o).egressId.U === io.in.bits.egress_id) {
route_q.io.enq.bits.vc_sel(o+nOutputs)(0) := true.B
}
}
}
assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))
val vcalloc_buffer = Module(new Queue(new Flit(cParam.payloadBits), 2))
val vcalloc_q = Module(new Queue(new VCAllocResp(outParams, egressParams),
1, pipe=true))
vcalloc_buffer.io.enq.bits := route_buffer.io.deq.bits
io.vcalloc_req.bits.vc_sel := route_q.io.deq.bits.vc_sel
io.vcalloc_req.bits.flow := route_buffer.io.deq.bits.flow
io.vcalloc_req.bits.in_vc := 0.U
val head = route_buffer.io.deq.bits.head
val tail = route_buffer.io.deq.bits.tail
vcalloc_buffer.io.enq.valid := (route_buffer.io.deq.valid &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head)
)
io.vcalloc_req.valid := (route_buffer.io.deq.valid && route_q.io.deq.valid &&
head && vcalloc_buffer.io.enq.ready && vcalloc_q.io.enq.ready)
route_buffer.io.deq.ready := (vcalloc_buffer.io.enq.ready &&
(route_q.io.deq.valid || !head) &&
(io.vcalloc_req.ready || !head) &&
(vcalloc_q.io.enq.ready || !head))
route_q.io.deq.ready := (route_buffer.io.deq.fire && tail)
vcalloc_q.io.enq.valid := io.vcalloc_req.fire
vcalloc_q.io.enq.bits := io.vcalloc_resp
assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))
io.salloc_req(0).bits.vc_sel := vcalloc_q.io.deq.bits.vc_sel
io.salloc_req(0).bits.tail := vcalloc_buffer.io.deq.bits.tail
val c = (vcalloc_q.io.deq.bits.vc_sel.asUInt & io.out_credit_available.asUInt) =/= 0.U
val vcalloc_tail = vcalloc_buffer.io.deq.bits.tail
io.salloc_req(0).valid := vcalloc_buffer.io.deq.valid && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_buffer.io.deq.ready := io.salloc_req(0).ready && vcalloc_q.io.deq.valid && c && !io.block
vcalloc_q.io.deq.ready := vcalloc_tail && vcalloc_buffer.io.deq.fire
val out_bundle = if (combineSAST) {
Wire(Valid(new SwitchBundle(outParams, egressParams)))
} else {
Reg(Valid(new SwitchBundle(outParams, egressParams)))
}
io.out(0) := out_bundle
out_bundle.valid := vcalloc_buffer.io.deq.fire
out_bundle.bits.flit := vcalloc_buffer.io.deq.bits
out_bundle.bits.flit.virt_channel_id := 0.U
val out_channel_oh = vcalloc_q.io.deq.bits.vc_sel.map(_.reduce(_||_)).toSeq
out_bundle.bits.out_virt_channel := Mux1H(out_channel_oh,
vcalloc_q.io.deq.bits.vc_sel.map(v => OHToUInt(v)).toSeq)
io.debug.va_stall := io.vcalloc_req.valid && !io.vcalloc_req.ready
io.debug.sa_stall := io.salloc_req(0).valid && !io.salloc_req(0).ready
// TODO: We should not generate input/ingress/output/egress units for untraversable channels
if (!cParam.traversable) {
io.in.ready := false.B
io.router_req.valid := false.B
io.router_req.bits := DontCare
io.vcalloc_req.valid := false.B
io.vcalloc_req.bits := DontCare
io.salloc_req.foreach(_.valid := false.B)
io.salloc_req.foreach(_.bits := DontCare)
io.out.foreach(_.valid := false.B)
io.out.foreach(_.bits := DontCare)
}
}
|
module IngressUnit_1( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_3, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_4, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_5, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_6, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_7, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_8, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_9, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_3, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_5, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_6, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_7, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_9, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_3, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_4, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_5, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_6, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_7, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_8, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_9, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [72:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [72:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_3; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_4; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_5; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_6; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_7; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_8; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_9; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_head; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire [72:0] _vcalloc_buffer_io_deq_bits_payload; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:75:30]
wire [3:0] _vcalloc_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:75:30]
wire [2:0] _vcalloc_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [72:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'hE; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h11; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h17; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_WIRE = {_route_buffer_io_enq_bits_flow_egress_node_id_T_7, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0) | {3{_route_buffer_io_enq_bits_flow_egress_node_id_T_6}}}; // @[Mux.scala:30:73]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & ~(|_route_buffer_io_enq_bits_flow_egress_node_WIRE); // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & (|_route_buffer_io_enq_bits_flow_egress_node_WIRE); // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35]
|
Generate the Verilog code corresponding to the following Chisel files.
File TLChannelCompactor.scala:
package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)
|
module TLEFromBeat_SerialRAM_a64d64s8k8z8c( // @[TLChannelCompactor.scala:140:7]
input clock, // @[TLChannelCompactor.scala:140:7]
input reset, // @[TLChannelCompactor.scala:140:7]
output io_protocol_valid, // @[TLChannelCompactor.scala:75:14]
output [7:0] io_protocol_bits_sink, // @[TLChannelCompactor.scala:75:14]
output io_beat_ready, // @[TLChannelCompactor.scala:75:14]
input io_beat_valid, // @[TLChannelCompactor.scala:75:14]
input [7:0] io_beat_bits_payload, // @[TLChannelCompactor.scala:75:14]
input io_beat_bits_head, // @[TLChannelCompactor.scala:75:14]
input io_beat_bits_tail // @[TLChannelCompactor.scala:75:14]
);
wire io_beat_valid_0 = io_beat_valid; // @[TLChannelCompactor.scala:140:7]
wire [7:0] io_beat_bits_payload_0 = io_beat_bits_payload; // @[TLChannelCompactor.scala:140:7]
wire io_beat_bits_head_0 = io_beat_bits_head; // @[TLChannelCompactor.scala:140:7]
wire io_beat_bits_tail_0 = io_beat_bits_tail; // @[TLChannelCompactor.scala:140:7]
wire io_protocol_ready = 1'h0; // @[TLChannelCompactor.scala:140:7]
wire protocol_ready = 1'h0; // @[TLChannelCompactor.scala:83:22]
wire protocol_valid; // @[TLChannelCompactor.scala:83:22]
wire [7:0] protocol_bits_sink; // @[TLChannelCompactor.scala:83:22]
wire _io_beat_ready_T_2; // @[TLChannelCompactor.scala:91:53]
wire [7:0] io_protocol_bits_sink_0; // @[TLChannelCompactor.scala:140:7]
wire io_protocol_valid_0; // @[TLChannelCompactor.scala:140:7]
wire io_beat_ready_0; // @[TLChannelCompactor.scala:140:7]
wire _protocol_valid_T_2; // @[TLChannelCompactor.scala:92:54]
assign io_protocol_valid_0 = protocol_valid; // @[TLChannelCompactor.scala:83:22, :140:7]
wire [7:0] _protocol_bits_sink_WIRE; // @[TLChannelCompactor.scala:97:22]
assign io_protocol_bits_sink_0 = protocol_bits_sink; // @[TLChannelCompactor.scala:83:22, :140:7]
reg is_const; // @[TLChannelCompactor.scala:88:25]
reg [7:0] const_reg; // @[TLChannelCompactor.scala:89:22]
wire [7:0] const_0 = io_beat_bits_head_0 ? io_beat_bits_payload_0 : const_reg; // @[TLChannelCompactor.scala:89:22, :90:18, :140:7]
assign _protocol_bits_sink_WIRE = const_0; // @[TLChannelCompactor.scala:90:18, :97:22]
wire _io_beat_ready_T = ~io_beat_bits_tail_0; // @[TLChannelCompactor.scala:91:33, :140:7]
wire _io_beat_ready_T_1 = is_const & _io_beat_ready_T; // @[TLChannelCompactor.scala:88:25, :91:{30,33}]
assign _io_beat_ready_T_2 = _io_beat_ready_T_1; // @[TLChannelCompactor.scala:91:{30,53}]
assign io_beat_ready_0 = _io_beat_ready_T_2; // @[TLChannelCompactor.scala:91:53, :140:7]
wire _protocol_valid_T = ~is_const; // @[TLChannelCompactor.scala:88:25, :92:22]
wire _protocol_valid_T_1 = _protocol_valid_T | io_beat_bits_tail_0; // @[TLChannelCompactor.scala:92:{22,32}, :140:7]
assign _protocol_valid_T_2 = _protocol_valid_T_1 & io_beat_valid_0; // @[TLChannelCompactor.scala:92:{32,54}, :140:7]
assign protocol_valid = _protocol_valid_T_2; // @[TLChannelCompactor.scala:83:22, :92:54]
assign protocol_bits_sink = _protocol_bits_sink_WIRE; // @[TLChannelCompactor.scala:83:22, :97:22]
wire _T_3 = io_beat_ready_0 & io_beat_valid_0; // @[Decoupled.scala:51:35]
wire _T_2 = _T_3 & io_beat_bits_head_0; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TLChannelCompactor.scala:140:7]
if (reset) // @[TLChannelCompactor.scala:140:7]
is_const <= 1'h1; // @[TLChannelCompactor.scala:88:25]
else // @[TLChannelCompactor.scala:140:7]
is_const <= _T_3 & io_beat_bits_tail_0 | ~_T_2 & is_const; // @[Decoupled.scala:51:35]
if (_T_2) // @[TLChannelCompactor.scala:104:22]
const_reg <= io_beat_bits_payload_0; // @[TLChannelCompactor.scala:89:22, :140:7]
always @(posedge)
assign io_protocol_valid = io_protocol_valid_0; // @[TLChannelCompactor.scala:140:7]
assign io_protocol_bits_sink = io_protocol_bits_sink_0; // @[TLChannelCompactor.scala:140:7]
assign io_beat_ready = io_beat_ready_0; // @[TLChannelCompactor.scala:140:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File functional-unit.scala:
//******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Functional Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// If regfile bypassing is disabled, then the functional unit must do its own
// bypassing in here on the WB stage (i.e., bypassing the io.resp.data)
//
// TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass?
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import freechips.rocketchip.tile
import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}
import boom.v3.common._
import boom.v3.ifu._
import boom.v3.util._
/**t
* Functional unit constants
*/
object FUConstants
{
// bit mask, since a given execution pipeline may support multiple functional units
val FUC_SZ = 10
val FU_X = BitPat.dontCare(FUC_SZ)
val FU_ALU = 1.U(FUC_SZ.W)
val FU_JMP = 2.U(FUC_SZ.W)
val FU_MEM = 4.U(FUC_SZ.W)
val FU_MUL = 8.U(FUC_SZ.W)
val FU_DIV = 16.U(FUC_SZ.W)
val FU_CSR = 32.U(FUC_SZ.W)
val FU_FPU = 64.U(FUC_SZ.W)
val FU_FDV = 128.U(FUC_SZ.W)
val FU_I2F = 256.U(FUC_SZ.W)
val FU_F2I = 512.U(FUC_SZ.W)
// FP stores generate data through FP F2I, and generate address through MemAddrCalc
val FU_F2IMEM = 516.U(FUC_SZ.W)
}
import FUConstants._
/**
* Class to tell the FUDecoders what units it needs to support
*
* @param alu support alu unit?
* @param bru support br unit?
* @param mem support mem unit?
* @param muld support multiple div unit?
* @param fpu support FP unit?
* @param csr support csr writing unit?
* @param fdiv support FP div unit?
* @param ifpu support int to FP unit?
*/
class SupportedFuncUnits(
val alu: Boolean = false,
val jmp: Boolean = false,
val mem: Boolean = false,
val muld: Boolean = false,
val fpu: Boolean = false,
val csr: Boolean = false,
val fdiv: Boolean = false,
val ifpu: Boolean = false)
{
}
/**
* Bundle for signals sent to the functional unit
*
* @param dataWidth width of the data sent to the functional unit
*/
class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val numOperands = 3
val rs1_data = UInt(dataWidth.W)
val rs2_data = UInt(dataWidth.W)
val rs3_data = UInt(dataWidth.W) // only used for FMA units
val pred_data = Bool()
val kill = Bool() // kill everything
}
/**
* Bundle for the signals sent out of the function unit
*
* @param dataWidth data sent from the functional unit
*/
class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val predicated = Bool() // Was this response from a predicated-off instruction
val data = UInt(dataWidth.W)
val fflags = new ValidIO(new FFlagsResp)
val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU
val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU
val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc
}
/**
* Branch resolution information given from the branch unit
*/
class BrResolutionInfo(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp
val valid = Bool()
val mispredict = Bool()
val taken = Bool() // which direction did the branch go?
val cfi_type = UInt(CFI_SZ.W)
// Info for recalculating the pc for this branch
val pc_sel = UInt(2.W)
val jalr_target = UInt(vaddrBitsExtended.W)
val target_offset = SInt()
}
class BrUpdateInfo(implicit p: Parameters) extends BoomBundle
{
// On the first cycle we get masks to kill registers
val b1 = new BrUpdateMasks
// On the second cycle we get indices to reset pointers
val b2 = new BrResolutionInfo
}
class BrUpdateMasks(implicit p: Parameters) extends BoomBundle
{
val resolve_mask = UInt(maxBrCount.W)
val mispredict_mask = UInt(maxBrCount.W)
}
/**
* Abstract top level functional unit class that wraps a lower level hand made functional unit
*
* @param isPipelined is the functional unit pipelined?
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class FunctionalUnit(
val isPipelined: Boolean,
val numStages: Int,
val numBypassStages: Int,
val dataWidth: Int,
val isJmpUnit: Boolean = false,
val isAluUnit: Boolean = false,
val isMemAddrCalcUnit: Boolean = false,
val needsFcsr: Boolean = false)
(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))
val resp = (new DecoupledIO(new FuncUnitResp(dataWidth)))
val brupdate = Input(new BrUpdateInfo())
val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))
// only used by the fpu unit
val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null
// only used by branch unit
val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null
val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null
val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null
// only used by memaddr calc unit
val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null
val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null
val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null
})
io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare }
io.resp.valid := false.B
io.resp.bits := DontCare
if (isJmpUnit) {
io.get_ftq_pc.ftq_idx := DontCare
}
}
/**
* Abstract top level pipelined functional unit
*
* Note: this helps track which uops get killed while in intermediate stages,
* but it is the job of the consumer to check for kills on the same cycle as consumption!!!
*
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param earliestBypassStage first stage that you can start bypassing from
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class PipelinedFunctionalUnit(
numStages: Int,
numBypassStages: Int,
earliestBypassStage: Int,
dataWidth: Int,
isJmpUnit: Boolean = false,
isAluUnit: Boolean = false,
isMemAddrCalcUnit: Boolean = false,
needsFcsr: Boolean = false
)(implicit p: Parameters) extends FunctionalUnit(
isPipelined = true,
numStages = numStages,
numBypassStages = numBypassStages,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit,
isAluUnit = isAluUnit,
isMemAddrCalcUnit = isMemAddrCalcUnit,
needsFcsr = needsFcsr)
{
// Pipelined functional unit is always ready.
io.req.ready := true.B
if (numStages > 0) {
val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_uops = Reg(Vec(numStages, new MicroOp()))
// handle incoming request
r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill
r_uops(0) := io.req.bits.uop
r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
// handle middle of the pipeline
for (i <- 1 until numStages) {
r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill
r_uops(i) := r_uops(i-1)
r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1))
if (numBypassStages > 0) {
io.bypass(i-1).bits.uop := r_uops(i-1)
}
}
// handle outgoing (branch could still kill it)
// consumer must also check for pipeline flushes (kills)
io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1))
io.resp.bits.predicated := false.B
io.resp.bits.uop := r_uops(numStages-1)
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1))
// bypassing (TODO allow bypass vector to have a different size from numStages)
if (numBypassStages > 0 && earliestBypassStage == 0) {
io.bypass(0).bits.uop := io.req.bits.uop
for (i <- 1 until numBypassStages) {
io.bypass(i).bits.uop := r_uops(i-1)
}
}
} else {
require (numStages == 0)
// pass req straight through to response
// valid doesn't check kill signals, let consumer deal with it.
// The LSU already handles it and this hurts critical path.
io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop)
io.resp.bits.predicated := false.B
io.resp.bits.uop := io.req.bits.uop
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
}
}
/**
* Functional unit that wraps RocketChips ALU
*
* @param isBranchUnit is this a branch unit?
* @param numStages how many pipeline stages does the functional unit have
* @param dataWidth width of the data being operated on in the functional unit
*/
class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = numStages,
isAluUnit = true,
earliestBypassStage = 0,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit)
with boom.v3.ifu.HasBoomFrontendParameters
{
val uop = io.req.bits.uop
// immediate generation
val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel)
// operand 1 select
var op1_data: UInt = null
if (isJmpUnit) {
// Get the uop PC for jumps
val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes)
val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U)
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen),
0.U))
} else {
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
0.U)
}
// operand 2 select
val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen),
Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0),
Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data,
Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U),
0.U))))
val alu = Module(new freechips.rocketchip.rocket.ALU())
alu.io.in1 := op1_data.asUInt
alu.io.in2 := op2_data.asUInt
alu.io.fn := uop.ctrl.op_fcn
alu.io.dw := uop.ctrl.fcn_dw
// Did I just get killed by the previous cycle's branch,
// or by a flush pipeline?
val killed = WireInit(false.B)
when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) {
killed := true.B
}
val rs1 = io.req.bits.rs1_data
val rs2 = io.req.bits.rs2_data
val br_eq = (rs1 === rs2)
val br_ltu = (rs1.asUInt < rs2.asUInt)
val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu |
rs1(xLen-1) & ~rs2(xLen-1)).asBool
val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)(
Seq( BR_N -> PC_PLUS4,
BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4),
BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4),
BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4),
BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4),
BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4),
BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4),
BR_J -> PC_BRJMP,
BR_JR -> PC_JALR
))
val is_taken = io.req.valid &&
!killed &&
(uop.is_br || uop.is_jalr || uop.is_jal) &&
(pc_sel =/= PC_PLUS4)
// "mispredict" means that a branch has been resolved and it must be killed
val mispredict = WireInit(false.B)
val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb
val is_jal = io.req.valid && !killed && uop.is_jal
val is_jalr = io.req.valid && !killed && uop.is_jalr
when (is_br || is_jalr) {
if (!isJmpUnit) {
assert (pc_sel =/= PC_JALR)
}
when (pc_sel === PC_PLUS4) {
mispredict := uop.taken
}
when (pc_sel === PC_BRJMP) {
mispredict := !uop.taken
}
}
val brinfo = Wire(new BrResolutionInfo)
// note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit
brinfo.valid := is_br || is_jalr
brinfo.mispredict := mispredict
brinfo.uop := uop
brinfo.cfi_type := Mux(is_jalr, CFI_JALR,
Mux(is_br , CFI_BR, CFI_X))
brinfo.taken := is_taken
brinfo.pc_sel := pc_sel
brinfo.jalr_target := DontCare
// Branch/Jump Target Calculation
// For jumps we read the FTQ, and can calculate the target
// For branches we emit the offset for the core to redirect if necessary
val target_offset = imm_xprlen(20,0).asSInt
brinfo.jalr_target := DontCare
if (isJmpUnit) {
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) {
ea
} else {
// Efficient means to compress 64-bit VA into vaddrBits+1 bits.
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).
val a = a0.asSInt >> vaddrBits
val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))
Cat(msb, ea(vaddrBits-1,0))
}
val jalr_target_base = io.req.bits.rs1_data.asSInt
val jalr_target_xlen = Wire(UInt(xLen.W))
jalr_target_xlen := (jalr_target_base + target_offset).asUInt
val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt
brinfo.jalr_target := jalr_target
val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1)
when (pc_sel === PC_JALR) {
mispredict := !io.get_ftq_pc.next_val ||
(io.get_ftq_pc.next_pc =/= jalr_target) ||
!io.get_ftq_pc.entry.cfi_idx.valid ||
(io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx)
}
}
brinfo.target_offset := target_offset
io.brinfo := brinfo
// Response
// TODO add clock gate on resp bits from functional units
// io.resp.bits.data := RegEnable(alu.io.out, io.req.valid)
// val reg_data = Reg(outType = Bits(width = xLen))
// reg_data := alu.io.out
// io.resp.bits.data := reg_data
val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_data = Reg(Vec(numStages, UInt(xLen.W)))
val r_pred = Reg(Vec(numStages, Bool()))
val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data,
Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data),
Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out))
r_val (0) := io.req.valid
r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data
for (i <- 1 until numStages) {
r_val(i) := r_val(i-1)
r_data(i) := r_data(i-1)
r_pred(i) := r_pred(i-1)
}
io.resp.bits.data := r_data(numStages-1)
io.resp.bits.predicated := r_pred(numStages-1)
// Bypass
// for the ALU, we can bypass same cycle as compute
require (numStages >= 1)
require (numBypassStages >= 1)
io.bypass(0).valid := io.req.valid
io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
for (i <- 1 until numStages) {
io.bypass(i).valid := r_val(i-1)
io.bypass(i).bits.data := r_data(i-1)
}
// Exceptions
io.resp.bits.fflags.valid := false.B
}
/**
* Functional unit that passes in base+imm to calculate addresses, and passes store data
* to the LSU.
* For floating point, 65bit FP store-data needs to be decoded into 64bit FP form
*/
class MemAddrCalcUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = 0,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65, // TODO enable this only if FP is enabled?
isMemAddrCalcUnit = true)
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
// perform address calculation
val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt
val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U,
sum(63,vaddrBits) =/= 0.U)
val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt
val store_data = io.req.bits.rs2_data
io.resp.bits.addr := effective_address
io.resp.bits.data := store_data
if (dataWidth > 63) {
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&
io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.")
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),
"FP store-data should now be going through a different unit.")
}
assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=
uopLD && io.req.bits.uop.uopc =/= uopSTA),
"[maddrcalc] assert we never get store data in here.")
// Handle misaligned exceptions
val size = io.req.bits.uop.mem_size
val misaligned =
(size === 1.U && (effective_address(0) =/= 0.U)) ||
(size === 2.U && (effective_address(1,0) =/= 0.U)) ||
(size === 3.U && (effective_address(2,0) =/= 0.U))
val bkptu = Module(new BreakpointUnit(nBreakpoints))
bkptu.io.status := io.status
bkptu.io.bp := io.bp
bkptu.io.pc := DontCare
bkptu.io.ea := effective_address
bkptu.io.mcontext := io.mcontext
bkptu.io.scontext := io.scontext
val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned
val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned
val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st))
val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st))
def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
val (xcpt_val, xcpt_cause) = checkExceptions(List(
(ma_ld, (Causes.misaligned_load).U),
(ma_st, (Causes.misaligned_store).U),
(dbg_bp, (CSR.debugTriggerCause).U),
(bp, (Causes.breakpoint).U)))
io.resp.bits.mxcpt.valid := xcpt_val
io.resp.bits.mxcpt.bits := xcpt_cause
assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.")
io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE
io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0)
io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1)
io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data
io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data
}
/**
* Functional unit to wrap lower level FPU
*
* Currently, bypassing is unsupported!
* All FP instructions are padded out to the max latency unit for easy
* write-port scheduling.
*/
class FPUUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = p(tile.TileKey).core.fpu.get.dfmaLatency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
{
val fpu = Module(new FPU())
fpu.io.req.valid := io.req.valid
fpu.io.req.bits.uop := io.req.bits.uop
fpu.io.req.bits.rs1_data := io.req.bits.rs1_data
fpu.io.req.bits.rs2_data := io.req.bits.rs2_data
fpu.io.req.bits.rs3_data := io.req.bits.rs3_data
fpu.io.req.bits.fcsr_rm := io.fcsr_rm
io.resp.bits.data := fpu.io.resp.bits.data
io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now
}
/**
* Int to FP conversion functional unit
*
* @param latency the amount of stages to delay by
*/
class IntToFPUnit(latency: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = latency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
with tile.HasFPUParameters
{
val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder
val io_req = io.req.bits
fp_decoder.io.uopc := io_req.uop.uopc
val fp_ctrl = fp_decoder.io.sigs
val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))
val req = Wire(new tile.FPInput)
val tag = fp_ctrl.typeTagIn
req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl
req.rm := fp_rm
req.in1 := unbox(io_req.rs1_data, tag, None)
req.in2 := unbox(io_req.rs2_data, tag, None)
req.in3 := DontCare
req.typ := ImmGenTyp(io_req.uop.imm_packed)
req.fmt := DontCare // FIXME: this may not be the right thing to do here
req.fmaCmd := DontCare
assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),
"[func] IntToFP integer input has 65th high-order bit set!")
assert (!(io.req.valid && !fp_ctrl.fromint),
"[func] Only support fromInt micro-ops.")
val ifpu = Module(new tile.IntToFP(intToFpLatency))
ifpu.io.in.valid := io.req.valid
ifpu.io.in.bits := req
ifpu.io.in.bits.in1 := io_req.rs1_data
val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits
//io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single)
io.resp.bits.data := box(ifpu.io.out.bits.data, out_double)
io.resp.bits.fflags.valid := ifpu.io.out.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc
}
/**
* Iterative/unpipelined functional unit, can only hold a single MicroOp at a time
* assumes at least one register between request and response
*
* TODO allow up to N micro-ops simultaneously.
*
* @param dataWidth width of the data to be passed into the functional unit
*/
abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters)
extends FunctionalUnit(
isPipelined = false,
numStages = 1,
numBypassStages = 0,
dataWidth = dataWidth)
{
val r_uop = Reg(new MicroOp())
val do_kill = Wire(Bool())
do_kill := io.req.bits.kill // irrelevant default
when (io.req.fire) {
// update incoming uop
do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill
r_uop := io.req.bits.uop
r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
} .otherwise {
do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill
r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop)
}
// assumes at least one pipeline register between request and response
io.resp.bits.uop := r_uop
}
/**
* Divide functional unit.
*
* @param dataWidth data to be passed into the functional unit
*/
class DivUnit(dataWidth: Int)(implicit p: Parameters)
extends IterativeFunctionalUnit(dataWidth)
{
// We don't use the iterative multiply functionality here.
// Instead we use the PipelinedMultiplier
val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth))
// request
div.io.req.valid := io.req.valid && !this.do_kill
div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
div.io.req.bits.in1 := io.req.bits.rs1_data
div.io.req.bits.in2 := io.req.bits.rs2_data
div.io.req.bits.tag := DontCare
io.req.ready := div.io.req.ready
// handle pipeline kills and branch misspeculations
div.io.kill := this.do_kill
// response
io.resp.valid := div.io.resp.valid && !this.do_kill
div.io.resp.ready := io.resp.ready
io.resp.bits.data := div.io.resp.bits.data
}
/**
* Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier
*
* @param numStages number of pipeline stages
* @param dataWidth size of the data being passed into the functional unit
*/
class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = dataWidth)
{
val imul = Module(new PipelinedMultiplier(xLen, numStages))
// request
imul.io.req.valid := io.req.valid
imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
imul.io.req.bits.in1 := io.req.bits.rs1_data
imul.io.req.bits.in2 := io.req.bits.rs2_data
imul.io.req.bits.tag := DontCare
// response
io.resp.bits.data := imul.io.resp.bits.data
}
|
module FPUUnit( // @[functional-unit.scala:564:7]
input clock, // @[functional-unit.scala:564:7]
input reset, // @[functional-unit.scala:564:7]
input io_req_valid, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
input [7:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_req_bits_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14]
input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14]
input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input [64:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14]
input [64:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14]
input [64:0] io_req_bits_rs3_data, // @[functional-unit.scala:168:14]
input io_req_bits_kill, // @[functional-unit.scala:168:14]
output io_resp_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [64:0] io_resp_bits_data, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_fflags_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_fflags_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_fflags_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_fflags_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_fflags_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [7:0] io_resp_bits_fflags_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_fflags_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_fflags_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_fflags_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_fflags_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_fflags_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_fflags_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_fflags_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_fflags_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_fflags_bits_flags, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_valid, // @[functional-unit.scala:168:14]
input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14]
input io_brupdate_b2_taken, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14]
input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14]
input [2:0] io_fcsr_rm // @[functional-unit.scala:168:14]
);
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:564:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:564:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7]
wire [4:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:564:7]
wire [7:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:564:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:564:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:564:7]
wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:564:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:564:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:564:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:564:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:564:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:564:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:564:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:564:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:564:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:564:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:564:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:564:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:564:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:564:7]
wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:564:7]
wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:564:7]
wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:564:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:564:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:564:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:564:7]
wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:564:7]
wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:564:7]
wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:564:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:564:7]
wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:564:7]
wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:564:7]
wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:564:7]
wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:564:7]
wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:564:7]
wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:564:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:564:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:564:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:564:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:564:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:564:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:564:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:564:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:564:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:564:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:564:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:564:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:564:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:564:7]
wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:564:7]
wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:564:7]
wire [64:0] io_req_bits_rs3_data_0 = io_req_bits_rs3_data; // @[functional-unit.scala:564:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:564:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:564:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:564:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:564:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:564:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:564:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:564:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:564:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:564:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:564:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:564:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:564:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:564:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:564:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:564:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:564:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:564:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:564:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:564:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:564:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:564:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:564:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:564:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:564:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:564:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:564:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:564:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:564:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:564:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:564:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:564:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:564:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:564:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:564:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:564:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:564:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:564:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:564:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:564:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:564:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:564:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:564:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:564:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:564:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:564:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:564:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:564:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:564:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:564:7]
wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[functional-unit.scala:564:7]
wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:564:7]
wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:564:7]
wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:564:7]
wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:564:7]
wire io_resp_ready = 1'h0; // @[functional-unit.scala:564:7]
wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:564:7]
wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:564:7]
wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:564:7]
wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:564:7]
wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:564:7]
wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:564:7]
wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:564:7]
wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:564:7]
wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35]
wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35]
wire _r_valids_WIRE_2 = 1'h0; // @[functional-unit.scala:236:35]
wire _r_valids_WIRE_3 = 1'h0; // @[functional-unit.scala:236:35]
wire io_req_ready = 1'h1; // @[functional-unit.scala:564:7]
wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47]
wire [6:0] io_resp_bits_fflags_bits_uop_uopc_0 = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:564:7]
wire [31:0] io_resp_bits_fflags_bits_uop_inst_0 = io_resp_bits_uop_inst_0; // @[functional-unit.scala:564:7]
wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst_0 = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_is_rvc_0 = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7]
wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc_0 = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_fflags_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:564:7]
wire [9:0] io_resp_bits_fflags_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:564:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type_0 = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0 = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0 = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0 = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0 = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0 = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0 = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_load_0 = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_sta_0 = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_std_0 = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_fflags_bits_uop_iw_state_0 = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0 = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0 = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_is_br_0 = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_is_jalr_0 = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_is_jal_0 = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_is_sfb_0 = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7]
wire [7:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [7:0] io_resp_bits_fflags_bits_uop_br_mask_0 = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_fflags_bits_uop_br_tag_0 = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:564:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ftq_idx_0 = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_edge_inst_0 = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob_0 = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_taken_0 = io_resp_bits_uop_taken_0; // @[functional-unit.scala:564:7]
wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed_0 = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7]
wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr_0 = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7]
wire [4:0] io_resp_bits_fflags_bits_uop_rob_idx_0 = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ldq_idx_0 = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7]
wire [2:0] io_resp_bits_fflags_bits_uop_stq_idx_0 = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx_0 = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pdst_0 = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs1_0 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs2_0 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_fflags_bits_uop_prs3_0 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:564:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ppred_0 = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_prs1_busy_0 = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_prs2_busy_0 = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_prs3_busy_0 = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_ppred_busy_0 = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_fflags_bits_uop_stale_pdst_0 = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_exception_0 = io_resp_bits_uop_exception_0; // @[functional-unit.scala:564:7]
wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause_0 = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_bypassable_0 = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:564:7]
wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd_0 = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_fflags_bits_uop_mem_size_0 = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_mem_signed_0 = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_is_fence_0 = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_is_fencei_0 = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_is_amo_0 = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_uses_ldq_0 = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_uses_stq_0 = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0 = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_is_unique_0 = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_flush_on_commit_0 = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_ldst_is_rs1_0 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_fflags_bits_uop_ldst_0 = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs1_0 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs2_0 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:564:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs3_0 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_ldst_val_0 = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype_0 = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype_0 = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype_0 = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_frs3_en_0 = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_fp_val_0 = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_fp_single_0 = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_xcpt_pf_if_0 = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ae_if_0 = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ma_if_0 = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_bp_debug_if_0 = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_bits_uop_bp_xcpt_if_0 = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc_0 = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc_0 = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7]
wire [4:0] io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:564:7]
wire io_resp_bits_fflags_valid_0; // @[functional-unit.scala:564:7]
wire [64:0] io_resp_bits_data_0; // @[functional-unit.scala:564:7]
wire io_resp_valid_0; // @[functional-unit.scala:564:7]
reg r_valids_0; // @[functional-unit.scala:236:27]
reg r_valids_1; // @[functional-unit.scala:236:27]
reg r_valids_2; // @[functional-unit.scala:236:27]
reg r_valids_3; // @[functional-unit.scala:236:27]
reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23]
reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23]
reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23]
reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23]
reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23]
reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23]
reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23]
reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23]
reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23]
reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23]
reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23]
reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23]
reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23]
reg r_uops_0_is_br; // @[functional-unit.scala:237:23]
reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23]
reg r_uops_0_is_jal; // @[functional-unit.scala:237:23]
reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23]
reg [7:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23]
reg [3:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23]
reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23]
reg r_uops_0_taken; // @[functional-unit.scala:237:23]
reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23]
reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23]
reg [4:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_0_pdst; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_0_prs1; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_0_prs2; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_0_prs3; // @[functional-unit.scala:237:23]
reg [3:0] r_uops_0_ppred; // @[functional-unit.scala:237:23]
reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23]
reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23]
reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23]
reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23]
reg r_uops_0_exception; // @[functional-unit.scala:237:23]
reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23]
reg r_uops_0_bypassable; // @[functional-unit.scala:237:23]
reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23]
reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23]
reg r_uops_0_is_fence; // @[functional-unit.scala:237:23]
reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23]
reg r_uops_0_is_amo; // @[functional-unit.scala:237:23]
reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23]
reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23]
reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23]
reg r_uops_0_is_unique; // @[functional-unit.scala:237:23]
reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23]
reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23]
reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23]
reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23]
reg r_uops_0_fp_val; // @[functional-unit.scala:237:23]
reg r_uops_0_fp_single; // @[functional-unit.scala:237:23]
reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23]
reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23]
reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23]
reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23]
reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23]
reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23]
reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23]
reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23]
reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23]
reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23]
reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23]
reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23]
reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23]
reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23]
reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23]
reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23]
reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23]
reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23]
reg r_uops_1_is_br; // @[functional-unit.scala:237:23]
reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23]
reg r_uops_1_is_jal; // @[functional-unit.scala:237:23]
reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23]
reg [7:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23]
reg [3:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23]
reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23]
reg r_uops_1_taken; // @[functional-unit.scala:237:23]
reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23]
reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23]
reg [4:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_1_pdst; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_1_prs1; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_1_prs2; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_1_prs3; // @[functional-unit.scala:237:23]
reg [3:0] r_uops_1_ppred; // @[functional-unit.scala:237:23]
reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23]
reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23]
reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23]
reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23]
reg r_uops_1_exception; // @[functional-unit.scala:237:23]
reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23]
reg r_uops_1_bypassable; // @[functional-unit.scala:237:23]
reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23]
reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23]
reg r_uops_1_is_fence; // @[functional-unit.scala:237:23]
reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23]
reg r_uops_1_is_amo; // @[functional-unit.scala:237:23]
reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23]
reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23]
reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23]
reg r_uops_1_is_unique; // @[functional-unit.scala:237:23]
reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23]
reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23]
reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23]
reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23]
reg r_uops_1_fp_val; // @[functional-unit.scala:237:23]
reg r_uops_1_fp_single; // @[functional-unit.scala:237:23]
reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23]
reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23]
reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23]
reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23]
reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23]
reg [6:0] r_uops_2_uopc; // @[functional-unit.scala:237:23]
reg [31:0] r_uops_2_inst; // @[functional-unit.scala:237:23]
reg [31:0] r_uops_2_debug_inst; // @[functional-unit.scala:237:23]
reg r_uops_2_is_rvc; // @[functional-unit.scala:237:23]
reg [39:0] r_uops_2_debug_pc; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_2_iq_type; // @[functional-unit.scala:237:23]
reg [9:0] r_uops_2_fu_code; // @[functional-unit.scala:237:23]
reg [3:0] r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23]
reg [4:0] r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23]
reg r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
reg r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23]
reg r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23]
reg r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_2_iw_state; // @[functional-unit.scala:237:23]
reg r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23]
reg r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23]
reg r_uops_2_is_br; // @[functional-unit.scala:237:23]
reg r_uops_2_is_jalr; // @[functional-unit.scala:237:23]
reg r_uops_2_is_jal; // @[functional-unit.scala:237:23]
reg r_uops_2_is_sfb; // @[functional-unit.scala:237:23]
reg [7:0] r_uops_2_br_mask; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_2_br_tag; // @[functional-unit.scala:237:23]
reg [3:0] r_uops_2_ftq_idx; // @[functional-unit.scala:237:23]
reg r_uops_2_edge_inst; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_2_pc_lob; // @[functional-unit.scala:237:23]
reg r_uops_2_taken; // @[functional-unit.scala:237:23]
reg [19:0] r_uops_2_imm_packed; // @[functional-unit.scala:237:23]
reg [11:0] r_uops_2_csr_addr; // @[functional-unit.scala:237:23]
reg [4:0] r_uops_2_rob_idx; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_2_ldq_idx; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_2_stq_idx; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_2_rxq_idx; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_2_pdst; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_2_prs1; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_2_prs2; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_2_prs3; // @[functional-unit.scala:237:23]
reg [3:0] r_uops_2_ppred; // @[functional-unit.scala:237:23]
reg r_uops_2_prs1_busy; // @[functional-unit.scala:237:23]
reg r_uops_2_prs2_busy; // @[functional-unit.scala:237:23]
reg r_uops_2_prs3_busy; // @[functional-unit.scala:237:23]
reg r_uops_2_ppred_busy; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_2_stale_pdst; // @[functional-unit.scala:237:23]
reg r_uops_2_exception; // @[functional-unit.scala:237:23]
reg [63:0] r_uops_2_exc_cause; // @[functional-unit.scala:237:23]
reg r_uops_2_bypassable; // @[functional-unit.scala:237:23]
reg [4:0] r_uops_2_mem_cmd; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_2_mem_size; // @[functional-unit.scala:237:23]
reg r_uops_2_mem_signed; // @[functional-unit.scala:237:23]
reg r_uops_2_is_fence; // @[functional-unit.scala:237:23]
reg r_uops_2_is_fencei; // @[functional-unit.scala:237:23]
reg r_uops_2_is_amo; // @[functional-unit.scala:237:23]
reg r_uops_2_uses_ldq; // @[functional-unit.scala:237:23]
reg r_uops_2_uses_stq; // @[functional-unit.scala:237:23]
reg r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23]
reg r_uops_2_is_unique; // @[functional-unit.scala:237:23]
reg r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23]
reg r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_2_ldst; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_2_lrs1; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_2_lrs2; // @[functional-unit.scala:237:23]
reg [5:0] r_uops_2_lrs3; // @[functional-unit.scala:237:23]
reg r_uops_2_ldst_val; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_2_dst_rtype; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23]
reg r_uops_2_frs3_en; // @[functional-unit.scala:237:23]
reg r_uops_2_fp_val; // @[functional-unit.scala:237:23]
reg r_uops_2_fp_single; // @[functional-unit.scala:237:23]
reg r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23]
reg r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23]
reg r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23]
reg r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23]
reg r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23]
reg [1:0] r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23]
reg [6:0] r_uops_3_uopc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_uopc_0 = r_uops_3_uopc; // @[functional-unit.scala:237:23, :564:7]
reg [31:0] r_uops_3_inst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_inst_0 = r_uops_3_inst; // @[functional-unit.scala:237:23, :564:7]
reg [31:0] r_uops_3_debug_inst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_inst_0 = r_uops_3_debug_inst; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_is_rvc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_rvc_0 = r_uops_3_is_rvc; // @[functional-unit.scala:237:23, :564:7]
reg [39:0] r_uops_3_debug_pc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_pc_0 = r_uops_3_debug_pc; // @[functional-unit.scala:237:23, :564:7]
reg [2:0] r_uops_3_iq_type; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iq_type_0 = r_uops_3_iq_type; // @[functional-unit.scala:237:23, :564:7]
reg [9:0] r_uops_3_fu_code; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_fu_code_0 = r_uops_3_fu_code; // @[functional-unit.scala:237:23, :564:7]
reg [3:0] r_uops_3_ctrl_br_type; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_3_ctrl_br_type; // @[functional-unit.scala:237:23, :564:7]
reg [1:0] r_uops_3_ctrl_op1_sel; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_3_ctrl_op1_sel; // @[functional-unit.scala:237:23, :564:7]
reg [2:0] r_uops_3_ctrl_op2_sel; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_3_ctrl_op2_sel; // @[functional-unit.scala:237:23, :564:7]
reg [2:0] r_uops_3_ctrl_imm_sel; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_3_ctrl_imm_sel; // @[functional-unit.scala:237:23, :564:7]
reg [4:0] r_uops_3_ctrl_op_fcn; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_3_ctrl_op_fcn; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_3_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :564:7]
reg [2:0] r_uops_3_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_3_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_ctrl_is_load; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_3_ctrl_is_load; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_ctrl_is_sta; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_3_ctrl_is_sta; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_ctrl_is_std; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_3_ctrl_is_std; // @[functional-unit.scala:237:23, :564:7]
reg [1:0] r_uops_3_iw_state; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iw_state_0 = r_uops_3_iw_state; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_iw_p1_poisoned; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_3_iw_p1_poisoned; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_iw_p2_poisoned; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_3_iw_p2_poisoned; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_is_br; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_br_0 = r_uops_3_is_br; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_is_jalr; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_jalr_0 = r_uops_3_is_jalr; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_is_jal; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_jal_0 = r_uops_3_is_jal; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_is_sfb; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_sfb_0 = r_uops_3_is_sfb; // @[functional-unit.scala:237:23, :564:7]
reg [7:0] r_uops_3_br_mask; // @[functional-unit.scala:237:23]
reg [2:0] r_uops_3_br_tag; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_br_tag_0 = r_uops_3_br_tag; // @[functional-unit.scala:237:23, :564:7]
reg [3:0] r_uops_3_ftq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ftq_idx_0 = r_uops_3_ftq_idx; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_edge_inst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_edge_inst_0 = r_uops_3_edge_inst; // @[functional-unit.scala:237:23, :564:7]
reg [5:0] r_uops_3_pc_lob; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_pc_lob_0 = r_uops_3_pc_lob; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_taken; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_taken_0 = r_uops_3_taken; // @[functional-unit.scala:237:23, :564:7]
reg [19:0] r_uops_3_imm_packed; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_imm_packed_0 = r_uops_3_imm_packed; // @[functional-unit.scala:237:23, :564:7]
reg [11:0] r_uops_3_csr_addr; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_csr_addr_0 = r_uops_3_csr_addr; // @[functional-unit.scala:237:23, :564:7]
reg [4:0] r_uops_3_rob_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_rob_idx_0 = r_uops_3_rob_idx; // @[functional-unit.scala:237:23, :564:7]
reg [2:0] r_uops_3_ldq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldq_idx_0 = r_uops_3_ldq_idx; // @[functional-unit.scala:237:23, :564:7]
reg [2:0] r_uops_3_stq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_stq_idx_0 = r_uops_3_stq_idx; // @[functional-unit.scala:237:23, :564:7]
reg [1:0] r_uops_3_rxq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_rxq_idx_0 = r_uops_3_rxq_idx; // @[functional-unit.scala:237:23, :564:7]
reg [5:0] r_uops_3_pdst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_pdst_0 = r_uops_3_pdst; // @[functional-unit.scala:237:23, :564:7]
reg [5:0] r_uops_3_prs1; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs1_0 = r_uops_3_prs1; // @[functional-unit.scala:237:23, :564:7]
reg [5:0] r_uops_3_prs2; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs2_0 = r_uops_3_prs2; // @[functional-unit.scala:237:23, :564:7]
reg [5:0] r_uops_3_prs3; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs3_0 = r_uops_3_prs3; // @[functional-unit.scala:237:23, :564:7]
reg [3:0] r_uops_3_ppred; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ppred_0 = r_uops_3_ppred; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_prs1_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs1_busy_0 = r_uops_3_prs1_busy; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_prs2_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs2_busy_0 = r_uops_3_prs2_busy; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_prs3_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs3_busy_0 = r_uops_3_prs3_busy; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_ppred_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ppred_busy_0 = r_uops_3_ppred_busy; // @[functional-unit.scala:237:23, :564:7]
reg [5:0] r_uops_3_stale_pdst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_stale_pdst_0 = r_uops_3_stale_pdst; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_exception; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_exception_0 = r_uops_3_exception; // @[functional-unit.scala:237:23, :564:7]
reg [63:0] r_uops_3_exc_cause; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_exc_cause_0 = r_uops_3_exc_cause; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_bypassable; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_bypassable_0 = r_uops_3_bypassable; // @[functional-unit.scala:237:23, :564:7]
reg [4:0] r_uops_3_mem_cmd; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_mem_cmd_0 = r_uops_3_mem_cmd; // @[functional-unit.scala:237:23, :564:7]
reg [1:0] r_uops_3_mem_size; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_mem_size_0 = r_uops_3_mem_size; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_mem_signed; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_mem_signed_0 = r_uops_3_mem_signed; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_is_fence; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_fence_0 = r_uops_3_is_fence; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_is_fencei; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_fencei_0 = r_uops_3_is_fencei; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_is_amo; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_amo_0 = r_uops_3_is_amo; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_uses_ldq; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_uses_ldq_0 = r_uops_3_uses_ldq; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_uses_stq; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_uses_stq_0 = r_uops_3_uses_stq; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_is_sys_pc2epc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_3_is_sys_pc2epc; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_is_unique; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_unique_0 = r_uops_3_is_unique; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_flush_on_commit; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_flush_on_commit_0 = r_uops_3_flush_on_commit; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_ldst_is_rs1; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_3_ldst_is_rs1; // @[functional-unit.scala:237:23, :564:7]
reg [5:0] r_uops_3_ldst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldst_0 = r_uops_3_ldst; // @[functional-unit.scala:237:23, :564:7]
reg [5:0] r_uops_3_lrs1; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs1_0 = r_uops_3_lrs1; // @[functional-unit.scala:237:23, :564:7]
reg [5:0] r_uops_3_lrs2; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs2_0 = r_uops_3_lrs2; // @[functional-unit.scala:237:23, :564:7]
reg [5:0] r_uops_3_lrs3; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs3_0 = r_uops_3_lrs3; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_ldst_val; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldst_val_0 = r_uops_3_ldst_val; // @[functional-unit.scala:237:23, :564:7]
reg [1:0] r_uops_3_dst_rtype; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_dst_rtype_0 = r_uops_3_dst_rtype; // @[functional-unit.scala:237:23, :564:7]
reg [1:0] r_uops_3_lrs1_rtype; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_3_lrs1_rtype; // @[functional-unit.scala:237:23, :564:7]
reg [1:0] r_uops_3_lrs2_rtype; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_3_lrs2_rtype; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_frs3_en; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_frs3_en_0 = r_uops_3_frs3_en; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_fp_val; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_fp_val_0 = r_uops_3_fp_val; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_fp_single; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_fp_single_0 = r_uops_3_fp_single; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_xcpt_pf_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_3_xcpt_pf_if; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_xcpt_ae_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_3_xcpt_ae_if; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_xcpt_ma_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_3_xcpt_ma_if; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_bp_debug_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_bp_debug_if_0 = r_uops_3_bp_debug_if; // @[functional-unit.scala:237:23, :564:7]
reg r_uops_3_bp_xcpt_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_3_bp_xcpt_if; // @[functional-unit.scala:237:23, :564:7]
reg [1:0] r_uops_3_debug_fsrc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_fsrc_0 = r_uops_3_debug_fsrc; // @[functional-unit.scala:237:23, :564:7]
reg [1:0] r_uops_3_debug_tsrc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_tsrc_0 = r_uops_3_debug_tsrc; // @[functional-unit.scala:237:23, :564:7]
wire [7:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51]
wire _r_valids_0_T_1 = |_r_valids_0_T; // @[util.scala:118:{51,59}]
wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59]
wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :564:7]
wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :564:7]
wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}]
wire [7:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}]
wire [7:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51]
wire _r_valids_1_T_1 = |_r_valids_1_T; // @[util.scala:118:{51,59}]
wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59]
wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}]
wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :564:7]
wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}]
wire [7:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}]
wire [7:0] _r_valids_2_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51]
wire _r_valids_2_T_1 = |_r_valids_2_T; // @[util.scala:118:{51,59}]
wire _r_valids_2_T_2 = ~_r_valids_2_T_1; // @[util.scala:118:59]
wire _r_valids_2_T_3 = r_valids_1 & _r_valids_2_T_2; // @[functional-unit.scala:236:27, :246:{36,39}]
wire _r_valids_2_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :564:7]
wire _r_valids_2_T_5 = _r_valids_2_T_3 & _r_valids_2_T_4; // @[functional-unit.scala:246:{36,83,86}]
wire [7:0] _r_uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_uops_2_br_mask_T_1 = r_uops_1_br_mask & _r_uops_2_br_mask_T; // @[util.scala:85:{25,27}]
wire [7:0] _r_valids_3_T = io_brupdate_b1_mispredict_mask_0 & r_uops_2_br_mask; // @[util.scala:118:51]
wire _r_valids_3_T_1 = |_r_valids_3_T; // @[util.scala:118:{51,59}]
wire _r_valids_3_T_2 = ~_r_valids_3_T_1; // @[util.scala:118:59]
wire _r_valids_3_T_3 = r_valids_2 & _r_valids_3_T_2; // @[functional-unit.scala:236:27, :246:{36,39}]
wire _r_valids_3_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :564:7]
wire _r_valids_3_T_5 = _r_valids_3_T_3 & _r_valids_3_T_4; // @[functional-unit.scala:246:{36,83,86}]
wire [7:0] _r_uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [7:0] _r_uops_3_br_mask_T_1 = r_uops_2_br_mask & _r_uops_3_br_mask_T; // @[util.scala:85:{25,27}]
wire [7:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_3_br_mask; // @[util.scala:118:51]
wire _io_resp_valid_T_1 = |_io_resp_valid_T; // @[util.scala:118:{51,59}]
wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59]
assign _io_resp_valid_T_3 = r_valids_3 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}]
assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :564:7]
wire [7:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
assign _io_resp_bits_uop_br_mask_T_1 = r_uops_3_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}]
assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25]
always @(posedge clock) begin // @[functional-unit.scala:564:7]
if (reset) begin // @[functional-unit.scala:564:7]
r_valids_0 <= 1'h0; // @[functional-unit.scala:236:27]
r_valids_1 <= 1'h0; // @[functional-unit.scala:236:27]
r_valids_2 <= 1'h0; // @[functional-unit.scala:236:27]
r_valids_3 <= 1'h0; // @[functional-unit.scala:236:27]
end
else begin // @[functional-unit.scala:564:7]
r_valids_0 <= _r_valids_0_T_5; // @[functional-unit.scala:236:27, :240:84]
r_valids_1 <= _r_valids_1_T_5; // @[functional-unit.scala:236:27, :246:83]
r_valids_2 <= _r_valids_2_T_5; // @[functional-unit.scala:236:27, :246:83]
r_valids_3 <= _r_valids_3_T_5; // @[functional-unit.scala:236:27, :246:83]
end
r_uops_0_uopc <= io_req_bits_uop_uopc_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_inst <= io_req_bits_uop_inst_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_debug_inst <= io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_is_rvc <= io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_debug_pc <= io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_iq_type <= io_req_bits_uop_iq_type_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_fu_code <= io_req_bits_uop_fu_code_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ctrl_br_type <= io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ctrl_op1_sel <= io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ctrl_op2_sel <= io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ctrl_imm_sel <= io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ctrl_op_fcn <= io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ctrl_fcn_dw <= io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ctrl_csr_cmd <= io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ctrl_is_load <= io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ctrl_is_sta <= io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ctrl_is_std <= io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_iw_state <= io_req_bits_uop_iw_state_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_iw_p1_poisoned <= io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_iw_p2_poisoned <= io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_is_br <= io_req_bits_uop_is_br_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_is_jalr <= io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_is_jal <= io_req_bits_uop_is_jal_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_is_sfb <= io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_br_mask <= _r_uops_0_br_mask_T_1; // @[util.scala:85:25]
r_uops_0_br_tag <= io_req_bits_uop_br_tag_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ftq_idx <= io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_edge_inst <= io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_pc_lob <= io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_taken <= io_req_bits_uop_taken_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_imm_packed <= io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_csr_addr <= io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_rob_idx <= io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ldq_idx <= io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_stq_idx <= io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_rxq_idx <= io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_pdst <= io_req_bits_uop_pdst_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_prs1 <= io_req_bits_uop_prs1_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_prs2 <= io_req_bits_uop_prs2_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_prs3 <= io_req_bits_uop_prs3_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ppred <= io_req_bits_uop_ppred_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_prs1_busy <= io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_prs2_busy <= io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_prs3_busy <= io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ppred_busy <= io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_stale_pdst <= io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_exception <= io_req_bits_uop_exception_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_exc_cause <= io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_bypassable <= io_req_bits_uop_bypassable_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_mem_cmd <= io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_mem_size <= io_req_bits_uop_mem_size_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_mem_signed <= io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_is_fence <= io_req_bits_uop_is_fence_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_is_fencei <= io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_is_amo <= io_req_bits_uop_is_amo_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_uses_ldq <= io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_uses_stq <= io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_is_sys_pc2epc <= io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_is_unique <= io_req_bits_uop_is_unique_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_flush_on_commit <= io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ldst_is_rs1 <= io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ldst <= io_req_bits_uop_ldst_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_lrs1 <= io_req_bits_uop_lrs1_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_lrs2 <= io_req_bits_uop_lrs2_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_lrs3 <= io_req_bits_uop_lrs3_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_ldst_val <= io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_dst_rtype <= io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_lrs1_rtype <= io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_lrs2_rtype <= io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_frs3_en <= io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_fp_val <= io_req_bits_uop_fp_val_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_fp_single <= io_req_bits_uop_fp_single_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_xcpt_pf_if <= io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_xcpt_ae_if <= io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_xcpt_ma_if <= io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_bp_debug_if <= io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_bp_xcpt_if <= io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_debug_fsrc <= io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_0_debug_tsrc <= io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:237:23, :564:7]
r_uops_1_uopc <= r_uops_0_uopc; // @[functional-unit.scala:237:23]
r_uops_1_inst <= r_uops_0_inst; // @[functional-unit.scala:237:23]
r_uops_1_debug_inst <= r_uops_0_debug_inst; // @[functional-unit.scala:237:23]
r_uops_1_is_rvc <= r_uops_0_is_rvc; // @[functional-unit.scala:237:23]
r_uops_1_debug_pc <= r_uops_0_debug_pc; // @[functional-unit.scala:237:23]
r_uops_1_iq_type <= r_uops_0_iq_type; // @[functional-unit.scala:237:23]
r_uops_1_fu_code <= r_uops_0_fu_code; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_br_type <= r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_op1_sel <= r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_op2_sel <= r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_imm_sel <= r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_op_fcn <= r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_fcn_dw <= r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_csr_cmd <= r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_is_load <= r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_is_sta <= r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23]
r_uops_1_ctrl_is_std <= r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23]
r_uops_1_iw_state <= r_uops_0_iw_state; // @[functional-unit.scala:237:23]
r_uops_1_iw_p1_poisoned <= r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23]
r_uops_1_iw_p2_poisoned <= r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23]
r_uops_1_is_br <= r_uops_0_is_br; // @[functional-unit.scala:237:23]
r_uops_1_is_jalr <= r_uops_0_is_jalr; // @[functional-unit.scala:237:23]
r_uops_1_is_jal <= r_uops_0_is_jal; // @[functional-unit.scala:237:23]
r_uops_1_is_sfb <= r_uops_0_is_sfb; // @[functional-unit.scala:237:23]
r_uops_1_br_mask <= _r_uops_1_br_mask_T_1; // @[util.scala:85:25]
r_uops_1_br_tag <= r_uops_0_br_tag; // @[functional-unit.scala:237:23]
r_uops_1_ftq_idx <= r_uops_0_ftq_idx; // @[functional-unit.scala:237:23]
r_uops_1_edge_inst <= r_uops_0_edge_inst; // @[functional-unit.scala:237:23]
r_uops_1_pc_lob <= r_uops_0_pc_lob; // @[functional-unit.scala:237:23]
r_uops_1_taken <= r_uops_0_taken; // @[functional-unit.scala:237:23]
r_uops_1_imm_packed <= r_uops_0_imm_packed; // @[functional-unit.scala:237:23]
r_uops_1_csr_addr <= r_uops_0_csr_addr; // @[functional-unit.scala:237:23]
r_uops_1_rob_idx <= r_uops_0_rob_idx; // @[functional-unit.scala:237:23]
r_uops_1_ldq_idx <= r_uops_0_ldq_idx; // @[functional-unit.scala:237:23]
r_uops_1_stq_idx <= r_uops_0_stq_idx; // @[functional-unit.scala:237:23]
r_uops_1_rxq_idx <= r_uops_0_rxq_idx; // @[functional-unit.scala:237:23]
r_uops_1_pdst <= r_uops_0_pdst; // @[functional-unit.scala:237:23]
r_uops_1_prs1 <= r_uops_0_prs1; // @[functional-unit.scala:237:23]
r_uops_1_prs2 <= r_uops_0_prs2; // @[functional-unit.scala:237:23]
r_uops_1_prs3 <= r_uops_0_prs3; // @[functional-unit.scala:237:23]
r_uops_1_ppred <= r_uops_0_ppred; // @[functional-unit.scala:237:23]
r_uops_1_prs1_busy <= r_uops_0_prs1_busy; // @[functional-unit.scala:237:23]
r_uops_1_prs2_busy <= r_uops_0_prs2_busy; // @[functional-unit.scala:237:23]
r_uops_1_prs3_busy <= r_uops_0_prs3_busy; // @[functional-unit.scala:237:23]
r_uops_1_ppred_busy <= r_uops_0_ppred_busy; // @[functional-unit.scala:237:23]
r_uops_1_stale_pdst <= r_uops_0_stale_pdst; // @[functional-unit.scala:237:23]
r_uops_1_exception <= r_uops_0_exception; // @[functional-unit.scala:237:23]
r_uops_1_exc_cause <= r_uops_0_exc_cause; // @[functional-unit.scala:237:23]
r_uops_1_bypassable <= r_uops_0_bypassable; // @[functional-unit.scala:237:23]
r_uops_1_mem_cmd <= r_uops_0_mem_cmd; // @[functional-unit.scala:237:23]
r_uops_1_mem_size <= r_uops_0_mem_size; // @[functional-unit.scala:237:23]
r_uops_1_mem_signed <= r_uops_0_mem_signed; // @[functional-unit.scala:237:23]
r_uops_1_is_fence <= r_uops_0_is_fence; // @[functional-unit.scala:237:23]
r_uops_1_is_fencei <= r_uops_0_is_fencei; // @[functional-unit.scala:237:23]
r_uops_1_is_amo <= r_uops_0_is_amo; // @[functional-unit.scala:237:23]
r_uops_1_uses_ldq <= r_uops_0_uses_ldq; // @[functional-unit.scala:237:23]
r_uops_1_uses_stq <= r_uops_0_uses_stq; // @[functional-unit.scala:237:23]
r_uops_1_is_sys_pc2epc <= r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23]
r_uops_1_is_unique <= r_uops_0_is_unique; // @[functional-unit.scala:237:23]
r_uops_1_flush_on_commit <= r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23]
r_uops_1_ldst_is_rs1 <= r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23]
r_uops_1_ldst <= r_uops_0_ldst; // @[functional-unit.scala:237:23]
r_uops_1_lrs1 <= r_uops_0_lrs1; // @[functional-unit.scala:237:23]
r_uops_1_lrs2 <= r_uops_0_lrs2; // @[functional-unit.scala:237:23]
r_uops_1_lrs3 <= r_uops_0_lrs3; // @[functional-unit.scala:237:23]
r_uops_1_ldst_val <= r_uops_0_ldst_val; // @[functional-unit.scala:237:23]
r_uops_1_dst_rtype <= r_uops_0_dst_rtype; // @[functional-unit.scala:237:23]
r_uops_1_lrs1_rtype <= r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23]
r_uops_1_lrs2_rtype <= r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23]
r_uops_1_frs3_en <= r_uops_0_frs3_en; // @[functional-unit.scala:237:23]
r_uops_1_fp_val <= r_uops_0_fp_val; // @[functional-unit.scala:237:23]
r_uops_1_fp_single <= r_uops_0_fp_single; // @[functional-unit.scala:237:23]
r_uops_1_xcpt_pf_if <= r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23]
r_uops_1_xcpt_ae_if <= r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23]
r_uops_1_xcpt_ma_if <= r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23]
r_uops_1_bp_debug_if <= r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23]
r_uops_1_bp_xcpt_if <= r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23]
r_uops_1_debug_fsrc <= r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23]
r_uops_1_debug_tsrc <= r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23]
r_uops_2_uopc <= r_uops_1_uopc; // @[functional-unit.scala:237:23]
r_uops_2_inst <= r_uops_1_inst; // @[functional-unit.scala:237:23]
r_uops_2_debug_inst <= r_uops_1_debug_inst; // @[functional-unit.scala:237:23]
r_uops_2_is_rvc <= r_uops_1_is_rvc; // @[functional-unit.scala:237:23]
r_uops_2_debug_pc <= r_uops_1_debug_pc; // @[functional-unit.scala:237:23]
r_uops_2_iq_type <= r_uops_1_iq_type; // @[functional-unit.scala:237:23]
r_uops_2_fu_code <= r_uops_1_fu_code; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_br_type <= r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_op1_sel <= r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_op2_sel <= r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_imm_sel <= r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_op_fcn <= r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_fcn_dw <= r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_csr_cmd <= r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_is_load <= r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_is_sta <= r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23]
r_uops_2_ctrl_is_std <= r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23]
r_uops_2_iw_state <= r_uops_1_iw_state; // @[functional-unit.scala:237:23]
r_uops_2_iw_p1_poisoned <= r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23]
r_uops_2_iw_p2_poisoned <= r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23]
r_uops_2_is_br <= r_uops_1_is_br; // @[functional-unit.scala:237:23]
r_uops_2_is_jalr <= r_uops_1_is_jalr; // @[functional-unit.scala:237:23]
r_uops_2_is_jal <= r_uops_1_is_jal; // @[functional-unit.scala:237:23]
r_uops_2_is_sfb <= r_uops_1_is_sfb; // @[functional-unit.scala:237:23]
r_uops_2_br_mask <= _r_uops_2_br_mask_T_1; // @[util.scala:85:25]
r_uops_2_br_tag <= r_uops_1_br_tag; // @[functional-unit.scala:237:23]
r_uops_2_ftq_idx <= r_uops_1_ftq_idx; // @[functional-unit.scala:237:23]
r_uops_2_edge_inst <= r_uops_1_edge_inst; // @[functional-unit.scala:237:23]
r_uops_2_pc_lob <= r_uops_1_pc_lob; // @[functional-unit.scala:237:23]
r_uops_2_taken <= r_uops_1_taken; // @[functional-unit.scala:237:23]
r_uops_2_imm_packed <= r_uops_1_imm_packed; // @[functional-unit.scala:237:23]
r_uops_2_csr_addr <= r_uops_1_csr_addr; // @[functional-unit.scala:237:23]
r_uops_2_rob_idx <= r_uops_1_rob_idx; // @[functional-unit.scala:237:23]
r_uops_2_ldq_idx <= r_uops_1_ldq_idx; // @[functional-unit.scala:237:23]
r_uops_2_stq_idx <= r_uops_1_stq_idx; // @[functional-unit.scala:237:23]
r_uops_2_rxq_idx <= r_uops_1_rxq_idx; // @[functional-unit.scala:237:23]
r_uops_2_pdst <= r_uops_1_pdst; // @[functional-unit.scala:237:23]
r_uops_2_prs1 <= r_uops_1_prs1; // @[functional-unit.scala:237:23]
r_uops_2_prs2 <= r_uops_1_prs2; // @[functional-unit.scala:237:23]
r_uops_2_prs3 <= r_uops_1_prs3; // @[functional-unit.scala:237:23]
r_uops_2_ppred <= r_uops_1_ppred; // @[functional-unit.scala:237:23]
r_uops_2_prs1_busy <= r_uops_1_prs1_busy; // @[functional-unit.scala:237:23]
r_uops_2_prs2_busy <= r_uops_1_prs2_busy; // @[functional-unit.scala:237:23]
r_uops_2_prs3_busy <= r_uops_1_prs3_busy; // @[functional-unit.scala:237:23]
r_uops_2_ppred_busy <= r_uops_1_ppred_busy; // @[functional-unit.scala:237:23]
r_uops_2_stale_pdst <= r_uops_1_stale_pdst; // @[functional-unit.scala:237:23]
r_uops_2_exception <= r_uops_1_exception; // @[functional-unit.scala:237:23]
r_uops_2_exc_cause <= r_uops_1_exc_cause; // @[functional-unit.scala:237:23]
r_uops_2_bypassable <= r_uops_1_bypassable; // @[functional-unit.scala:237:23]
r_uops_2_mem_cmd <= r_uops_1_mem_cmd; // @[functional-unit.scala:237:23]
r_uops_2_mem_size <= r_uops_1_mem_size; // @[functional-unit.scala:237:23]
r_uops_2_mem_signed <= r_uops_1_mem_signed; // @[functional-unit.scala:237:23]
r_uops_2_is_fence <= r_uops_1_is_fence; // @[functional-unit.scala:237:23]
r_uops_2_is_fencei <= r_uops_1_is_fencei; // @[functional-unit.scala:237:23]
r_uops_2_is_amo <= r_uops_1_is_amo; // @[functional-unit.scala:237:23]
r_uops_2_uses_ldq <= r_uops_1_uses_ldq; // @[functional-unit.scala:237:23]
r_uops_2_uses_stq <= r_uops_1_uses_stq; // @[functional-unit.scala:237:23]
r_uops_2_is_sys_pc2epc <= r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23]
r_uops_2_is_unique <= r_uops_1_is_unique; // @[functional-unit.scala:237:23]
r_uops_2_flush_on_commit <= r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23]
r_uops_2_ldst_is_rs1 <= r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23]
r_uops_2_ldst <= r_uops_1_ldst; // @[functional-unit.scala:237:23]
r_uops_2_lrs1 <= r_uops_1_lrs1; // @[functional-unit.scala:237:23]
r_uops_2_lrs2 <= r_uops_1_lrs2; // @[functional-unit.scala:237:23]
r_uops_2_lrs3 <= r_uops_1_lrs3; // @[functional-unit.scala:237:23]
r_uops_2_ldst_val <= r_uops_1_ldst_val; // @[functional-unit.scala:237:23]
r_uops_2_dst_rtype <= r_uops_1_dst_rtype; // @[functional-unit.scala:237:23]
r_uops_2_lrs1_rtype <= r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23]
r_uops_2_lrs2_rtype <= r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23]
r_uops_2_frs3_en <= r_uops_1_frs3_en; // @[functional-unit.scala:237:23]
r_uops_2_fp_val <= r_uops_1_fp_val; // @[functional-unit.scala:237:23]
r_uops_2_fp_single <= r_uops_1_fp_single; // @[functional-unit.scala:237:23]
r_uops_2_xcpt_pf_if <= r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23]
r_uops_2_xcpt_ae_if <= r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23]
r_uops_2_xcpt_ma_if <= r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23]
r_uops_2_bp_debug_if <= r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23]
r_uops_2_bp_xcpt_if <= r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23]
r_uops_2_debug_fsrc <= r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23]
r_uops_2_debug_tsrc <= r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23]
r_uops_3_uopc <= r_uops_2_uopc; // @[functional-unit.scala:237:23]
r_uops_3_inst <= r_uops_2_inst; // @[functional-unit.scala:237:23]
r_uops_3_debug_inst <= r_uops_2_debug_inst; // @[functional-unit.scala:237:23]
r_uops_3_is_rvc <= r_uops_2_is_rvc; // @[functional-unit.scala:237:23]
r_uops_3_debug_pc <= r_uops_2_debug_pc; // @[functional-unit.scala:237:23]
r_uops_3_iq_type <= r_uops_2_iq_type; // @[functional-unit.scala:237:23]
r_uops_3_fu_code <= r_uops_2_fu_code; // @[functional-unit.scala:237:23]
r_uops_3_ctrl_br_type <= r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23]
r_uops_3_ctrl_op1_sel <= r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23]
r_uops_3_ctrl_op2_sel <= r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23]
r_uops_3_ctrl_imm_sel <= r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23]
r_uops_3_ctrl_op_fcn <= r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23]
r_uops_3_ctrl_fcn_dw <= r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
r_uops_3_ctrl_csr_cmd <= r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
r_uops_3_ctrl_is_load <= r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23]
r_uops_3_ctrl_is_sta <= r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23]
r_uops_3_ctrl_is_std <= r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23]
r_uops_3_iw_state <= r_uops_2_iw_state; // @[functional-unit.scala:237:23]
r_uops_3_iw_p1_poisoned <= r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23]
r_uops_3_iw_p2_poisoned <= r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23]
r_uops_3_is_br <= r_uops_2_is_br; // @[functional-unit.scala:237:23]
r_uops_3_is_jalr <= r_uops_2_is_jalr; // @[functional-unit.scala:237:23]
r_uops_3_is_jal <= r_uops_2_is_jal; // @[functional-unit.scala:237:23]
r_uops_3_is_sfb <= r_uops_2_is_sfb; // @[functional-unit.scala:237:23]
r_uops_3_br_mask <= _r_uops_3_br_mask_T_1; // @[util.scala:85:25]
r_uops_3_br_tag <= r_uops_2_br_tag; // @[functional-unit.scala:237:23]
r_uops_3_ftq_idx <= r_uops_2_ftq_idx; // @[functional-unit.scala:237:23]
r_uops_3_edge_inst <= r_uops_2_edge_inst; // @[functional-unit.scala:237:23]
r_uops_3_pc_lob <= r_uops_2_pc_lob; // @[functional-unit.scala:237:23]
r_uops_3_taken <= r_uops_2_taken; // @[functional-unit.scala:237:23]
r_uops_3_imm_packed <= r_uops_2_imm_packed; // @[functional-unit.scala:237:23]
r_uops_3_csr_addr <= r_uops_2_csr_addr; // @[functional-unit.scala:237:23]
r_uops_3_rob_idx <= r_uops_2_rob_idx; // @[functional-unit.scala:237:23]
r_uops_3_ldq_idx <= r_uops_2_ldq_idx; // @[functional-unit.scala:237:23]
r_uops_3_stq_idx <= r_uops_2_stq_idx; // @[functional-unit.scala:237:23]
r_uops_3_rxq_idx <= r_uops_2_rxq_idx; // @[functional-unit.scala:237:23]
r_uops_3_pdst <= r_uops_2_pdst; // @[functional-unit.scala:237:23]
r_uops_3_prs1 <= r_uops_2_prs1; // @[functional-unit.scala:237:23]
r_uops_3_prs2 <= r_uops_2_prs2; // @[functional-unit.scala:237:23]
r_uops_3_prs3 <= r_uops_2_prs3; // @[functional-unit.scala:237:23]
r_uops_3_ppred <= r_uops_2_ppred; // @[functional-unit.scala:237:23]
r_uops_3_prs1_busy <= r_uops_2_prs1_busy; // @[functional-unit.scala:237:23]
r_uops_3_prs2_busy <= r_uops_2_prs2_busy; // @[functional-unit.scala:237:23]
r_uops_3_prs3_busy <= r_uops_2_prs3_busy; // @[functional-unit.scala:237:23]
r_uops_3_ppred_busy <= r_uops_2_ppred_busy; // @[functional-unit.scala:237:23]
r_uops_3_stale_pdst <= r_uops_2_stale_pdst; // @[functional-unit.scala:237:23]
r_uops_3_exception <= r_uops_2_exception; // @[functional-unit.scala:237:23]
r_uops_3_exc_cause <= r_uops_2_exc_cause; // @[functional-unit.scala:237:23]
r_uops_3_bypassable <= r_uops_2_bypassable; // @[functional-unit.scala:237:23]
r_uops_3_mem_cmd <= r_uops_2_mem_cmd; // @[functional-unit.scala:237:23]
r_uops_3_mem_size <= r_uops_2_mem_size; // @[functional-unit.scala:237:23]
r_uops_3_mem_signed <= r_uops_2_mem_signed; // @[functional-unit.scala:237:23]
r_uops_3_is_fence <= r_uops_2_is_fence; // @[functional-unit.scala:237:23]
r_uops_3_is_fencei <= r_uops_2_is_fencei; // @[functional-unit.scala:237:23]
r_uops_3_is_amo <= r_uops_2_is_amo; // @[functional-unit.scala:237:23]
r_uops_3_uses_ldq <= r_uops_2_uses_ldq; // @[functional-unit.scala:237:23]
r_uops_3_uses_stq <= r_uops_2_uses_stq; // @[functional-unit.scala:237:23]
r_uops_3_is_sys_pc2epc <= r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23]
r_uops_3_is_unique <= r_uops_2_is_unique; // @[functional-unit.scala:237:23]
r_uops_3_flush_on_commit <= r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23]
r_uops_3_ldst_is_rs1 <= r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23]
r_uops_3_ldst <= r_uops_2_ldst; // @[functional-unit.scala:237:23]
r_uops_3_lrs1 <= r_uops_2_lrs1; // @[functional-unit.scala:237:23]
r_uops_3_lrs2 <= r_uops_2_lrs2; // @[functional-unit.scala:237:23]
r_uops_3_lrs3 <= r_uops_2_lrs3; // @[functional-unit.scala:237:23]
r_uops_3_ldst_val <= r_uops_2_ldst_val; // @[functional-unit.scala:237:23]
r_uops_3_dst_rtype <= r_uops_2_dst_rtype; // @[functional-unit.scala:237:23]
r_uops_3_lrs1_rtype <= r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23]
r_uops_3_lrs2_rtype <= r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23]
r_uops_3_frs3_en <= r_uops_2_frs3_en; // @[functional-unit.scala:237:23]
r_uops_3_fp_val <= r_uops_2_fp_val; // @[functional-unit.scala:237:23]
r_uops_3_fp_single <= r_uops_2_fp_single; // @[functional-unit.scala:237:23]
r_uops_3_xcpt_pf_if <= r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23]
r_uops_3_xcpt_ae_if <= r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23]
r_uops_3_xcpt_ma_if <= r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23]
r_uops_3_bp_debug_if <= r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23]
r_uops_3_bp_xcpt_if <= r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23]
r_uops_3_debug_fsrc <= r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23]
r_uops_3_debug_tsrc <= r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23]
always @(posedge)
FPU fpu ( // @[functional-unit.scala:572:19]
.clock (clock),
.reset (reset),
.io_req_valid (io_req_valid_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_uopc (io_req_bits_uop_uopc_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_inst (io_req_bits_uop_inst_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_iq_type (io_req_bits_uop_iq_type_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_fu_code (io_req_bits_uop_fu_code_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_iw_state (io_req_bits_uop_iw_state_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_iw_p1_poisoned (io_req_bits_uop_iw_p1_poisoned_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_iw_p2_poisoned (io_req_bits_uop_iw_p2_poisoned_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_is_br (io_req_bits_uop_is_br_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_is_jal (io_req_bits_uop_is_jal_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_br_mask (io_req_bits_uop_br_mask_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_br_tag (io_req_bits_uop_br_tag_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_taken (io_req_bits_uop_taken_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_csr_addr (io_req_bits_uop_csr_addr_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_pdst (io_req_bits_uop_pdst_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_prs1 (io_req_bits_uop_prs1_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_prs2 (io_req_bits_uop_prs2_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_prs3 (io_req_bits_uop_prs3_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ppred (io_req_bits_uop_ppred_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_exception (io_req_bits_uop_exception_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_bypassable (io_req_bits_uop_bypassable_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_mem_size (io_req_bits_uop_mem_size_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_is_fence (io_req_bits_uop_is_fence_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_is_amo (io_req_bits_uop_is_amo_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_is_unique (io_req_bits_uop_is_unique_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ldst (io_req_bits_uop_ldst_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_ldst_val (io_req_bits_uop_ldst_val_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_fp_val (io_req_bits_uop_fp_val_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_fp_single (io_req_bits_uop_fp_single_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc_0), // @[functional-unit.scala:564:7]
.io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc_0), // @[functional-unit.scala:564:7]
.io_req_bits_rs1_data (io_req_bits_rs1_data_0), // @[functional-unit.scala:564:7]
.io_req_bits_rs2_data (io_req_bits_rs2_data_0), // @[functional-unit.scala:564:7]
.io_req_bits_rs3_data (io_req_bits_rs3_data_0), // @[functional-unit.scala:564:7]
.io_req_bits_fcsr_rm (io_fcsr_rm_0), // @[functional-unit.scala:564:7]
.io_resp_bits_data (io_resp_bits_data_0),
.io_resp_bits_fflags_valid (io_resp_bits_fflags_valid_0),
.io_resp_bits_fflags_bits_flags (io_resp_bits_fflags_bits_flags_0)
); // @[functional-unit.scala:572:19]
assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_uopc = io_resp_bits_uop_uopc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_iq_type = io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_fu_code = io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ctrl_br_type = io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ctrl_op1_sel = io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ctrl_op2_sel = io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ctrl_imm_sel = io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ctrl_op_fcn = io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ctrl_fcn_dw = io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ctrl_csr_cmd = io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ctrl_is_load = io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ctrl_is_sta = io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ctrl_is_std = io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_iw_state = io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_iw_p1_poisoned = io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_iw_p2_poisoned = io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_is_br = io_resp_bits_uop_is_br_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_is_jalr = io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_is_jal = io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_csr_addr = io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_bypassable = io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_ldst_val = io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_fp_single = io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_valid = io_resp_bits_fflags_valid_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_uopc = io_resp_bits_fflags_bits_uop_uopc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_inst = io_resp_bits_fflags_bits_uop_inst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_debug_inst = io_resp_bits_fflags_bits_uop_debug_inst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_is_rvc = io_resp_bits_fflags_bits_uop_is_rvc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_debug_pc = io_resp_bits_fflags_bits_uop_debug_pc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_iq_type = io_resp_bits_fflags_bits_uop_iq_type_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_fu_code = io_resp_bits_fflags_bits_uop_fu_code_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ctrl_br_type = io_resp_bits_fflags_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ctrl_op1_sel = io_resp_bits_fflags_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ctrl_op2_sel = io_resp_bits_fflags_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ctrl_imm_sel = io_resp_bits_fflags_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ctrl_op_fcn = io_resp_bits_fflags_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = io_resp_bits_fflags_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = io_resp_bits_fflags_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ctrl_is_load = io_resp_bits_fflags_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ctrl_is_sta = io_resp_bits_fflags_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ctrl_is_std = io_resp_bits_fflags_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_iw_state = io_resp_bits_fflags_bits_uop_iw_state_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_iw_p1_poisoned = io_resp_bits_fflags_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_iw_p2_poisoned = io_resp_bits_fflags_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_is_br = io_resp_bits_fflags_bits_uop_is_br_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_is_jalr = io_resp_bits_fflags_bits_uop_is_jalr_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_is_jal = io_resp_bits_fflags_bits_uop_is_jal_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_is_sfb = io_resp_bits_fflags_bits_uop_is_sfb_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_br_mask = io_resp_bits_fflags_bits_uop_br_mask_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_br_tag = io_resp_bits_fflags_bits_uop_br_tag_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ftq_idx = io_resp_bits_fflags_bits_uop_ftq_idx_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_edge_inst = io_resp_bits_fflags_bits_uop_edge_inst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_pc_lob = io_resp_bits_fflags_bits_uop_pc_lob_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_taken = io_resp_bits_fflags_bits_uop_taken_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_imm_packed = io_resp_bits_fflags_bits_uop_imm_packed_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_csr_addr = io_resp_bits_fflags_bits_uop_csr_addr_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_rob_idx = io_resp_bits_fflags_bits_uop_rob_idx_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ldq_idx = io_resp_bits_fflags_bits_uop_ldq_idx_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_stq_idx = io_resp_bits_fflags_bits_uop_stq_idx_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_rxq_idx = io_resp_bits_fflags_bits_uop_rxq_idx_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_pdst = io_resp_bits_fflags_bits_uop_pdst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_prs1 = io_resp_bits_fflags_bits_uop_prs1_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_prs2 = io_resp_bits_fflags_bits_uop_prs2_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_prs3 = io_resp_bits_fflags_bits_uop_prs3_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ppred = io_resp_bits_fflags_bits_uop_ppred_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_prs1_busy = io_resp_bits_fflags_bits_uop_prs1_busy_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_prs2_busy = io_resp_bits_fflags_bits_uop_prs2_busy_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_prs3_busy = io_resp_bits_fflags_bits_uop_prs3_busy_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ppred_busy = io_resp_bits_fflags_bits_uop_ppred_busy_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_stale_pdst = io_resp_bits_fflags_bits_uop_stale_pdst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_exception = io_resp_bits_fflags_bits_uop_exception_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_exc_cause = io_resp_bits_fflags_bits_uop_exc_cause_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_bypassable = io_resp_bits_fflags_bits_uop_bypassable_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_mem_cmd = io_resp_bits_fflags_bits_uop_mem_cmd_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_mem_size = io_resp_bits_fflags_bits_uop_mem_size_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_mem_signed = io_resp_bits_fflags_bits_uop_mem_signed_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_is_fence = io_resp_bits_fflags_bits_uop_is_fence_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_is_fencei = io_resp_bits_fflags_bits_uop_is_fencei_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_is_amo = io_resp_bits_fflags_bits_uop_is_amo_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_uses_ldq = io_resp_bits_fflags_bits_uop_uses_ldq_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_uses_stq = io_resp_bits_fflags_bits_uop_uses_stq_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_is_sys_pc2epc = io_resp_bits_fflags_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_is_unique = io_resp_bits_fflags_bits_uop_is_unique_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_flush_on_commit = io_resp_bits_fflags_bits_uop_flush_on_commit_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ldst_is_rs1 = io_resp_bits_fflags_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ldst = io_resp_bits_fflags_bits_uop_ldst_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_lrs1 = io_resp_bits_fflags_bits_uop_lrs1_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_lrs2 = io_resp_bits_fflags_bits_uop_lrs2_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_lrs3 = io_resp_bits_fflags_bits_uop_lrs3_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_ldst_val = io_resp_bits_fflags_bits_uop_ldst_val_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_dst_rtype = io_resp_bits_fflags_bits_uop_dst_rtype_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_lrs1_rtype = io_resp_bits_fflags_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_lrs2_rtype = io_resp_bits_fflags_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_frs3_en = io_resp_bits_fflags_bits_uop_frs3_en_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_fp_val = io_resp_bits_fflags_bits_uop_fp_val_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_fp_single = io_resp_bits_fflags_bits_uop_fp_single_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_xcpt_pf_if = io_resp_bits_fflags_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_xcpt_ae_if = io_resp_bits_fflags_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_xcpt_ma_if = io_resp_bits_fflags_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_bp_debug_if = io_resp_bits_fflags_bits_uop_bp_debug_if_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_bp_xcpt_if = io_resp_bits_fflags_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_debug_fsrc = io_resp_bits_fflags_bits_uop_debug_fsrc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_uop_debug_tsrc = io_resp_bits_fflags_bits_uop_debug_tsrc_0; // @[functional-unit.scala:564:7]
assign io_resp_bits_fflags_bits_flags = io_resp_bits_fflags_bits_flags_0; // @[functional-unit.scala:564:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File DCache.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.amba.AMBAProt
import freechips.rocketchip.diplomacy.{BufferParams}
import freechips.rocketchip.prci.{ClockCrossingType, RationalCrossing, SynchronousCrossing, AsynchronousCrossing, CreditedCrossing}
import freechips.rocketchip.tile.{CoreBundle, LookupByHartId}
import freechips.rocketchip.tilelink.{TLFIFOFixer,ClientMetadata, TLBundleA, TLAtomics, TLBundleB, TLPermissions}
import freechips.rocketchip.tilelink.TLMessages.{AccessAck, HintAck, AccessAckData, Grant, GrantData, ReleaseAck}
import freechips.rocketchip.util.{CanHaveErrors, ClockGate, IdentityCode, ReplacementPolicy, DescribedSRAM, property}
import freechips.rocketchip.util.BooleanToAugmentedBoolean
import freechips.rocketchip.util.UIntToAugmentedUInt
import freechips.rocketchip.util.UIntIsOneOf
import freechips.rocketchip.util.IntToAugmentedInt
import freechips.rocketchip.util.SeqToAugmentedSeq
import freechips.rocketchip.util.SeqBoolBitwiseOps
// TODO: delete this trait once deduplication is smart enough to avoid globally inlining matching circuits
trait InlineInstance { self: chisel3.experimental.BaseModule =>
chisel3.experimental.annotate(
new chisel3.experimental.ChiselAnnotation {
def toFirrtl: firrtl.annotations.Annotation = firrtl.passes.InlineAnnotation(self.toNamed) } )
}
class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p)
with CanHaveErrors {
val correctable = (cacheParams.tagCode.canCorrect || cacheParams.dataCode.canCorrect).option(Valid(UInt(paddrBits.W)))
val uncorrectable = (cacheParams.tagCode.canDetect || cacheParams.dataCode.canDetect).option(Valid(UInt(paddrBits.W)))
val bus = Valid(UInt(paddrBits.W))
}
class DCacheDataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val addr = UInt(untagBits.W)
val write = Bool()
val wdata = UInt((encBits * rowBytes / eccBytes).W)
val wordMask = UInt((rowBytes / subWordBytes).W)
val eccMask = UInt((wordBytes / eccBytes).W)
val way_en = UInt(nWays.W)
}
class DCacheDataArray(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val io = IO(new Bundle {
val req = Flipped(Valid(new DCacheDataReq))
val resp = Output(Vec(nWays, UInt((req.bits.wdata.getWidth).W)))
})
require(rowBits % subWordBits == 0, "rowBits must be a multiple of subWordBits")
val eccMask = if (eccBits == subWordBits) Seq(true.B) else io.req.bits.eccMask.asBools
val wMask = if (nWays == 1) eccMask else (0 until nWays).flatMap(i => eccMask.map(_ && io.req.bits.way_en(i)))
val wWords = io.req.bits.wdata.grouped(encBits * (subWordBits / eccBits))
val addr = io.req.bits.addr >> rowOffBits
val data_arrays = Seq.tabulate(rowBits / subWordBits) {
i =>
DescribedSRAM(
name = s"${tileParams.baseName}_dcache_data_arrays_${i}",
desc = "DCache Data Array",
size = nSets * cacheBlockBytes / rowBytes,
data = Vec(nWays * (subWordBits / eccBits), UInt(encBits.W))
)
}
val rdata = for ((array , i) <- data_arrays.zipWithIndex) yield {
val valid = io.req.valid && ((data_arrays.size == 1).B || io.req.bits.wordMask(i))
when (valid && io.req.bits.write) {
val wMaskSlice = (0 until wMask.size).filter(j => i % (wordBits/subWordBits) == (j % (wordBytes/eccBytes)) / (subWordBytes/eccBytes)).map(wMask(_))
val wData = wWords(i).grouped(encBits)
array.write(addr, VecInit((0 until nWays).flatMap(i => wData)), wMaskSlice)
}
val data = array.read(addr, valid && !io.req.bits.write)
data.grouped(subWordBits / eccBits).map(_.asUInt).toSeq
}
(io.resp zip rdata.transpose).foreach { case (resp, data) => resp := data.asUInt }
}
class DCacheMetadataReq(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
val write = Bool()
val addr = UInt(vaddrBitsExtended.W)
val idx = UInt(idxBits.W)
val way_en = UInt(nWays.W)
val data = UInt(cacheParams.tagCode.width(new L1Metadata().getWidth).W)
}
class DCache(staticIdForMetadataUseOnly: Int, val crossing: ClockCrossingType)(implicit p: Parameters) extends HellaCache(staticIdForMetadataUseOnly)(p) {
override lazy val module = new DCacheModule(this)
}
class DCacheTLBPort(implicit p: Parameters) extends CoreBundle()(p) {
val req = Flipped(Decoupled(new TLBReq(coreDataBytes.log2)))
val s1_resp = Output(new TLBResp(coreDataBytes.log2))
val s2_kill = Input(Bool())
}
class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
val tECC = cacheParams.tagCode
val dECC = cacheParams.dataCode
require(subWordBits % eccBits == 0, "subWordBits must be a multiple of eccBits")
require(eccBytes == 1 || !dECC.isInstanceOf[IdentityCode])
require(cacheParams.silentDrop || cacheParams.acquireBeforeRelease, "!silentDrop requires acquireBeforeRelease")
val usingRMW = eccBytes > 1 || usingAtomicsInCache
val mmioOffset = outer.firstMMIO
edge.manager.requireFifo(TLFIFOFixer.allVolatile) // TileLink pipelining MMIO requests
val clock_en_reg = Reg(Bool())
io.cpu.clock_enabled := clock_en_reg
val gated_clock =
if (!cacheParams.clockGate) clock
else ClockGate(clock, clock_en_reg, "dcache_clock_gate")
class DCacheModuleImpl { // entering gated-clock domain
val tlb = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)))
val pma_checker = Module(new TLB(false, log2Ceil(coreDataBytes), TLBConfig(nTLBSets, nTLBWays, cacheParams.nTLBBasePageSectors, cacheParams.nTLBSuperpages)) with InlineInstance)
// tags
val replacer = ReplacementPolicy.fromString(cacheParams.replacementPolicy, nWays)
/** Metadata Arbiter:
* 0: Tag update on reset
* 1: Tag update on ECC error
* 2: Tag update on hit
* 3: Tag update on refill
* 4: Tag update on release
* 5: Tag update on flush
* 6: Tag update on probe
* 7: Tag update on CPU request
*/
val metaArb = Module(new Arbiter(new DCacheMetadataReq, 8) with InlineInstance)
val tag_array = DescribedSRAM(
name = s"${tileParams.baseName}_dcache_tag_array",
desc = "DCache Tag Array",
size = nSets,
data = Vec(nWays, chiselTypeOf(metaArb.io.out.bits.data))
)
// data
val data = Module(new DCacheDataArray)
/** Data Arbiter
* 0: data from pending store buffer
* 1: data from TL-D refill
* 2: release to TL-A
* 3: hit path to CPU
*/
val dataArb = Module(new Arbiter(new DCacheDataReq, 4) with InlineInstance)
dataArb.io.in.tail.foreach(_.bits.wdata := dataArb.io.in.head.bits.wdata) // tie off write ports by default
data.io.req.bits <> dataArb.io.out.bits
data.io.req.valid := dataArb.io.out.valid
dataArb.io.out.ready := true.B
metaArb.io.out.ready := clock_en_reg
val tl_out_a = Wire(chiselTypeOf(tl_out.a))
tl_out.a <> {
val a_queue_depth = outer.crossing match {
case RationalCrossing(_) => // TODO make this depend on the actual ratio?
if (cacheParams.separateUncachedResp) (maxUncachedInFlight + 1) / 2
else 2 min maxUncachedInFlight-1
case SynchronousCrossing(BufferParams.none) => 1 // Need some buffering to guarantee livelock freedom
case SynchronousCrossing(_) => 0 // Adequate buffering within the crossing
case _: AsynchronousCrossing => 0 // Adequate buffering within the crossing
case _: CreditedCrossing => 0 // Adequate buffering within the crossing
}
Queue(tl_out_a, a_queue_depth, flow = true)
}
val (tl_out_c, release_queue_empty) =
if (cacheParams.acquireBeforeRelease) {
val q = Module(new Queue(chiselTypeOf(tl_out.c.bits), cacheDataBeats, flow = true))
tl_out.c <> q.io.deq
(q.io.enq, q.io.count === 0.U)
} else {
(tl_out.c, true.B)
}
val s1_valid = RegNext(io.cpu.req.fire, false.B)
val s1_probe = RegNext(tl_out.b.fire, false.B)
val probe_bits = RegEnable(tl_out.b.bits, tl_out.b.fire) // TODO has data now :(
val s1_nack = WireDefault(false.B)
val s1_valid_masked = s1_valid && !io.cpu.s1_kill
val s1_valid_not_nacked = s1_valid && !s1_nack
val s1_tlb_req_valid = RegNext(io.tlb_port.req.fire, false.B)
val s2_tlb_req_valid = RegNext(s1_tlb_req_valid, false.B)
val s0_clk_en = metaArb.io.out.valid && !metaArb.io.out.bits.write
val s0_req = WireInit(io.cpu.req.bits)
s0_req.addr := Cat(metaArb.io.out.bits.addr >> blockOffBits, io.cpu.req.bits.addr(blockOffBits-1,0))
s0_req.idx.foreach(_ := Cat(metaArb.io.out.bits.idx, s0_req.addr(blockOffBits-1, 0)))
when (!metaArb.io.in(7).ready) { s0_req.phys := true.B }
val s1_req = RegEnable(s0_req, s0_clk_en)
val s1_vaddr = Cat(s1_req.idx.getOrElse(s1_req.addr) >> tagLSB, s1_req.addr(tagLSB-1, 0))
val s0_tlb_req = WireInit(io.tlb_port.req.bits)
when (!io.tlb_port.req.fire) {
s0_tlb_req.passthrough := s0_req.phys
s0_tlb_req.vaddr := s0_req.addr
s0_tlb_req.size := s0_req.size
s0_tlb_req.cmd := s0_req.cmd
s0_tlb_req.prv := s0_req.dprv
s0_tlb_req.v := s0_req.dv
}
val s1_tlb_req = RegEnable(s0_tlb_req, s0_clk_en || io.tlb_port.req.valid)
val s1_read = isRead(s1_req.cmd)
val s1_write = isWrite(s1_req.cmd)
val s1_readwrite = s1_read || s1_write
val s1_sfence = s1_req.cmd === M_SFENCE || s1_req.cmd === M_HFENCEV || s1_req.cmd === M_HFENCEG
val s1_flush_line = s1_req.cmd === M_FLUSH_ALL && s1_req.size(0)
val s1_flush_valid = Reg(Bool())
val s1_waw_hazard = Wire(Bool())
val s_ready :: s_voluntary_writeback :: s_probe_rep_dirty :: s_probe_rep_clean :: s_probe_retry :: s_probe_rep_miss :: s_voluntary_write_meta :: s_probe_write_meta :: s_dummy :: s_voluntary_release :: Nil = Enum(10)
val supports_flush = outer.flushOnFenceI || coreParams.haveCFlush
val flushed = RegInit(true.B)
val flushing = RegInit(false.B)
val flushing_req = Reg(chiselTypeOf(s1_req))
val cached_grant_wait = RegInit(false.B)
val resetting = RegInit(false.B)
val flushCounter = RegInit((nSets * (nWays-1)).U(log2Ceil(nSets * nWays).W))
val release_ack_wait = RegInit(false.B)
val release_ack_addr = Reg(UInt(paddrBits.W))
val release_state = RegInit(s_ready)
val refill_way = Reg(UInt())
val any_pstore_valid = Wire(Bool())
val inWriteback = release_state.isOneOf(s_voluntary_writeback, s_probe_rep_dirty)
val releaseWay = Wire(UInt())
io.cpu.req.ready := (release_state === s_ready) && !cached_grant_wait && !s1_nack
// I/O MSHRs
val uncachedInFlight = RegInit(VecInit(Seq.fill(maxUncachedInFlight)(false.B)))
val uncachedReqs = Reg(Vec(maxUncachedInFlight, new HellaCacheReq))
val uncachedResp = WireInit(new HellaCacheReq, DontCare)
// hit initiation path
val s0_read = isRead(io.cpu.req.bits.cmd)
dataArb.io.in(3).valid := io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)
dataArb.io.in(3).bits := dataArb.io.in(1).bits
dataArb.io.in(3).bits.write := false.B
dataArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.idx.getOrElse(io.cpu.req.bits.addr) >> tagLSB, io.cpu.req.bits.addr(tagLSB-1, 0))
dataArb.io.in(3).bits.wordMask := {
val mask = (subWordBytes.log2 until rowOffBits).foldLeft(1.U) { case (in, i) =>
val upper_mask = Mux((i >= wordBytes.log2).B || io.cpu.req.bits.size <= i.U, 0.U,
((BigInt(1) << (1 << (i - subWordBytes.log2)))-1).U)
val upper = Mux(io.cpu.req.bits.addr(i), in, 0.U) | upper_mask
val lower = Mux(io.cpu.req.bits.addr(i), 0.U, in)
upper ## lower
}
Fill(subWordBytes / eccBytes, mask)
}
dataArb.io.in(3).bits.eccMask := ~0.U((wordBytes / eccBytes).W)
dataArb.io.in(3).bits.way_en := ~0.U(nWays.W)
when (!dataArb.io.in(3).ready && s0_read) { io.cpu.req.ready := false.B }
val s1_did_read = RegEnable(dataArb.io.in(3).ready && (io.cpu.req.valid && needsRead(io.cpu.req.bits)), s0_clk_en)
val s1_read_mask = RegEnable(dataArb.io.in(3).bits.wordMask, s0_clk_en)
metaArb.io.in(7).valid := io.cpu.req.valid
metaArb.io.in(7).bits.write := false.B
metaArb.io.in(7).bits.idx := dataArb.io.in(3).bits.addr(idxMSB, idxLSB)
metaArb.io.in(7).bits.addr := io.cpu.req.bits.addr
metaArb.io.in(7).bits.way_en := metaArb.io.in(4).bits.way_en
metaArb.io.in(7).bits.data := metaArb.io.in(4).bits.data
when (!metaArb.io.in(7).ready) { io.cpu.req.ready := false.B }
// address translation
val s1_cmd_uses_tlb = s1_readwrite || s1_flush_line || s1_req.cmd === M_WOK
io.ptw <> tlb.io.ptw
tlb.io.kill := io.cpu.s2_kill || s2_tlb_req_valid && io.tlb_port.s2_kill
tlb.io.req.valid := s1_tlb_req_valid || s1_valid && !io.cpu.s1_kill && s1_cmd_uses_tlb
tlb.io.req.bits := s1_tlb_req
when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false.B }
when (!s1_tlb_req_valid && s1_valid && s1_cmd_uses_tlb && tlb.io.resp.miss) { s1_nack := true.B }
tlb.io.sfence.valid := s1_valid && !io.cpu.s1_kill && s1_sfence
tlb.io.sfence.bits.rs1 := s1_req.size(0)
tlb.io.sfence.bits.rs2 := s1_req.size(1)
tlb.io.sfence.bits.asid := io.cpu.s1_data.data
tlb.io.sfence.bits.addr := s1_req.addr
tlb.io.sfence.bits.hv := s1_req.cmd === M_HFENCEV
tlb.io.sfence.bits.hg := s1_req.cmd === M_HFENCEG
io.tlb_port.req.ready := clock_en_reg
io.tlb_port.s1_resp := tlb.io.resp
when (s1_tlb_req_valid && s1_valid && !(s1_req.phys && s1_req.no_xcpt)) { s1_nack := true.B }
pma_checker.io <> DontCare
pma_checker.io.req.bits.passthrough := true.B
pma_checker.io.req.bits.vaddr := s1_req.addr
pma_checker.io.req.bits.size := s1_req.size
pma_checker.io.req.bits.cmd := s1_req.cmd
pma_checker.io.req.bits.prv := s1_req.dprv
pma_checker.io.req.bits.v := s1_req.dv
val s1_paddr = Cat(Mux(s1_tlb_req_valid, s1_req.addr(paddrBits-1, pgIdxBits), tlb.io.resp.paddr >> pgIdxBits), s1_req.addr(pgIdxBits-1, 0))
val s1_victim_way = Wire(UInt())
val (s1_hit_way, s1_hit_state, s1_meta) =
if (usingDataScratchpad) {
val baseAddr = p(LookupByHartId)(_.dcache.flatMap(_.scratch.map(_.U)), io_hartid.get) | io_mmio_address_prefix.get
val inScratchpad = s1_paddr >= baseAddr && s1_paddr < baseAddr + (nSets * cacheBlockBytes).U
val hitState = Mux(inScratchpad, ClientMetadata.maximum, ClientMetadata.onReset)
val dummyMeta = L1Metadata(0.U, ClientMetadata.onReset)
(inScratchpad, hitState, Seq(tECC.encode(dummyMeta.asUInt)))
} else {
val metaReq = metaArb.io.out
val metaIdx = metaReq.bits.idx
when (metaReq.valid && metaReq.bits.write) {
val wmask = if (nWays == 1) Seq(true.B) else metaReq.bits.way_en.asBools
tag_array.write(metaIdx, VecInit(Seq.fill(nWays)(metaReq.bits.data)), wmask)
}
val s1_meta = tag_array.read(metaIdx, metaReq.valid && !metaReq.bits.write)
val s1_meta_uncorrected = s1_meta.map(tECC.decode(_).uncorrected.asTypeOf(new L1Metadata))
val s1_tag = s1_paddr >> tagLSB
val s1_meta_hit_way = s1_meta_uncorrected.map(r => r.coh.isValid() && r.tag === s1_tag).asUInt
val s1_meta_hit_state = (
s1_meta_uncorrected.map(r => Mux(r.tag === s1_tag && !s1_flush_valid, r.coh.asUInt, 0.U))
.reduce (_|_)).asTypeOf(chiselTypeOf(ClientMetadata.onReset))
(s1_meta_hit_way, s1_meta_hit_state, s1_meta)
}
val s1_data_way = WireDefault(if (nWays == 1) 1.U else Mux(inWriteback, releaseWay, s1_hit_way))
val tl_d_data_encoded = Wire(chiselTypeOf(encodeData(tl_out.d.bits.data, false.B)))
val s1_all_data_ways = VecInit(data.io.resp ++ (!cacheParams.separateUncachedResp).option(tl_d_data_encoded))
val s1_mask_xwr = new StoreGen(s1_req.size, s1_req.addr, 0.U, wordBytes).mask
val s1_mask = Mux(s1_req.cmd === M_PWR, io.cpu.s1_data.mask, s1_mask_xwr)
// for partial writes, s1_data.mask must be a subset of s1_mask_xwr
assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR)
val s2_valid = RegNext(s1_valid_masked && !s1_sfence, init=false.B)
val s2_valid_no_xcpt = s2_valid && !io.cpu.s2_xcpt.asUInt.orR
val s2_probe = RegNext(s1_probe, init=false.B)
val releaseInFlight = s1_probe || s2_probe || release_state =/= s_ready
val s2_not_nacked_in_s1 = RegNext(!s1_nack)
val s2_valid_not_nacked_in_s1 = s2_valid && s2_not_nacked_in_s1
val s2_valid_masked = s2_valid_no_xcpt && s2_not_nacked_in_s1
val s2_valid_not_killed = s2_valid_masked && !io.cpu.s2_kill
val s2_req = Reg(chiselTypeOf(io.cpu.req.bits))
val s2_cmd_flush_all = s2_req.cmd === M_FLUSH_ALL && !s2_req.size(0)
val s2_cmd_flush_line = s2_req.cmd === M_FLUSH_ALL && s2_req.size(0)
val s2_tlb_xcpt = Reg(chiselTypeOf(tlb.io.resp))
val s2_pma = Reg(chiselTypeOf(tlb.io.resp))
val s2_uncached_resp_addr = Reg(chiselTypeOf(s2_req.addr)) // should be DCE'd in synthesis
when (s1_valid_not_nacked || s1_flush_valid) {
s2_req := s1_req
s2_req.addr := s1_paddr
s2_tlb_xcpt := tlb.io.resp
s2_pma := Mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp)
}
val s2_vaddr = Cat(RegEnable(s1_vaddr, s1_valid_not_nacked || s1_flush_valid) >> tagLSB, s2_req.addr(tagLSB-1, 0))
val s2_read = isRead(s2_req.cmd)
val s2_write = isWrite(s2_req.cmd)
val s2_readwrite = s2_read || s2_write
val s2_flush_valid_pre_tag_ecc = RegNext(s1_flush_valid)
val s1_meta_decoded = s1_meta.map(tECC.decode(_))
val s1_meta_clk_en = s1_valid_not_nacked || s1_flush_valid || s1_probe
val s2_meta_correctable_errors = s1_meta_decoded.map(m => RegEnable(m.correctable, s1_meta_clk_en)).asUInt
val s2_meta_uncorrectable_errors = s1_meta_decoded.map(m => RegEnable(m.uncorrectable, s1_meta_clk_en)).asUInt
val s2_meta_error_uncorrectable = s2_meta_uncorrectable_errors.orR
val s2_meta_corrected = s1_meta_decoded.map(m => RegEnable(m.corrected, s1_meta_clk_en).asTypeOf(new L1Metadata))
val s2_meta_error = (s2_meta_uncorrectable_errors | s2_meta_correctable_errors).orR
val s2_flush_valid = s2_flush_valid_pre_tag_ecc && !s2_meta_error
val s2_data = {
val wordsPerRow = rowBits / subWordBits
val en = s1_valid || inWriteback || io.cpu.replay_next
val word_en = Mux(inWriteback, Fill(wordsPerRow, 1.U), Mux(s1_did_read, s1_read_mask, 0.U))
val s1_way_words = s1_all_data_ways.map(_.grouped(dECC.width(eccBits) * (subWordBits / eccBits)))
if (cacheParams.pipelineWayMux) {
val s1_word_en = Mux(io.cpu.replay_next, 0.U, word_en)
(for (i <- 0 until wordsPerRow) yield {
val s2_way_en = RegEnable(Mux(s1_word_en(i), s1_data_way, 0.U), en)
val s2_way_words = (0 until nWays).map(j => RegEnable(s1_way_words(j)(i), en && word_en(i)))
(0 until nWays).map(j => Mux(s2_way_en(j), s2_way_words(j), 0.U)).reduce(_|_)
}).asUInt
} else {
val s1_word_en = Mux(!io.cpu.replay_next, word_en, UIntToOH(uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes)), wordsPerRow))
(for (i <- 0 until wordsPerRow) yield {
RegEnable(Mux1H(Mux(s1_word_en(i), s1_data_way, 0.U), s1_way_words.map(_(i))), en)
}).asUInt
}
}
val s2_probe_way = RegEnable(s1_hit_way, s1_probe)
val s2_probe_state = RegEnable(s1_hit_state, s1_probe)
val s2_hit_way = RegEnable(s1_hit_way, s1_valid_not_nacked)
val s2_hit_state = RegEnable(s1_hit_state, s1_valid_not_nacked || s1_flush_valid)
val s2_waw_hazard = RegEnable(s1_waw_hazard, s1_valid_not_nacked)
val s2_store_merge = Wire(Bool())
val s2_hit_valid = s2_hit_state.isValid()
val (s2_hit, s2_grow_param, s2_new_hit_state) = s2_hit_state.onAccess(s2_req.cmd)
val s2_data_decoded = decodeData(s2_data)
val s2_word_idx = s2_req.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes))
val s2_data_error = s2_data_decoded.map(_.error).orR
val s2_data_error_uncorrectable = s2_data_decoded.map(_.uncorrectable).orR
val s2_data_corrected = (s2_data_decoded.map(_.corrected): Seq[UInt]).asUInt
val s2_data_uncorrected = (s2_data_decoded.map(_.uncorrected): Seq[UInt]).asUInt
val s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = s2_valid_masked && !s2_meta_error && s2_hit
val s2_no_alloc_hazard = if (!usingVM || pgIdxBits >= untagBits) false.B else {
// make sure that any in-flight non-allocating accesses are ordered before
// any allocating accesses. this can only happen if aliasing is possible.
val any_no_alloc_in_flight = Reg(Bool())
when (!uncachedInFlight.asUInt.orR) { any_no_alloc_in_flight := false.B }
when (s2_valid && s2_req.no_alloc) { any_no_alloc_in_flight := true.B }
val s1_need_check = any_no_alloc_in_flight || s2_valid && s2_req.no_alloc
val concerns = (uncachedInFlight zip uncachedReqs) :+ (s2_valid && s2_req.no_alloc, s2_req)
val s1_uncached_hits = concerns.map { c =>
val concern_wmask = new StoreGen(c._2.size, c._2.addr, 0.U, wordBytes).mask
val addr_match = (c._2.addr ^ s1_paddr)(pgIdxBits+pgLevelBits-1, wordBytes.log2) === 0.U
val mask_match = (concern_wmask & s1_mask_xwr).orR || c._2.cmd === M_PWR || s1_req.cmd === M_PWR
val cmd_match = isWrite(c._2.cmd) || isWrite(s1_req.cmd)
c._1 && s1_need_check && cmd_match && addr_match && mask_match
}
val s2_uncached_hits = RegEnable(s1_uncached_hits.asUInt, s1_valid_not_nacked)
s2_uncached_hits.orR
}
val s2_valid_hit_pre_data_ecc_and_waw = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_readwrite && !s2_no_alloc_hazard
val s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw && s2_cmd_flush_line
val s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw && (!s2_waw_hazard || s2_store_merge)
val s2_valid_data_error = s2_valid_hit_pre_data_ecc_and_waw && s2_data_error
val s2_valid_hit = s2_valid_hit_pre_data_ecc && !s2_data_error
val s2_valid_miss = s2_valid_masked && s2_readwrite && !s2_meta_error && !s2_hit
val s2_uncached = !s2_pma.cacheable || s2_req.no_alloc && !s2_pma.must_alloc && !s2_hit_valid
val s2_valid_cached_miss = s2_valid_miss && !s2_uncached && !uncachedInFlight.asUInt.orR
dontTouch(s2_valid_cached_miss)
val s2_want_victimize = (!usingDataScratchpad).B && (s2_valid_cached_miss || s2_valid_flush_line || s2_valid_data_error || s2_flush_valid)
val s2_cannot_victimize = !s2_flush_valid && io.cpu.s2_kill
val s2_victimize = s2_want_victimize && !s2_cannot_victimize
val s2_valid_uncached_pending = s2_valid_miss && s2_uncached && !uncachedInFlight.asUInt.andR
val s2_victim_way = UIntToOH(RegEnable(s1_victim_way, s1_valid_not_nacked || s1_flush_valid))
val s2_victim_or_hit_way = Mux(s2_hit_valid, s2_hit_way, s2_victim_way)
val s2_victim_tag = Mux(s2_valid_data_error || s2_valid_flush_line, s2_req.addr(paddrBits-1, tagLSB), Mux1H(s2_victim_way, s2_meta_corrected).tag)
val s2_victim_state = Mux(s2_hit_valid, s2_hit_state, Mux1H(s2_victim_way, s2_meta_corrected).coh)
val (s2_prb_ack_data, s2_report_param, probeNewCoh)= s2_probe_state.onProbe(probe_bits.param)
val (s2_victim_dirty, s2_shrink_param, voluntaryNewCoh) = s2_victim_state.onCacheControl(M_FLUSH)
dontTouch(s2_victim_dirty)
val s2_update_meta = s2_hit_state =/= s2_new_hit_state
val s2_dont_nack_uncached = s2_valid_uncached_pending && tl_out_a.ready
val s2_dont_nack_misc = s2_valid_masked && !s2_meta_error &&
(supports_flush.B && s2_cmd_flush_all && flushed && !flushing ||
supports_flush.B && s2_cmd_flush_line && !s2_hit ||
s2_req.cmd === M_WOK)
io.cpu.s2_nack := s2_valid_no_xcpt && !s2_dont_nack_uncached && !s2_dont_nack_misc && !s2_valid_hit
when (io.cpu.s2_nack || (s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta)) { s1_nack := true.B }
// tag updates on ECC errors
val s2_first_meta_corrected = PriorityMux(s2_meta_correctable_errors, s2_meta_corrected)
metaArb.io.in(1).valid := s2_meta_error && (s2_valid_masked || s2_flush_valid_pre_tag_ecc || s2_probe)
metaArb.io.in(1).bits.write := true.B
metaArb.io.in(1).bits.way_en := s2_meta_uncorrectable_errors | Mux(s2_meta_error_uncorrectable, 0.U, PriorityEncoderOH(s2_meta_correctable_errors))
metaArb.io.in(1).bits.idx := Mux(s2_probe, probeIdx(probe_bits), s2_vaddr(idxMSB, idxLSB))
metaArb.io.in(1).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(1).bits.idx << blockOffBits)
metaArb.io.in(1).bits.data := tECC.encode {
val new_meta = WireDefault(s2_first_meta_corrected)
when (s2_meta_error_uncorrectable) { new_meta.coh := ClientMetadata.onReset }
new_meta.asUInt
}
// tag updates on hit
metaArb.io.in(2).valid := s2_valid_hit_pre_data_ecc_and_waw && s2_update_meta
metaArb.io.in(2).bits.write := !io.cpu.s2_kill
metaArb.io.in(2).bits.way_en := s2_victim_or_hit_way
metaArb.io.in(2).bits.idx := s2_vaddr(idxMSB, idxLSB)
metaArb.io.in(2).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0))
metaArb.io.in(2).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_new_hit_state).asUInt)
// load reservations and TL error reporting
val s2_lr = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XLR
val s2_sc = (usingAtomics && !usingDataScratchpad).B && s2_req.cmd === M_XSC
val lrscCount = RegInit(0.U)
val lrscValid = lrscCount > lrscBackoff.U
val lrscBackingOff = lrscCount > 0.U && !lrscValid
val lrscAddr = Reg(UInt())
val lrscAddrMatch = lrscAddr === (s2_req.addr >> blockOffBits)
val s2_sc_fail = s2_sc && !(lrscValid && lrscAddrMatch)
when ((s2_valid_hit && s2_lr && !cached_grant_wait || s2_valid_cached_miss) && !io.cpu.s2_kill) {
lrscCount := Mux(s2_hit, (lrscCycles - 1).U, 0.U)
lrscAddr := s2_req.addr >> blockOffBits
}
when (lrscCount > 0.U) { lrscCount := lrscCount - 1.U }
when (s2_valid_not_killed && lrscValid) { lrscCount := lrscBackoff.U }
when (s1_probe) { lrscCount := 0.U }
// don't perform data correction if it might clobber a recent store
val s2_correct = s2_data_error && !any_pstore_valid && !RegNext(any_pstore_valid || s2_valid) && usingDataScratchpad.B
// pending store buffer
val s2_valid_correct = s2_valid_hit_pre_data_ecc_and_waw && s2_correct && !io.cpu.s2_kill
def s2_store_valid_pre_kill = s2_valid_hit && s2_write && !s2_sc_fail
def s2_store_valid = s2_store_valid_pre_kill && !io.cpu.s2_kill
val pstore1_cmd = RegEnable(s1_req.cmd, s1_valid_not_nacked && s1_write)
val pstore1_addr = RegEnable(s1_vaddr, s1_valid_not_nacked && s1_write)
val pstore1_data = RegEnable(io.cpu.s1_data.data, s1_valid_not_nacked && s1_write)
val pstore1_way = RegEnable(s1_hit_way, s1_valid_not_nacked && s1_write)
val pstore1_mask = RegEnable(s1_mask, s1_valid_not_nacked && s1_write)
val pstore1_storegen_data = WireDefault(pstore1_data)
val pstore1_rmw = usingRMW.B && RegEnable(needsRead(s1_req), s1_valid_not_nacked && s1_write)
val pstore1_merge_likely = s2_valid_not_nacked_in_s1 && s2_write && s2_store_merge
val pstore1_merge = s2_store_valid && s2_store_merge
val pstore2_valid = RegInit(false.B)
val pstore_drain_opportunistic = !(io.cpu.req.valid && likelyNeedsRead(io.cpu.req.bits)) && !(s1_valid && s1_waw_hazard)
val pstore_drain_on_miss = releaseInFlight || RegNext(io.cpu.s2_nack)
val pstore1_held = RegInit(false.B)
val pstore1_valid_likely = s2_valid && s2_write || pstore1_held
def pstore1_valid_not_rmw(s2_kill: Bool) = s2_valid_hit_pre_data_ecc && s2_write && !s2_kill || pstore1_held
val pstore1_valid = s2_store_valid || pstore1_held
any_pstore_valid := pstore1_held || pstore2_valid
val pstore_drain_structural = pstore1_valid_likely && pstore2_valid && ((s1_valid && s1_write) || pstore1_rmw)
assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid)
ccover(pstore_drain_structural, "STORE_STRUCTURAL_HAZARD", "D$ read-modify-write structural hazard")
ccover(pstore1_valid && pstore_drain_on_miss, "STORE_DRAIN_ON_MISS", "D$ store buffer drain on miss")
ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard")
def should_pstore_drain(truly: Bool) = {
val s2_kill = truly && io.cpu.s2_kill
!pstore1_merge_likely &&
(usingRMW.B && pstore_drain_structural ||
(((pstore1_valid_not_rmw(s2_kill) && !pstore1_rmw) || pstore2_valid) && (pstore_drain_opportunistic || pstore_drain_on_miss)))
}
val pstore_drain = should_pstore_drain(true.B)
pstore1_held := (s2_store_valid && !s2_store_merge || pstore1_held) && pstore2_valid && !pstore_drain
val advance_pstore1 = (pstore1_valid || s2_valid_correct) && (pstore2_valid === pstore_drain)
pstore2_valid := pstore2_valid && !pstore_drain || advance_pstore1
val pstore2_addr = RegEnable(Mux(s2_correct, s2_vaddr, pstore1_addr), advance_pstore1)
val pstore2_way = RegEnable(Mux(s2_correct, s2_hit_way, pstore1_way), advance_pstore1)
val pstore2_storegen_data = {
for (i <- 0 until wordBytes)
yield RegEnable(pstore1_storegen_data(8*(i+1)-1, 8*i), advance_pstore1 || pstore1_merge && pstore1_mask(i))
}.asUInt
val pstore2_storegen_mask = {
val mask = Reg(UInt(wordBytes.W))
when (advance_pstore1 || pstore1_merge) {
val mergedMask = pstore1_mask | Mux(pstore1_merge, mask, 0.U)
mask := ~Mux(s2_correct, 0.U, ~mergedMask)
}
mask
}
s2_store_merge := (if (eccBytes == 1) false.B else {
ccover(pstore1_merge, "STORE_MERGED", "D$ store merged")
// only merge stores to ECC granules that are already stored-to, to avoid
// WAW hazards
val wordMatch = (eccMask(pstore2_storegen_mask) | ~eccMask(pstore1_mask)).andR
val idxMatch = s2_vaddr(untagBits-1, log2Ceil(wordBytes)) === pstore2_addr(untagBits-1, log2Ceil(wordBytes))
val tagMatch = (s2_hit_way & pstore2_way).orR
pstore2_valid && wordMatch && idxMatch && tagMatch
})
dataArb.io.in(0).valid := should_pstore_drain(false.B)
dataArb.io.in(0).bits.write := pstore_drain
dataArb.io.in(0).bits.addr := Mux(pstore2_valid, pstore2_addr, pstore1_addr)
dataArb.io.in(0).bits.way_en := Mux(pstore2_valid, pstore2_way, pstore1_way)
dataArb.io.in(0).bits.wdata := encodeData(Fill(rowWords, Mux(pstore2_valid, pstore2_storegen_data, pstore1_data)), false.B)
dataArb.io.in(0).bits.wordMask := {
val eccMask = dataArb.io.in(0).bits.eccMask.asBools.grouped(subWordBytes/eccBytes).map(_.orR).toSeq.asUInt
val wordMask = UIntToOH(Mux(pstore2_valid, pstore2_addr, pstore1_addr).extract(rowOffBits-1, wordBytes.log2))
FillInterleaved(wordBytes/subWordBytes, wordMask) & Fill(rowBytes/wordBytes, eccMask)
}
dataArb.io.in(0).bits.eccMask := eccMask(Mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask))
// store->load RAW hazard detection
def s1Depends(addr: UInt, mask: UInt) =
addr(idxMSB, wordOffBits) === s1_vaddr(idxMSB, wordOffBits) &&
Mux(s1_write, (eccByteMask(mask) & eccByteMask(s1_mask_xwr)).orR, (mask & s1_mask_xwr).orR)
val s1_hazard =
(pstore1_valid_likely && s1Depends(pstore1_addr, pstore1_mask)) ||
(pstore2_valid && s1Depends(pstore2_addr, pstore2_storegen_mask))
val s1_raw_hazard = s1_read && s1_hazard
s1_waw_hazard := (if (eccBytes == 1) false.B else {
ccover(s1_valid_not_nacked && s1_waw_hazard, "WAW_HAZARD", "D$ write-after-write hazard")
s1_write && (s1_hazard || needsRead(s1_req) && !s1_did_read)
})
when (s1_valid && s1_raw_hazard) { s1_nack := true.B }
// performance hints to processor
io.cpu.s2_nack_cause_raw := RegNext(s1_raw_hazard) || !(!s2_waw_hazard || s2_store_merge)
// Prepare a TileLink request message that initiates a transaction
val a_source = PriorityEncoder(~uncachedInFlight.asUInt << mmioOffset) // skip the MSHR
val acquire_address = (s2_req.addr >> idxLSB) << idxLSB
val access_address = s2_req.addr
val a_size = s2_req.size
val a_data = Fill(beatWords, pstore1_data)
val a_mask = pstore1_mask << (access_address.extract(beatBytes.log2-1, wordBytes.log2) << 3)
val get = edge.Get(a_source, access_address, a_size)._2
val put = edge.Put(a_source, access_address, a_size, a_data)._2
val putpartial = edge.Put(a_source, access_address, a_size, a_data, a_mask)._2
val atomics = if (edge.manager.anySupportLogical) {
MuxLookup(s2_req.cmd, WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle))))(Array(
M_XA_SWAP -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.SWAP)._2,
M_XA_XOR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.XOR) ._2,
M_XA_OR -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.OR) ._2,
M_XA_AND -> edge.Logical(a_source, access_address, a_size, a_data, TLAtomics.AND) ._2,
M_XA_ADD -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.ADD)._2,
M_XA_MIN -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MIN)._2,
M_XA_MAX -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAX)._2,
M_XA_MINU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MINU)._2,
M_XA_MAXU -> edge.Arithmetic(a_source, access_address, a_size, a_data, TLAtomics.MAXU)._2))
} else {
// If no managers support atomics, assert fail if processor asks for them
assert (!(tl_out_a.valid && s2_read && s2_write && s2_uncached))
WireDefault(new TLBundleA(edge.bundle), DontCare)
}
tl_out_a.valid := !io.cpu.s2_kill &&
(s2_valid_uncached_pending ||
(s2_valid_cached_miss &&
!(release_ack_wait && (s2_req.addr ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U) &&
(cacheParams.acquireBeforeRelease.B && !release_ack_wait && release_queue_empty || !s2_victim_dirty)))
tl_out_a.bits := Mux(!s2_uncached, acquire(s2_vaddr, s2_req.addr, s2_grow_param),
Mux(!s2_write, get,
Mux(s2_req.cmd === M_PWR, putpartial,
Mux(!s2_read, put, atomics))))
// Drive APROT Bits
tl_out_a.bits.user.lift(AMBAProt).foreach { x =>
val user_bit_cacheable = s2_pma.cacheable
x.privileged := s2_req.dprv === PRV.M.U || user_bit_cacheable
// if the address is cacheable, enable outer caches
x.bufferable := user_bit_cacheable
x.modifiable := user_bit_cacheable
x.readalloc := user_bit_cacheable
x.writealloc := user_bit_cacheable
// Following are always tied off
x.fetch := false.B
x.secure := true.B
}
// Set pending bits for outstanding TileLink transaction
val a_sel = UIntToOH(a_source, maxUncachedInFlight+mmioOffset) >> mmioOffset
when (tl_out_a.fire) {
when (s2_uncached) {
(a_sel.asBools zip (uncachedInFlight zip uncachedReqs)) foreach { case (s, (f, r)) =>
when (s) {
f := true.B
r := s2_req
r.cmd := Mux(s2_write, Mux(s2_req.cmd === M_PWR, M_PWR, M_XWR), M_XRD)
}
}
}.otherwise {
cached_grant_wait := true.B
refill_way := s2_victim_or_hit_way
}
}
// grant
val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d)
val (d_opc, grantIsUncached, grantIsUncachedData) = {
val uncachedGrantOpcodesSansData = Seq(AccessAck, HintAck)
val uncachedGrantOpcodesWithData = Seq(AccessAckData)
val uncachedGrantOpcodes = uncachedGrantOpcodesWithData ++ uncachedGrantOpcodesSansData
val whole_opc = tl_out.d.bits.opcode
if (usingDataScratchpad) {
assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes))
// the only valid TL-D messages are uncached, so we can do some pruning
val opc = whole_opc(uncachedGrantOpcodes.map(_.getWidth).max - 1, 0)
val data = DecodeLogic(opc, uncachedGrantOpcodesWithData, uncachedGrantOpcodesSansData)
(opc, true.B, data)
} else {
(whole_opc, whole_opc.isOneOf(uncachedGrantOpcodes), whole_opc.isOneOf(uncachedGrantOpcodesWithData))
}
}
tl_d_data_encoded := encodeData(tl_out.d.bits.data, tl_out.d.bits.corrupt && !io.ptw.customCSRs.suppressCorruptOnGrantData && !grantIsUncached)
val grantIsCached = d_opc.isOneOf(Grant, GrantData)
val grantIsVoluntary = d_opc === ReleaseAck // Clears a different pending bit
val grantIsRefill = d_opc === GrantData // Writes the data array
val grantInProgress = RegInit(false.B)
val blockProbeAfterGrantCount = RegInit(0.U)
when (blockProbeAfterGrantCount > 0.U) { blockProbeAfterGrantCount := blockProbeAfterGrantCount - 1.U }
val canAcceptCachedGrant = !release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)
tl_out.d.ready := Mux(grantIsCached, (!d_first || tl_out.e.ready) && canAcceptCachedGrant, true.B)
val uncachedRespIdxOH = UIntToOH(tl_out.d.bits.source, maxUncachedInFlight+mmioOffset) >> mmioOffset
uncachedResp := Mux1H(uncachedRespIdxOH, uncachedReqs)
when (tl_out.d.fire) {
when (grantIsCached) {
grantInProgress := true.B
assert(cached_grant_wait, "A GrantData was unexpected by the dcache.")
when(d_last) {
cached_grant_wait := false.B
grantInProgress := false.B
blockProbeAfterGrantCount := (blockProbeAfterGrantCycles - 1).U
replacer.miss
}
} .elsewhen (grantIsUncached) {
(uncachedRespIdxOH.asBools zip uncachedInFlight) foreach { case (s, f) =>
when (s && d_last) {
assert(f, "An AccessAck was unexpected by the dcache.") // TODO must handle Ack coming back on same cycle!
f := false.B
}
}
when (grantIsUncachedData) {
if (!cacheParams.separateUncachedResp) {
if (!cacheParams.pipelineWayMux)
s1_data_way := 1.U << nWays
s2_req.cmd := M_XRD
s2_req.size := uncachedResp.size
s2_req.signed := uncachedResp.signed
s2_req.tag := uncachedResp.tag
s2_req.addr := {
require(rowOffBits >= beatOffBits)
val dontCareBits = s1_paddr >> rowOffBits << rowOffBits
dontCareBits | uncachedResp.addr(beatOffBits-1, 0)
}
s2_uncached_resp_addr := uncachedResp.addr
}
}
} .elsewhen (grantIsVoluntary) {
assert(release_ack_wait, "A ReleaseAck was unexpected by the dcache.") // TODO should handle Ack coming back on same cycle!
release_ack_wait := false.B
}
}
// Finish TileLink transaction by issuing a GrantAck
tl_out.e.valid := tl_out.d.valid && d_first && grantIsCached && canAcceptCachedGrant
tl_out.e.bits := edge.GrantAck(tl_out.d.bits)
assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached))
// data refill
// note this ready-valid signaling ignores E-channel backpressure, which
// benignly means the data RAM might occasionally be redundantly written
dataArb.io.in(1).valid := tl_out.d.valid && grantIsRefill && canAcceptCachedGrant
when (grantIsRefill && !dataArb.io.in(1).ready) {
tl_out.e.valid := false.B
tl_out.d.ready := false.B
}
if (!usingDataScratchpad) {
dataArb.io.in(1).bits.write := true.B
dataArb.io.in(1).bits.addr := (s2_vaddr >> idxLSB) << idxLSB | d_address_inc
dataArb.io.in(1).bits.way_en := refill_way
dataArb.io.in(1).bits.wdata := tl_d_data_encoded
dataArb.io.in(1).bits.wordMask := ~0.U((rowBytes / subWordBytes).W)
dataArb.io.in(1).bits.eccMask := ~0.U((wordBytes / eccBytes).W)
} else {
dataArb.io.in(1).bits := dataArb.io.in(0).bits
}
// tag updates on refill
// ignore backpressure from metaArb, which can only be caused by tag ECC
// errors on hit-under-miss. failing to write the new tag will leave the
// line invalid, so we'll simply request the line again later.
metaArb.io.in(3).valid := grantIsCached && d_done && !tl_out.d.bits.denied
metaArb.io.in(3).bits.write := true.B
metaArb.io.in(3).bits.way_en := refill_way
metaArb.io.in(3).bits.idx := s2_vaddr(idxMSB, idxLSB)
metaArb.io.in(3).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, s2_vaddr(idxMSB, 0))
metaArb.io.in(3).bits.data := tECC.encode(L1Metadata(s2_req.addr >> tagLSB, s2_hit_state.onGrant(s2_req.cmd, tl_out.d.bits.param)).asUInt)
if (!cacheParams.separateUncachedResp) {
// don't accept uncached grants if there's a structural hazard on s2_data...
val blockUncachedGrant = Reg(Bool())
blockUncachedGrant := dataArb.io.out.valid
when (grantIsUncachedData && (blockUncachedGrant || s1_valid)) {
tl_out.d.ready := false.B
// ...but insert bubble to guarantee grant's eventual forward progress
when (tl_out.d.valid) {
io.cpu.req.ready := false.B
dataArb.io.in(1).valid := true.B
dataArb.io.in(1).bits.write := false.B
blockUncachedGrant := !dataArb.io.in(1).ready
}
}
}
ccover(tl_out.d.valid && !tl_out.d.ready, "BLOCK_D", "D$ D-channel blocked")
// Handle an incoming TileLink Probe message
val block_probe_for_core_progress = blockProbeAfterGrantCount > 0.U || lrscValid
val block_probe_for_pending_release_ack = release_ack_wait && (tl_out.b.bits.address ^ release_ack_addr)(((pgIdxBits + pgLevelBits) min paddrBits) - 1, idxLSB) === 0.U
val block_probe_for_ordering = releaseInFlight || block_probe_for_pending_release_ack || grantInProgress
metaArb.io.in(6).valid := tl_out.b.valid && (!block_probe_for_core_progress || lrscBackingOff)
tl_out.b.ready := metaArb.io.in(6).ready && !(block_probe_for_core_progress || block_probe_for_ordering || s1_valid || s2_valid)
metaArb.io.in(6).bits.write := false.B
metaArb.io.in(6).bits.idx := probeIdx(tl_out.b.bits)
metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, tl_out.b.bits.address)
metaArb.io.in(6).bits.way_en := metaArb.io.in(4).bits.way_en
metaArb.io.in(6).bits.data := metaArb.io.in(4).bits.data
// replacement policy
s1_victim_way := (if (replacer.perSet && nWays > 1) {
val repl_array = Mem(nSets, UInt(replacer.nBits.W))
val s1_repl_idx = s1_req.addr(idxBits+blockOffBits-1, blockOffBits)
val s2_repl_idx = s2_vaddr(idxBits+blockOffBits-1, blockOffBits)
val s2_repl_state = Reg(UInt(replacer.nBits.W))
val s2_new_repl_state = replacer.get_next_state(s2_repl_state, OHToUInt(s2_hit_way))
val s2_repl_wen = s2_valid_masked && s2_hit_way.orR && s2_repl_state =/= s2_new_repl_state
val s1_repl_state = Mux(s2_repl_wen && s2_repl_idx === s1_repl_idx, s2_new_repl_state, repl_array(s1_repl_idx))
when (s1_valid_not_nacked) { s2_repl_state := s1_repl_state }
val waddr = Mux(resetting, flushCounter(idxBits-1, 0), s2_repl_idx)
val wdata = Mux(resetting, 0.U, s2_new_repl_state)
val wen = resetting || s2_repl_wen
when (wen) { repl_array(waddr) := wdata }
replacer.get_replace_way(s1_repl_state)
} else {
replacer.way
})
// release
val (c_first, c_last, releaseDone, c_count) = edge.count(tl_out_c)
val releaseRejected = Wire(Bool())
val s1_release_data_valid = RegNext(dataArb.io.in(2).fire)
val s2_release_data_valid = RegNext(s1_release_data_valid && !releaseRejected)
releaseRejected := s2_release_data_valid && !tl_out_c.fire
val releaseDataBeat = Cat(0.U, c_count) + Mux(releaseRejected, 0.U, s1_release_data_valid + Cat(0.U, s2_release_data_valid))
val nackResponseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = TLPermissions.NtoN)
val cleanReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param)
val dirtyReleaseMessage = edge.ProbeAck(b = probe_bits, reportPermissions = s2_report_param, data = 0.U)
tl_out_c.valid := (s2_release_data_valid || (!cacheParams.silentDrop.B && release_state === s_voluntary_release)) && !(c_first && release_ack_wait)
tl_out_c.bits := nackResponseMessage
val newCoh = WireDefault(probeNewCoh)
releaseWay := s2_probe_way
if (!usingDataScratchpad) {
when (s2_victimize) {
assert(s2_valid_flush_line || s2_flush_valid || io.cpu.s2_nack)
val discard_line = s2_valid_flush_line && s2_req.size(1) || s2_flush_valid && flushing_req.size(1)
release_state := Mux(s2_victim_dirty && !discard_line, s_voluntary_writeback,
Mux(!cacheParams.silentDrop.B && !release_ack_wait && release_queue_empty && s2_victim_state.isValid() && (s2_valid_flush_line || s2_flush_valid || s2_readwrite && !s2_hit_valid), s_voluntary_release,
s_voluntary_write_meta))
probe_bits := addressToProbe(s2_vaddr, Cat(s2_victim_tag, s2_req.addr(tagLSB-1, idxLSB)) << idxLSB)
}
when (s2_probe) {
val probeNack = WireDefault(true.B)
when (s2_meta_error) {
release_state := s_probe_retry
}.elsewhen (s2_prb_ack_data) {
release_state := s_probe_rep_dirty
}.elsewhen (s2_probe_state.isValid()) {
tl_out_c.valid := true.B
tl_out_c.bits := cleanReleaseMessage
release_state := Mux(releaseDone, s_probe_write_meta, s_probe_rep_clean)
}.otherwise {
tl_out_c.valid := true.B
probeNack := !releaseDone
release_state := Mux(releaseDone, s_ready, s_probe_rep_miss)
}
when (probeNack) { s1_nack := true.B }
}
when (release_state === s_probe_retry) {
metaArb.io.in(6).valid := true.B
metaArb.io.in(6).bits.idx := probeIdx(probe_bits)
metaArb.io.in(6).bits.addr := Cat(io.cpu.req.bits.addr >> paddrBits, probe_bits.address)
when (metaArb.io.in(6).ready) {
release_state := s_ready
s1_probe := true.B
}
}
when (release_state === s_probe_rep_miss) {
tl_out_c.valid := true.B
when (releaseDone) { release_state := s_ready }
}
when (release_state === s_probe_rep_clean) {
tl_out_c.valid := true.B
tl_out_c.bits := cleanReleaseMessage
when (releaseDone) { release_state := s_probe_write_meta }
}
when (release_state === s_probe_rep_dirty) {
tl_out_c.bits := dirtyReleaseMessage
when (releaseDone) { release_state := s_probe_write_meta }
}
when (release_state.isOneOf(s_voluntary_writeback, s_voluntary_write_meta, s_voluntary_release)) {
when (release_state === s_voluntary_release) {
tl_out_c.bits := edge.Release(fromSource = 0.U,
toAddress = 0.U,
lgSize = lgCacheBlockBytes.U,
shrinkPermissions = s2_shrink_param)._2
}.otherwise {
tl_out_c.bits := edge.Release(fromSource = 0.U,
toAddress = 0.U,
lgSize = lgCacheBlockBytes.U,
shrinkPermissions = s2_shrink_param,
data = 0.U)._2
}
newCoh := voluntaryNewCoh
releaseWay := s2_victim_or_hit_way
when (releaseDone) { release_state := s_voluntary_write_meta }
when (tl_out_c.fire && c_first) {
release_ack_wait := true.B
release_ack_addr := probe_bits.address
}
}
tl_out_c.bits.source := probe_bits.source
tl_out_c.bits.address := probe_bits.address
tl_out_c.bits.data := s2_data_corrected
tl_out_c.bits.corrupt := inWriteback && s2_data_error_uncorrectable
}
tl_out_c.bits.user.lift(AMBAProt).foreach { x =>
x.fetch := false.B
x.secure := true.B
x.privileged := true.B
x.bufferable := true.B
x.modifiable := true.B
x.readalloc := true.B
x.writealloc := true.B
}
dataArb.io.in(2).valid := inWriteback && releaseDataBeat < refillCycles.U
dataArb.io.in(2).bits := dataArb.io.in(1).bits
dataArb.io.in(2).bits.write := false.B
dataArb.io.in(2).bits.addr := (probeIdx(probe_bits) << blockOffBits) | (releaseDataBeat(log2Up(refillCycles)-1,0) << rowOffBits)
dataArb.io.in(2).bits.wordMask := ~0.U((rowBytes / subWordBytes).W)
dataArb.io.in(2).bits.eccMask := ~0.U((wordBytes / eccBytes).W)
dataArb.io.in(2).bits.way_en := ~0.U(nWays.W)
metaArb.io.in(4).valid := release_state.isOneOf(s_voluntary_write_meta, s_probe_write_meta)
metaArb.io.in(4).bits.write := true.B
metaArb.io.in(4).bits.way_en := releaseWay
metaArb.io.in(4).bits.idx := probeIdx(probe_bits)
metaArb.io.in(4).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, probe_bits.address(idxMSB, 0))
metaArb.io.in(4).bits.data := tECC.encode(L1Metadata(tl_out_c.bits.address >> tagLSB, newCoh).asUInt)
when (metaArb.io.in(4).fire) { release_state := s_ready }
// cached response
(io.cpu.resp.bits: Data).waiveAll :<>= (s2_req: Data).waiveAll
io.cpu.resp.bits.has_data := s2_read
io.cpu.resp.bits.replay := false.B
io.cpu.s2_uncached := s2_uncached && !s2_hit
io.cpu.s2_paddr := s2_req.addr
io.cpu.s2_gpa := s2_tlb_xcpt.gpa
io.cpu.s2_gpa_is_pte := s2_tlb_xcpt.gpa_is_pte
// report whether there are any outstanding accesses. disregard any
// slave-port accesses, since they don't affect local memory ordering.
val s1_isSlavePortAccess = s1_req.no_xcpt
val s2_isSlavePortAccess = s2_req.no_xcpt
io.cpu.ordered := !(s1_valid && !s1_isSlavePortAccess || s2_valid && !s2_isSlavePortAccess || cached_grant_wait || uncachedInFlight.asUInt.orR)
io.cpu.store_pending := (cached_grant_wait && isWrite(s2_req.cmd)) || uncachedInFlight.asUInt.orR
val s1_xcpt_valid = tlb.io.req.valid && !s1_isSlavePortAccess && !s1_nack
io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), s2_tlb_xcpt, 0.U.asTypeOf(s2_tlb_xcpt))
if (usingDataScratchpad) {
assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC)))
} else {
ccover(tl_out.b.valid && !tl_out.b.ready, "BLOCK_B", "D$ B-channel blocked")
}
// uncached response
val s1_uncached_data_word = {
val word_idx = uncachedResp.addr.extract(log2Up(rowBits/8)-1, log2Up(wordBytes))
val words = tl_out.d.bits.data.grouped(wordBits)
words(word_idx)
}
val s2_uncached_data_word = RegEnable(s1_uncached_data_word, io.cpu.replay_next)
val doUncachedResp = RegNext(io.cpu.replay_next)
io.cpu.resp.valid := (s2_valid_hit_pre_data_ecc || doUncachedResp) && !s2_data_error
io.cpu.replay_next := tl_out.d.fire && grantIsUncachedData && !cacheParams.separateUncachedResp.B
when (doUncachedResp) {
assert(!s2_valid_hit)
io.cpu.resp.bits.replay := true.B
io.cpu.resp.bits.addr := s2_uncached_resp_addr
}
io.cpu.uncached_resp.map { resp =>
resp.valid := tl_out.d.valid && grantIsUncachedData
resp.bits.tag := uncachedResp.tag
resp.bits.size := uncachedResp.size
resp.bits.signed := uncachedResp.signed
resp.bits.data := new LoadGen(uncachedResp.size, uncachedResp.signed, uncachedResp.addr, s1_uncached_data_word, false.B, wordBytes).data
resp.bits.data_raw := s1_uncached_data_word
when (grantIsUncachedData && !resp.ready) {
tl_out.d.ready := false.B
}
}
// load data subword mux/sign extension
val s2_data_word = (0 until rowBits by wordBits).map(i => s2_data_uncorrected(wordBits+i-1,i)).reduce(_|_)
val s2_data_word_corrected = (0 until rowBits by wordBits).map(i => s2_data_corrected(wordBits+i-1,i)).reduce(_|_)
val s2_data_word_possibly_uncached = Mux(cacheParams.pipelineWayMux.B && doUncachedResp, s2_uncached_data_word, 0.U) | s2_data_word
val loadgen = new LoadGen(s2_req.size, s2_req.signed, s2_req.addr, s2_data_word_possibly_uncached, s2_sc, wordBytes)
io.cpu.resp.bits.data := loadgen.data | s2_sc_fail
io.cpu.resp.bits.data_word_bypass := loadgen.wordData
io.cpu.resp.bits.data_raw := s2_data_word
io.cpu.resp.bits.store_data := pstore1_data
// AMOs
if (usingRMW) {
val amoalus = (0 until coreDataBits / xLen).map { i =>
val amoalu = Module(new AMOALU(xLen))
amoalu.io.mask := pstore1_mask >> (i * xBytes)
amoalu.io.cmd := (if (usingAtomicsInCache) pstore1_cmd else M_XWR)
amoalu.io.lhs := s2_data_word >> (i * xLen)
amoalu.io.rhs := pstore1_data >> (i * xLen)
amoalu
}
pstore1_storegen_data := (if (!usingDataScratchpad) amoalus.map(_.io.out).asUInt else {
val mask = FillInterleaved(8, Mux(s2_correct, 0.U, pstore1_mask))
amoalus.map(_.io.out_unmasked).asUInt & mask | s2_data_word_corrected & ~mask
})
} else if (!usingAtomics) {
assert(!(s1_valid_masked && s1_read && s1_write), "unsupported D$ operation")
}
if (coreParams.useVector) {
edge.manager.managers.foreach { m =>
// Statically ensure that no-allocate accesses are permitted.
// We could consider turning some of these into dynamic PMA checks.
require(!m.supportsAcquireB || m.supportsGet, "With a vector unit, cacheable memory must support Get")
require(!m.supportsAcquireT || m.supportsPutPartial, "With a vector unit, cacheable memory must support PutPartial")
}
}
// flushes
if (!usingDataScratchpad)
when (RegNext(reset.asBool)) { resetting := true.B }
val flushCounterNext = flushCounter +& 1.U
val flushDone = (flushCounterNext >> log2Ceil(nSets)) === nWays.U
val flushCounterWrap = flushCounterNext(log2Ceil(nSets)-1, 0)
ccover(s2_valid_masked && s2_cmd_flush_all && s2_meta_error, "TAG_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in tag array during cache flush")
ccover(s2_valid_masked && s2_cmd_flush_all && s2_data_error, "DATA_ECC_ERROR_DURING_FENCE_I", "D$ ECC error in data array during cache flush")
s1_flush_valid := metaArb.io.in(5).fire && !s1_flush_valid && !s2_flush_valid_pre_tag_ecc && release_state === s_ready && !release_ack_wait
metaArb.io.in(5).valid := flushing && !flushed
metaArb.io.in(5).bits.write := false.B
metaArb.io.in(5).bits.idx := flushCounter(idxBits-1, 0)
metaArb.io.in(5).bits.addr := Cat(io.cpu.req.bits.addr >> untagBits, metaArb.io.in(5).bits.idx << blockOffBits)
metaArb.io.in(5).bits.way_en := metaArb.io.in(4).bits.way_en
metaArb.io.in(5).bits.data := metaArb.io.in(4).bits.data
// Only flush D$ on FENCE.I if some cached executable regions are untracked.
if (supports_flush) {
when (s2_valid_masked && s2_cmd_flush_all) {
when (!flushed && !io.cpu.s2_kill && !release_ack_wait && !uncachedInFlight.asUInt.orR) {
flushing := true.B
flushing_req := s2_req
}
}
when (tl_out_a.fire && !s2_uncached) { flushed := false.B }
when (flushing) {
s1_victim_way := flushCounter >> log2Up(nSets)
when (s2_flush_valid) {
flushCounter := flushCounterNext
when (flushDone) {
flushed := true.B
if (!isPow2(nWays)) flushCounter := flushCounterWrap
}
}
when (flushed && release_state === s_ready && !release_ack_wait) {
flushing := false.B
}
}
}
metaArb.io.in(0).valid := resetting
metaArb.io.in(0).bits := metaArb.io.in(5).bits
metaArb.io.in(0).bits.write := true.B
metaArb.io.in(0).bits.way_en := ~0.U(nWays.W)
metaArb.io.in(0).bits.data := tECC.encode(L1Metadata(0.U, ClientMetadata.onReset).asUInt)
when (resetting) {
flushCounter := flushCounterNext
when (flushDone) {
resetting := false.B
if (!isPow2(nWays)) flushCounter := flushCounterWrap
}
}
// gate the clock
clock_en_reg := !cacheParams.clockGate.B ||
io.ptw.customCSRs.disableDCacheClockGate ||
io.cpu.keep_clock_enabled ||
metaArb.io.out.valid || // subsumes resetting || flushing
s1_probe || s2_probe ||
s1_valid || s2_valid ||
io.tlb_port.req.valid ||
s1_tlb_req_valid || s2_tlb_req_valid ||
pstore1_held || pstore2_valid ||
release_state =/= s_ready ||
release_ack_wait || !release_queue_empty ||
!tlb.io.req.ready ||
cached_grant_wait || uncachedInFlight.asUInt.orR ||
lrscCount > 0.U || blockProbeAfterGrantCount > 0.U
// performance events
io.cpu.perf.acquire := edge.done(tl_out_a)
io.cpu.perf.release := edge.done(tl_out_c)
io.cpu.perf.grant := tl_out.d.valid && d_last
io.cpu.perf.tlbMiss := io.ptw.req.fire
io.cpu.perf.storeBufferEmptyAfterLoad := !(
(s1_valid && s1_write) ||
((s2_valid && s2_write && !s2_waw_hazard) || pstore1_held) ||
pstore2_valid)
io.cpu.perf.storeBufferEmptyAfterStore := !(
(s1_valid && s1_write) ||
(s2_valid && s2_write && pstore1_rmw) ||
((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) && pstore2_valid))
io.cpu.perf.canAcceptStoreThenLoad := !(
((s2_valid && s2_write && pstore1_rmw) && (s1_valid && s1_write && !s1_waw_hazard)) ||
(pstore2_valid && pstore1_valid_likely && (s1_valid && s1_write)))
io.cpu.perf.canAcceptStoreThenRMW := io.cpu.perf.canAcceptStoreThenLoad && !pstore2_valid
io.cpu.perf.canAcceptLoadThenLoad := !((s1_valid && s1_write && needsRead(s1_req)) && ((s2_valid && s2_write && !s2_waw_hazard || pstore1_held) || pstore2_valid))
io.cpu.perf.blocked := {
// stop reporting blocked just before unblocking to avoid overly conservative stalling
val beatsBeforeEnd = outer.crossing match {
case SynchronousCrossing(_) => 2
case RationalCrossing(_) => 1 // assumes 1 < ratio <= 2; need more bookkeeping for optimal handling of >2
case _: AsynchronousCrossing => 1 // likewise
case _: CreditedCrossing => 1 // likewise
}
val near_end_of_refill = if (cacheBlockBytes / beatBytes <= beatsBeforeEnd) tl_out.d.valid else {
val refill_count = RegInit(0.U((cacheBlockBytes / beatBytes).log2.W))
when (tl_out.d.fire && grantIsRefill) { refill_count := refill_count + 1.U }
refill_count >= (cacheBlockBytes / beatBytes - beatsBeforeEnd).U
}
cached_grant_wait && !near_end_of_refill
}
// report errors
val (data_error, data_error_uncorrectable, data_error_addr) =
if (usingDataScratchpad) (s2_valid_data_error, s2_data_error_uncorrectable, s2_req.addr) else {
(RegNext(tl_out_c.fire && inWriteback && s2_data_error),
RegNext(s2_data_error_uncorrectable),
probe_bits.address) // This is stable for a cycle after tl_out_c.fire, so don't need a register
}
{
val error_addr =
Mux(metaArb.io.in(1).valid, Cat(s2_first_meta_corrected.tag, metaArb.io.in(1).bits.addr(tagLSB-1, idxLSB)),
data_error_addr >> idxLSB) << idxLSB
io.errors.uncorrectable.foreach { u =>
u.valid := metaArb.io.in(1).valid && s2_meta_error_uncorrectable || data_error && data_error_uncorrectable
u.bits := error_addr
}
io.errors.correctable.foreach { c =>
c.valid := metaArb.io.in(1).valid || data_error
c.bits := error_addr
io.errors.uncorrectable.foreach { u => when (u.valid) { c.valid := false.B } }
}
io.errors.bus.valid := tl_out.d.fire && (tl_out.d.bits.denied || tl_out.d.bits.corrupt)
io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U)
ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached")
ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached")
}
if (usingDataScratchpad) {
val data_error_cover = Seq(
property.CoverBoolean(!data_error, Seq("no_data_error")),
property.CoverBoolean(data_error && !data_error_uncorrectable, Seq("data_correctable_error")),
property.CoverBoolean(data_error && data_error_uncorrectable, Seq("data_uncorrectable_error")))
val request_source = Seq(
property.CoverBoolean(s2_isSlavePortAccess, Seq("from_TL")),
property.CoverBoolean(!s2_isSlavePortAccess, Seq("from_CPU")))
property.cover(new property.CrossProperty(
Seq(data_error_cover, request_source),
Seq(),
"MemorySystem;;Scratchpad Memory Bit Flip Cross Covers"))
} else {
val data_error_type = Seq(
property.CoverBoolean(!s2_valid_data_error, Seq("no_data_error")),
property.CoverBoolean(s2_valid_data_error && !s2_data_error_uncorrectable, Seq("data_correctable_error")),
property.CoverBoolean(s2_valid_data_error && s2_data_error_uncorrectable, Seq("data_uncorrectable_error")))
val data_error_dirty = Seq(
property.CoverBoolean(!s2_victim_dirty, Seq("data_clean")),
property.CoverBoolean(s2_victim_dirty, Seq("data_dirty")))
val request_source = if (supports_flush) {
Seq(
property.CoverBoolean(!flushing, Seq("access")),
property.CoverBoolean(flushing, Seq("during_flush")))
} else {
Seq(property.CoverBoolean(true.B, Seq("never_flush")))
}
val tag_error_cover = Seq(
property.CoverBoolean( !s2_meta_error, Seq("no_tag_error")),
property.CoverBoolean( s2_meta_error && !s2_meta_error_uncorrectable, Seq("tag_correctable_error")),
property.CoverBoolean( s2_meta_error && s2_meta_error_uncorrectable, Seq("tag_uncorrectable_error")))
property.cover(new property.CrossProperty(
Seq(data_error_type, data_error_dirty, request_source, tag_error_cover),
Seq(),
"MemorySystem;;Cache Memory Bit Flip Cross Covers"))
}
} // leaving gated-clock domain
val dcacheImpl = withClock (gated_clock) { new DCacheModuleImpl }
def encodeData(x: UInt, poison: Bool) = x.grouped(eccBits).map(dECC.encode(_, if (dECC.canDetect) poison else false.B)).asUInt
def dummyEncodeData(x: UInt) = x.grouped(eccBits).map(dECC.swizzle(_)).asUInt
def decodeData(x: UInt) = x.grouped(dECC.width(eccBits)).map(dECC.decode(_))
def eccMask(byteMask: UInt) = byteMask.grouped(eccBytes).map(_.orR).asUInt
def eccByteMask(byteMask: UInt) = FillInterleaved(eccBytes, eccMask(byteMask))
def likelyNeedsRead(req: HellaCacheReq) = {
val res = !req.cmd.isOneOf(M_XWR, M_PFW) || req.size < log2Ceil(eccBytes).U
assert(!needsRead(req) || res)
res
}
def needsRead(req: HellaCacheReq) =
isRead(req.cmd) ||
(isWrite(req.cmd) && (req.cmd === M_PWR || req.size < log2Ceil(eccBytes).U))
def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
property.cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc)
def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) =
if (!usingDataScratchpad) ccover(cond, label, desc)
require(!usingVM || tagLSB <= pgIdxBits, s"D$$ set size must not exceed ${1<<(pgIdxBits-10)} KiB; got ${(nSets * cacheBlockBytes)>>10} KiB")
def tagLSB: Int = untagBits
def probeIdx(b: TLBundleB): UInt = b.address(idxMSB, idxLSB)
def addressToProbe(vaddr: UInt, paddr: UInt): TLBundleB = {
val res = Wire(new TLBundleB(edge.bundle))
res :#= DontCare
res.address := paddr
res.source := (mmioOffset - 1).U
res
}
def acquire(vaddr: UInt, paddr: UInt, param: UInt): TLBundleA = {
if (!edge.manager.anySupportAcquireB) WireDefault(0.U.asTypeOf(new TLBundleA(edge.bundle)))
else edge.AcquireBlock(0.U, paddr >> lgCacheBlockBytes << lgCacheBlockBytes, lgCacheBlockBytes.U, param)._2
}
}
File DescribedSRAM.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3.{Data, SyncReadMem, Vec}
import chisel3.util.log2Ceil
object DescribedSRAM {
def apply[T <: Data](
name: String,
desc: String,
size: BigInt, // depth
data: T
): SyncReadMem[T] = {
val mem = SyncReadMem(size, data)
mem.suggestName(name)
val granWidth = data match {
case v: Vec[_] => v.head.getWidth
case d => d.getWidth
}
val uid = 0
Annotated.srams(
component = mem,
name = name,
address_width = log2Ceil(size),
data_width = data.getWidth,
depth = size,
description = desc,
write_mask_granularity = granWidth
)
mem
}
}
|
module DCacheDataArray_5( // @[DCache.scala:49:7]
input clock, // @[DCache.scala:49:7]
input reset, // @[DCache.scala:49:7]
input io_req_valid, // @[DCache.scala:50:14]
input [11:0] io_req_bits_addr, // @[DCache.scala:50:14]
input io_req_bits_write, // @[DCache.scala:50:14]
input [63:0] io_req_bits_wdata, // @[DCache.scala:50:14]
input io_req_bits_wordMask, // @[DCache.scala:50:14]
input [7:0] io_req_bits_eccMask, // @[DCache.scala:50:14]
input [7:0] io_req_bits_way_en, // @[DCache.scala:50:14]
output [63:0] io_resp_0, // @[DCache.scala:50:14]
output [63:0] io_resp_1, // @[DCache.scala:50:14]
output [63:0] io_resp_2, // @[DCache.scala:50:14]
output [63:0] io_resp_3, // @[DCache.scala:50:14]
output [63:0] io_resp_4, // @[DCache.scala:50:14]
output [63:0] io_resp_5, // @[DCache.scala:50:14]
output [63:0] io_resp_6, // @[DCache.scala:50:14]
output [63:0] io_resp_7 // @[DCache.scala:50:14]
);
wire [511:0] _rockettile_dcache_data_arrays_0_RW0_rdata; // @[DescribedSRAM.scala:17:26]
wire io_req_valid_0 = io_req_valid; // @[DCache.scala:49:7]
wire [11:0] io_req_bits_addr_0 = io_req_bits_addr; // @[DCache.scala:49:7]
wire io_req_bits_write_0 = io_req_bits_write; // @[DCache.scala:49:7]
wire [63:0] io_req_bits_wdata_0 = io_req_bits_wdata; // @[DCache.scala:49:7]
wire io_req_bits_wordMask_0 = io_req_bits_wordMask; // @[DCache.scala:49:7]
wire [7:0] io_req_bits_eccMask_0 = io_req_bits_eccMask; // @[DCache.scala:49:7]
wire [7:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[DCache.scala:49:7]
wire _rdata_valid_T_1 = 1'h1; // @[DCache.scala:71:60]
wire rdata_valid = io_req_valid_0; // @[DCache.scala:49:7, :71:30]
wire [63:0] wWords_0 = io_req_bits_wdata_0; // @[package.scala:211:50]
wire _rdata_valid_T = io_req_bits_wordMask_0; // @[DCache.scala:49:7, :71:83]
wire [63:0] rdata_0_0; // @[package.scala:45:27]
wire [63:0] rdata_0_1; // @[package.scala:45:27]
wire [63:0] rdata_0_2; // @[package.scala:45:27]
wire [63:0] rdata_0_3; // @[package.scala:45:27]
wire [63:0] rdata_0_4; // @[package.scala:45:27]
wire [63:0] rdata_0_5; // @[package.scala:45:27]
wire [63:0] rdata_0_6; // @[package.scala:45:27]
wire [63:0] rdata_0_7; // @[package.scala:45:27]
wire [63:0] io_resp_0_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_1_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_2_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_3_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_4_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_5_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_6_0; // @[DCache.scala:49:7]
wire [63:0] io_resp_7_0; // @[DCache.scala:49:7]
wire eccMask_0 = io_req_bits_eccMask_0[0]; // @[DCache.scala:49:7, :56:82]
wire eccMask_1 = io_req_bits_eccMask_0[1]; // @[DCache.scala:49:7, :56:82]
wire eccMask_2 = io_req_bits_eccMask_0[2]; // @[DCache.scala:49:7, :56:82]
wire eccMask_3 = io_req_bits_eccMask_0[3]; // @[DCache.scala:49:7, :56:82]
wire eccMask_4 = io_req_bits_eccMask_0[4]; // @[DCache.scala:49:7, :56:82]
wire eccMask_5 = io_req_bits_eccMask_0[5]; // @[DCache.scala:49:7, :56:82]
wire eccMask_6 = io_req_bits_eccMask_0[6]; // @[DCache.scala:49:7, :56:82]
wire eccMask_7 = io_req_bits_eccMask_0[7]; // @[DCache.scala:49:7, :56:82]
wire _wMask_T = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_1 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_2 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_3 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_4 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_5 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_6 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_7 = io_req_bits_way_en_0[0]; // @[DCache.scala:49:7, :57:108]
wire wMask_0 = eccMask_0 & _wMask_T; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_1 = eccMask_1 & _wMask_T_1; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_2 = eccMask_2 & _wMask_T_2; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_3 = eccMask_3 & _wMask_T_3; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_4 = eccMask_4 & _wMask_T_4; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_5 = eccMask_5 & _wMask_T_5; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_6 = eccMask_6 & _wMask_T_6; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_7 = eccMask_7 & _wMask_T_7; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_8 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_9 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_10 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_11 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_12 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_13 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_14 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_15 = io_req_bits_way_en_0[1]; // @[DCache.scala:49:7, :57:108]
wire wMask_8 = eccMask_0 & _wMask_T_8; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_9 = eccMask_1 & _wMask_T_9; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_10 = eccMask_2 & _wMask_T_10; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_11 = eccMask_3 & _wMask_T_11; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_12 = eccMask_4 & _wMask_T_12; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_13 = eccMask_5 & _wMask_T_13; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_14 = eccMask_6 & _wMask_T_14; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_15 = eccMask_7 & _wMask_T_15; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_16 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_17 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_18 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_19 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_20 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_21 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_22 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_23 = io_req_bits_way_en_0[2]; // @[DCache.scala:49:7, :57:108]
wire wMask_16 = eccMask_0 & _wMask_T_16; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_17 = eccMask_1 & _wMask_T_17; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_18 = eccMask_2 & _wMask_T_18; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_19 = eccMask_3 & _wMask_T_19; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_20 = eccMask_4 & _wMask_T_20; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_21 = eccMask_5 & _wMask_T_21; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_22 = eccMask_6 & _wMask_T_22; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_23 = eccMask_7 & _wMask_T_23; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_24 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_25 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_26 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_27 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_28 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_29 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_30 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_31 = io_req_bits_way_en_0[3]; // @[DCache.scala:49:7, :57:108]
wire wMask_24 = eccMask_0 & _wMask_T_24; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_25 = eccMask_1 & _wMask_T_25; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_26 = eccMask_2 & _wMask_T_26; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_27 = eccMask_3 & _wMask_T_27; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_28 = eccMask_4 & _wMask_T_28; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_29 = eccMask_5 & _wMask_T_29; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_30 = eccMask_6 & _wMask_T_30; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_31 = eccMask_7 & _wMask_T_31; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_32 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_33 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_34 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_35 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_36 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_37 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_38 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_39 = io_req_bits_way_en_0[4]; // @[DCache.scala:49:7, :57:108]
wire wMask_32 = eccMask_0 & _wMask_T_32; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_33 = eccMask_1 & _wMask_T_33; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_34 = eccMask_2 & _wMask_T_34; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_35 = eccMask_3 & _wMask_T_35; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_36 = eccMask_4 & _wMask_T_36; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_37 = eccMask_5 & _wMask_T_37; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_38 = eccMask_6 & _wMask_T_38; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_39 = eccMask_7 & _wMask_T_39; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_40 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_41 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_42 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_43 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_44 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_45 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_46 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_47 = io_req_bits_way_en_0[5]; // @[DCache.scala:49:7, :57:108]
wire wMask_40 = eccMask_0 & _wMask_T_40; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_41 = eccMask_1 & _wMask_T_41; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_42 = eccMask_2 & _wMask_T_42; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_43 = eccMask_3 & _wMask_T_43; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_44 = eccMask_4 & _wMask_T_44; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_45 = eccMask_5 & _wMask_T_45; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_46 = eccMask_6 & _wMask_T_46; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_47 = eccMask_7 & _wMask_T_47; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_48 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_49 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_50 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_51 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_52 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_53 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_54 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_55 = io_req_bits_way_en_0[6]; // @[DCache.scala:49:7, :57:108]
wire wMask_48 = eccMask_0 & _wMask_T_48; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_49 = eccMask_1 & _wMask_T_49; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_50 = eccMask_2 & _wMask_T_50; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_51 = eccMask_3 & _wMask_T_51; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_52 = eccMask_4 & _wMask_T_52; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_53 = eccMask_5 & _wMask_T_53; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_54 = eccMask_6 & _wMask_T_54; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_55 = eccMask_7 & _wMask_T_55; // @[DCache.scala:56:82, :57:{87,108}]
wire _wMask_T_56 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_57 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_58 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_59 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_60 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_61 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_62 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire _wMask_T_63 = io_req_bits_way_en_0[7]; // @[DCache.scala:49:7, :57:108]
wire wMask_56 = eccMask_0 & _wMask_T_56; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_57 = eccMask_1 & _wMask_T_57; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_58 = eccMask_2 & _wMask_T_58; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_59 = eccMask_3 & _wMask_T_59; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_60 = eccMask_4 & _wMask_T_60; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_61 = eccMask_5 & _wMask_T_61; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_62 = eccMask_6 & _wMask_T_62; // @[DCache.scala:56:82, :57:{87,108}]
wire wMask_63 = eccMask_7 & _wMask_T_63; // @[DCache.scala:56:82, :57:{87,108}]
wire [8:0] addr = io_req_bits_addr_0[11:3]; // @[DCache.scala:49:7, :59:31]
wire [8:0] _rdata_data_WIRE = addr; // @[DCache.scala:59:31, :77:26]
wire _rdata_T; // @[DCache.scala:72:17]
wire _rdata_data_T_1; // @[DCache.scala:77:39]
wire [7:0] _rdata_WIRE_0; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_1; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_2; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_3; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_4; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_5; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_6; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_7; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_8; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_9; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_10; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_11; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_12; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_13; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_14; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_15; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_16; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_17; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_18; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_19; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_20; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_21; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_22; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_23; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_24; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_25; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_26; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_27; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_28; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_29; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_30; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_31; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_32; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_33; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_34; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_35; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_36; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_37; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_38; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_39; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_40; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_41; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_42; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_43; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_44; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_45; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_46; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_47; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_48; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_49; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_50; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_51; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_52; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_53; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_54; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_55; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_56; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_57; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_58; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_59; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_60; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_61; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_62; // @[DCache.scala:75:32]
wire [7:0] _rdata_WIRE_63; // @[DCache.scala:75:32]
assign _rdata_T = rdata_valid & io_req_bits_write_0; // @[DCache.scala:49:7, :71:30, :72:17]
wire [7:0] rdata_wData_0 = wWords_0[7:0]; // @[package.scala:211:50]
assign _rdata_WIRE_0 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_8 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_16 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_24 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_32 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_40 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_48 = rdata_wData_0; // @[package.scala:211:50]
assign _rdata_WIRE_56 = rdata_wData_0; // @[package.scala:211:50]
wire [7:0] rdata_wData_1 = wWords_0[15:8]; // @[package.scala:211:50]
assign _rdata_WIRE_1 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_9 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_17 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_25 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_33 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_41 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_49 = rdata_wData_1; // @[package.scala:211:50]
assign _rdata_WIRE_57 = rdata_wData_1; // @[package.scala:211:50]
wire [7:0] rdata_wData_2 = wWords_0[23:16]; // @[package.scala:211:50]
assign _rdata_WIRE_2 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_10 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_18 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_26 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_34 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_42 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_50 = rdata_wData_2; // @[package.scala:211:50]
assign _rdata_WIRE_58 = rdata_wData_2; // @[package.scala:211:50]
wire [7:0] rdata_wData_3 = wWords_0[31:24]; // @[package.scala:211:50]
assign _rdata_WIRE_3 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_11 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_19 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_27 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_35 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_43 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_51 = rdata_wData_3; // @[package.scala:211:50]
assign _rdata_WIRE_59 = rdata_wData_3; // @[package.scala:211:50]
wire [7:0] rdata_wData_4 = wWords_0[39:32]; // @[package.scala:211:50]
assign _rdata_WIRE_4 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_12 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_20 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_28 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_36 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_44 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_52 = rdata_wData_4; // @[package.scala:211:50]
assign _rdata_WIRE_60 = rdata_wData_4; // @[package.scala:211:50]
wire [7:0] rdata_wData_5 = wWords_0[47:40]; // @[package.scala:211:50]
assign _rdata_WIRE_5 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_13 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_21 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_29 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_37 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_45 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_53 = rdata_wData_5; // @[package.scala:211:50]
assign _rdata_WIRE_61 = rdata_wData_5; // @[package.scala:211:50]
wire [7:0] rdata_wData_6 = wWords_0[55:48]; // @[package.scala:211:50]
assign _rdata_WIRE_6 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_14 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_22 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_30 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_38 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_46 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_54 = rdata_wData_6; // @[package.scala:211:50]
assign _rdata_WIRE_62 = rdata_wData_6; // @[package.scala:211:50]
wire [7:0] rdata_wData_7 = wWords_0[63:56]; // @[package.scala:211:50]
assign _rdata_WIRE_7 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_15 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_23 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_31 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_39 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_47 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_55 = rdata_wData_7; // @[package.scala:211:50]
assign _rdata_WIRE_63 = rdata_wData_7; // @[package.scala:211:50]
wire _rdata_data_T = ~io_req_bits_write_0; // @[DCache.scala:49:7, :77:42]
assign _rdata_data_T_1 = rdata_valid & _rdata_data_T; // @[DCache.scala:71:30, :77:{39,42}]
wire [15:0] rdata_lo_lo = _rockettile_dcache_data_arrays_0_RW0_rdata[15:0]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi = _rockettile_dcache_data_arrays_0_RW0_rdata[31:16]; // @[package.scala:45:27]
wire [31:0] rdata_lo = {rdata_lo_hi, rdata_lo_lo}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo = _rockettile_dcache_data_arrays_0_RW0_rdata[47:32]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi = _rockettile_dcache_data_arrays_0_RW0_rdata[63:48]; // @[package.scala:45:27]
wire [31:0] rdata_hi = {rdata_hi_hi, rdata_hi_lo}; // @[package.scala:45:27]
assign rdata_0_0 = {rdata_hi, rdata_lo}; // @[package.scala:45:27]
assign io_resp_0_0 = rdata_0_0; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[79:64]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[95:80]; // @[package.scala:45:27]
wire [31:0] rdata_lo_1 = {rdata_lo_hi_1, rdata_lo_lo_1}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[111:96]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_1 = _rockettile_dcache_data_arrays_0_RW0_rdata[127:112]; // @[package.scala:45:27]
wire [31:0] rdata_hi_1 = {rdata_hi_hi_1, rdata_hi_lo_1}; // @[package.scala:45:27]
assign rdata_0_1 = {rdata_hi_1, rdata_lo_1}; // @[package.scala:45:27]
assign io_resp_1_0 = rdata_0_1; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[143:128]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[159:144]; // @[package.scala:45:27]
wire [31:0] rdata_lo_2 = {rdata_lo_hi_2, rdata_lo_lo_2}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[175:160]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_2 = _rockettile_dcache_data_arrays_0_RW0_rdata[191:176]; // @[package.scala:45:27]
wire [31:0] rdata_hi_2 = {rdata_hi_hi_2, rdata_hi_lo_2}; // @[package.scala:45:27]
assign rdata_0_2 = {rdata_hi_2, rdata_lo_2}; // @[package.scala:45:27]
assign io_resp_2_0 = rdata_0_2; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[207:192]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[223:208]; // @[package.scala:45:27]
wire [31:0] rdata_lo_3 = {rdata_lo_hi_3, rdata_lo_lo_3}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[239:224]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_3 = _rockettile_dcache_data_arrays_0_RW0_rdata[255:240]; // @[package.scala:45:27]
wire [31:0] rdata_hi_3 = {rdata_hi_hi_3, rdata_hi_lo_3}; // @[package.scala:45:27]
assign rdata_0_3 = {rdata_hi_3, rdata_lo_3}; // @[package.scala:45:27]
assign io_resp_3_0 = rdata_0_3; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[271:256]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[287:272]; // @[package.scala:45:27]
wire [31:0] rdata_lo_4 = {rdata_lo_hi_4, rdata_lo_lo_4}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[303:288]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_4 = _rockettile_dcache_data_arrays_0_RW0_rdata[319:304]; // @[package.scala:45:27]
wire [31:0] rdata_hi_4 = {rdata_hi_hi_4, rdata_hi_lo_4}; // @[package.scala:45:27]
assign rdata_0_4 = {rdata_hi_4, rdata_lo_4}; // @[package.scala:45:27]
assign io_resp_4_0 = rdata_0_4; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[335:320]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[351:336]; // @[package.scala:45:27]
wire [31:0] rdata_lo_5 = {rdata_lo_hi_5, rdata_lo_lo_5}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[367:352]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_5 = _rockettile_dcache_data_arrays_0_RW0_rdata[383:368]; // @[package.scala:45:27]
wire [31:0] rdata_hi_5 = {rdata_hi_hi_5, rdata_hi_lo_5}; // @[package.scala:45:27]
assign rdata_0_5 = {rdata_hi_5, rdata_lo_5}; // @[package.scala:45:27]
assign io_resp_5_0 = rdata_0_5; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[399:384]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[415:400]; // @[package.scala:45:27]
wire [31:0] rdata_lo_6 = {rdata_lo_hi_6, rdata_lo_lo_6}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[431:416]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_6 = _rockettile_dcache_data_arrays_0_RW0_rdata[447:432]; // @[package.scala:45:27]
wire [31:0] rdata_hi_6 = {rdata_hi_hi_6, rdata_hi_lo_6}; // @[package.scala:45:27]
assign rdata_0_6 = {rdata_hi_6, rdata_lo_6}; // @[package.scala:45:27]
assign io_resp_6_0 = rdata_0_6; // @[package.scala:45:27]
wire [15:0] rdata_lo_lo_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[463:448]; // @[package.scala:45:27]
wire [15:0] rdata_lo_hi_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[479:464]; // @[package.scala:45:27]
wire [31:0] rdata_lo_7 = {rdata_lo_hi_7, rdata_lo_lo_7}; // @[package.scala:45:27]
wire [15:0] rdata_hi_lo_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[495:480]; // @[package.scala:45:27]
wire [15:0] rdata_hi_hi_7 = _rockettile_dcache_data_arrays_0_RW0_rdata[511:496]; // @[package.scala:45:27]
wire [31:0] rdata_hi_7 = {rdata_hi_hi_7, rdata_hi_lo_7}; // @[package.scala:45:27]
assign rdata_0_7 = {rdata_hi_7, rdata_lo_7}; // @[package.scala:45:27]
assign io_resp_7_0 = rdata_0_7; // @[package.scala:45:27]
rockettile_dcache_data_arrays_0_4 rockettile_dcache_data_arrays_0 ( // @[DescribedSRAM.scala:17:26]
.RW0_addr (_rdata_T ? addr : _rdata_data_WIRE), // @[DescribedSRAM.scala:17:26]
.RW0_en (_rdata_data_T_1 | _rdata_T), // @[DescribedSRAM.scala:17:26]
.RW0_clk (clock),
.RW0_wmode (io_req_bits_write_0), // @[DCache.scala:49:7]
.RW0_wdata ({_rdata_WIRE_63, _rdata_WIRE_62, _rdata_WIRE_61, _rdata_WIRE_60, _rdata_WIRE_59, _rdata_WIRE_58, _rdata_WIRE_57, _rdata_WIRE_56, _rdata_WIRE_55, _rdata_WIRE_54, _rdata_WIRE_53, _rdata_WIRE_52, _rdata_WIRE_51, _rdata_WIRE_50, _rdata_WIRE_49, _rdata_WIRE_48, _rdata_WIRE_47, _rdata_WIRE_46, _rdata_WIRE_45, _rdata_WIRE_44, _rdata_WIRE_43, _rdata_WIRE_42, _rdata_WIRE_41, _rdata_WIRE_40, _rdata_WIRE_39, _rdata_WIRE_38, _rdata_WIRE_37, _rdata_WIRE_36, _rdata_WIRE_35, _rdata_WIRE_34, _rdata_WIRE_33, _rdata_WIRE_32, _rdata_WIRE_31, _rdata_WIRE_30, _rdata_WIRE_29, _rdata_WIRE_28, _rdata_WIRE_27, _rdata_WIRE_26, _rdata_WIRE_25, _rdata_WIRE_24, _rdata_WIRE_23, _rdata_WIRE_22, _rdata_WIRE_21, _rdata_WIRE_20, _rdata_WIRE_19, _rdata_WIRE_18, _rdata_WIRE_17, _rdata_WIRE_16, _rdata_WIRE_15, _rdata_WIRE_14, _rdata_WIRE_13, _rdata_WIRE_12, _rdata_WIRE_11, _rdata_WIRE_10, _rdata_WIRE_9, _rdata_WIRE_8, _rdata_WIRE_7, _rdata_WIRE_6, _rdata_WIRE_5, _rdata_WIRE_4, _rdata_WIRE_3, _rdata_WIRE_2, _rdata_WIRE_1, _rdata_WIRE_0}), // @[DescribedSRAM.scala:17:26]
.RW0_rdata (_rockettile_dcache_data_arrays_0_RW0_rdata),
.RW0_wmask ({wMask_63, wMask_62, wMask_61, wMask_60, wMask_59, wMask_58, wMask_57, wMask_56, wMask_55, wMask_54, wMask_53, wMask_52, wMask_51, wMask_50, wMask_49, wMask_48, wMask_47, wMask_46, wMask_45, wMask_44, wMask_43, wMask_42, wMask_41, wMask_40, wMask_39, wMask_38, wMask_37, wMask_36, wMask_35, wMask_34, wMask_33, wMask_32, wMask_31, wMask_30, wMask_29, wMask_28, wMask_27, wMask_26, wMask_25, wMask_24, wMask_23, wMask_22, wMask_21, wMask_20, wMask_19, wMask_18, wMask_17, wMask_16, wMask_15, wMask_14, wMask_13, wMask_12, wMask_11, wMask_10, wMask_9, wMask_8, wMask_7, wMask_6, wMask_5, wMask_4, wMask_3, wMask_2, wMask_1, wMask_0}) // @[DescribedSRAM.scala:17:26]
); // @[DescribedSRAM.scala:17:26]
assign io_resp_0 = io_resp_0_0; // @[DCache.scala:49:7]
assign io_resp_1 = io_resp_1_0; // @[DCache.scala:49:7]
assign io_resp_2 = io_resp_2_0; // @[DCache.scala:49:7]
assign io_resp_3 = io_resp_3_0; // @[DCache.scala:49:7]
assign io_resp_4 = io_resp_4_0; // @[DCache.scala:49:7]
assign io_resp_5 = io_resp_5_0; // @[DCache.scala:49:7]
assign io_resp_6 = io_resp_6_0; // @[DCache.scala:49:7]
assign io_resp_7 = io_resp_7_0; // @[DCache.scala:49:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_50( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_63 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
|
module OptimizationBarrier_TLBEntryData_241( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File recFNFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object recFNFromFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits) =
{
val rawIn = rawFloatFromFN(expWidth, sigWidth, in)
rawIn.sign ##
(Mux(rawIn.isZero, 0.U(3.W), rawIn.sExp(expWidth, expWidth - 2)) |
Mux(rawIn.isNaN, 1.U, 0.U)) ##
rawIn.sExp(expWidth - 3, 0) ##
rawIn.sig(sigWidth - 2, 0)
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
File Configs.scala:
package gemmini
import chisel3._
import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.diplomacy.LazyModule
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{BuildRoCC, OpcodeSet}
import freechips.rocketchip.rocket._
import freechips.rocketchip.tile._
import freechips.rocketchip.system._
import freechips.rocketchip.diplomacy._
import gemmini.Arithmetic.SIntArithmetic
import hardfloat._
// -----------------------
// Component Mixin Configs
// -----------------------
object GemminiConfigs {
val defaultConfig = GemminiArrayConfig[SInt, Float, Float](
// Datatypes
inputType = SInt(8.W),
accType = SInt(32.W),
spatialArrayOutputType = SInt(20.W),
// Spatial array size options
tileRows = 1,
tileColumns = 1,
meshRows = 16,
meshColumns = 16,
// Spatial array PE options
dataflow = Dataflow.BOTH,
// Scratchpad and accumulator
sp_capacity = CapacityInKilobytes(256),
acc_capacity = CapacityInKilobytes(64),
sp_banks = 4,
acc_banks = 2,
sp_singleported = true,
acc_singleported = false,
// DNN options
has_training_convs = true,
has_max_pool = true,
has_nonlinear_activations = true,
// Reservation station entries
reservation_station_entries_ld = 8,
reservation_station_entries_st = 4,
reservation_station_entries_ex = 16,
// Ld/Ex/St instruction queue lengths
ld_queue_length = 8,
st_queue_length = 2,
ex_queue_length = 8,
// DMA options
max_in_flight_mem_reqs = 16,
dma_maxbytes = 64,
dma_buswidth = 128,
// TLB options
tlb_size = 4,
// Mvin and Accumulator scalar multiply options
mvin_scale_args = Some(ScaleArguments(
(t: SInt, f: Float) => {
val f_rec = recFNFromFN(f.expWidth, f.sigWidth, f.bits)
val in_to_rec_fn = Module(new INToRecFN(t.getWidth, f.expWidth, f.sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := t.asTypeOf(UInt(t.getWidth.W))
in_to_rec_fn.io.roundingMode := consts.round_near_even
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val t_rec = in_to_rec_fn.io.out
val muladder = Module(new MulAddRecFN(f.expWidth, f.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec
muladder.io.b := f_rec
muladder.io.c := 0.U
val rec_fn_to_in = Module(new RecFNToIN(f.expWidth, f.sigWidth, t.getWidth))
rec_fn_to_in.io.in := muladder.io.out
rec_fn_to_in.io.roundingMode := consts.round_near_even
rec_fn_to_in.io.signedOut := true.B
val overflow = rec_fn_to_in.io.intExceptionFlags(1)
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
val sign = rawFloatFromRecFN(f.expWidth, f.sigWidth, rec_fn_to_in.io.in).sign
val sat = Mux(sign, minsat, maxsat)
Mux(overflow, sat, rec_fn_to_in.io.out.asTypeOf(t))
},
4, Float(8, 24), 4,
identity = "1.0",
c_str = "({float y = ROUND_NEAR_EVEN((x) * (scale)); y > INT8_MAX ? INT8_MAX : (y < INT8_MIN ? INT8_MIN : (elem_t)y);})"
)),
mvin_scale_acc_args = None,
mvin_scale_shared = false,
acc_scale_args = Some(ScaleArguments(
(t: SInt, f: Float) => {
val f_rec = recFNFromFN(f.expWidth, f.sigWidth, f.bits)
val in_to_rec_fn = Module(new INToRecFN(t.getWidth, f.expWidth, f.sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := t.asTypeOf(UInt(t.getWidth.W))
in_to_rec_fn.io.roundingMode := consts.round_near_even
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val t_rec = in_to_rec_fn.io.out
val muladder = Module(new MulAddRecFN(f.expWidth, f.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec
muladder.io.b := f_rec
muladder.io.c := 0.U
val rec_fn_to_in = Module(new RecFNToIN(f.expWidth, f.sigWidth, t.getWidth))
rec_fn_to_in.io.in := muladder.io.out
rec_fn_to_in.io.roundingMode := consts.round_near_even
rec_fn_to_in.io.signedOut := true.B
val overflow = rec_fn_to_in.io.intExceptionFlags(1)
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
val sign = rawFloatFromRecFN(f.expWidth, f.sigWidth, rec_fn_to_in.io.in).sign
val sat = Mux(sign, minsat, maxsat)
Mux(overflow, sat, rec_fn_to_in.io.out.asTypeOf(t))
},
8, Float(8, 24), -1,
identity = "1.0",
c_str = "({float y = ROUND_NEAR_EVEN((x) * (scale)); y > INT8_MAX ? INT8_MAX : (y < INT8_MIN ? INT8_MIN : (acc_t)y);})"
)),
// SoC counters options
num_counter = 8,
// Scratchpad and Accumulator input/output options
acc_read_full_width = true,
acc_read_small_width = true,
ex_read_from_spad = true,
ex_read_from_acc = true,
ex_write_to_spad = true,
ex_write_to_acc = true,
)
val dummyConfig = GemminiArrayConfig[DummySInt, Float, Float](
inputType = DummySInt(8),
accType = DummySInt(32),
spatialArrayOutputType = DummySInt(20),
tileRows = defaultConfig.tileRows,
tileColumns = defaultConfig.tileColumns,
meshRows = defaultConfig.meshRows,
meshColumns = defaultConfig.meshColumns,
dataflow = defaultConfig.dataflow,
sp_capacity = CapacityInKilobytes(128),
acc_capacity = CapacityInKilobytes(128),
sp_banks = defaultConfig.sp_banks,
acc_banks = defaultConfig.acc_banks,
sp_singleported = defaultConfig.sp_singleported,
acc_singleported = defaultConfig.acc_singleported,
has_training_convs = false,
has_max_pool = defaultConfig.has_max_pool,
has_nonlinear_activations = false,
reservation_station_entries_ld = defaultConfig.reservation_station_entries_ld,
reservation_station_entries_st = defaultConfig.reservation_station_entries_st,
reservation_station_entries_ex = defaultConfig.reservation_station_entries_ex,
ld_queue_length = defaultConfig.ld_queue_length,
st_queue_length = defaultConfig.st_queue_length,
ex_queue_length = defaultConfig.ex_queue_length,
max_in_flight_mem_reqs = defaultConfig.max_in_flight_mem_reqs,
dma_maxbytes = defaultConfig.dma_maxbytes,
dma_buswidth = defaultConfig.dma_buswidth,
tlb_size = defaultConfig.tlb_size,
mvin_scale_args = Some(ScaleArguments(
(t: DummySInt, f: Float) => t.dontCare,
4, Float(8, 24), 4,
identity = "1.0",
c_str = "({float y = ROUND_NEAR_EVEN((x) * (scale)); y > INT8_MAX ? INT8_MAX : (y < INT8_MIN ? INT8_MIN : (elem_t)y);})"
)),
mvin_scale_acc_args = None,
mvin_scale_shared = defaultConfig.mvin_scale_shared,
acc_scale_args = Some(ScaleArguments(
(t: DummySInt, f: Float) => t.dontCare,
1, Float(8, 24), -1,
identity = "1.0",
c_str = "({float y = ROUND_NEAR_EVEN((x) * (scale)); y > INT8_MAX ? INT8_MAX : (y < INT8_MIN ? INT8_MIN : (acc_t)y);})"
)),
num_counter = 0,
acc_read_full_width = false,
acc_read_small_width = defaultConfig.acc_read_small_width,
ex_read_from_spad = defaultConfig.ex_read_from_spad,
ex_read_from_acc = false,
ex_write_to_spad = false,
ex_write_to_acc = defaultConfig.ex_write_to_acc,
)
val chipConfig = defaultConfig.copy(sp_capacity=CapacityInKilobytes(64), acc_capacity=CapacityInKilobytes(32), dataflow=Dataflow.WS,
acc_scale_args=Some(defaultConfig.acc_scale_args.get.copy(latency=4)),
acc_singleported=true,
acc_sub_banks=2,
mesh_output_delay = 2,
ex_read_from_acc=false,
ex_write_to_spad=false,
hardcode_d_to_garbage_addr = true
)
val largeChipConfig = chipConfig.copy(sp_capacity=CapacityInKilobytes(128), acc_capacity=CapacityInKilobytes(64),
tileRows=1, tileColumns=1,
meshRows=32, meshColumns=32
)
val leanConfig = defaultConfig.copy(dataflow=Dataflow.WS, max_in_flight_mem_reqs = 64, acc_read_full_width = false, ex_read_from_acc = false, ex_write_to_spad = false, hardcode_d_to_garbage_addr = true)
val leanPrintfConfig = defaultConfig.copy(dataflow=Dataflow.WS, max_in_flight_mem_reqs = 64, acc_read_full_width = false, ex_read_from_acc = false, ex_write_to_spad = false, hardcode_d_to_garbage_addr = true, use_firesim_simulation_counters=true)
}
/**
* Mixin which sets the default parameters for a systolic array accelerator.
Also sets the system bus width to 128 bits (instead of the deafult 64 bits) to
allow for the default 16x16 8-bit systolic array to be attached.
*/
class DefaultGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.defaultConfig
) extends Config((site, here, up) => {
case BuildRoCC => up(BuildRoCC) ++ Seq(
(p: Parameters) => {
implicit val q = p
val gemmini = LazyModule(new Gemmini(gemminiConfig))
gemmini
}
)
})
/**
* Mixin which sets the default lean parameters for a systolic array accelerator.
*/
class LeanGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.leanConfig
) extends Config((site, here, up) => {
case BuildRoCC => up(BuildRoCC) ++ Seq(
(p: Parameters) => {
implicit val q = p
val gemmini = LazyModule(new Gemmini(gemminiConfig))
gemmini
}
)
})
class LeanGemminiPrintfConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.leanPrintfConfig
) extends Config((site, here, up) => {
case BuildRoCC => up(BuildRoCC) ++ Seq(
(p: Parameters) => {
implicit val q = p
val gemmini = LazyModule(new Gemmini(gemminiConfig))
gemmini
}
)
})
class DummyDefaultGemminiConfig[T <: Data : Arithmetic, U <: Data, V <: Data](
gemminiConfig: GemminiArrayConfig[T,U,V] = GemminiConfigs.dummyConfig
) extends Config((site, here, up) => {
case BuildRoCC => up(BuildRoCC) ++ Seq(
(p: Parameters) => {
implicit val q = p
val gemmini = LazyModule(new Gemmini(gemminiConfig))
gemmini
}
)
})
// This Gemmini config has both an Int and an FP Gemmini side-by-side, sharing
// the same scratchpad.
class DualGemminiConfig extends Config((site, here, up) => {
case BuildRoCC => {
var int_gemmini: Gemmini[_,_,_] = null
var fp_gemmini: Gemmini[_,_,_] = null
val int_fn = (p: Parameters) => {
implicit val q = p
int_gemmini = LazyModule(new Gemmini(GemminiConfigs.chipConfig.copy(
opcodes = OpcodeSet.custom3,
use_shared_ext_mem = true,
clock_gate = true
)))
int_gemmini
}
val fp_fn = (p: Parameters) => {
implicit val q = p
fp_gemmini = LazyModule(new Gemmini(GemminiFPConfigs.BF16DefaultConfig.copy(
opcodes = OpcodeSet.custom2,
sp_capacity=CapacityInKilobytes(64), acc_capacity=CapacityInKilobytes(32),
tileColumns = 1, tileRows = 1,
meshColumns = 8, meshRows = 8,
acc_singleported = true, acc_banks = 2, acc_sub_banks = 2,
use_shared_ext_mem = true,
ex_read_from_acc=false,
ex_write_to_spad=false,
hardcode_d_to_garbage_addr = true,
headerFileName = "gemmini_params_bf16.h",
acc_latency = 3,
dataflow = Dataflow.WS,
mesh_output_delay = 3,
clock_gate = true
)))
InModuleBody {
require(int_gemmini.config.sp_banks == fp_gemmini.config.sp_banks)
require(int_gemmini.config.acc_banks == fp_gemmini.config.acc_banks)
require(int_gemmini.config.acc_sub_banks == fp_gemmini.config.acc_sub_banks)
require(int_gemmini.config.sp_singleported && fp_gemmini.config.sp_singleported)
require(int_gemmini.config.acc_singleported && fp_gemmini.config.acc_singleported)
require(int_gemmini.config.sp_bank_entries == fp_gemmini.config.sp_bank_entries)
require(int_gemmini.spad.module.spad_mems(0).mask_len == fp_gemmini.spad.module.spad_mems(0).mask_len)
require(int_gemmini.spad.module.spad_mems(0).mask_elem.getWidth == fp_gemmini.spad.module.spad_mems(0).mask_elem.getWidth)
println(int_gemmini.config.acc_bank_entries, fp_gemmini.config.acc_bank_entries)
println(int_gemmini.spad.module.acc_mems(0).mask_len, fp_gemmini.spad.module.acc_mems(0).mask_len)
println(int_gemmini.spad.module.acc_mems(0).mask_elem.getWidth, fp_gemmini.spad.module.acc_mems(0).mask_elem.getWidth)
require(int_gemmini.config.acc_bank_entries == fp_gemmini.config.acc_bank_entries / 2)
require(int_gemmini.config.acc_sub_banks == fp_gemmini.config.acc_sub_banks)
require(int_gemmini.spad.module.acc_mems(0).mask_len == fp_gemmini.spad.module.acc_mems(0).mask_len * 2)
require(int_gemmini.spad.module.acc_mems(0).mask_elem.getWidth == fp_gemmini.spad.module.acc_mems(0).mask_elem.getWidth)
val spad_mask_len = int_gemmini.spad.module.spad_mems(0).mask_len
val spad_data_len = int_gemmini.spad.module.spad_mems(0).mask_elem.getWidth
val acc_mask_len = int_gemmini.spad.module.acc_mems(0).mask_len
val acc_data_len = int_gemmini.spad.module.acc_mems(0).mask_elem.getWidth
val shared_mem = Module(new SharedExtMem(
int_gemmini.config.sp_banks, int_gemmini.config.acc_banks, int_gemmini.config.acc_sub_banks,
int_gemmini.config.sp_bank_entries, spad_mask_len, spad_data_len,
int_gemmini.config.acc_bank_entries / int_gemmini.config.acc_sub_banks, acc_mask_len, acc_data_len
))
shared_mem.io.in(0) <> int_gemmini.module.ext_mem_io.get
shared_mem.io.in(1) <> fp_gemmini.module.ext_mem_io.get
}
fp_gemmini
}
up(BuildRoCC) ++ Seq(int_fn, fp_fn)
}
})
File Pipeline.scala:
package gemmini
import chisel3._
import chisel3.util._
class Pipeline[T <: Data] (gen: T, latency: Int)(comb: Seq[T => T] = Seq.fill(latency+1)((x: T) => x)) extends Module {
val io = IO(new Bundle {
val in = Flipped(Decoupled(gen))
val out = Decoupled(gen)
val busy = Output(Bool())
})
require(comb.size == latency+1, "length of combinational is incorrect")
if (latency == 0) {
io.in.ready := io.out.ready
io.out.valid := io.in.valid
io.out.bits := comb.head(io.in.bits)
io.busy := io.in.valid
} else {
val stages = Reg(Vec(latency, gen))
val valids = RegInit(VecInit(Seq.fill(latency)(false.B)))
val stalling = VecInit(Seq.fill(latency)(false.B))
io.busy := io.in.valid || valids.reduce(_||_)
// Stall signals
io.in.ready := !stalling.head
stalling.last := valids.last && !io.out.ready
(stalling.init, stalling.tail, valids.init).zipped.foreach { case (s1, s2, v1) =>
s1 := v1 && s2
}
// Valid signals
// When the pipeline stage ahead of you isn't stalling, then make yourself invalid
io.out.valid := valids.last
when(io.out.ready) {
valids.last := false.B
}
(valids.init, stalling.tail).zipped.foreach { case (v1, s2) =>
when(!s2) {
v1 := false.B
}
}
// When the pipeline stage behind you is valid then become true
when(io.in.fire) {
valids.head := true.B
}
(valids.tail, valids.init).zipped.foreach { case (v2, v1) =>
when(v1) {
v2 := true.B
}
}
// Stages
when(io.in.fire) {
stages.head := comb.head(io.in.bits)
}
io.out.bits := comb.last(stages.last)
((stages.tail zip stages.init) zip (stalling.tail zip comb.tail.init)).foreach { case ((st2, st1), (s2, c1)) =>
when(!s2) {
st2 := c1(st1)
}
}
}
}
object Pipeline {
def apply[T <: Data](in: ReadyValidIO[T], latency: Int, comb: Seq[T => T]): DecoupledIO[T] = {
val p = Module(new Pipeline(in.bits.cloneType, latency)(comb))
p.io.in <> in
p.io.out
}
def apply[T <: Data](in: ReadyValidIO[T], latency: Int): DecoupledIO[T] = {
val p = Module(new Pipeline(in.bits.cloneType, latency)())
p.io.in <> in
p.io.out
}
}
File AccumulatorScale.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
class AccumulatorReadRespWithFullData[T <: Data: Arithmetic, U <: Data](fullDataType: Vec[Vec[T]], scale_t: U)
extends Bundle {
val resp = new AccumulatorReadResp(fullDataType, scale_t)
val full_data = fullDataType.cloneType
}
class AccumulatorScaleResp[T <: Data: Arithmetic](fullDataType: Vec[Vec[T]], rDataType: Vec[Vec[T]]) extends Bundle {
val full_data = fullDataType.cloneType
val data = rDataType.cloneType
val acc_bank_id = UInt(2.W)
val fromDMA = Bool()
}
class AccumulatorScaleIO[T <: Data: Arithmetic, U <: Data](
fullDataType: Vec[Vec[T]], scale_t: U,
rDataType: Vec[Vec[T]]
) extends Bundle {
val in = Flipped(Decoupled(new NormalizedOutput[T,U](fullDataType, scale_t)))
val out = Decoupled(new AccumulatorScaleResp[T](fullDataType, rDataType))
}
class AccScaleDataWithIndex[T <: Data: Arithmetic, U <: Data](t: T, u: U) extends Bundle {
val scale = u.cloneType
val act = UInt(Activation.bitwidth.W)
val igelu_qb = t.cloneType
val igelu_qc = t.cloneType
val iexp_qln2 = t.cloneType
val iexp_qln2_inv = t.cloneType
val mean = t.cloneType
val max = t.cloneType
val inv_stddev = u.cloneType
val inv_sum_exp = u.cloneType
val data = t.cloneType
val full_data = t.cloneType
val id = UInt(2.W) // TODO hardcoded
val index = UInt()
}
class AccScalePipe[T <: Data, U <: Data](t: T, rDataType: Vec[Vec[T]], scale_func: (T, U) => T, scale_t: U,
latency: Int, has_nonlinear_activations: Boolean, has_normalizations: Boolean)
(implicit ev: Arithmetic[T]) extends Module {
val u = scale_t
val io = IO(new Bundle {
val in = Input(Valid(new AccScaleDataWithIndex(t, u)(ev)))
val out = Output(Valid(new AccScaleDataWithIndex(t, u)(ev)))
})
import ev._
val out = WireInit(io.in)
val e = io.in.bits.data
val act = io.in.bits.act
// make sure no normalizations gets passed in if no functional units present
assert(has_normalizations.B || (!io.in.fire) ||
(act =/= Activation.LAYERNORM && act =/= Activation.SOFTMAX && act =/= Activation.IGELU))
val e_act = MuxCase(e, Seq(
(has_nonlinear_activations.B && act === Activation.RELU) -> e.relu,
(has_nonlinear_activations.B && has_normalizations.B && act === Activation.LAYERNORM) ->
(e - io.in.bits.mean),
(has_nonlinear_activations.B && has_normalizations.B && act === Activation.IGELU) ->
AccumulatorScale.igelu(e, io.in.bits.igelu_qb, io.in.bits.igelu_qc),
(has_nonlinear_activations.B && has_normalizations.B && act === Activation.SOFTMAX) ->
AccumulatorScale.iexp(e - io.in.bits.max, io.in.bits.iexp_qln2, io.in.bits.iexp_qln2_inv, io.in.bits.igelu_qb, io.in.bits.igelu_qc),
))
val e_scaled = scale_func(e_act, MuxCase(io.in.bits.scale, Seq(
(has_nonlinear_activations.B && has_normalizations.B && act === Activation.LAYERNORM) ->
io.in.bits.inv_stddev,
(has_nonlinear_activations.B && has_normalizations.B && act === Activation.SOFTMAX) ->
io.in.bits.inv_sum_exp.asTypeOf(scale_t)
)).asTypeOf(scale_t))
val e_clipped = e_scaled.clippedToWidthOf(rDataType.head.head)
out.bits.data := e_clipped
io.out := Pipe(out, latency)
}
class AccumulatorScale[T <: Data, U <: Data](
fullDataType: Vec[Vec[T]], rDataType: Vec[Vec[T]],
scale_t: U,
read_small_data: Boolean, read_full_data: Boolean,
scale_func: (T, U) => T,
num_scale_units: Int,
latency: Int,
has_nonlinear_activations: Boolean, has_normalizations: Boolean)(implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new AccumulatorScaleIO[T,U](
fullDataType, scale_t, rDataType
)(ev))
val t = io.in.bits.acc_read_resp.data(0)(0).cloneType
val acc_read_data = io.in.bits.acc_read_resp.data
val out = Wire(Decoupled(new AccumulatorScaleResp[T](
fullDataType, rDataType)(ev)))
if (num_scale_units == -1) {
val data = io.in.bits.acc_read_resp.data
val act = io.in.bits.acc_read_resp.act
val igelu_qb = io.in.bits.acc_read_resp.igelu_qb
val igelu_qc = io.in.bits.acc_read_resp.igelu_qc
val iexp_qln2 = io.in.bits.acc_read_resp.iexp_qln2
val iexp_qln2_inv = io.in.bits.acc_read_resp.iexp_qln2_inv
val scale = io.in.bits.acc_read_resp.scale
val activated_data = VecInit(data.map(v => VecInit(v.map { e =>
val e_act = MuxCase(e, Seq(
(has_nonlinear_activations.B && act === Activation.RELU) -> e.relu,
(has_nonlinear_activations.B && has_normalizations.B && act === Activation.LAYERNORM) ->
(e - io.in.bits.mean),
(has_nonlinear_activations.B && has_normalizations.B && act === Activation.IGELU) ->
AccumulatorScale.igelu(e, igelu_qb, igelu_qc),
(has_nonlinear_activations.B && has_normalizations.B && act === Activation.SOFTMAX) ->
AccumulatorScale.iexp(e - io.in.bits.max, iexp_qln2, iexp_qln2_inv, igelu_qb, igelu_qc),
))
val e_scaled = scale_func(e_act, MuxCase(scale, Seq(
(has_nonlinear_activations.B && has_normalizations.B && act === Activation.LAYERNORM) ->
io.in.bits.inv_stddev,
(has_nonlinear_activations.B && has_normalizations.B && act === Activation.SOFTMAX) ->
io.in.bits.inv_sum_exp.asTypeOf(scale_t)
)).asTypeOf(scale_t))
val e_clipped = e_scaled.clippedToWidthOf(rDataType.head.head)
e_clipped
})))
val in = Wire(Decoupled(new AccumulatorReadRespWithFullData(fullDataType, scale_t)(ev)))
in.valid := io.in.valid
io.in.ready := in.ready
in.bits.resp := io.in.bits.acc_read_resp
in.bits.full_data := acc_read_data
in.bits.resp.data := activated_data
val pipe_out = Pipeline(in, latency)
out.valid := pipe_out.valid
pipe_out.ready := out.ready
out.bits.full_data := pipe_out.bits.full_data
out.bits.data := pipe_out.bits.resp.data
out.bits.fromDMA := pipe_out.bits.resp.fromDMA
out.bits.acc_bank_id := pipe_out.bits.resp.acc_bank_id
} else {
val width = acc_read_data.size * acc_read_data(0).size
val nEntries = 3
/*val regs = Reg(Vec(nEntries, Valid(new AccumulatorReadResp[T,U](
fullDataType, scale_t)(ev))))*/
val regs = Reg(Vec(nEntries, Valid(new NormalizedOutput[T,U](
fullDataType, scale_t)(ev))))
val out_regs = Reg(Vec(nEntries, new AccumulatorScaleResp[T](
fullDataType, rDataType)(ev)))
val fired_masks = Reg(Vec(nEntries, Vec(width, Bool())))
val completed_masks = Reg(Vec(nEntries, Vec(width, Bool())))
val head_oh = RegInit(1.U(nEntries.W))
val tail_oh = RegInit(1.U(nEntries.W))
out.valid := Mux1H(head_oh.asBools, (regs zip completed_masks).map({case (r, c) => r.valid && c.reduce(_&&_)}))
out.bits := Mux1H(head_oh.asBools, out_regs)
when (out.fire) {
for (i <- 0 until nEntries) {
when (head_oh(i)) {
regs(i).valid := false.B
}
}
head_oh := (head_oh << 1).asUInt | head_oh(nEntries-1)
}
io.in.ready := !Mux1H(tail_oh.asBools, regs.map(_.valid)) || (tail_oh === head_oh && out.fire)
when (io.in.fire) {
for (i <- 0 until nEntries) {
when (tail_oh(i)) {
regs(i).valid := true.B
regs(i).bits := io.in.bits
out_regs(i).fromDMA := io.in.bits.acc_read_resp.fromDMA
out_regs(i).acc_bank_id := io.in.bits.acc_read_resp.acc_bank_id
fired_masks(i).foreach(_ := false.B)
completed_masks(i).foreach(_ := false.B)
}
}
tail_oh := (tail_oh << 1).asUInt | tail_oh(nEntries-1)
}
val num_units_with_norm = 4 // TODO: move to configs
val inputs_norm = Seq.fill(width*nEntries) { Wire(Decoupled(new AccScaleDataWithIndex(t, scale_t)(ev))) }
val inputs_non_norm = Seq.fill(width*nEntries) { Wire(Decoupled(new AccScaleDataWithIndex(t, scale_t)(ev))) }
val norm_mask = regs.map(r => r.valid && (
(r.bits.acc_read_resp.act === Activation.SOFTMAX) ||
(r.bits.acc_read_resp.act === Activation.LAYERNORM) ||
(r.bits.acc_read_resp.act === Activation.IGELU)
))
// input: norm_mask
// output: {b2, b1, b0} <-> b_i = whether entry i should use functional units with norm (1 = should)
val static_assignment_policy = Wire(Vec(1 << nEntries, UInt(nEntries.W)))
println("static policy for " + num_units_with_norm + " norm units:")
for (i <- 0 until (1 << nEntries)) {
val binaryString = String.format("%" + nEntries + "s", i.toBinaryString)
.replace(' ', '0').toCharArray.toList
val num_norm : Int = binaryString.count(_ == '1')
val ratio_of_norm_entries = num_norm.toFloat / nEntries.toFloat
val ratio_of_norm_units = num_units_with_norm.toFloat / num_scale_units.toFloat
if (ratio_of_norm_entries >= ratio_of_norm_units) {
// use norm units for all norm entries
static_assignment_policy(i.U) := i.U
println("input pattern " + binaryString.mkString("") + ": " + binaryString.mkString(""))
} else {
def flip_n_zeros (s: List[Char], n: Int): List[Char] = {
if (s.nonEmpty) {
if ((s.head == '0') && (n > 0))
'1' :: flip_n_zeros(s.tail, n - 1)
else
s.head :: flip_n_zeros(s.tail, n)
} else {
assert(n == 0, "cannot flip " + n + " zeros in an empty string")
List.empty
}
}
val flippedString = flip_n_zeros(
binaryString, Math.round(ratio_of_norm_units * nEntries) - num_norm)
val flipped = Integer.parseInt(flippedString.mkString(""), 2)
static_assignment_policy(i.U) := flipped.U
println("input pattern " + binaryString.mkString("") + ": " + flipped.toBinaryString)
}
}
// val inputs = Seq.fill(width*nEntries) { Wire(Decoupled(new AccScaleDataWithIndex(t, scale_t)(ev))) }
val current_policy = Wire(UInt(nEntries.W))
val norm_mask_int = Wire(UInt(nEntries.W))
norm_mask_int := VecInit(norm_mask).asUInt
dontTouch(norm_mask_int)
current_policy := static_assignment_policy(norm_mask_int)
for (i <- 0 until nEntries) {
for (w <- 0 until width) {
val input = inputs_norm(i*width+w)
val acc_read_resp = regs(i).bits.acc_read_resp
input.valid := regs(i).valid && !fired_masks(i)(w) && /*norm_mask(i)*/ current_policy(i)
input.bits.data := acc_read_resp.data(w / acc_read_data(0).size)(w % acc_read_data(0).size)
input.bits.full_data := acc_read_resp.data(w / acc_read_data(0).size)(w % acc_read_data(0).size)
input.bits.scale := acc_read_resp.scale
input.bits.act := acc_read_resp.act
input.bits.igelu_qb := acc_read_resp.igelu_qb
input.bits.igelu_qc := acc_read_resp.igelu_qc
input.bits.iexp_qln2 := acc_read_resp.iexp_qln2
input.bits.iexp_qln2_inv := acc_read_resp.iexp_qln2_inv
input.bits.mean := regs(i).bits.mean
input.bits.max := regs(i).bits.max
input.bits.inv_stddev := regs(i).bits.inv_stddev
input.bits.inv_sum_exp := regs(i).bits.inv_sum_exp
input.bits.id := i.U
input.bits.index := w.U
when (input.fire) {
fired_masks(i)(w) := true.B
}
}
}
for (i <- 0 until nEntries) {
for (w <- 0 until width) {
val input = inputs_non_norm(i*width+w)
val acc_read_resp = regs(i).bits.acc_read_resp
input.valid := regs(i).valid && !fired_masks(i)(w) && (!current_policy(i))
input.bits.data := acc_read_resp.data(w / acc_read_data(0).size)(w % acc_read_data(0).size)
input.bits.full_data := acc_read_resp.data(w / acc_read_data(0).size)(w % acc_read_data(0).size)
input.bits.scale := acc_read_resp.scale
input.bits.act := acc_read_resp.act
input.bits.igelu_qb := DontCare
input.bits.igelu_qc := DontCare
input.bits.iexp_qln2 := DontCare
input.bits.iexp_qln2_inv := DontCare
input.bits.mean := DontCare
input.bits.max := DontCare
input.bits.inv_stddev := DontCare
input.bits.inv_sum_exp := DontCare
input.bits.id := i.U
input.bits.index := w.U
if (num_scale_units == num_units_with_norm) {
input.ready := false.B
}
when (input.fire) {
fired_masks(i)(w) := true.B
}
}
}
for (i <- 0 until num_scale_units) {
val norm_supported = (i < num_units_with_norm) && has_normalizations
val arbIn =
if (norm_supported)
// for norm units, prioritize norm operations
inputs_norm.zipWithIndex.filter({ case (_, w) => w % num_units_with_norm == i }).map(_._1)
else
inputs_non_norm.zipWithIndex.filter({ case (_, w) => w % (num_scale_units - num_units_with_norm) == (i - num_units_with_norm) }).map(_._1)
val arb = Module(new RRArbiter(new AccScaleDataWithIndex(t, scale_t)(ev), arbIn.length))
arb.io.in <> arbIn
arb.io.out.ready := true.B
val arbOut = Reg(Valid(new AccScaleDataWithIndex(t, scale_t)(ev)))
arbOut.valid := arb.io.out.valid
arbOut.bits := arb.io.out.bits
when (reset.asBool) {
arbOut.valid := false.B
}
val pipe = Module(new AccScalePipe(t, rDataType, scale_func, scale_t, latency,
has_nonlinear_activations, norm_supported))
pipe.io.in := arbOut
val pipe_out = pipe.io.out
for (j <- 0 until nEntries) {
for (w <- 0 until width) {
val id0 = w % acc_read_data(0).size
val id1 = w / acc_read_data(0).size
if ((j*width+w) % num_units_with_norm == i) {
when (pipe_out.fire && pipe_out.bits.id === j.U && pipe_out.bits.index === w.U) {
out_regs(j).data (id1)(id0) := pipe_out.bits.data
out_regs(j).full_data(id1)(id0) := pipe_out.bits.full_data
completed_masks(j)(w) := true.B
}
}
if (num_scale_units > num_units_with_norm) {
if ((j*width+w) % (num_scale_units - num_units_with_norm) == (i - num_units_with_norm)) {
val id0 = w % acc_read_data(0).size
val id1 = w / acc_read_data(0).size
when (pipe_out.fire && pipe_out.bits.id === j.U && pipe_out.bits.index === w.U) {
out_regs(j).data (id1)(id0) := pipe_out.bits.data
out_regs(j).full_data(id1)(id0) := pipe_out.bits.full_data
completed_masks(j)(w) := true.B
}
}
}
}
}
}
when (reset.asBool) {
regs.foreach(_.valid := false.B)
}
}
io.out <> out
if (read_small_data)
io.out.bits.data := out.bits.data
else
io.out.bits.data := DontCare
if (read_full_data)
io.out.bits.full_data := out.bits.full_data
else
io.out.bits.full_data := DontCare
}
object AccumulatorScale {
def igelu[T <: Data](q: T, qb: T, qc: T)(implicit ev: Arithmetic[T]): T = {
import ev._
val zero = q.zero
val one = q.identity
def neg(x: T) = zero-x
val q_sign = Mux(q.zero > q, neg(one), one)
val q_abs = Mux(q.zero > q, neg(q), q)
val q_clipped = Mux(q_abs > neg(qb), neg(qb), q_abs)
val q_poly = qc.mac(q_clipped + qb, q_clipped + qb).withWidthOf(q)
val q_erf = (q_sign * q_poly).withWidthOf(q)
(q * (q_erf + qc)).withWidthOf(q)
}
def iexp[T <: Data](q: T, qln2: T, qln2_inv: T, qb: T, qc: T)(implicit ev: Arithmetic[T]): T = {
import ev._
val zero = q.zero
def neg(x: T) = zero-x
// qln2_inv needs scale to be 1 / (2 ** 16) / S
// qln2_inv / S / (2 ** 16) = 1 / ln2
// q * qln2_inv = x / S / ln2 * S * (2 ** 16) = x / ln2 * (2 ** 16)
val neg_q_iexp = neg(q)
val z_iexp = (neg_q_iexp * qln2_inv).asUInt.do_>>(16).asTypeOf(q) // q is non-positive
val z_iexp_saturated = Wire(z_iexp.cloneType)
z_iexp_saturated := Mux((5 until 16).map(z_iexp.asUInt(_)).reduce(_ | _), 32.S.asTypeOf(z_iexp), z_iexp)
val qp_iexp = q.mac(z_iexp, qln2).withWidthOf(q)
val q_poly_iexp = qc.mac(qp_iexp + qb, qp_iexp + qb).withWidthOf(q)
// we dont want a rounding shift
// TODO: z overflow
(q_poly_iexp.asUInt.do_>>(z_iexp_saturated.asUInt)).asTypeOf(q)
}}
File rawFloatFromFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
object rawFloatFromFN {
def apply(expWidth: Int, sigWidth: Int, in: Bits) = {
val sign = in(expWidth + sigWidth - 1)
val expIn = in(expWidth + sigWidth - 2, sigWidth - 1)
val fractIn = in(sigWidth - 2, 0)
val isZeroExpIn = (expIn === 0.U)
val isZeroFractIn = (fractIn === 0.U)
val normDist = countLeadingZeros(fractIn)
val subnormFract = (fractIn << normDist) (sigWidth - 3, 0) << 1
val adjustedExp =
Mux(isZeroExpIn,
normDist ^ ((BigInt(1) << (expWidth + 1)) - 1).U,
expIn
) + ((BigInt(1) << (expWidth - 1)).U
| Mux(isZeroExpIn, 2.U, 1.U))
val isZero = isZeroExpIn && isZeroFractIn
val isSpecial = adjustedExp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && !isZeroFractIn
out.isInf := isSpecial && isZeroFractIn
out.isZero := isZero
out.sign := sign
out.sExp := adjustedExp(expWidth, 0).zext
out.sig :=
0.U(1.W) ## !isZero ## Mux(isZeroExpIn, subnormFract, fractIn)
out
}
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
|
module AccumulatorScale( // @[AccumulatorScale.scala:88:7]
input clock, // @[AccumulatorScale.scala:88:7]
input reset, // @[AccumulatorScale.scala:88:7]
output io_in_ready, // @[AccumulatorScale.scala:99:14]
input io_in_valid, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_0_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_1_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_2_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_3_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_4_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_5_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_6_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_7_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_8_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_9_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_10_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_11_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_12_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_13_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_14_0, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_data_15_0, // @[AccumulatorScale.scala:99:14]
input io_in_bits_acc_read_resp_fromDMA, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_scale_bits, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_igelu_qb, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_igelu_qc, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_iexp_qln2, // @[AccumulatorScale.scala:99:14]
input [31:0] io_in_bits_acc_read_resp_iexp_qln2_inv, // @[AccumulatorScale.scala:99:14]
input [2:0] io_in_bits_acc_read_resp_act, // @[AccumulatorScale.scala:99:14]
input [1:0] io_in_bits_acc_read_resp_acc_bank_id, // @[AccumulatorScale.scala:99:14]
input io_out_ready, // @[AccumulatorScale.scala:99:14]
output io_out_valid, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_0_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_1_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_2_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_3_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_4_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_5_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_6_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_7_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_8_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_9_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_10_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_11_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_12_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_13_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_14_0, // @[AccumulatorScale.scala:99:14]
output [7:0] io_out_bits_data_15_0, // @[AccumulatorScale.scala:99:14]
output [1:0] io_out_bits_acc_bank_id, // @[AccumulatorScale.scala:99:14]
output io_out_bits_fromDMA // @[AccumulatorScale.scala:99:14]
);
wire activated_data_e_scaled_f_rec_rawIn_15_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_14_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_13_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_12_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_11_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_10_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_9_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_8_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_7_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_6_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_5_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_4_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_3_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19]
wire activated_data_e_scaled_f_rec_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_0_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_1_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_2_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_3_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_4_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_5_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_6_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_7_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_8_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_9_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_10_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_11_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_12_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_13_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_14_0; // @[Pipeline.scala:75:19]
wire [31:0] _pipe_out_p_io_out_bits_resp_data_15_0; // @[Pipeline.scala:75:19]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_15_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_15_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_15_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_14_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_14_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_14_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_13_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_13_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_13_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_12_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_12_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_12_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_11_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_11_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_11_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_10_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_10_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_10_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_9_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_9_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_9_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_8_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_8_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_8_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_7_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_7_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_7_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_6_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_6_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_6_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_5_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_5_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_5_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_4_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_4_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_4_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_3_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_3_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_3_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_2_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_2_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_2_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_1_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_1_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_1_io_out; // @[Configs.scala:118:34]
wire [2:0] _activated_data_e_scaled_rec_fn_to_in_io_intExceptionFlags; // @[Configs.scala:135:34]
wire [32:0] _activated_data_e_scaled_muladder_io_out; // @[Configs.scala:126:30]
wire [32:0] _activated_data_e_scaled_in_to_rec_fn_io_out; // @[Configs.scala:118:34]
wire io_in_valid_0 = io_in_valid; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_0_0_0 = io_in_bits_acc_read_resp_data_0_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_1_0_0 = io_in_bits_acc_read_resp_data_1_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_2_0_0 = io_in_bits_acc_read_resp_data_2_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_3_0_0 = io_in_bits_acc_read_resp_data_3_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_4_0_0 = io_in_bits_acc_read_resp_data_4_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_5_0_0 = io_in_bits_acc_read_resp_data_5_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_6_0_0 = io_in_bits_acc_read_resp_data_6_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_7_0_0 = io_in_bits_acc_read_resp_data_7_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_8_0_0 = io_in_bits_acc_read_resp_data_8_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_9_0_0 = io_in_bits_acc_read_resp_data_9_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_10_0_0 = io_in_bits_acc_read_resp_data_10_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_11_0_0 = io_in_bits_acc_read_resp_data_11_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_12_0_0 = io_in_bits_acc_read_resp_data_12_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_13_0_0 = io_in_bits_acc_read_resp_data_13_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_14_0_0 = io_in_bits_acc_read_resp_data_14_0; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_data_15_0_0 = io_in_bits_acc_read_resp_data_15_0; // @[AccumulatorScale.scala:88:7]
wire io_in_bits_acc_read_resp_fromDMA_0 = io_in_bits_acc_read_resp_fromDMA; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_scale_bits_0 = io_in_bits_acc_read_resp_scale_bits; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_igelu_qb_0 = io_in_bits_acc_read_resp_igelu_qb; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_igelu_qc_0 = io_in_bits_acc_read_resp_igelu_qc; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_iexp_qln2_0 = io_in_bits_acc_read_resp_iexp_qln2; // @[AccumulatorScale.scala:88:7]
wire [31:0] io_in_bits_acc_read_resp_iexp_qln2_inv_0 = io_in_bits_acc_read_resp_iexp_qln2_inv; // @[AccumulatorScale.scala:88:7]
wire [2:0] io_in_bits_acc_read_resp_act_0 = io_in_bits_acc_read_resp_act; // @[AccumulatorScale.scala:88:7]
wire [1:0] io_in_bits_acc_read_resp_acc_bank_id_0 = io_in_bits_acc_read_resp_acc_bank_id; // @[AccumulatorScale.scala:88:7]
wire io_out_ready_0 = io_out_ready; // @[AccumulatorScale.scala:88:7]
wire [2:0] _activated_data_e_act_q_sign_T_1 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_5 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_9 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_13 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_17 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_21 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_25 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_29 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_33 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_37 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_41 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_45 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_49 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_53 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_57 = 3'h7; // @[Arithmetic.scala:95:38]
wire [2:0] _activated_data_e_act_q_sign_T_61 = 3'h7; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_2 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_3 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_6 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_7 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_10 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_11 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_14 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_15 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_18 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_19 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_22 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_23 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_26 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_27 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_30 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_31 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_34 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_35 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_38 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_39 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_42 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_43 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_46 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_47 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_50 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_51 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_54 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_55 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_58 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_59 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_62 = 2'h3; // @[Arithmetic.scala:95:38]
wire [1:0] _activated_data_e_act_q_sign_T_63 = 2'h3; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_1 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_2 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_3 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_4 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_5 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_6 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_7 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_8 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_9 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_10 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_11 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_12 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_13 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_14 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire [31:0] _activated_data_e_act_z_iexp_saturated_WIRE_15 = 32'h20; // @[AccumulatorScale.scala:400:92]
wire _activated_data_e_act_T_4 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_6 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_10 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_12 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_19 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_21 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_2 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_3 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_5 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_36 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_38 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_42 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_44 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_51 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_53 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_11 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_13 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_14 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_16 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_68 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_70 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_74 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_76 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_83 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_85 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_22 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_24 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_25 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_27 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_100 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_102 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_106 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_108 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_115 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_117 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_33 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_35 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_36 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_38 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_132 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_134 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_138 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_140 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_147 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_149 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_44 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_46 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_47 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_49 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_164 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_166 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_170 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_172 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_179 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_181 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_55 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_57 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_58 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_60 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_196 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_198 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_202 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_204 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_211 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_213 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_66 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_68 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_69 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_71 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_228 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_230 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_234 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_236 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_243 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_245 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_77 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_79 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_80 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_82 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_260 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_262 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_266 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_268 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_275 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_277 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_88 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_90 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_91 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_93 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_292 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_294 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_298 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_300 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_307 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_309 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_99 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_101 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_102 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_104 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_324 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_326 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_330 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_332 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_339 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_341 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_110 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_112 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_113 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_115 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_356 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_358 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_362 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_364 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_371 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_373 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_121 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_123 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_124 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_126 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_388 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_390 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_394 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_396 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_403 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_405 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_132 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_134 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_135 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_137 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_420 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_422 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_426 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_428 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_435 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_437 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_143 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_145 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_146 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_148 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_452 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_454 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_458 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_460 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_467 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_469 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_154 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_156 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_157 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_159 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire _activated_data_e_act_T_484 = 1'h0; // @[AccumulatorScale.scala:119:38]
wire _activated_data_e_act_T_486 = 1'h0; // @[AccumulatorScale.scala:119:62]
wire _activated_data_e_act_T_490 = 1'h0; // @[AccumulatorScale.scala:121:38]
wire _activated_data_e_act_T_492 = 1'h0; // @[AccumulatorScale.scala:121:62]
wire _activated_data_e_act_T_499 = 1'h0; // @[AccumulatorScale.scala:123:38]
wire _activated_data_e_act_T_501 = 1'h0; // @[AccumulatorScale.scala:123:62]
wire _activated_data_e_scaled_T_165 = 1'h0; // @[AccumulatorScale.scala:128:38]
wire _activated_data_e_scaled_T_167 = 1'h0; // @[AccumulatorScale.scala:128:62]
wire _activated_data_e_scaled_T_168 = 1'h0; // @[AccumulatorScale.scala:130:38]
wire _activated_data_e_scaled_T_170 = 1'h0; // @[AccumulatorScale.scala:130:62]
wire [31:0] io_in_bits_mean = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_in_bits_max = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_in_bits_inv_stddev_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_in_bits_inv_sum_exp_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_0_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_1_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_2_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_3_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_4_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_5_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_6_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_7_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_8_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_9_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_10_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_11_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_12_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_13_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_14_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] io_out_bits_full_data_15_0 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_1 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_6 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_5_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_6 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_17 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_10_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_11 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_28 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_15_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_16 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_39 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_20_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_21 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_50 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_25_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_26 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_61 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_30_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_31 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_72 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_35_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_36 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_83 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_40_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_41 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_94 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_45_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_46 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_105 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_50_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_51 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_116 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_55_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_56 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_127 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_60_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_61 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_138 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_65_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_66 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_149 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_70_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_71 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_160 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_75_bits = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_WIRE_76 = 32'h0; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_scaled_T_171 = 32'h0; // @[Arithmetic.scala:128:42]
wire in_ready; // @[AccumulatorScale.scala:139:18]
wire in_valid = io_in_valid_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_29 = io_in_bits_acc_read_resp_data_0_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_0_0 = io_in_bits_acc_read_resp_data_0_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_61 = io_in_bits_acc_read_resp_data_1_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_1_0 = io_in_bits_acc_read_resp_data_1_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_93 = io_in_bits_acc_read_resp_data_2_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_2_0 = io_in_bits_acc_read_resp_data_2_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_125 = io_in_bits_acc_read_resp_data_3_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_3_0 = io_in_bits_acc_read_resp_data_3_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_157 = io_in_bits_acc_read_resp_data_4_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_4_0 = io_in_bits_acc_read_resp_data_4_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_189 = io_in_bits_acc_read_resp_data_5_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_5_0 = io_in_bits_acc_read_resp_data_5_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_221 = io_in_bits_acc_read_resp_data_6_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_6_0 = io_in_bits_acc_read_resp_data_6_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_253 = io_in_bits_acc_read_resp_data_7_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_7_0 = io_in_bits_acc_read_resp_data_7_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_285 = io_in_bits_acc_read_resp_data_8_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_8_0 = io_in_bits_acc_read_resp_data_8_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_317 = io_in_bits_acc_read_resp_data_9_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_9_0 = io_in_bits_acc_read_resp_data_9_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_349 = io_in_bits_acc_read_resp_data_10_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_10_0 = io_in_bits_acc_read_resp_data_10_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_381 = io_in_bits_acc_read_resp_data_11_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_11_0 = io_in_bits_acc_read_resp_data_11_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_413 = io_in_bits_acc_read_resp_data_12_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_12_0 = io_in_bits_acc_read_resp_data_12_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_445 = io_in_bits_acc_read_resp_data_13_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_13_0 = io_in_bits_acc_read_resp_data_13_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_477 = io_in_bits_acc_read_resp_data_14_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_14_0 = io_in_bits_acc_read_resp_data_14_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_act_T_509 = io_in_bits_acc_read_resp_data_15_0_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_full_data_15_0 = io_in_bits_acc_read_resp_data_15_0_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire in_bits_resp_fromDMA = io_in_bits_acc_read_resp_fromDMA_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] _activated_data_e_scaled_T_7_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_18_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_29_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_40_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_51_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_62_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_73_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_84_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_95_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_106_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_117_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_128_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_139_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_150_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_161_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_172_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[Mux.scala:126:16]
wire [31:0] in_bits_resp_scale_bits = io_in_bits_acc_read_resp_scale_bits_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] in_bits_resp_igelu_qb = io_in_bits_acc_read_resp_igelu_qb_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] in_bits_resp_igelu_qc = io_in_bits_acc_read_resp_igelu_qc_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] in_bits_resp_iexp_qln2 = io_in_bits_acc_read_resp_iexp_qln2_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] in_bits_resp_iexp_qln2_inv = io_in_bits_acc_read_resp_iexp_qln2_inv_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [2:0] in_bits_resp_act = io_in_bits_acc_read_resp_act_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire [1:0] in_bits_resp_acc_bank_id = io_in_bits_acc_read_resp_acc_bank_id_0; // @[AccumulatorScale.scala:88:7, :139:18]
wire out_ready = io_out_ready_0; // @[AccumulatorScale.scala:88:7, :104:17]
wire out_valid; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_0_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_1_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_2_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_3_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_4_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_5_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_6_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_7_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_8_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_9_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_10_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_11_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_12_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_13_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_14_0; // @[AccumulatorScale.scala:104:17]
wire [7:0] out_bits_data_15_0; // @[AccumulatorScale.scala:104:17]
wire [1:0] out_bits_acc_bank_id; // @[AccumulatorScale.scala:104:17]
wire out_bits_fromDMA; // @[AccumulatorScale.scala:104:17]
wire io_in_ready_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_0_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_1_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_2_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_3_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_4_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_5_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_6_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_7_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_8_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_9_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_10_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_11_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_12_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_13_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_14_0_0; // @[AccumulatorScale.scala:88:7]
wire [7:0] io_out_bits_data_15_0_0; // @[AccumulatorScale.scala:88:7]
wire [1:0] io_out_bits_acc_bank_id_0; // @[AccumulatorScale.scala:88:7]
wire io_out_bits_fromDMA_0; // @[AccumulatorScale.scala:88:7]
wire io_out_valid_0; // @[AccumulatorScale.scala:88:7]
assign io_out_valid_0 = out_valid; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_0_0_0 = out_bits_data_0_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_1_0_0 = out_bits_data_1_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_2_0_0 = out_bits_data_2_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_3_0_0 = out_bits_data_3_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_4_0_0 = out_bits_data_4_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_5_0_0 = out_bits_data_5_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_6_0_0 = out_bits_data_6_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_7_0_0 = out_bits_data_7_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_8_0_0 = out_bits_data_8_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_9_0_0 = out_bits_data_9_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_10_0_0 = out_bits_data_10_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_11_0_0 = out_bits_data_11_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_12_0_0 = out_bits_data_12_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_13_0_0 = out_bits_data_13_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_14_0_0 = out_bits_data_14_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_data_15_0_0 = out_bits_data_15_0; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_acc_bank_id_0 = out_bits_acc_bank_id; // @[AccumulatorScale.scala:88:7, :104:17]
assign io_out_bits_fromDMA_0 = out_bits_fromDMA; // @[AccumulatorScale.scala:88:7, :104:17]
wire [31:0] out_bits_full_data_0_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_1_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_2_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_3_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_4_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_5_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_6_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_7_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_8_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_9_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_10_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_11_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_12_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_13_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_14_0; // @[AccumulatorScale.scala:104:17]
wire [31:0] out_bits_full_data_15_0; // @[AccumulatorScale.scala:104:17]
wire _GEN = io_in_bits_acc_read_resp_act_0 == 3'h1; // @[AccumulatorScale.scala:88:7, :118:45]
wire _activated_data_e_act_T; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_32; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_32 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_64; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_64 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_96; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_96 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_128; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_128 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_160; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_160 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_192; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_192 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_224; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_224 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_256; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_256 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_288; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_288 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_320; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_320 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_352; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_352 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_384; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_384 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_416; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_416 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_448; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_448 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_480; // @[AccumulatorScale.scala:118:45]
assign _activated_data_e_act_T_480 = _GEN; // @[AccumulatorScale.scala:118:45]
wire _activated_data_e_act_T_1 = _activated_data_e_act_T; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_2 = $signed(io_in_bits_acc_read_resp_data_0_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_3 = _activated_data_e_act_T_2 ? io_in_bits_acc_read_resp_data_0_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire _GEN_0 = io_in_bits_acc_read_resp_act_0 == 3'h2; // @[AccumulatorScale.scala:88:7, :119:69]
wire _activated_data_e_act_T_5; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_5 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_1; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_1 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_37; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_37 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_12; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_12 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_69; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_69 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_23; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_23 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_101; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_101 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_34; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_34 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_133; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_133 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_45; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_45 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_165; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_165 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_56; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_56 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_197; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_197 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_67; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_67 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_229; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_229 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_78; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_78 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_261; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_261 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_89; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_89 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_293; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_293 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_100; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_100 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_325; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_325 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_111; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_111 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_357; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_357 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_122; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_122 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_389; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_389 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_133; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_133 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_421; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_421 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_144; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_144 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_453; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_453 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_155; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_155 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire _activated_data_e_act_T_485; // @[AccumulatorScale.scala:119:69]
assign _activated_data_e_act_T_485 = _GEN_0; // @[AccumulatorScale.scala:119:69]
wire _activated_data_e_scaled_T_166; // @[AccumulatorScale.scala:128:69]
assign _activated_data_e_scaled_T_166 = _GEN_0; // @[AccumulatorScale.scala:119:69, :128:69]
wire [32:0] _GEN_1 = {io_in_bits_acc_read_resp_data_0_0_0[31], io_in_bits_acc_read_resp_data_0_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_7; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_7 = _GEN_1; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_22; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_22 = _GEN_1; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_8 = _activated_data_e_act_T_7[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_9 = _activated_data_e_act_T_8; // @[Arithmetic.scala:95:38]
wire _GEN_2 = io_in_bits_acc_read_resp_act_0 == 3'h3; // @[AccumulatorScale.scala:88:7, :121:69]
wire _activated_data_e_act_T_11; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_11 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_43; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_43 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_75; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_75 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_107; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_107 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_139; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_139 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_171; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_171 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_203; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_203 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_235; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_235 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_267; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_267 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_299; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_299 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_331; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_331 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_363; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_363 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_395; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_395 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_427; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_427 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_459; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_459 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _activated_data_e_act_T_491; // @[AccumulatorScale.scala:121:69]
assign _activated_data_e_act_T_491 = _GEN_2; // @[AccumulatorScale.scala:121:69]
wire _GEN_3 = $signed(io_in_bits_acc_read_resp_data_0_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T = _GEN_3; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T = _GEN_3; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign = {_activated_data_e_act_q_sign_T, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_1 = 33'h0 - _GEN_1; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_2 = _activated_data_e_act_q_abs_T_1[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_3 = _activated_data_e_act_q_abs_T_2; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs = _activated_data_e_act_q_abs_T ? _activated_data_e_act_q_abs_T_3 : io_in_bits_acc_read_resp_data_0_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_4 = {io_in_bits_acc_read_resp_igelu_qb_0[31], io_in_bits_acc_read_resp_igelu_qb_0}; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _GEN_5 = 33'h0 - _GEN_4; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_4; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_4 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_7; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_7 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_11; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_11 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_14; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_14 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_18; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_18 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_21; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_21 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_25; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_25 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_28; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_28 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_32; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_32 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_35; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_35 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_39; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_39 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_42; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_42 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_46; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_46 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_49; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_49 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_53; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_53 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_56; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_56 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_60; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_60 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_63; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_63 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_67; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_67 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_70; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_70 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_74; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_74 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_77; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_77 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_81; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_81 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_84; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_84 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_88; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_88 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_91; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_91 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_95; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_95 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_98; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_98 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_102; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_102 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_105; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_105 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [32:0] _activated_data_e_act_q_clipped_T_109; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_q_clipped_T_109 = _GEN_5; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_clipped_T_1 = _activated_data_e_act_q_clipped_T[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_2 = _activated_data_e_act_q_clipped_T_1; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_3 = $signed(activated_data_e_act_q_abs) > $signed(_activated_data_e_act_q_clipped_T_2); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_5 = _activated_data_e_act_q_clipped_T_4[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_6 = _activated_data_e_act_q_clipped_T_5; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped = _activated_data_e_act_q_clipped_T_3 ? _activated_data_e_act_q_clipped_T_6 : activated_data_e_act_q_abs; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_6 = {activated_data_e_act_q_clipped[31], activated_data_e_act_q_clipped} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T = _GEN_6; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_3; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_3 = _GEN_6; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_1 = _activated_data_e_act_q_poly_T[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_2 = _activated_data_e_act_q_poly_T_1; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_4 = _activated_data_e_act_q_poly_T_3[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_5 = _activated_data_e_act_q_poly_T_4; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_6 = {{32{_activated_data_e_act_q_poly_T_2[31]}}, _activated_data_e_act_q_poly_T_2} * {{32{_activated_data_e_act_q_poly_T_5[31]}}, _activated_data_e_act_q_poly_T_5}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _GEN_7 = {{33{io_in_bits_acc_read_resp_igelu_qc_0[31]}}, io_in_bits_acc_read_resp_igelu_qc_0}; // @[Arithmetic.scala:93:54]
wire [64:0] _activated_data_e_act_q_poly_T_7 = {_activated_data_e_act_q_poly_T_6[63], _activated_data_e_act_q_poly_T_6} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_8 = _activated_data_e_act_q_poly_T_7[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_9 = _activated_data_e_act_q_poly_T_8; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_10 = _activated_data_e_act_q_poly_T_9[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly = _activated_data_e_act_q_poly_T_10; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T = {{32{activated_data_e_act_q_sign[1]}}, activated_data_e_act_q_sign} * {{2{activated_data_e_act_q_poly[31]}}, activated_data_e_act_q_poly}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_1 = _activated_data_e_act_q_erf_T[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf = _activated_data_e_act_q_erf_T_1; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_8 = {io_in_bits_acc_read_resp_igelu_qc_0[31], io_in_bits_acc_read_resp_igelu_qc_0}; // @[Arithmetic.scala:93:54, :94:38]
wire [32:0] _activated_data_e_act_T_13 = {activated_data_e_act_q_erf[31], activated_data_e_act_q_erf} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_14 = _activated_data_e_act_T_13[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_15 = _activated_data_e_act_T_14; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_16 = {{32{io_in_bits_acc_read_resp_data_0_0_0[31]}}, io_in_bits_acc_read_resp_data_0_0_0} * {{32{_activated_data_e_act_T_15[31]}}, _activated_data_e_act_T_15}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_17 = _activated_data_e_act_T_16[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_18 = _activated_data_e_act_T_17; // @[Arithmetic.scala:114:{15,33}]
wire _GEN_9 = io_in_bits_acc_read_resp_act_0 == 3'h4; // @[AccumulatorScale.scala:88:7, :123:69]
wire _activated_data_e_act_T_20; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_20 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_4; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_4 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_52; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_52 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_15; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_15 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_84; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_84 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_26; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_26 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_116; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_116 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_37; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_37 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_148; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_148 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_48; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_48 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_180; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_180 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_59; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_59 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_212; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_212 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_70; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_70 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_244; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_244 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_81; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_81 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_276; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_276 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_92; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_92 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_308; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_308 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_103; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_103 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_340; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_340 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_114; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_114 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_372; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_372 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_125; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_125 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_404; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_404 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_136; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_136 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_436; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_436 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_147; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_147 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_468; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_468 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_158; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_158 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire _activated_data_e_act_T_500; // @[AccumulatorScale.scala:123:69]
assign _activated_data_e_act_T_500 = _GEN_9; // @[AccumulatorScale.scala:123:69]
wire _activated_data_e_scaled_T_169; // @[AccumulatorScale.scala:130:69]
assign _activated_data_e_scaled_T_169 = _GEN_9; // @[AccumulatorScale.scala:123:69, :130:69]
wire [31:0] _activated_data_e_act_T_23 = _activated_data_e_act_T_22[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_24 = _activated_data_e_act_T_23; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T = 33'h0 - {_activated_data_e_act_T_24[31], _activated_data_e_act_T_24}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_1 = _activated_data_e_act_neg_q_iexp_T[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp = _activated_data_e_act_neg_q_iexp_T_1; // @[Arithmetic.scala:95:38]
wire [63:0] _GEN_10 = {{32{io_in_bits_acc_read_resp_iexp_qln2_inv_0[31]}}, io_in_bits_acc_read_resp_iexp_qln2_inv_0}; // @[Arithmetic.scala:92:38]
wire [63:0] _activated_data_e_act_z_iexp_T = {{32{activated_data_e_act_neg_q_iexp[31]}}, activated_data_e_act_neg_q_iexp} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_1 = _activated_data_e_act_z_iexp_T; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_2 = _activated_data_e_act_z_iexp_T_1[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_3 = _activated_data_e_act_z_iexp_T_2; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_2 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_4 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_6 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_8 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_10 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_12 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_14 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_16 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_18 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_20 = activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp = _activated_data_e_act_z_iexp_T_3[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_32; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_26 = activated_data_e_act_z_iexp_saturated; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_1 = _activated_data_e_act_z_iexp_saturated_T[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_3 = _activated_data_e_act_z_iexp_saturated_T_2[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_5 = _activated_data_e_act_z_iexp_saturated_T_4[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_7 = _activated_data_e_act_z_iexp_saturated_T_6[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_9 = _activated_data_e_act_z_iexp_saturated_T_8[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_11 = _activated_data_e_act_z_iexp_saturated_T_10[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_13 = _activated_data_e_act_z_iexp_saturated_T_12[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_15 = _activated_data_e_act_z_iexp_saturated_T_14[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_17 = _activated_data_e_act_z_iexp_saturated_T_16[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_19 = _activated_data_e_act_z_iexp_saturated_T_18[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_21 = _activated_data_e_act_z_iexp_saturated_T_20[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_22 = _activated_data_e_act_z_iexp_saturated_T_1 | _activated_data_e_act_z_iexp_saturated_T_3; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_23 = _activated_data_e_act_z_iexp_saturated_T_22 | _activated_data_e_act_z_iexp_saturated_T_5; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_24 = _activated_data_e_act_z_iexp_saturated_T_23 | _activated_data_e_act_z_iexp_saturated_T_7; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_25 = _activated_data_e_act_z_iexp_saturated_T_24 | _activated_data_e_act_z_iexp_saturated_T_9; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_26 = _activated_data_e_act_z_iexp_saturated_T_25 | _activated_data_e_act_z_iexp_saturated_T_11; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_27 = _activated_data_e_act_z_iexp_saturated_T_26 | _activated_data_e_act_z_iexp_saturated_T_13; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_28 = _activated_data_e_act_z_iexp_saturated_T_27 | _activated_data_e_act_z_iexp_saturated_T_15; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_29 = _activated_data_e_act_z_iexp_saturated_T_28 | _activated_data_e_act_z_iexp_saturated_T_17; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_30 = _activated_data_e_act_z_iexp_saturated_T_29 | _activated_data_e_act_z_iexp_saturated_T_19; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_31 = _activated_data_e_act_z_iexp_saturated_T_30 | _activated_data_e_act_z_iexp_saturated_T_21; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_32 = _activated_data_e_act_z_iexp_saturated_T_31 ? 32'h20 : activated_data_e_act_z_iexp; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated = _activated_data_e_act_z_iexp_saturated_T_32; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _GEN_11 = {{32{io_in_bits_acc_read_resp_iexp_qln2_0[31]}}, io_in_bits_acc_read_resp_iexp_qln2_0}; // @[Arithmetic.scala:93:49]
wire [63:0] _activated_data_e_act_qp_iexp_T = {{32{activated_data_e_act_z_iexp[31]}}, activated_data_e_act_z_iexp} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_1 = {_activated_data_e_act_qp_iexp_T[63], _activated_data_e_act_qp_iexp_T} + {{33{_activated_data_e_act_T_24[31]}}, _activated_data_e_act_T_24}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_2 = _activated_data_e_act_qp_iexp_T_1[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_3 = _activated_data_e_act_qp_iexp_T_2; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_4 = _activated_data_e_act_qp_iexp_T_3[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp = _activated_data_e_act_qp_iexp_T_4; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_12 = {activated_data_e_act_qp_iexp[31], activated_data_e_act_qp_iexp} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T = _GEN_12; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_3; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_3 = _GEN_12; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_1 = _activated_data_e_act_q_poly_iexp_T[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_2 = _activated_data_e_act_q_poly_iexp_T_1; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_4 = _activated_data_e_act_q_poly_iexp_T_3[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_5 = _activated_data_e_act_q_poly_iexp_T_4; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_6 = {{32{_activated_data_e_act_q_poly_iexp_T_2[31]}}, _activated_data_e_act_q_poly_iexp_T_2} * {{32{_activated_data_e_act_q_poly_iexp_T_5[31]}}, _activated_data_e_act_q_poly_iexp_T_5}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_7 = {_activated_data_e_act_q_poly_iexp_T_6[63], _activated_data_e_act_q_poly_iexp_T_6} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_8 = _activated_data_e_act_q_poly_iexp_T_7[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_9 = _activated_data_e_act_q_poly_iexp_T_8; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_10 = _activated_data_e_act_q_poly_iexp_T_9[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp = _activated_data_e_act_q_poly_iexp_T_10; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_25 = activated_data_e_act_q_poly_iexp; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_27 = _activated_data_e_act_T_25 >> _activated_data_e_act_T_26; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_28 = _activated_data_e_act_T_27; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE = _activated_data_e_act_T_28; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_30 = _activated_data_e_act_T_29; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_31 = _activated_data_e_act_T_30; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act = _activated_data_e_act_T_1 ? _activated_data_e_act_T_3 : _activated_data_e_act_T_31; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T = activated_data_e_act; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_8_bits = _activated_data_e_scaled_T_7_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_3 = _activated_data_e_scaled_T_8_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_9; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_9 = _activated_data_e_scaled_WIRE_3; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_2_bits = _activated_data_e_scaled_T_9; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign = _activated_data_e_scaled_WIRE_2_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_0 = activated_data_e_scaled_f_rec_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn = _activated_data_e_scaled_WIRE_2_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn = _activated_data_e_scaled_WIRE_2_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn = activated_data_e_scaled_f_rec_rawIn_expIn == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn = activated_data_e_scaled_f_rec_rawIn_fractIn == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T = activated_data_e_scaled_f_rec_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_1 = activated_data_e_scaled_f_rec_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_2 = activated_data_e_scaled_f_rec_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_3 = activated_data_e_scaled_f_rec_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_4 = activated_data_e_scaled_f_rec_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_5 = activated_data_e_scaled_f_rec_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_6 = activated_data_e_scaled_f_rec_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_7 = activated_data_e_scaled_f_rec_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_8 = activated_data_e_scaled_f_rec_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_9 = activated_data_e_scaled_f_rec_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_10 = activated_data_e_scaled_f_rec_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_11 = activated_data_e_scaled_f_rec_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_12 = activated_data_e_scaled_f_rec_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_13 = activated_data_e_scaled_f_rec_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_14 = activated_data_e_scaled_f_rec_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_15 = activated_data_e_scaled_f_rec_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_16 = activated_data_e_scaled_f_rec_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_17 = activated_data_e_scaled_f_rec_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_18 = activated_data_e_scaled_f_rec_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_19 = activated_data_e_scaled_f_rec_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_20 = activated_data_e_scaled_f_rec_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_21 = activated_data_e_scaled_f_rec_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_22 = activated_data_e_scaled_f_rec_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_23 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_1 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_24 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_2 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_23; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_25 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_3 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_24; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_26 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_4 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_25; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_27 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_5 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_26; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_28 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_6 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_27; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_29 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_7 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_28; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_30 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_8 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_29; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_31 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_9 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_30; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_32 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_10 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_31; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_33 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_11 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_34 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_12 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_35 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_13 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_36 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_14 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_37 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_15 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_38 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_16 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_39 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_17 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_40 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_18 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_41 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_19 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_42 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_20 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_43 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_21 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_42; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist = _activated_data_e_scaled_f_rec_rawIn_normDist_T_22 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_43; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn} << activated_data_e_scaled_f_rec_rawIn_normDist; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_1 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_1 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_2 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_3 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_4 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_1} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_4[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T = activated_data_e_scaled_f_rec_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_isZero_0 = activated_data_e_scaled_f_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T = activated_data_e_scaled_f_rec_rawIn_adjustedExp[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_2 = activated_data_e_scaled_f_rec_rawIn_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_1 = activated_data_e_scaled_f_rec_rawIn_isSpecial & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T = activated_data_e_scaled_f_rec_rawIn_isSpecial & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_1 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T = ~activated_data_e_scaled_f_rec_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_1 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_2 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn ? activated_data_e_scaled_f_rec_rawIn_subnormFract : activated_data_e_scaled_f_rec_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_3 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_1, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T = activated_data_e_scaled_f_rec_rawIn_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_1 = activated_data_e_scaled_f_rec_rawIn_isZero_0 ? 3'h0 : _activated_data_e_scaled_f_rec_T; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_3 = {_activated_data_e_scaled_f_rec_T_1[2:1], _activated_data_e_scaled_f_rec_T_1[0] | _activated_data_e_scaled_f_rec_T_2}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_4 = {activated_data_e_scaled_f_rec_rawIn_sign_0, _activated_data_e_scaled_f_rec_T_3}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_5 = activated_data_e_scaled_f_rec_rawIn_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_6 = {_activated_data_e_scaled_f_rec_T_4, _activated_data_e_scaled_f_rec_T_5}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_7 = activated_data_e_scaled_f_rec_rawIn_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec = {_activated_data_e_scaled_f_rec_T_6, _activated_data_e_scaled_f_rec_T_7}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE = _activated_data_e_scaled_in_to_rec_fn_io_in_T; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow = _activated_data_e_scaled_rec_fn_to_in_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp = _activated_data_e_scaled_muladder_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T = activated_data_e_scaled_sign_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero = _activated_data_e_scaled_sign_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_isZero = activated_data_e_scaled_sign_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T = activated_data_e_scaled_sign_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial = &_activated_data_e_scaled_sign_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T = activated_data_e_scaled_sign_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T = activated_data_e_scaled_sign_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_1 = activated_data_e_scaled_sign_isSpecial & _activated_data_e_scaled_sign_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_1 = ~_activated_data_e_scaled_sign_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_2 = activated_data_e_scaled_sign_isSpecial & _activated_data_e_scaled_sign_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_isInf = _activated_data_e_scaled_sign_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T = _activated_data_e_scaled_muladder_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_sign = _activated_data_e_scaled_sign_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T = {1'h0, activated_data_e_scaled_sign_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_sExp = _activated_data_e_scaled_sign_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T = ~activated_data_e_scaled_sign_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_1 = {1'h0, _activated_data_e_scaled_sign_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_2 = _activated_data_e_scaled_muladder_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_3 = {_activated_data_e_scaled_sign_out_sig_T_1, _activated_data_e_scaled_sign_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_sig = _activated_data_e_scaled_sign_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat = activated_data_e_scaled_sign_out_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_10; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_4 = _activated_data_e_scaled_T_10; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled = activated_data_e_scaled_overflow ? activated_data_e_scaled_sat : _activated_data_e_scaled_WIRE_4; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T = $signed(activated_data_e_scaled) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_1 = $signed(activated_data_e_scaled) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_2 = _activated_data_e_clipped_T_1 ? 32'hFFFFFF80 : activated_data_e_scaled; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_3 = _activated_data_e_clipped_T ? 32'h7F : _activated_data_e_clipped_T_2; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_4 = _activated_data_e_clipped_T_3[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped = _activated_data_e_clipped_T_4; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_0 = activated_data_e_clipped; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_0_0 = _activated_data_WIRE_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_33 = _activated_data_e_act_T_32; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_34 = $signed(io_in_bits_acc_read_resp_data_1_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_35 = _activated_data_e_act_T_34 ? io_in_bits_acc_read_resp_data_1_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_13 = {io_in_bits_acc_read_resp_data_1_0_0[31], io_in_bits_acc_read_resp_data_1_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_39; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_39 = _GEN_13; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_54; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_54 = _GEN_13; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_40 = _activated_data_e_act_T_39[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_41 = _activated_data_e_act_T_40; // @[Arithmetic.scala:95:38]
wire _GEN_14 = $signed(io_in_bits_acc_read_resp_data_1_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_4; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_4 = _GEN_14; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_4; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_4 = _GEN_14; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_1 = {_activated_data_e_act_q_sign_T_4, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_5 = 33'h0 - _GEN_13; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_6 = _activated_data_e_act_q_abs_T_5[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_7 = _activated_data_e_act_q_abs_T_6; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_1 = _activated_data_e_act_q_abs_T_4 ? _activated_data_e_act_q_abs_T_7 : io_in_bits_acc_read_resp_data_1_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_8 = _activated_data_e_act_q_clipped_T_7[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_9 = _activated_data_e_act_q_clipped_T_8; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_10 = $signed(activated_data_e_act_q_abs_1) > $signed(_activated_data_e_act_q_clipped_T_9); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_12 = _activated_data_e_act_q_clipped_T_11[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_13 = _activated_data_e_act_q_clipped_T_12; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_1 = _activated_data_e_act_q_clipped_T_10 ? _activated_data_e_act_q_clipped_T_13 : activated_data_e_act_q_abs_1; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_15 = {activated_data_e_act_q_clipped_1[31], activated_data_e_act_q_clipped_1} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_11; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_11 = _GEN_15; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_14; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_14 = _GEN_15; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_12 = _activated_data_e_act_q_poly_T_11[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_13 = _activated_data_e_act_q_poly_T_12; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_15 = _activated_data_e_act_q_poly_T_14[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_16 = _activated_data_e_act_q_poly_T_15; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_17 = {{32{_activated_data_e_act_q_poly_T_13[31]}}, _activated_data_e_act_q_poly_T_13} * {{32{_activated_data_e_act_q_poly_T_16[31]}}, _activated_data_e_act_q_poly_T_16}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_18 = {_activated_data_e_act_q_poly_T_17[63], _activated_data_e_act_q_poly_T_17} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_19 = _activated_data_e_act_q_poly_T_18[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_20 = _activated_data_e_act_q_poly_T_19; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_21 = _activated_data_e_act_q_poly_T_20[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_1 = _activated_data_e_act_q_poly_T_21; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_2 = {{32{activated_data_e_act_q_sign_1[1]}}, activated_data_e_act_q_sign_1} * {{2{activated_data_e_act_q_poly_1[31]}}, activated_data_e_act_q_poly_1}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_3 = _activated_data_e_act_q_erf_T_2[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_1 = _activated_data_e_act_q_erf_T_3; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_45 = {activated_data_e_act_q_erf_1[31], activated_data_e_act_q_erf_1} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_46 = _activated_data_e_act_T_45[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_47 = _activated_data_e_act_T_46; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_48 = {{32{io_in_bits_acc_read_resp_data_1_0_0[31]}}, io_in_bits_acc_read_resp_data_1_0_0} * {{32{_activated_data_e_act_T_47[31]}}, _activated_data_e_act_T_47}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_49 = _activated_data_e_act_T_48[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_50 = _activated_data_e_act_T_49; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_55 = _activated_data_e_act_T_54[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_56 = _activated_data_e_act_T_55; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_2 = 33'h0 - {_activated_data_e_act_T_56[31], _activated_data_e_act_T_56}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_3 = _activated_data_e_act_neg_q_iexp_T_2[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_1 = _activated_data_e_act_neg_q_iexp_T_3; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_4 = {{32{activated_data_e_act_neg_q_iexp_1[31]}}, activated_data_e_act_neg_q_iexp_1} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_5 = _activated_data_e_act_z_iexp_T_4; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_6 = _activated_data_e_act_z_iexp_T_5[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_7 = _activated_data_e_act_z_iexp_T_6; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_33 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_35 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_37 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_39 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_41 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_43 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_45 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_47 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_49 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_51 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_53 = activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_1 = _activated_data_e_act_z_iexp_T_7[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_65; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_1; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_58 = activated_data_e_act_z_iexp_saturated_1; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_34 = _activated_data_e_act_z_iexp_saturated_T_33[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_36 = _activated_data_e_act_z_iexp_saturated_T_35[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_38 = _activated_data_e_act_z_iexp_saturated_T_37[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_40 = _activated_data_e_act_z_iexp_saturated_T_39[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_42 = _activated_data_e_act_z_iexp_saturated_T_41[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_44 = _activated_data_e_act_z_iexp_saturated_T_43[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_46 = _activated_data_e_act_z_iexp_saturated_T_45[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_48 = _activated_data_e_act_z_iexp_saturated_T_47[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_50 = _activated_data_e_act_z_iexp_saturated_T_49[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_52 = _activated_data_e_act_z_iexp_saturated_T_51[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_54 = _activated_data_e_act_z_iexp_saturated_T_53[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_55 = _activated_data_e_act_z_iexp_saturated_T_34 | _activated_data_e_act_z_iexp_saturated_T_36; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_56 = _activated_data_e_act_z_iexp_saturated_T_55 | _activated_data_e_act_z_iexp_saturated_T_38; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_57 = _activated_data_e_act_z_iexp_saturated_T_56 | _activated_data_e_act_z_iexp_saturated_T_40; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_58 = _activated_data_e_act_z_iexp_saturated_T_57 | _activated_data_e_act_z_iexp_saturated_T_42; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_59 = _activated_data_e_act_z_iexp_saturated_T_58 | _activated_data_e_act_z_iexp_saturated_T_44; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_60 = _activated_data_e_act_z_iexp_saturated_T_59 | _activated_data_e_act_z_iexp_saturated_T_46; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_61 = _activated_data_e_act_z_iexp_saturated_T_60 | _activated_data_e_act_z_iexp_saturated_T_48; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_62 = _activated_data_e_act_z_iexp_saturated_T_61 | _activated_data_e_act_z_iexp_saturated_T_50; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_63 = _activated_data_e_act_z_iexp_saturated_T_62 | _activated_data_e_act_z_iexp_saturated_T_52; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_64 = _activated_data_e_act_z_iexp_saturated_T_63 | _activated_data_e_act_z_iexp_saturated_T_54; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_65 = _activated_data_e_act_z_iexp_saturated_T_64 ? 32'h20 : activated_data_e_act_z_iexp_1; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_1 = _activated_data_e_act_z_iexp_saturated_T_65; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_5 = {{32{activated_data_e_act_z_iexp_1[31]}}, activated_data_e_act_z_iexp_1} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_6 = {_activated_data_e_act_qp_iexp_T_5[63], _activated_data_e_act_qp_iexp_T_5} + {{33{_activated_data_e_act_T_56[31]}}, _activated_data_e_act_T_56}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_7 = _activated_data_e_act_qp_iexp_T_6[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_8 = _activated_data_e_act_qp_iexp_T_7; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_9 = _activated_data_e_act_qp_iexp_T_8[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_1 = _activated_data_e_act_qp_iexp_T_9; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_16 = {activated_data_e_act_qp_iexp_1[31], activated_data_e_act_qp_iexp_1} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_11; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_11 = _GEN_16; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_14; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_14 = _GEN_16; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_12 = _activated_data_e_act_q_poly_iexp_T_11[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_13 = _activated_data_e_act_q_poly_iexp_T_12; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_15 = _activated_data_e_act_q_poly_iexp_T_14[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_16 = _activated_data_e_act_q_poly_iexp_T_15; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_17 = {{32{_activated_data_e_act_q_poly_iexp_T_13[31]}}, _activated_data_e_act_q_poly_iexp_T_13} * {{32{_activated_data_e_act_q_poly_iexp_T_16[31]}}, _activated_data_e_act_q_poly_iexp_T_16}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_18 = {_activated_data_e_act_q_poly_iexp_T_17[63], _activated_data_e_act_q_poly_iexp_T_17} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_19 = _activated_data_e_act_q_poly_iexp_T_18[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_20 = _activated_data_e_act_q_poly_iexp_T_19; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_21 = _activated_data_e_act_q_poly_iexp_T_20[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_1 = _activated_data_e_act_q_poly_iexp_T_21; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_57 = activated_data_e_act_q_poly_iexp_1; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_59 = _activated_data_e_act_T_57 >> _activated_data_e_act_T_58; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_60 = _activated_data_e_act_T_59; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_1 = _activated_data_e_act_T_60; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_62 = _activated_data_e_act_T_61; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_63 = _activated_data_e_act_T_62; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_1 = _activated_data_e_act_T_33 ? _activated_data_e_act_T_35 : _activated_data_e_act_T_63; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_1 = activated_data_e_act_1; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_19_bits = _activated_data_e_scaled_T_18_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_8 = _activated_data_e_scaled_T_19_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_20; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_20 = _activated_data_e_scaled_WIRE_8; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_7_bits = _activated_data_e_scaled_T_20; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_1 = _activated_data_e_scaled_WIRE_7_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_1_sign = activated_data_e_scaled_f_rec_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_1 = _activated_data_e_scaled_WIRE_7_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_1 = _activated_data_e_scaled_WIRE_7_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 = activated_data_e_scaled_f_rec_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1 = activated_data_e_scaled_f_rec_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_44 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_45 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_46 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_47 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_48 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_49 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_50 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_51 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_52 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_53 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_54 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_55 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_56 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_57 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_58 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_59 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_60 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_61 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_62 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_63 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_64 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_65 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_66 = activated_data_e_scaled_f_rec_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_67 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_45 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_68 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_46 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_67; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_69 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_47 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_68; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_70 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_48 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_69; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_71 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_49 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_70; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_72 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_50 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_71; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_73 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_51 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_72; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_74 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_52 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_73; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_75 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_53 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_74; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_76 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_54 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_75; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_77 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_55 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_76; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_78 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_56 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_77; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_79 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_57 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_78; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_80 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_58 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_79; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_81 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_59 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_80; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_82 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_60 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_81; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_83 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_61 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_82; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_84 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_62 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_83; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_85 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_63 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_84; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_86 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_64 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_85; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_87 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_65 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_86; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_1 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_66 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_87; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_2 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_1} << activated_data_e_scaled_f_rec_rawIn_normDist_1; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_3 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_1 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_5 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_1}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_6 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_5 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_7 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_8 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_9 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_6} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_1 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_2 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_1 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_1_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_1 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_1 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_10 = activated_data_e_scaled_f_rec_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_2 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_3 = activated_data_e_scaled_f_rec_rawIn_isSpecial_1 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_1_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_1 = activated_data_e_scaled_f_rec_rawIn_isSpecial_1 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_1_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_3 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_1_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_4 = ~activated_data_e_scaled_f_rec_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_5 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_6 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_1 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_1 : activated_data_e_scaled_f_rec_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_7 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_5, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_1_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_8 = activated_data_e_scaled_f_rec_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_9 = activated_data_e_scaled_f_rec_rawIn_1_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_8; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_11 = {_activated_data_e_scaled_f_rec_T_9[2:1], _activated_data_e_scaled_f_rec_T_9[0] | _activated_data_e_scaled_f_rec_T_10}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_12 = {activated_data_e_scaled_f_rec_rawIn_1_sign, _activated_data_e_scaled_f_rec_T_11}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_13 = activated_data_e_scaled_f_rec_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_14 = {_activated_data_e_scaled_f_rec_T_12, _activated_data_e_scaled_f_rec_T_13}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_15 = activated_data_e_scaled_f_rec_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_1 = {_activated_data_e_scaled_f_rec_T_14, _activated_data_e_scaled_f_rec_T_15}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_1 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_1; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_1 = _activated_data_e_scaled_rec_fn_to_in_1_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_1 = _activated_data_e_scaled_muladder_1_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_1 = activated_data_e_scaled_sign_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_1 = _activated_data_e_scaled_sign_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_1_isZero = activated_data_e_scaled_sign_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_1 = activated_data_e_scaled_sign_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_1 = &_activated_data_e_scaled_sign_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_1_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_1_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_1_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_1_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_1_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_2 = activated_data_e_scaled_sign_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_3 = activated_data_e_scaled_sign_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_3 = activated_data_e_scaled_sign_isSpecial_1 & _activated_data_e_scaled_sign_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_1_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_4 = ~_activated_data_e_scaled_sign_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_5 = activated_data_e_scaled_sign_isSpecial_1 & _activated_data_e_scaled_sign_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_1_isInf = _activated_data_e_scaled_sign_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_1 = _activated_data_e_scaled_muladder_1_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_1_sign = _activated_data_e_scaled_sign_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_1 = {1'h0, activated_data_e_scaled_sign_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_1_sExp = _activated_data_e_scaled_sign_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_4 = ~activated_data_e_scaled_sign_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_5 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_6 = _activated_data_e_scaled_muladder_1_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_7 = {_activated_data_e_scaled_sign_out_sig_T_5, _activated_data_e_scaled_sign_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_1_sig = _activated_data_e_scaled_sign_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_1 = activated_data_e_scaled_sign_out_1_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_21; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_9 = _activated_data_e_scaled_T_21; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_1 = activated_data_e_scaled_overflow_1 ? activated_data_e_scaled_sat_1 : _activated_data_e_scaled_WIRE_9; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_5 = $signed(activated_data_e_scaled_1) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_6 = $signed(activated_data_e_scaled_1) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_7 = _activated_data_e_clipped_T_6 ? 32'hFFFFFF80 : activated_data_e_scaled_1; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_8 = _activated_data_e_clipped_T_5 ? 32'h7F : _activated_data_e_clipped_T_7; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_9 = _activated_data_e_clipped_T_8[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_1 = _activated_data_e_clipped_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_1_0 = activated_data_e_clipped_1; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_1_0 = _activated_data_WIRE_1_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_65 = _activated_data_e_act_T_64; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_66 = $signed(io_in_bits_acc_read_resp_data_2_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_67 = _activated_data_e_act_T_66 ? io_in_bits_acc_read_resp_data_2_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_17 = {io_in_bits_acc_read_resp_data_2_0_0[31], io_in_bits_acc_read_resp_data_2_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_71; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_71 = _GEN_17; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_86; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_86 = _GEN_17; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_72 = _activated_data_e_act_T_71[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_73 = _activated_data_e_act_T_72; // @[Arithmetic.scala:95:38]
wire _GEN_18 = $signed(io_in_bits_acc_read_resp_data_2_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_8; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_8 = _GEN_18; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_8; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_8 = _GEN_18; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_2 = {_activated_data_e_act_q_sign_T_8, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_9 = 33'h0 - _GEN_17; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_10 = _activated_data_e_act_q_abs_T_9[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_11 = _activated_data_e_act_q_abs_T_10; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_2 = _activated_data_e_act_q_abs_T_8 ? _activated_data_e_act_q_abs_T_11 : io_in_bits_acc_read_resp_data_2_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_15 = _activated_data_e_act_q_clipped_T_14[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_16 = _activated_data_e_act_q_clipped_T_15; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_17 = $signed(activated_data_e_act_q_abs_2) > $signed(_activated_data_e_act_q_clipped_T_16); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_19 = _activated_data_e_act_q_clipped_T_18[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_20 = _activated_data_e_act_q_clipped_T_19; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_2 = _activated_data_e_act_q_clipped_T_17 ? _activated_data_e_act_q_clipped_T_20 : activated_data_e_act_q_abs_2; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_19 = {activated_data_e_act_q_clipped_2[31], activated_data_e_act_q_clipped_2} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_22; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_22 = _GEN_19; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_25; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_25 = _GEN_19; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_23 = _activated_data_e_act_q_poly_T_22[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_24 = _activated_data_e_act_q_poly_T_23; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_26 = _activated_data_e_act_q_poly_T_25[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_27 = _activated_data_e_act_q_poly_T_26; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_28 = {{32{_activated_data_e_act_q_poly_T_24[31]}}, _activated_data_e_act_q_poly_T_24} * {{32{_activated_data_e_act_q_poly_T_27[31]}}, _activated_data_e_act_q_poly_T_27}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_29 = {_activated_data_e_act_q_poly_T_28[63], _activated_data_e_act_q_poly_T_28} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_30 = _activated_data_e_act_q_poly_T_29[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_31 = _activated_data_e_act_q_poly_T_30; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_32 = _activated_data_e_act_q_poly_T_31[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_2 = _activated_data_e_act_q_poly_T_32; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_4 = {{32{activated_data_e_act_q_sign_2[1]}}, activated_data_e_act_q_sign_2} * {{2{activated_data_e_act_q_poly_2[31]}}, activated_data_e_act_q_poly_2}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_5 = _activated_data_e_act_q_erf_T_4[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_2 = _activated_data_e_act_q_erf_T_5; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_77 = {activated_data_e_act_q_erf_2[31], activated_data_e_act_q_erf_2} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_78 = _activated_data_e_act_T_77[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_79 = _activated_data_e_act_T_78; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_80 = {{32{io_in_bits_acc_read_resp_data_2_0_0[31]}}, io_in_bits_acc_read_resp_data_2_0_0} * {{32{_activated_data_e_act_T_79[31]}}, _activated_data_e_act_T_79}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_81 = _activated_data_e_act_T_80[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_82 = _activated_data_e_act_T_81; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_87 = _activated_data_e_act_T_86[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_88 = _activated_data_e_act_T_87; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_4 = 33'h0 - {_activated_data_e_act_T_88[31], _activated_data_e_act_T_88}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_5 = _activated_data_e_act_neg_q_iexp_T_4[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_2 = _activated_data_e_act_neg_q_iexp_T_5; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_8 = {{32{activated_data_e_act_neg_q_iexp_2[31]}}, activated_data_e_act_neg_q_iexp_2} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_9 = _activated_data_e_act_z_iexp_T_8; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_10 = _activated_data_e_act_z_iexp_T_9[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_11 = _activated_data_e_act_z_iexp_T_10; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_66 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_68 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_70 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_72 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_74 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_76 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_78 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_80 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_82 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_84 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_86 = activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_2 = _activated_data_e_act_z_iexp_T_11[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_98; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_2; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_90 = activated_data_e_act_z_iexp_saturated_2; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_67 = _activated_data_e_act_z_iexp_saturated_T_66[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_69 = _activated_data_e_act_z_iexp_saturated_T_68[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_71 = _activated_data_e_act_z_iexp_saturated_T_70[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_73 = _activated_data_e_act_z_iexp_saturated_T_72[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_75 = _activated_data_e_act_z_iexp_saturated_T_74[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_77 = _activated_data_e_act_z_iexp_saturated_T_76[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_79 = _activated_data_e_act_z_iexp_saturated_T_78[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_81 = _activated_data_e_act_z_iexp_saturated_T_80[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_83 = _activated_data_e_act_z_iexp_saturated_T_82[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_85 = _activated_data_e_act_z_iexp_saturated_T_84[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_87 = _activated_data_e_act_z_iexp_saturated_T_86[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_88 = _activated_data_e_act_z_iexp_saturated_T_67 | _activated_data_e_act_z_iexp_saturated_T_69; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_89 = _activated_data_e_act_z_iexp_saturated_T_88 | _activated_data_e_act_z_iexp_saturated_T_71; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_90 = _activated_data_e_act_z_iexp_saturated_T_89 | _activated_data_e_act_z_iexp_saturated_T_73; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_91 = _activated_data_e_act_z_iexp_saturated_T_90 | _activated_data_e_act_z_iexp_saturated_T_75; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_92 = _activated_data_e_act_z_iexp_saturated_T_91 | _activated_data_e_act_z_iexp_saturated_T_77; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_93 = _activated_data_e_act_z_iexp_saturated_T_92 | _activated_data_e_act_z_iexp_saturated_T_79; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_94 = _activated_data_e_act_z_iexp_saturated_T_93 | _activated_data_e_act_z_iexp_saturated_T_81; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_95 = _activated_data_e_act_z_iexp_saturated_T_94 | _activated_data_e_act_z_iexp_saturated_T_83; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_96 = _activated_data_e_act_z_iexp_saturated_T_95 | _activated_data_e_act_z_iexp_saturated_T_85; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_97 = _activated_data_e_act_z_iexp_saturated_T_96 | _activated_data_e_act_z_iexp_saturated_T_87; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_98 = _activated_data_e_act_z_iexp_saturated_T_97 ? 32'h20 : activated_data_e_act_z_iexp_2; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_2 = _activated_data_e_act_z_iexp_saturated_T_98; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_10 = {{32{activated_data_e_act_z_iexp_2[31]}}, activated_data_e_act_z_iexp_2} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_11 = {_activated_data_e_act_qp_iexp_T_10[63], _activated_data_e_act_qp_iexp_T_10} + {{33{_activated_data_e_act_T_88[31]}}, _activated_data_e_act_T_88}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_12 = _activated_data_e_act_qp_iexp_T_11[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_13 = _activated_data_e_act_qp_iexp_T_12; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_14 = _activated_data_e_act_qp_iexp_T_13[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_2 = _activated_data_e_act_qp_iexp_T_14; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_20 = {activated_data_e_act_qp_iexp_2[31], activated_data_e_act_qp_iexp_2} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_22; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_22 = _GEN_20; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_25; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_25 = _GEN_20; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_23 = _activated_data_e_act_q_poly_iexp_T_22[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_24 = _activated_data_e_act_q_poly_iexp_T_23; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_26 = _activated_data_e_act_q_poly_iexp_T_25[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_27 = _activated_data_e_act_q_poly_iexp_T_26; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_28 = {{32{_activated_data_e_act_q_poly_iexp_T_24[31]}}, _activated_data_e_act_q_poly_iexp_T_24} * {{32{_activated_data_e_act_q_poly_iexp_T_27[31]}}, _activated_data_e_act_q_poly_iexp_T_27}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_29 = {_activated_data_e_act_q_poly_iexp_T_28[63], _activated_data_e_act_q_poly_iexp_T_28} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_30 = _activated_data_e_act_q_poly_iexp_T_29[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_31 = _activated_data_e_act_q_poly_iexp_T_30; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_32 = _activated_data_e_act_q_poly_iexp_T_31[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_2 = _activated_data_e_act_q_poly_iexp_T_32; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_89 = activated_data_e_act_q_poly_iexp_2; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_91 = _activated_data_e_act_T_89 >> _activated_data_e_act_T_90; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_92 = _activated_data_e_act_T_91; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_2 = _activated_data_e_act_T_92; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_94 = _activated_data_e_act_T_93; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_95 = _activated_data_e_act_T_94; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_2 = _activated_data_e_act_T_65 ? _activated_data_e_act_T_67 : _activated_data_e_act_T_95; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_2 = activated_data_e_act_2; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_30_bits = _activated_data_e_scaled_T_29_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_13 = _activated_data_e_scaled_T_30_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_31; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_31 = _activated_data_e_scaled_WIRE_13; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_12_bits = _activated_data_e_scaled_T_31; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_2 = _activated_data_e_scaled_WIRE_12_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_2_sign = activated_data_e_scaled_f_rec_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_2 = _activated_data_e_scaled_WIRE_12_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_2 = _activated_data_e_scaled_WIRE_12_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 = activated_data_e_scaled_f_rec_rawIn_expIn_2 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2 = activated_data_e_scaled_f_rec_rawIn_fractIn_2 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_88 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_89 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_90 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_91 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_92 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_93 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_94 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_95 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_96 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_97 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_98 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_99 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_100 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_101 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_102 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_103 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_104 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_105 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_106 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_107 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_108 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_109 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_110 = activated_data_e_scaled_f_rec_rawIn_fractIn_2[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_111 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_89 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_112 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_90 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_111; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_113 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_91 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_112; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_114 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_92 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_113; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_115 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_93 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_114; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_116 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_94 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_115; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_117 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_95 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_116; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_118 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_96 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_117; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_119 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_97 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_118; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_120 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_98 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_119; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_121 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_99 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_120; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_122 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_100 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_121; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_123 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_101 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_122; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_124 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_102 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_123; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_125 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_103 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_124; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_126 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_104 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_125; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_127 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_105 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_126; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_128 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_106 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_127; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_129 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_107 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_128; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_130 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_108 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_129; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_131 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_109 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_130; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_2 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_110 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_131; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_4 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_2} << activated_data_e_scaled_f_rec_rawIn_normDist_2; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_5 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_4[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_2 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_10 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_2}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_11 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_10 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_12 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_13 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_14 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_11} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_2 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_14[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_4 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_2 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_2_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_2 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_2[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_2 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_18 = activated_data_e_scaled_f_rec_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_4 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_5 = activated_data_e_scaled_f_rec_rawIn_isSpecial_2 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_2_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_2 = activated_data_e_scaled_f_rec_rawIn_isSpecial_2 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_2_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_5 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_2_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_8 = ~activated_data_e_scaled_f_rec_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_9 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_10 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_2 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_2 : activated_data_e_scaled_f_rec_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_11 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_9, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_2_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_16 = activated_data_e_scaled_f_rec_rawIn_2_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_17 = activated_data_e_scaled_f_rec_rawIn_2_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_16; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_19 = {_activated_data_e_scaled_f_rec_T_17[2:1], _activated_data_e_scaled_f_rec_T_17[0] | _activated_data_e_scaled_f_rec_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_20 = {activated_data_e_scaled_f_rec_rawIn_2_sign, _activated_data_e_scaled_f_rec_T_19}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_21 = activated_data_e_scaled_f_rec_rawIn_2_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_22 = {_activated_data_e_scaled_f_rec_T_20, _activated_data_e_scaled_f_rec_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_23 = activated_data_e_scaled_f_rec_rawIn_2_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_2 = {_activated_data_e_scaled_f_rec_T_22, _activated_data_e_scaled_f_rec_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_2 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_2; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_2 = _activated_data_e_scaled_rec_fn_to_in_2_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_2 = _activated_data_e_scaled_muladder_2_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_2 = activated_data_e_scaled_sign_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_2 = _activated_data_e_scaled_sign_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_2_isZero = activated_data_e_scaled_sign_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_2 = activated_data_e_scaled_sign_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_2 = &_activated_data_e_scaled_sign_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_2_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_2_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_2_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_2_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_2_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_4 = activated_data_e_scaled_sign_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_6 = activated_data_e_scaled_sign_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_5 = activated_data_e_scaled_sign_isSpecial_2 & _activated_data_e_scaled_sign_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_2_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_7 = ~_activated_data_e_scaled_sign_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_8 = activated_data_e_scaled_sign_isSpecial_2 & _activated_data_e_scaled_sign_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_2_isInf = _activated_data_e_scaled_sign_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_2 = _activated_data_e_scaled_muladder_2_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_2_sign = _activated_data_e_scaled_sign_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_2 = {1'h0, activated_data_e_scaled_sign_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_2_sExp = _activated_data_e_scaled_sign_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_8 = ~activated_data_e_scaled_sign_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_9 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_10 = _activated_data_e_scaled_muladder_2_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_11 = {_activated_data_e_scaled_sign_out_sig_T_9, _activated_data_e_scaled_sign_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_2_sig = _activated_data_e_scaled_sign_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_2 = activated_data_e_scaled_sign_out_2_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_32; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_14 = _activated_data_e_scaled_T_32; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_2 = activated_data_e_scaled_overflow_2 ? activated_data_e_scaled_sat_2 : _activated_data_e_scaled_WIRE_14; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_10 = $signed(activated_data_e_scaled_2) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_11 = $signed(activated_data_e_scaled_2) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_12 = _activated_data_e_clipped_T_11 ? 32'hFFFFFF80 : activated_data_e_scaled_2; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_13 = _activated_data_e_clipped_T_10 ? 32'h7F : _activated_data_e_clipped_T_12; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_14 = _activated_data_e_clipped_T_13[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_2 = _activated_data_e_clipped_T_14; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_2_0 = activated_data_e_clipped_2; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_2_0 = _activated_data_WIRE_2_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_97 = _activated_data_e_act_T_96; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_98 = $signed(io_in_bits_acc_read_resp_data_3_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_99 = _activated_data_e_act_T_98 ? io_in_bits_acc_read_resp_data_3_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_21 = {io_in_bits_acc_read_resp_data_3_0_0[31], io_in_bits_acc_read_resp_data_3_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_103; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_103 = _GEN_21; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_118; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_118 = _GEN_21; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_104 = _activated_data_e_act_T_103[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_105 = _activated_data_e_act_T_104; // @[Arithmetic.scala:95:38]
wire _GEN_22 = $signed(io_in_bits_acc_read_resp_data_3_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_12; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_12 = _GEN_22; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_12; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_12 = _GEN_22; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_3 = {_activated_data_e_act_q_sign_T_12, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_13 = 33'h0 - _GEN_21; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_14 = _activated_data_e_act_q_abs_T_13[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_15 = _activated_data_e_act_q_abs_T_14; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_3 = _activated_data_e_act_q_abs_T_12 ? _activated_data_e_act_q_abs_T_15 : io_in_bits_acc_read_resp_data_3_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_22 = _activated_data_e_act_q_clipped_T_21[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_23 = _activated_data_e_act_q_clipped_T_22; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_24 = $signed(activated_data_e_act_q_abs_3) > $signed(_activated_data_e_act_q_clipped_T_23); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_26 = _activated_data_e_act_q_clipped_T_25[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_27 = _activated_data_e_act_q_clipped_T_26; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_3 = _activated_data_e_act_q_clipped_T_24 ? _activated_data_e_act_q_clipped_T_27 : activated_data_e_act_q_abs_3; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_23 = {activated_data_e_act_q_clipped_3[31], activated_data_e_act_q_clipped_3} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_33; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_33 = _GEN_23; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_36; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_36 = _GEN_23; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_34 = _activated_data_e_act_q_poly_T_33[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_35 = _activated_data_e_act_q_poly_T_34; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_37 = _activated_data_e_act_q_poly_T_36[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_38 = _activated_data_e_act_q_poly_T_37; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_39 = {{32{_activated_data_e_act_q_poly_T_35[31]}}, _activated_data_e_act_q_poly_T_35} * {{32{_activated_data_e_act_q_poly_T_38[31]}}, _activated_data_e_act_q_poly_T_38}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_40 = {_activated_data_e_act_q_poly_T_39[63], _activated_data_e_act_q_poly_T_39} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_41 = _activated_data_e_act_q_poly_T_40[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_42 = _activated_data_e_act_q_poly_T_41; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_43 = _activated_data_e_act_q_poly_T_42[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_3 = _activated_data_e_act_q_poly_T_43; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_6 = {{32{activated_data_e_act_q_sign_3[1]}}, activated_data_e_act_q_sign_3} * {{2{activated_data_e_act_q_poly_3[31]}}, activated_data_e_act_q_poly_3}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_7 = _activated_data_e_act_q_erf_T_6[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_3 = _activated_data_e_act_q_erf_T_7; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_109 = {activated_data_e_act_q_erf_3[31], activated_data_e_act_q_erf_3} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_110 = _activated_data_e_act_T_109[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_111 = _activated_data_e_act_T_110; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_112 = {{32{io_in_bits_acc_read_resp_data_3_0_0[31]}}, io_in_bits_acc_read_resp_data_3_0_0} * {{32{_activated_data_e_act_T_111[31]}}, _activated_data_e_act_T_111}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_113 = _activated_data_e_act_T_112[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_114 = _activated_data_e_act_T_113; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_119 = _activated_data_e_act_T_118[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_120 = _activated_data_e_act_T_119; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_6 = 33'h0 - {_activated_data_e_act_T_120[31], _activated_data_e_act_T_120}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_7 = _activated_data_e_act_neg_q_iexp_T_6[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_3 = _activated_data_e_act_neg_q_iexp_T_7; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_12 = {{32{activated_data_e_act_neg_q_iexp_3[31]}}, activated_data_e_act_neg_q_iexp_3} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_13 = _activated_data_e_act_z_iexp_T_12; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_14 = _activated_data_e_act_z_iexp_T_13[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_15 = _activated_data_e_act_z_iexp_T_14; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_99 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_101 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_103 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_105 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_107 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_109 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_111 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_113 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_115 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_117 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_119 = activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_3 = _activated_data_e_act_z_iexp_T_15[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_131; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_3; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_122 = activated_data_e_act_z_iexp_saturated_3; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_100 = _activated_data_e_act_z_iexp_saturated_T_99[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_102 = _activated_data_e_act_z_iexp_saturated_T_101[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_104 = _activated_data_e_act_z_iexp_saturated_T_103[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_106 = _activated_data_e_act_z_iexp_saturated_T_105[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_108 = _activated_data_e_act_z_iexp_saturated_T_107[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_110 = _activated_data_e_act_z_iexp_saturated_T_109[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_112 = _activated_data_e_act_z_iexp_saturated_T_111[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_114 = _activated_data_e_act_z_iexp_saturated_T_113[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_116 = _activated_data_e_act_z_iexp_saturated_T_115[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_118 = _activated_data_e_act_z_iexp_saturated_T_117[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_120 = _activated_data_e_act_z_iexp_saturated_T_119[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_121 = _activated_data_e_act_z_iexp_saturated_T_100 | _activated_data_e_act_z_iexp_saturated_T_102; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_122 = _activated_data_e_act_z_iexp_saturated_T_121 | _activated_data_e_act_z_iexp_saturated_T_104; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_123 = _activated_data_e_act_z_iexp_saturated_T_122 | _activated_data_e_act_z_iexp_saturated_T_106; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_124 = _activated_data_e_act_z_iexp_saturated_T_123 | _activated_data_e_act_z_iexp_saturated_T_108; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_125 = _activated_data_e_act_z_iexp_saturated_T_124 | _activated_data_e_act_z_iexp_saturated_T_110; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_126 = _activated_data_e_act_z_iexp_saturated_T_125 | _activated_data_e_act_z_iexp_saturated_T_112; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_127 = _activated_data_e_act_z_iexp_saturated_T_126 | _activated_data_e_act_z_iexp_saturated_T_114; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_128 = _activated_data_e_act_z_iexp_saturated_T_127 | _activated_data_e_act_z_iexp_saturated_T_116; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_129 = _activated_data_e_act_z_iexp_saturated_T_128 | _activated_data_e_act_z_iexp_saturated_T_118; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_130 = _activated_data_e_act_z_iexp_saturated_T_129 | _activated_data_e_act_z_iexp_saturated_T_120; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_131 = _activated_data_e_act_z_iexp_saturated_T_130 ? 32'h20 : activated_data_e_act_z_iexp_3; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_3 = _activated_data_e_act_z_iexp_saturated_T_131; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_15 = {{32{activated_data_e_act_z_iexp_3[31]}}, activated_data_e_act_z_iexp_3} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_16 = {_activated_data_e_act_qp_iexp_T_15[63], _activated_data_e_act_qp_iexp_T_15} + {{33{_activated_data_e_act_T_120[31]}}, _activated_data_e_act_T_120}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_17 = _activated_data_e_act_qp_iexp_T_16[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_18 = _activated_data_e_act_qp_iexp_T_17; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_19 = _activated_data_e_act_qp_iexp_T_18[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_3 = _activated_data_e_act_qp_iexp_T_19; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_24 = {activated_data_e_act_qp_iexp_3[31], activated_data_e_act_qp_iexp_3} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_33; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_33 = _GEN_24; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_36; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_36 = _GEN_24; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_34 = _activated_data_e_act_q_poly_iexp_T_33[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_35 = _activated_data_e_act_q_poly_iexp_T_34; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_37 = _activated_data_e_act_q_poly_iexp_T_36[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_38 = _activated_data_e_act_q_poly_iexp_T_37; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_39 = {{32{_activated_data_e_act_q_poly_iexp_T_35[31]}}, _activated_data_e_act_q_poly_iexp_T_35} * {{32{_activated_data_e_act_q_poly_iexp_T_38[31]}}, _activated_data_e_act_q_poly_iexp_T_38}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_40 = {_activated_data_e_act_q_poly_iexp_T_39[63], _activated_data_e_act_q_poly_iexp_T_39} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_41 = _activated_data_e_act_q_poly_iexp_T_40[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_42 = _activated_data_e_act_q_poly_iexp_T_41; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_43 = _activated_data_e_act_q_poly_iexp_T_42[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_3 = _activated_data_e_act_q_poly_iexp_T_43; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_121 = activated_data_e_act_q_poly_iexp_3; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_123 = _activated_data_e_act_T_121 >> _activated_data_e_act_T_122; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_124 = _activated_data_e_act_T_123; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_3 = _activated_data_e_act_T_124; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_126 = _activated_data_e_act_T_125; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_127 = _activated_data_e_act_T_126; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_3 = _activated_data_e_act_T_97 ? _activated_data_e_act_T_99 : _activated_data_e_act_T_127; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_3 = activated_data_e_act_3; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_41_bits = _activated_data_e_scaled_T_40_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_18 = _activated_data_e_scaled_T_41_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_42; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_42 = _activated_data_e_scaled_WIRE_18; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_17_bits = _activated_data_e_scaled_T_42; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_3 = _activated_data_e_scaled_WIRE_17_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_3_sign = activated_data_e_scaled_f_rec_rawIn_sign_3; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_3 = _activated_data_e_scaled_WIRE_17_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_3 = _activated_data_e_scaled_WIRE_17_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 = activated_data_e_scaled_f_rec_rawIn_expIn_3 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3 = activated_data_e_scaled_f_rec_rawIn_fractIn_3 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_132 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_133 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_134 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_135 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_136 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_137 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_138 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_139 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_140 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_141 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_142 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_143 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_144 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_145 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_146 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_147 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_148 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_149 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_150 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_151 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_152 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_153 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_154 = activated_data_e_scaled_f_rec_rawIn_fractIn_3[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_155 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_133 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_156 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_134 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_155; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_157 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_135 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_156; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_158 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_136 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_157; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_159 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_137 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_158; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_160 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_138 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_159; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_161 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_139 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_160; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_162 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_140 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_161; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_163 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_141 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_162; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_164 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_142 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_163; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_165 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_143 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_164; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_166 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_144 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_165; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_167 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_145 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_166; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_168 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_146 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_167; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_169 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_147 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_168; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_170 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_148 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_169; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_171 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_149 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_170; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_172 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_150 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_171; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_173 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_151 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_172; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_174 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_152 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_173; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_175 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_153 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_174; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_3 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_154 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_175; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_6 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_3} << activated_data_e_scaled_f_rec_rawIn_normDist_3; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_7 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_6[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_3 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_7, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_15 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_3}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_16 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_15 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_3}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_17 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_18 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_17}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_19 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_16} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_18}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_3 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_19[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_6 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_3; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_3 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_3_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_3 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_3[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_3 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_3; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_26 = activated_data_e_scaled_f_rec_rawIn_3_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_3_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_3_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_3_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_6 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_7 = activated_data_e_scaled_f_rec_rawIn_isSpecial_3 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_6; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_3_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_7; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_3 = activated_data_e_scaled_f_rec_rawIn_isSpecial_3 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_3; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_3_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_3; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_7 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_6}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_3_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_7; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_12 = ~activated_data_e_scaled_f_rec_rawIn_isZero_3; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_13 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_12}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_14 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_3 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_3 : activated_data_e_scaled_f_rec_rawIn_fractIn_3; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_15 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_13, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_14}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_3_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_15; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_24 = activated_data_e_scaled_f_rec_rawIn_3_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_25 = activated_data_e_scaled_f_rec_rawIn_3_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_24; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_27 = {_activated_data_e_scaled_f_rec_T_25[2:1], _activated_data_e_scaled_f_rec_T_25[0] | _activated_data_e_scaled_f_rec_T_26}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_28 = {activated_data_e_scaled_f_rec_rawIn_3_sign, _activated_data_e_scaled_f_rec_T_27}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_29 = activated_data_e_scaled_f_rec_rawIn_3_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_30 = {_activated_data_e_scaled_f_rec_T_28, _activated_data_e_scaled_f_rec_T_29}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_31 = activated_data_e_scaled_f_rec_rawIn_3_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_3 = {_activated_data_e_scaled_f_rec_T_30, _activated_data_e_scaled_f_rec_T_31}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_3 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_3; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_3 = _activated_data_e_scaled_rec_fn_to_in_3_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_3 = _activated_data_e_scaled_muladder_3_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_3 = activated_data_e_scaled_sign_exp_3[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_3 = _activated_data_e_scaled_sign_isZero_T_3 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_3_isZero = activated_data_e_scaled_sign_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_3 = activated_data_e_scaled_sign_exp_3[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_3 = &_activated_data_e_scaled_sign_isSpecial_T_3; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_11; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_3; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_3; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_15; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_3_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_3_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_3_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_3_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_3_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_6 = activated_data_e_scaled_sign_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_9 = activated_data_e_scaled_sign_exp_3[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_7 = activated_data_e_scaled_sign_isSpecial_3 & _activated_data_e_scaled_sign_out_isNaN_T_6; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_3_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_7; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_10 = ~_activated_data_e_scaled_sign_out_isInf_T_9; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_11 = activated_data_e_scaled_sign_isSpecial_3 & _activated_data_e_scaled_sign_out_isInf_T_10; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_3_isInf = _activated_data_e_scaled_sign_out_isInf_T_11; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_3 = _activated_data_e_scaled_muladder_3_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_3_sign = _activated_data_e_scaled_sign_out_sign_T_3; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_3 = {1'h0, activated_data_e_scaled_sign_exp_3}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_3_sExp = _activated_data_e_scaled_sign_out_sExp_T_3; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_12 = ~activated_data_e_scaled_sign_isZero_3; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_13 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_12}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_14 = _activated_data_e_scaled_muladder_3_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_15 = {_activated_data_e_scaled_sign_out_sig_T_13, _activated_data_e_scaled_sign_out_sig_T_14}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_3_sig = _activated_data_e_scaled_sign_out_sig_T_15; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_3 = activated_data_e_scaled_sign_out_3_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_43; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_19 = _activated_data_e_scaled_T_43; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_3 = activated_data_e_scaled_overflow_3 ? activated_data_e_scaled_sat_3 : _activated_data_e_scaled_WIRE_19; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_15 = $signed(activated_data_e_scaled_3) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_16 = $signed(activated_data_e_scaled_3) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_17 = _activated_data_e_clipped_T_16 ? 32'hFFFFFF80 : activated_data_e_scaled_3; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_18 = _activated_data_e_clipped_T_15 ? 32'h7F : _activated_data_e_clipped_T_17; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_19 = _activated_data_e_clipped_T_18[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_3 = _activated_data_e_clipped_T_19; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_3_0 = activated_data_e_clipped_3; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_3_0 = _activated_data_WIRE_3_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_129 = _activated_data_e_act_T_128; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_130 = $signed(io_in_bits_acc_read_resp_data_4_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_131 = _activated_data_e_act_T_130 ? io_in_bits_acc_read_resp_data_4_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_25 = {io_in_bits_acc_read_resp_data_4_0_0[31], io_in_bits_acc_read_resp_data_4_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_135; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_135 = _GEN_25; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_150; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_150 = _GEN_25; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_136 = _activated_data_e_act_T_135[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_137 = _activated_data_e_act_T_136; // @[Arithmetic.scala:95:38]
wire _GEN_26 = $signed(io_in_bits_acc_read_resp_data_4_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_16; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_16 = _GEN_26; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_16; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_16 = _GEN_26; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_4 = {_activated_data_e_act_q_sign_T_16, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_17 = 33'h0 - _GEN_25; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_18 = _activated_data_e_act_q_abs_T_17[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_19 = _activated_data_e_act_q_abs_T_18; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_4 = _activated_data_e_act_q_abs_T_16 ? _activated_data_e_act_q_abs_T_19 : io_in_bits_acc_read_resp_data_4_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_29 = _activated_data_e_act_q_clipped_T_28[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_30 = _activated_data_e_act_q_clipped_T_29; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_31 = $signed(activated_data_e_act_q_abs_4) > $signed(_activated_data_e_act_q_clipped_T_30); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_33 = _activated_data_e_act_q_clipped_T_32[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_34 = _activated_data_e_act_q_clipped_T_33; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_4 = _activated_data_e_act_q_clipped_T_31 ? _activated_data_e_act_q_clipped_T_34 : activated_data_e_act_q_abs_4; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_27 = {activated_data_e_act_q_clipped_4[31], activated_data_e_act_q_clipped_4} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_44; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_44 = _GEN_27; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_47; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_47 = _GEN_27; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_45 = _activated_data_e_act_q_poly_T_44[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_46 = _activated_data_e_act_q_poly_T_45; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_48 = _activated_data_e_act_q_poly_T_47[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_49 = _activated_data_e_act_q_poly_T_48; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_50 = {{32{_activated_data_e_act_q_poly_T_46[31]}}, _activated_data_e_act_q_poly_T_46} * {{32{_activated_data_e_act_q_poly_T_49[31]}}, _activated_data_e_act_q_poly_T_49}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_51 = {_activated_data_e_act_q_poly_T_50[63], _activated_data_e_act_q_poly_T_50} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_52 = _activated_data_e_act_q_poly_T_51[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_53 = _activated_data_e_act_q_poly_T_52; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_54 = _activated_data_e_act_q_poly_T_53[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_4 = _activated_data_e_act_q_poly_T_54; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_8 = {{32{activated_data_e_act_q_sign_4[1]}}, activated_data_e_act_q_sign_4} * {{2{activated_data_e_act_q_poly_4[31]}}, activated_data_e_act_q_poly_4}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_9 = _activated_data_e_act_q_erf_T_8[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_4 = _activated_data_e_act_q_erf_T_9; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_141 = {activated_data_e_act_q_erf_4[31], activated_data_e_act_q_erf_4} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_142 = _activated_data_e_act_T_141[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_143 = _activated_data_e_act_T_142; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_144 = {{32{io_in_bits_acc_read_resp_data_4_0_0[31]}}, io_in_bits_acc_read_resp_data_4_0_0} * {{32{_activated_data_e_act_T_143[31]}}, _activated_data_e_act_T_143}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_145 = _activated_data_e_act_T_144[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_146 = _activated_data_e_act_T_145; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_151 = _activated_data_e_act_T_150[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_152 = _activated_data_e_act_T_151; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_8 = 33'h0 - {_activated_data_e_act_T_152[31], _activated_data_e_act_T_152}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_9 = _activated_data_e_act_neg_q_iexp_T_8[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_4 = _activated_data_e_act_neg_q_iexp_T_9; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_16 = {{32{activated_data_e_act_neg_q_iexp_4[31]}}, activated_data_e_act_neg_q_iexp_4} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_17 = _activated_data_e_act_z_iexp_T_16; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_18 = _activated_data_e_act_z_iexp_T_17[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_19 = _activated_data_e_act_z_iexp_T_18; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_132 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_134 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_136 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_138 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_140 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_142 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_144 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_146 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_148 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_150 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_152 = activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_4 = _activated_data_e_act_z_iexp_T_19[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_164; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_4; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_154 = activated_data_e_act_z_iexp_saturated_4; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_133 = _activated_data_e_act_z_iexp_saturated_T_132[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_135 = _activated_data_e_act_z_iexp_saturated_T_134[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_137 = _activated_data_e_act_z_iexp_saturated_T_136[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_139 = _activated_data_e_act_z_iexp_saturated_T_138[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_141 = _activated_data_e_act_z_iexp_saturated_T_140[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_143 = _activated_data_e_act_z_iexp_saturated_T_142[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_145 = _activated_data_e_act_z_iexp_saturated_T_144[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_147 = _activated_data_e_act_z_iexp_saturated_T_146[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_149 = _activated_data_e_act_z_iexp_saturated_T_148[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_151 = _activated_data_e_act_z_iexp_saturated_T_150[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_153 = _activated_data_e_act_z_iexp_saturated_T_152[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_154 = _activated_data_e_act_z_iexp_saturated_T_133 | _activated_data_e_act_z_iexp_saturated_T_135; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_155 = _activated_data_e_act_z_iexp_saturated_T_154 | _activated_data_e_act_z_iexp_saturated_T_137; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_156 = _activated_data_e_act_z_iexp_saturated_T_155 | _activated_data_e_act_z_iexp_saturated_T_139; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_157 = _activated_data_e_act_z_iexp_saturated_T_156 | _activated_data_e_act_z_iexp_saturated_T_141; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_158 = _activated_data_e_act_z_iexp_saturated_T_157 | _activated_data_e_act_z_iexp_saturated_T_143; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_159 = _activated_data_e_act_z_iexp_saturated_T_158 | _activated_data_e_act_z_iexp_saturated_T_145; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_160 = _activated_data_e_act_z_iexp_saturated_T_159 | _activated_data_e_act_z_iexp_saturated_T_147; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_161 = _activated_data_e_act_z_iexp_saturated_T_160 | _activated_data_e_act_z_iexp_saturated_T_149; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_162 = _activated_data_e_act_z_iexp_saturated_T_161 | _activated_data_e_act_z_iexp_saturated_T_151; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_163 = _activated_data_e_act_z_iexp_saturated_T_162 | _activated_data_e_act_z_iexp_saturated_T_153; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_164 = _activated_data_e_act_z_iexp_saturated_T_163 ? 32'h20 : activated_data_e_act_z_iexp_4; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_4 = _activated_data_e_act_z_iexp_saturated_T_164; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_20 = {{32{activated_data_e_act_z_iexp_4[31]}}, activated_data_e_act_z_iexp_4} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_21 = {_activated_data_e_act_qp_iexp_T_20[63], _activated_data_e_act_qp_iexp_T_20} + {{33{_activated_data_e_act_T_152[31]}}, _activated_data_e_act_T_152}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_22 = _activated_data_e_act_qp_iexp_T_21[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_23 = _activated_data_e_act_qp_iexp_T_22; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_24 = _activated_data_e_act_qp_iexp_T_23[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_4 = _activated_data_e_act_qp_iexp_T_24; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_28 = {activated_data_e_act_qp_iexp_4[31], activated_data_e_act_qp_iexp_4} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_44; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_44 = _GEN_28; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_47; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_47 = _GEN_28; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_45 = _activated_data_e_act_q_poly_iexp_T_44[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_46 = _activated_data_e_act_q_poly_iexp_T_45; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_48 = _activated_data_e_act_q_poly_iexp_T_47[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_49 = _activated_data_e_act_q_poly_iexp_T_48; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_50 = {{32{_activated_data_e_act_q_poly_iexp_T_46[31]}}, _activated_data_e_act_q_poly_iexp_T_46} * {{32{_activated_data_e_act_q_poly_iexp_T_49[31]}}, _activated_data_e_act_q_poly_iexp_T_49}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_51 = {_activated_data_e_act_q_poly_iexp_T_50[63], _activated_data_e_act_q_poly_iexp_T_50} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_52 = _activated_data_e_act_q_poly_iexp_T_51[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_53 = _activated_data_e_act_q_poly_iexp_T_52; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_54 = _activated_data_e_act_q_poly_iexp_T_53[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_4 = _activated_data_e_act_q_poly_iexp_T_54; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_153 = activated_data_e_act_q_poly_iexp_4; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_155 = _activated_data_e_act_T_153 >> _activated_data_e_act_T_154; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_156 = _activated_data_e_act_T_155; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_4 = _activated_data_e_act_T_156; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_158 = _activated_data_e_act_T_157; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_159 = _activated_data_e_act_T_158; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_4 = _activated_data_e_act_T_129 ? _activated_data_e_act_T_131 : _activated_data_e_act_T_159; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_4 = activated_data_e_act_4; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_52_bits = _activated_data_e_scaled_T_51_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_23 = _activated_data_e_scaled_T_52_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_53; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_53 = _activated_data_e_scaled_WIRE_23; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_22_bits = _activated_data_e_scaled_T_53; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_4 = _activated_data_e_scaled_WIRE_22_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_4_sign = activated_data_e_scaled_f_rec_rawIn_sign_4; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_4 = _activated_data_e_scaled_WIRE_22_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_4 = _activated_data_e_scaled_WIRE_22_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 = activated_data_e_scaled_f_rec_rawIn_expIn_4 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4 = activated_data_e_scaled_f_rec_rawIn_fractIn_4 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_176 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_177 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_178 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_179 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_180 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_181 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_182 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_183 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_184 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_185 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_186 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_187 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_188 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_189 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_190 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_191 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_192 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_193 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_194 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_195 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_196 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_197 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_198 = activated_data_e_scaled_f_rec_rawIn_fractIn_4[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_199 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_177 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_200 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_178 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_199; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_201 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_179 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_200; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_202 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_180 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_201; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_203 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_181 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_202; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_204 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_182 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_203; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_205 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_183 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_204; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_206 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_184 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_205; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_207 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_185 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_206; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_208 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_186 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_207; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_209 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_187 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_208; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_210 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_188 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_209; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_211 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_189 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_210; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_212 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_190 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_211; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_213 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_191 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_212; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_214 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_192 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_213; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_215 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_193 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_214; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_216 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_194 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_215; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_217 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_195 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_216; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_218 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_196 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_217; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_219 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_197 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_218; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_4 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_198 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_219; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_8 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_4} << activated_data_e_scaled_f_rec_rawIn_normDist_4; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_9 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_8[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_4 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_9, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_20 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_4}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_21 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_20 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_4}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_22 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_23 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_22}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_24 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_21} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_23}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_4 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_24[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_8 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_4; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_4 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_4_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_4 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_4[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_4 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_4; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_34 = activated_data_e_scaled_f_rec_rawIn_4_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_4_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_4_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_4_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_8 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_9 = activated_data_e_scaled_f_rec_rawIn_isSpecial_4 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_8; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_4_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_9; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_4 = activated_data_e_scaled_f_rec_rawIn_isSpecial_4 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_4; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_4_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_4; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_9 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_8}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_4_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_9; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_16 = ~activated_data_e_scaled_f_rec_rawIn_isZero_4; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_17 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_16}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_18 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_4 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_4 : activated_data_e_scaled_f_rec_rawIn_fractIn_4; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_19 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_17, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_18}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_4_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_19; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_32 = activated_data_e_scaled_f_rec_rawIn_4_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_33 = activated_data_e_scaled_f_rec_rawIn_4_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_32; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_35 = {_activated_data_e_scaled_f_rec_T_33[2:1], _activated_data_e_scaled_f_rec_T_33[0] | _activated_data_e_scaled_f_rec_T_34}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_36 = {activated_data_e_scaled_f_rec_rawIn_4_sign, _activated_data_e_scaled_f_rec_T_35}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_37 = activated_data_e_scaled_f_rec_rawIn_4_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_38 = {_activated_data_e_scaled_f_rec_T_36, _activated_data_e_scaled_f_rec_T_37}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_39 = activated_data_e_scaled_f_rec_rawIn_4_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_4 = {_activated_data_e_scaled_f_rec_T_38, _activated_data_e_scaled_f_rec_T_39}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_4 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_4; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_4 = _activated_data_e_scaled_rec_fn_to_in_4_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_4 = _activated_data_e_scaled_muladder_4_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_4 = activated_data_e_scaled_sign_exp_4[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_4 = _activated_data_e_scaled_sign_isZero_T_4 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_4_isZero = activated_data_e_scaled_sign_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_4 = activated_data_e_scaled_sign_exp_4[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_4 = &_activated_data_e_scaled_sign_isSpecial_T_4; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_14; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_4; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_4; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_19; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_4_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_4_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_4_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_4_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_4_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_8 = activated_data_e_scaled_sign_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_12 = activated_data_e_scaled_sign_exp_4[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_9 = activated_data_e_scaled_sign_isSpecial_4 & _activated_data_e_scaled_sign_out_isNaN_T_8; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_4_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_9; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_13 = ~_activated_data_e_scaled_sign_out_isInf_T_12; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_14 = activated_data_e_scaled_sign_isSpecial_4 & _activated_data_e_scaled_sign_out_isInf_T_13; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_4_isInf = _activated_data_e_scaled_sign_out_isInf_T_14; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_4 = _activated_data_e_scaled_muladder_4_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_4_sign = _activated_data_e_scaled_sign_out_sign_T_4; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_4 = {1'h0, activated_data_e_scaled_sign_exp_4}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_4_sExp = _activated_data_e_scaled_sign_out_sExp_T_4; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_16 = ~activated_data_e_scaled_sign_isZero_4; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_17 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_16}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_18 = _activated_data_e_scaled_muladder_4_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_19 = {_activated_data_e_scaled_sign_out_sig_T_17, _activated_data_e_scaled_sign_out_sig_T_18}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_4_sig = _activated_data_e_scaled_sign_out_sig_T_19; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_4 = activated_data_e_scaled_sign_out_4_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_54; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_24 = _activated_data_e_scaled_T_54; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_4 = activated_data_e_scaled_overflow_4 ? activated_data_e_scaled_sat_4 : _activated_data_e_scaled_WIRE_24; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_20 = $signed(activated_data_e_scaled_4) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_21 = $signed(activated_data_e_scaled_4) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_22 = _activated_data_e_clipped_T_21 ? 32'hFFFFFF80 : activated_data_e_scaled_4; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_23 = _activated_data_e_clipped_T_20 ? 32'h7F : _activated_data_e_clipped_T_22; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_24 = _activated_data_e_clipped_T_23[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_4 = _activated_data_e_clipped_T_24; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_4_0 = activated_data_e_clipped_4; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_4_0 = _activated_data_WIRE_4_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_161 = _activated_data_e_act_T_160; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_162 = $signed(io_in_bits_acc_read_resp_data_5_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_163 = _activated_data_e_act_T_162 ? io_in_bits_acc_read_resp_data_5_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_29 = {io_in_bits_acc_read_resp_data_5_0_0[31], io_in_bits_acc_read_resp_data_5_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_167; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_167 = _GEN_29; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_182; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_182 = _GEN_29; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_168 = _activated_data_e_act_T_167[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_169 = _activated_data_e_act_T_168; // @[Arithmetic.scala:95:38]
wire _GEN_30 = $signed(io_in_bits_acc_read_resp_data_5_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_20; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_20 = _GEN_30; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_20; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_20 = _GEN_30; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_5 = {_activated_data_e_act_q_sign_T_20, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_21 = 33'h0 - _GEN_29; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_22 = _activated_data_e_act_q_abs_T_21[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_23 = _activated_data_e_act_q_abs_T_22; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_5 = _activated_data_e_act_q_abs_T_20 ? _activated_data_e_act_q_abs_T_23 : io_in_bits_acc_read_resp_data_5_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_36 = _activated_data_e_act_q_clipped_T_35[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_37 = _activated_data_e_act_q_clipped_T_36; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_38 = $signed(activated_data_e_act_q_abs_5) > $signed(_activated_data_e_act_q_clipped_T_37); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_40 = _activated_data_e_act_q_clipped_T_39[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_41 = _activated_data_e_act_q_clipped_T_40; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_5 = _activated_data_e_act_q_clipped_T_38 ? _activated_data_e_act_q_clipped_T_41 : activated_data_e_act_q_abs_5; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_31 = {activated_data_e_act_q_clipped_5[31], activated_data_e_act_q_clipped_5} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_55; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_55 = _GEN_31; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_58; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_58 = _GEN_31; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_56 = _activated_data_e_act_q_poly_T_55[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_57 = _activated_data_e_act_q_poly_T_56; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_59 = _activated_data_e_act_q_poly_T_58[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_60 = _activated_data_e_act_q_poly_T_59; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_61 = {{32{_activated_data_e_act_q_poly_T_57[31]}}, _activated_data_e_act_q_poly_T_57} * {{32{_activated_data_e_act_q_poly_T_60[31]}}, _activated_data_e_act_q_poly_T_60}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_62 = {_activated_data_e_act_q_poly_T_61[63], _activated_data_e_act_q_poly_T_61} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_63 = _activated_data_e_act_q_poly_T_62[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_64 = _activated_data_e_act_q_poly_T_63; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_65 = _activated_data_e_act_q_poly_T_64[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_5 = _activated_data_e_act_q_poly_T_65; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_10 = {{32{activated_data_e_act_q_sign_5[1]}}, activated_data_e_act_q_sign_5} * {{2{activated_data_e_act_q_poly_5[31]}}, activated_data_e_act_q_poly_5}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_11 = _activated_data_e_act_q_erf_T_10[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_5 = _activated_data_e_act_q_erf_T_11; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_173 = {activated_data_e_act_q_erf_5[31], activated_data_e_act_q_erf_5} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_174 = _activated_data_e_act_T_173[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_175 = _activated_data_e_act_T_174; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_176 = {{32{io_in_bits_acc_read_resp_data_5_0_0[31]}}, io_in_bits_acc_read_resp_data_5_0_0} * {{32{_activated_data_e_act_T_175[31]}}, _activated_data_e_act_T_175}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_177 = _activated_data_e_act_T_176[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_178 = _activated_data_e_act_T_177; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_183 = _activated_data_e_act_T_182[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_184 = _activated_data_e_act_T_183; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_10 = 33'h0 - {_activated_data_e_act_T_184[31], _activated_data_e_act_T_184}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_11 = _activated_data_e_act_neg_q_iexp_T_10[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_5 = _activated_data_e_act_neg_q_iexp_T_11; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_20 = {{32{activated_data_e_act_neg_q_iexp_5[31]}}, activated_data_e_act_neg_q_iexp_5} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_21 = _activated_data_e_act_z_iexp_T_20; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_22 = _activated_data_e_act_z_iexp_T_21[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_23 = _activated_data_e_act_z_iexp_T_22; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_165 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_167 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_169 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_171 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_173 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_175 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_177 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_179 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_181 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_183 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_185 = activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_5 = _activated_data_e_act_z_iexp_T_23[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_197; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_5; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_186 = activated_data_e_act_z_iexp_saturated_5; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_166 = _activated_data_e_act_z_iexp_saturated_T_165[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_168 = _activated_data_e_act_z_iexp_saturated_T_167[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_170 = _activated_data_e_act_z_iexp_saturated_T_169[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_172 = _activated_data_e_act_z_iexp_saturated_T_171[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_174 = _activated_data_e_act_z_iexp_saturated_T_173[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_176 = _activated_data_e_act_z_iexp_saturated_T_175[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_178 = _activated_data_e_act_z_iexp_saturated_T_177[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_180 = _activated_data_e_act_z_iexp_saturated_T_179[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_182 = _activated_data_e_act_z_iexp_saturated_T_181[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_184 = _activated_data_e_act_z_iexp_saturated_T_183[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_186 = _activated_data_e_act_z_iexp_saturated_T_185[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_187 = _activated_data_e_act_z_iexp_saturated_T_166 | _activated_data_e_act_z_iexp_saturated_T_168; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_188 = _activated_data_e_act_z_iexp_saturated_T_187 | _activated_data_e_act_z_iexp_saturated_T_170; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_189 = _activated_data_e_act_z_iexp_saturated_T_188 | _activated_data_e_act_z_iexp_saturated_T_172; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_190 = _activated_data_e_act_z_iexp_saturated_T_189 | _activated_data_e_act_z_iexp_saturated_T_174; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_191 = _activated_data_e_act_z_iexp_saturated_T_190 | _activated_data_e_act_z_iexp_saturated_T_176; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_192 = _activated_data_e_act_z_iexp_saturated_T_191 | _activated_data_e_act_z_iexp_saturated_T_178; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_193 = _activated_data_e_act_z_iexp_saturated_T_192 | _activated_data_e_act_z_iexp_saturated_T_180; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_194 = _activated_data_e_act_z_iexp_saturated_T_193 | _activated_data_e_act_z_iexp_saturated_T_182; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_195 = _activated_data_e_act_z_iexp_saturated_T_194 | _activated_data_e_act_z_iexp_saturated_T_184; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_196 = _activated_data_e_act_z_iexp_saturated_T_195 | _activated_data_e_act_z_iexp_saturated_T_186; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_197 = _activated_data_e_act_z_iexp_saturated_T_196 ? 32'h20 : activated_data_e_act_z_iexp_5; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_5 = _activated_data_e_act_z_iexp_saturated_T_197; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_25 = {{32{activated_data_e_act_z_iexp_5[31]}}, activated_data_e_act_z_iexp_5} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_26 = {_activated_data_e_act_qp_iexp_T_25[63], _activated_data_e_act_qp_iexp_T_25} + {{33{_activated_data_e_act_T_184[31]}}, _activated_data_e_act_T_184}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_27 = _activated_data_e_act_qp_iexp_T_26[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_28 = _activated_data_e_act_qp_iexp_T_27; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_29 = _activated_data_e_act_qp_iexp_T_28[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_5 = _activated_data_e_act_qp_iexp_T_29; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_32 = {activated_data_e_act_qp_iexp_5[31], activated_data_e_act_qp_iexp_5} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_55; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_55 = _GEN_32; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_58; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_58 = _GEN_32; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_56 = _activated_data_e_act_q_poly_iexp_T_55[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_57 = _activated_data_e_act_q_poly_iexp_T_56; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_59 = _activated_data_e_act_q_poly_iexp_T_58[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_60 = _activated_data_e_act_q_poly_iexp_T_59; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_61 = {{32{_activated_data_e_act_q_poly_iexp_T_57[31]}}, _activated_data_e_act_q_poly_iexp_T_57} * {{32{_activated_data_e_act_q_poly_iexp_T_60[31]}}, _activated_data_e_act_q_poly_iexp_T_60}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_62 = {_activated_data_e_act_q_poly_iexp_T_61[63], _activated_data_e_act_q_poly_iexp_T_61} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_63 = _activated_data_e_act_q_poly_iexp_T_62[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_64 = _activated_data_e_act_q_poly_iexp_T_63; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_65 = _activated_data_e_act_q_poly_iexp_T_64[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_5 = _activated_data_e_act_q_poly_iexp_T_65; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_185 = activated_data_e_act_q_poly_iexp_5; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_187 = _activated_data_e_act_T_185 >> _activated_data_e_act_T_186; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_188 = _activated_data_e_act_T_187; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_5 = _activated_data_e_act_T_188; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_190 = _activated_data_e_act_T_189; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_191 = _activated_data_e_act_T_190; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_5 = _activated_data_e_act_T_161 ? _activated_data_e_act_T_163 : _activated_data_e_act_T_191; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_5 = activated_data_e_act_5; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_63_bits = _activated_data_e_scaled_T_62_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_28 = _activated_data_e_scaled_T_63_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_64; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_64 = _activated_data_e_scaled_WIRE_28; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_27_bits = _activated_data_e_scaled_T_64; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_5 = _activated_data_e_scaled_WIRE_27_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_5_sign = activated_data_e_scaled_f_rec_rawIn_sign_5; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_5 = _activated_data_e_scaled_WIRE_27_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_5 = _activated_data_e_scaled_WIRE_27_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 = activated_data_e_scaled_f_rec_rawIn_expIn_5 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5 = activated_data_e_scaled_f_rec_rawIn_fractIn_5 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_220 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_221 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_222 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_223 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_224 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_225 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_226 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_227 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_228 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_229 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_230 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_231 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_232 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_233 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_234 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_235 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_236 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_237 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_238 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_239 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_240 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_241 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_242 = activated_data_e_scaled_f_rec_rawIn_fractIn_5[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_243 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_221 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_244 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_222 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_243; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_245 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_223 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_244; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_246 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_224 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_245; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_247 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_225 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_246; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_248 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_226 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_247; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_249 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_227 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_248; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_250 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_228 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_249; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_251 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_229 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_250; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_252 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_230 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_251; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_253 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_231 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_252; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_254 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_232 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_253; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_255 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_233 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_254; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_256 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_234 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_255; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_257 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_235 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_256; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_258 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_236 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_257; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_259 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_237 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_258; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_260 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_238 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_259; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_261 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_239 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_260; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_262 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_240 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_261; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_263 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_241 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_262; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_5 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_242 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_263; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_10 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_5} << activated_data_e_scaled_f_rec_rawIn_normDist_5; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_11 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_10[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_5 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_11, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_25 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_5}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_26 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_25 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_5}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_27 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_28 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_27}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_29 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_26} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_28}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_5 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_29[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_10 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_5; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_5 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_5_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_5 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_5[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_5 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_5; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_42 = activated_data_e_scaled_f_rec_rawIn_5_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_5_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_5_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_5_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_10 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_11 = activated_data_e_scaled_f_rec_rawIn_isSpecial_5 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_10; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_5_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_11; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_5 = activated_data_e_scaled_f_rec_rawIn_isSpecial_5 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_5; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_5_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_5; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_11 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_10}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_5_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_11; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_20 = ~activated_data_e_scaled_f_rec_rawIn_isZero_5; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_21 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_20}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_22 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_5 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_5 : activated_data_e_scaled_f_rec_rawIn_fractIn_5; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_23 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_21, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_22}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_5_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_23; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_40 = activated_data_e_scaled_f_rec_rawIn_5_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_41 = activated_data_e_scaled_f_rec_rawIn_5_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_40; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_43 = {_activated_data_e_scaled_f_rec_T_41[2:1], _activated_data_e_scaled_f_rec_T_41[0] | _activated_data_e_scaled_f_rec_T_42}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_44 = {activated_data_e_scaled_f_rec_rawIn_5_sign, _activated_data_e_scaled_f_rec_T_43}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_45 = activated_data_e_scaled_f_rec_rawIn_5_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_46 = {_activated_data_e_scaled_f_rec_T_44, _activated_data_e_scaled_f_rec_T_45}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_47 = activated_data_e_scaled_f_rec_rawIn_5_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_5 = {_activated_data_e_scaled_f_rec_T_46, _activated_data_e_scaled_f_rec_T_47}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_5 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_5; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_5 = _activated_data_e_scaled_rec_fn_to_in_5_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_5 = _activated_data_e_scaled_muladder_5_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_5 = activated_data_e_scaled_sign_exp_5[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_5 = _activated_data_e_scaled_sign_isZero_T_5 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_5_isZero = activated_data_e_scaled_sign_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_5 = activated_data_e_scaled_sign_exp_5[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_5 = &_activated_data_e_scaled_sign_isSpecial_T_5; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_17; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_5; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_5; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_23; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_5_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_5_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_5_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_5_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_5_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_10 = activated_data_e_scaled_sign_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_15 = activated_data_e_scaled_sign_exp_5[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_11 = activated_data_e_scaled_sign_isSpecial_5 & _activated_data_e_scaled_sign_out_isNaN_T_10; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_5_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_11; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_16 = ~_activated_data_e_scaled_sign_out_isInf_T_15; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_17 = activated_data_e_scaled_sign_isSpecial_5 & _activated_data_e_scaled_sign_out_isInf_T_16; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_5_isInf = _activated_data_e_scaled_sign_out_isInf_T_17; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_5 = _activated_data_e_scaled_muladder_5_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_5_sign = _activated_data_e_scaled_sign_out_sign_T_5; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_5 = {1'h0, activated_data_e_scaled_sign_exp_5}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_5_sExp = _activated_data_e_scaled_sign_out_sExp_T_5; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_20 = ~activated_data_e_scaled_sign_isZero_5; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_21 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_20}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_22 = _activated_data_e_scaled_muladder_5_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_23 = {_activated_data_e_scaled_sign_out_sig_T_21, _activated_data_e_scaled_sign_out_sig_T_22}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_5_sig = _activated_data_e_scaled_sign_out_sig_T_23; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_5 = activated_data_e_scaled_sign_out_5_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_65; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_29 = _activated_data_e_scaled_T_65; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_5 = activated_data_e_scaled_overflow_5 ? activated_data_e_scaled_sat_5 : _activated_data_e_scaled_WIRE_29; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_25 = $signed(activated_data_e_scaled_5) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_26 = $signed(activated_data_e_scaled_5) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_27 = _activated_data_e_clipped_T_26 ? 32'hFFFFFF80 : activated_data_e_scaled_5; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_28 = _activated_data_e_clipped_T_25 ? 32'h7F : _activated_data_e_clipped_T_27; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_29 = _activated_data_e_clipped_T_28[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_5 = _activated_data_e_clipped_T_29; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_5_0 = activated_data_e_clipped_5; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_5_0 = _activated_data_WIRE_5_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_193 = _activated_data_e_act_T_192; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_194 = $signed(io_in_bits_acc_read_resp_data_6_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_195 = _activated_data_e_act_T_194 ? io_in_bits_acc_read_resp_data_6_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_33 = {io_in_bits_acc_read_resp_data_6_0_0[31], io_in_bits_acc_read_resp_data_6_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_199; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_199 = _GEN_33; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_214; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_214 = _GEN_33; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_200 = _activated_data_e_act_T_199[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_201 = _activated_data_e_act_T_200; // @[Arithmetic.scala:95:38]
wire _GEN_34 = $signed(io_in_bits_acc_read_resp_data_6_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_24; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_24 = _GEN_34; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_24; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_24 = _GEN_34; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_6 = {_activated_data_e_act_q_sign_T_24, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_25 = 33'h0 - _GEN_33; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_26 = _activated_data_e_act_q_abs_T_25[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_27 = _activated_data_e_act_q_abs_T_26; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_6 = _activated_data_e_act_q_abs_T_24 ? _activated_data_e_act_q_abs_T_27 : io_in_bits_acc_read_resp_data_6_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_43 = _activated_data_e_act_q_clipped_T_42[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_44 = _activated_data_e_act_q_clipped_T_43; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_45 = $signed(activated_data_e_act_q_abs_6) > $signed(_activated_data_e_act_q_clipped_T_44); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_47 = _activated_data_e_act_q_clipped_T_46[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_48 = _activated_data_e_act_q_clipped_T_47; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_6 = _activated_data_e_act_q_clipped_T_45 ? _activated_data_e_act_q_clipped_T_48 : activated_data_e_act_q_abs_6; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_35 = {activated_data_e_act_q_clipped_6[31], activated_data_e_act_q_clipped_6} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_66; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_66 = _GEN_35; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_69; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_69 = _GEN_35; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_67 = _activated_data_e_act_q_poly_T_66[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_68 = _activated_data_e_act_q_poly_T_67; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_70 = _activated_data_e_act_q_poly_T_69[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_71 = _activated_data_e_act_q_poly_T_70; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_72 = {{32{_activated_data_e_act_q_poly_T_68[31]}}, _activated_data_e_act_q_poly_T_68} * {{32{_activated_data_e_act_q_poly_T_71[31]}}, _activated_data_e_act_q_poly_T_71}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_73 = {_activated_data_e_act_q_poly_T_72[63], _activated_data_e_act_q_poly_T_72} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_74 = _activated_data_e_act_q_poly_T_73[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_75 = _activated_data_e_act_q_poly_T_74; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_76 = _activated_data_e_act_q_poly_T_75[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_6 = _activated_data_e_act_q_poly_T_76; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_12 = {{32{activated_data_e_act_q_sign_6[1]}}, activated_data_e_act_q_sign_6} * {{2{activated_data_e_act_q_poly_6[31]}}, activated_data_e_act_q_poly_6}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_13 = _activated_data_e_act_q_erf_T_12[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_6 = _activated_data_e_act_q_erf_T_13; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_205 = {activated_data_e_act_q_erf_6[31], activated_data_e_act_q_erf_6} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_206 = _activated_data_e_act_T_205[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_207 = _activated_data_e_act_T_206; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_208 = {{32{io_in_bits_acc_read_resp_data_6_0_0[31]}}, io_in_bits_acc_read_resp_data_6_0_0} * {{32{_activated_data_e_act_T_207[31]}}, _activated_data_e_act_T_207}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_209 = _activated_data_e_act_T_208[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_210 = _activated_data_e_act_T_209; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_215 = _activated_data_e_act_T_214[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_216 = _activated_data_e_act_T_215; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_12 = 33'h0 - {_activated_data_e_act_T_216[31], _activated_data_e_act_T_216}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_13 = _activated_data_e_act_neg_q_iexp_T_12[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_6 = _activated_data_e_act_neg_q_iexp_T_13; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_24 = {{32{activated_data_e_act_neg_q_iexp_6[31]}}, activated_data_e_act_neg_q_iexp_6} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_25 = _activated_data_e_act_z_iexp_T_24; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_26 = _activated_data_e_act_z_iexp_T_25[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_27 = _activated_data_e_act_z_iexp_T_26; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_198 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_200 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_202 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_204 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_206 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_208 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_210 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_212 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_214 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_216 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_218 = activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_6 = _activated_data_e_act_z_iexp_T_27[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_230; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_6; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_218 = activated_data_e_act_z_iexp_saturated_6; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_199 = _activated_data_e_act_z_iexp_saturated_T_198[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_201 = _activated_data_e_act_z_iexp_saturated_T_200[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_203 = _activated_data_e_act_z_iexp_saturated_T_202[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_205 = _activated_data_e_act_z_iexp_saturated_T_204[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_207 = _activated_data_e_act_z_iexp_saturated_T_206[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_209 = _activated_data_e_act_z_iexp_saturated_T_208[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_211 = _activated_data_e_act_z_iexp_saturated_T_210[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_213 = _activated_data_e_act_z_iexp_saturated_T_212[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_215 = _activated_data_e_act_z_iexp_saturated_T_214[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_217 = _activated_data_e_act_z_iexp_saturated_T_216[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_219 = _activated_data_e_act_z_iexp_saturated_T_218[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_220 = _activated_data_e_act_z_iexp_saturated_T_199 | _activated_data_e_act_z_iexp_saturated_T_201; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_221 = _activated_data_e_act_z_iexp_saturated_T_220 | _activated_data_e_act_z_iexp_saturated_T_203; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_222 = _activated_data_e_act_z_iexp_saturated_T_221 | _activated_data_e_act_z_iexp_saturated_T_205; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_223 = _activated_data_e_act_z_iexp_saturated_T_222 | _activated_data_e_act_z_iexp_saturated_T_207; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_224 = _activated_data_e_act_z_iexp_saturated_T_223 | _activated_data_e_act_z_iexp_saturated_T_209; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_225 = _activated_data_e_act_z_iexp_saturated_T_224 | _activated_data_e_act_z_iexp_saturated_T_211; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_226 = _activated_data_e_act_z_iexp_saturated_T_225 | _activated_data_e_act_z_iexp_saturated_T_213; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_227 = _activated_data_e_act_z_iexp_saturated_T_226 | _activated_data_e_act_z_iexp_saturated_T_215; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_228 = _activated_data_e_act_z_iexp_saturated_T_227 | _activated_data_e_act_z_iexp_saturated_T_217; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_229 = _activated_data_e_act_z_iexp_saturated_T_228 | _activated_data_e_act_z_iexp_saturated_T_219; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_230 = _activated_data_e_act_z_iexp_saturated_T_229 ? 32'h20 : activated_data_e_act_z_iexp_6; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_6 = _activated_data_e_act_z_iexp_saturated_T_230; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_30 = {{32{activated_data_e_act_z_iexp_6[31]}}, activated_data_e_act_z_iexp_6} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_31 = {_activated_data_e_act_qp_iexp_T_30[63], _activated_data_e_act_qp_iexp_T_30} + {{33{_activated_data_e_act_T_216[31]}}, _activated_data_e_act_T_216}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_32 = _activated_data_e_act_qp_iexp_T_31[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_33 = _activated_data_e_act_qp_iexp_T_32; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_34 = _activated_data_e_act_qp_iexp_T_33[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_6 = _activated_data_e_act_qp_iexp_T_34; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_36 = {activated_data_e_act_qp_iexp_6[31], activated_data_e_act_qp_iexp_6} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_66; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_66 = _GEN_36; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_69; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_69 = _GEN_36; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_67 = _activated_data_e_act_q_poly_iexp_T_66[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_68 = _activated_data_e_act_q_poly_iexp_T_67; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_70 = _activated_data_e_act_q_poly_iexp_T_69[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_71 = _activated_data_e_act_q_poly_iexp_T_70; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_72 = {{32{_activated_data_e_act_q_poly_iexp_T_68[31]}}, _activated_data_e_act_q_poly_iexp_T_68} * {{32{_activated_data_e_act_q_poly_iexp_T_71[31]}}, _activated_data_e_act_q_poly_iexp_T_71}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_73 = {_activated_data_e_act_q_poly_iexp_T_72[63], _activated_data_e_act_q_poly_iexp_T_72} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_74 = _activated_data_e_act_q_poly_iexp_T_73[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_75 = _activated_data_e_act_q_poly_iexp_T_74; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_76 = _activated_data_e_act_q_poly_iexp_T_75[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_6 = _activated_data_e_act_q_poly_iexp_T_76; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_217 = activated_data_e_act_q_poly_iexp_6; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_219 = _activated_data_e_act_T_217 >> _activated_data_e_act_T_218; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_220 = _activated_data_e_act_T_219; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_6 = _activated_data_e_act_T_220; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_222 = _activated_data_e_act_T_221; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_223 = _activated_data_e_act_T_222; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_6 = _activated_data_e_act_T_193 ? _activated_data_e_act_T_195 : _activated_data_e_act_T_223; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_6 = activated_data_e_act_6; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_74_bits = _activated_data_e_scaled_T_73_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_33 = _activated_data_e_scaled_T_74_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_75; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_75 = _activated_data_e_scaled_WIRE_33; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_32_bits = _activated_data_e_scaled_T_75; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_6 = _activated_data_e_scaled_WIRE_32_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_6_sign = activated_data_e_scaled_f_rec_rawIn_sign_6; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_6 = _activated_data_e_scaled_WIRE_32_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_6 = _activated_data_e_scaled_WIRE_32_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 = activated_data_e_scaled_f_rec_rawIn_expIn_6 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6 = activated_data_e_scaled_f_rec_rawIn_fractIn_6 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_264 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_265 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_266 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_267 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_268 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_269 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_270 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_271 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_272 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_273 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_274 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_275 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_276 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_277 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_278 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_279 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_280 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_281 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_282 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_283 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_284 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_285 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_286 = activated_data_e_scaled_f_rec_rawIn_fractIn_6[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_287 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_265 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_288 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_266 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_287; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_289 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_267 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_288; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_290 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_268 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_289; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_291 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_269 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_290; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_292 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_270 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_291; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_293 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_271 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_292; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_294 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_272 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_293; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_295 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_273 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_294; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_296 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_274 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_295; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_297 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_275 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_296; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_298 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_276 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_297; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_299 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_277 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_298; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_300 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_278 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_299; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_301 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_279 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_300; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_302 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_280 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_301; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_303 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_281 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_302; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_304 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_282 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_303; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_305 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_283 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_304; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_306 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_284 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_305; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_307 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_285 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_306; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_6 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_286 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_307; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_12 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_6} << activated_data_e_scaled_f_rec_rawIn_normDist_6; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_13 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_12[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_6 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_13, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_30 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_6}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_31 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_30 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_6}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_32 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_33 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_32}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_34 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_31} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_33}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_6 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_34[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_12 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_6; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_6 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_6_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_6 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_6[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_6 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_6; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_50 = activated_data_e_scaled_f_rec_rawIn_6_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_6_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_6_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_6_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_12 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_13 = activated_data_e_scaled_f_rec_rawIn_isSpecial_6 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_12; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_6_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_13; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_6 = activated_data_e_scaled_f_rec_rawIn_isSpecial_6 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_6; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_6_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_6; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_13 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_12}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_6_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_13; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_24 = ~activated_data_e_scaled_f_rec_rawIn_isZero_6; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_25 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_24}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_26 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_6 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_6 : activated_data_e_scaled_f_rec_rawIn_fractIn_6; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_27 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_25, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_26}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_6_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_27; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_48 = activated_data_e_scaled_f_rec_rawIn_6_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_49 = activated_data_e_scaled_f_rec_rawIn_6_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_48; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_51 = {_activated_data_e_scaled_f_rec_T_49[2:1], _activated_data_e_scaled_f_rec_T_49[0] | _activated_data_e_scaled_f_rec_T_50}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_52 = {activated_data_e_scaled_f_rec_rawIn_6_sign, _activated_data_e_scaled_f_rec_T_51}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_53 = activated_data_e_scaled_f_rec_rawIn_6_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_54 = {_activated_data_e_scaled_f_rec_T_52, _activated_data_e_scaled_f_rec_T_53}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_55 = activated_data_e_scaled_f_rec_rawIn_6_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_6 = {_activated_data_e_scaled_f_rec_T_54, _activated_data_e_scaled_f_rec_T_55}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_6 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_6; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_6 = _activated_data_e_scaled_rec_fn_to_in_6_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_6 = _activated_data_e_scaled_muladder_6_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_6 = activated_data_e_scaled_sign_exp_6[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_6 = _activated_data_e_scaled_sign_isZero_T_6 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_6_isZero = activated_data_e_scaled_sign_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_6 = activated_data_e_scaled_sign_exp_6[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_6 = &_activated_data_e_scaled_sign_isSpecial_T_6; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_20; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_6; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_6; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_27; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_6_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_6_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_6_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_6_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_6_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_12 = activated_data_e_scaled_sign_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_18 = activated_data_e_scaled_sign_exp_6[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_13 = activated_data_e_scaled_sign_isSpecial_6 & _activated_data_e_scaled_sign_out_isNaN_T_12; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_6_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_13; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_19 = ~_activated_data_e_scaled_sign_out_isInf_T_18; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_20 = activated_data_e_scaled_sign_isSpecial_6 & _activated_data_e_scaled_sign_out_isInf_T_19; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_6_isInf = _activated_data_e_scaled_sign_out_isInf_T_20; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_6 = _activated_data_e_scaled_muladder_6_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_6_sign = _activated_data_e_scaled_sign_out_sign_T_6; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_6 = {1'h0, activated_data_e_scaled_sign_exp_6}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_6_sExp = _activated_data_e_scaled_sign_out_sExp_T_6; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_24 = ~activated_data_e_scaled_sign_isZero_6; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_25 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_24}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_26 = _activated_data_e_scaled_muladder_6_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_27 = {_activated_data_e_scaled_sign_out_sig_T_25, _activated_data_e_scaled_sign_out_sig_T_26}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_6_sig = _activated_data_e_scaled_sign_out_sig_T_27; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_6 = activated_data_e_scaled_sign_out_6_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_76; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_34 = _activated_data_e_scaled_T_76; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_6 = activated_data_e_scaled_overflow_6 ? activated_data_e_scaled_sat_6 : _activated_data_e_scaled_WIRE_34; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_30 = $signed(activated_data_e_scaled_6) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_31 = $signed(activated_data_e_scaled_6) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_32 = _activated_data_e_clipped_T_31 ? 32'hFFFFFF80 : activated_data_e_scaled_6; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_33 = _activated_data_e_clipped_T_30 ? 32'h7F : _activated_data_e_clipped_T_32; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_34 = _activated_data_e_clipped_T_33[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_6 = _activated_data_e_clipped_T_34; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_6_0 = activated_data_e_clipped_6; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_6_0 = _activated_data_WIRE_6_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_225 = _activated_data_e_act_T_224; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_226 = $signed(io_in_bits_acc_read_resp_data_7_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_227 = _activated_data_e_act_T_226 ? io_in_bits_acc_read_resp_data_7_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_37 = {io_in_bits_acc_read_resp_data_7_0_0[31], io_in_bits_acc_read_resp_data_7_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_231; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_231 = _GEN_37; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_246; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_246 = _GEN_37; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_232 = _activated_data_e_act_T_231[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_233 = _activated_data_e_act_T_232; // @[Arithmetic.scala:95:38]
wire _GEN_38 = $signed(io_in_bits_acc_read_resp_data_7_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_28; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_28 = _GEN_38; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_28; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_28 = _GEN_38; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_7 = {_activated_data_e_act_q_sign_T_28, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_29 = 33'h0 - _GEN_37; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_30 = _activated_data_e_act_q_abs_T_29[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_31 = _activated_data_e_act_q_abs_T_30; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_7 = _activated_data_e_act_q_abs_T_28 ? _activated_data_e_act_q_abs_T_31 : io_in_bits_acc_read_resp_data_7_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_50 = _activated_data_e_act_q_clipped_T_49[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_51 = _activated_data_e_act_q_clipped_T_50; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_52 = $signed(activated_data_e_act_q_abs_7) > $signed(_activated_data_e_act_q_clipped_T_51); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_54 = _activated_data_e_act_q_clipped_T_53[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_55 = _activated_data_e_act_q_clipped_T_54; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_7 = _activated_data_e_act_q_clipped_T_52 ? _activated_data_e_act_q_clipped_T_55 : activated_data_e_act_q_abs_7; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_39 = {activated_data_e_act_q_clipped_7[31], activated_data_e_act_q_clipped_7} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_77; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_77 = _GEN_39; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_80; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_80 = _GEN_39; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_78 = _activated_data_e_act_q_poly_T_77[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_79 = _activated_data_e_act_q_poly_T_78; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_81 = _activated_data_e_act_q_poly_T_80[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_82 = _activated_data_e_act_q_poly_T_81; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_83 = {{32{_activated_data_e_act_q_poly_T_79[31]}}, _activated_data_e_act_q_poly_T_79} * {{32{_activated_data_e_act_q_poly_T_82[31]}}, _activated_data_e_act_q_poly_T_82}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_84 = {_activated_data_e_act_q_poly_T_83[63], _activated_data_e_act_q_poly_T_83} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_85 = _activated_data_e_act_q_poly_T_84[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_86 = _activated_data_e_act_q_poly_T_85; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_87 = _activated_data_e_act_q_poly_T_86[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_7 = _activated_data_e_act_q_poly_T_87; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_14 = {{32{activated_data_e_act_q_sign_7[1]}}, activated_data_e_act_q_sign_7} * {{2{activated_data_e_act_q_poly_7[31]}}, activated_data_e_act_q_poly_7}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_15 = _activated_data_e_act_q_erf_T_14[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_7 = _activated_data_e_act_q_erf_T_15; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_237 = {activated_data_e_act_q_erf_7[31], activated_data_e_act_q_erf_7} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_238 = _activated_data_e_act_T_237[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_239 = _activated_data_e_act_T_238; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_240 = {{32{io_in_bits_acc_read_resp_data_7_0_0[31]}}, io_in_bits_acc_read_resp_data_7_0_0} * {{32{_activated_data_e_act_T_239[31]}}, _activated_data_e_act_T_239}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_241 = _activated_data_e_act_T_240[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_242 = _activated_data_e_act_T_241; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_247 = _activated_data_e_act_T_246[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_248 = _activated_data_e_act_T_247; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_14 = 33'h0 - {_activated_data_e_act_T_248[31], _activated_data_e_act_T_248}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_15 = _activated_data_e_act_neg_q_iexp_T_14[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_7 = _activated_data_e_act_neg_q_iexp_T_15; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_28 = {{32{activated_data_e_act_neg_q_iexp_7[31]}}, activated_data_e_act_neg_q_iexp_7} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_29 = _activated_data_e_act_z_iexp_T_28; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_30 = _activated_data_e_act_z_iexp_T_29[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_31 = _activated_data_e_act_z_iexp_T_30; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_231 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_233 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_235 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_237 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_239 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_241 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_243 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_245 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_247 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_249 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_251 = activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_7 = _activated_data_e_act_z_iexp_T_31[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_263; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_7; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_250 = activated_data_e_act_z_iexp_saturated_7; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_232 = _activated_data_e_act_z_iexp_saturated_T_231[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_234 = _activated_data_e_act_z_iexp_saturated_T_233[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_236 = _activated_data_e_act_z_iexp_saturated_T_235[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_238 = _activated_data_e_act_z_iexp_saturated_T_237[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_240 = _activated_data_e_act_z_iexp_saturated_T_239[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_242 = _activated_data_e_act_z_iexp_saturated_T_241[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_244 = _activated_data_e_act_z_iexp_saturated_T_243[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_246 = _activated_data_e_act_z_iexp_saturated_T_245[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_248 = _activated_data_e_act_z_iexp_saturated_T_247[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_250 = _activated_data_e_act_z_iexp_saturated_T_249[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_252 = _activated_data_e_act_z_iexp_saturated_T_251[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_253 = _activated_data_e_act_z_iexp_saturated_T_232 | _activated_data_e_act_z_iexp_saturated_T_234; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_254 = _activated_data_e_act_z_iexp_saturated_T_253 | _activated_data_e_act_z_iexp_saturated_T_236; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_255 = _activated_data_e_act_z_iexp_saturated_T_254 | _activated_data_e_act_z_iexp_saturated_T_238; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_256 = _activated_data_e_act_z_iexp_saturated_T_255 | _activated_data_e_act_z_iexp_saturated_T_240; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_257 = _activated_data_e_act_z_iexp_saturated_T_256 | _activated_data_e_act_z_iexp_saturated_T_242; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_258 = _activated_data_e_act_z_iexp_saturated_T_257 | _activated_data_e_act_z_iexp_saturated_T_244; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_259 = _activated_data_e_act_z_iexp_saturated_T_258 | _activated_data_e_act_z_iexp_saturated_T_246; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_260 = _activated_data_e_act_z_iexp_saturated_T_259 | _activated_data_e_act_z_iexp_saturated_T_248; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_261 = _activated_data_e_act_z_iexp_saturated_T_260 | _activated_data_e_act_z_iexp_saturated_T_250; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_262 = _activated_data_e_act_z_iexp_saturated_T_261 | _activated_data_e_act_z_iexp_saturated_T_252; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_263 = _activated_data_e_act_z_iexp_saturated_T_262 ? 32'h20 : activated_data_e_act_z_iexp_7; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_7 = _activated_data_e_act_z_iexp_saturated_T_263; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_35 = {{32{activated_data_e_act_z_iexp_7[31]}}, activated_data_e_act_z_iexp_7} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_36 = {_activated_data_e_act_qp_iexp_T_35[63], _activated_data_e_act_qp_iexp_T_35} + {{33{_activated_data_e_act_T_248[31]}}, _activated_data_e_act_T_248}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_37 = _activated_data_e_act_qp_iexp_T_36[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_38 = _activated_data_e_act_qp_iexp_T_37; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_39 = _activated_data_e_act_qp_iexp_T_38[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_7 = _activated_data_e_act_qp_iexp_T_39; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_40 = {activated_data_e_act_qp_iexp_7[31], activated_data_e_act_qp_iexp_7} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_77; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_77 = _GEN_40; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_80; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_80 = _GEN_40; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_78 = _activated_data_e_act_q_poly_iexp_T_77[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_79 = _activated_data_e_act_q_poly_iexp_T_78; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_81 = _activated_data_e_act_q_poly_iexp_T_80[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_82 = _activated_data_e_act_q_poly_iexp_T_81; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_83 = {{32{_activated_data_e_act_q_poly_iexp_T_79[31]}}, _activated_data_e_act_q_poly_iexp_T_79} * {{32{_activated_data_e_act_q_poly_iexp_T_82[31]}}, _activated_data_e_act_q_poly_iexp_T_82}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_84 = {_activated_data_e_act_q_poly_iexp_T_83[63], _activated_data_e_act_q_poly_iexp_T_83} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_85 = _activated_data_e_act_q_poly_iexp_T_84[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_86 = _activated_data_e_act_q_poly_iexp_T_85; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_87 = _activated_data_e_act_q_poly_iexp_T_86[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_7 = _activated_data_e_act_q_poly_iexp_T_87; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_249 = activated_data_e_act_q_poly_iexp_7; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_251 = _activated_data_e_act_T_249 >> _activated_data_e_act_T_250; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_252 = _activated_data_e_act_T_251; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_7 = _activated_data_e_act_T_252; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_254 = _activated_data_e_act_T_253; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_255 = _activated_data_e_act_T_254; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_7 = _activated_data_e_act_T_225 ? _activated_data_e_act_T_227 : _activated_data_e_act_T_255; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_7 = activated_data_e_act_7; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_85_bits = _activated_data_e_scaled_T_84_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_38 = _activated_data_e_scaled_T_85_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_86; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_86 = _activated_data_e_scaled_WIRE_38; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_37_bits = _activated_data_e_scaled_T_86; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_7 = _activated_data_e_scaled_WIRE_37_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_7_sign = activated_data_e_scaled_f_rec_rawIn_sign_7; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_7 = _activated_data_e_scaled_WIRE_37_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_7 = _activated_data_e_scaled_WIRE_37_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 = activated_data_e_scaled_f_rec_rawIn_expIn_7 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7 = activated_data_e_scaled_f_rec_rawIn_fractIn_7 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_308 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_309 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_310 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_311 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_312 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_313 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_314 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_315 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_316 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_317 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_318 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_319 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_320 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_321 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_322 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_323 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_324 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_325 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_326 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_327 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_328 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_329 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_330 = activated_data_e_scaled_f_rec_rawIn_fractIn_7[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_331 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_309 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_332 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_310 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_331; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_333 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_311 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_332; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_334 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_312 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_333; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_335 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_313 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_334; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_336 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_314 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_335; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_337 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_315 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_336; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_338 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_316 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_337; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_339 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_317 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_338; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_340 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_318 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_339; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_341 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_319 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_340; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_342 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_320 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_341; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_343 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_321 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_342; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_344 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_322 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_343; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_345 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_323 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_344; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_346 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_324 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_345; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_347 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_325 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_346; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_348 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_326 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_347; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_349 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_327 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_348; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_350 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_328 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_349; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_351 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_329 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_350; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_7 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_330 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_351; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_14 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_7} << activated_data_e_scaled_f_rec_rawIn_normDist_7; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_15 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_14[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_7 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_15, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_35 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_7}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_36 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_35 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_7}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_37 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_38 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_37}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_39 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_36} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_38}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_7 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_39[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_14 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_7; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_7 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_7_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_7 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_7[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_7 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_7; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_58 = activated_data_e_scaled_f_rec_rawIn_7_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_7_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_7_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_7_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_14 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_15 = activated_data_e_scaled_f_rec_rawIn_isSpecial_7 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_14; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_7_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_15; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_7 = activated_data_e_scaled_f_rec_rawIn_isSpecial_7 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_7; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_7_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_7; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_15 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_14}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_7_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_15; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_28 = ~activated_data_e_scaled_f_rec_rawIn_isZero_7; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_29 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_28}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_30 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_7 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_7 : activated_data_e_scaled_f_rec_rawIn_fractIn_7; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_31 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_29, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_30}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_7_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_31; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_56 = activated_data_e_scaled_f_rec_rawIn_7_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_57 = activated_data_e_scaled_f_rec_rawIn_7_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_56; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_59 = {_activated_data_e_scaled_f_rec_T_57[2:1], _activated_data_e_scaled_f_rec_T_57[0] | _activated_data_e_scaled_f_rec_T_58}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_60 = {activated_data_e_scaled_f_rec_rawIn_7_sign, _activated_data_e_scaled_f_rec_T_59}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_61 = activated_data_e_scaled_f_rec_rawIn_7_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_62 = {_activated_data_e_scaled_f_rec_T_60, _activated_data_e_scaled_f_rec_T_61}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_63 = activated_data_e_scaled_f_rec_rawIn_7_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_7 = {_activated_data_e_scaled_f_rec_T_62, _activated_data_e_scaled_f_rec_T_63}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_7 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_7; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_7 = _activated_data_e_scaled_rec_fn_to_in_7_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_7 = _activated_data_e_scaled_muladder_7_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_7 = activated_data_e_scaled_sign_exp_7[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_7 = _activated_data_e_scaled_sign_isZero_T_7 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_7_isZero = activated_data_e_scaled_sign_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_7 = activated_data_e_scaled_sign_exp_7[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_7 = &_activated_data_e_scaled_sign_isSpecial_T_7; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_23; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_7; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_7; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_31; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_7_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_7_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_7_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_7_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_7_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_14 = activated_data_e_scaled_sign_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_21 = activated_data_e_scaled_sign_exp_7[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_15 = activated_data_e_scaled_sign_isSpecial_7 & _activated_data_e_scaled_sign_out_isNaN_T_14; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_7_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_15; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_22 = ~_activated_data_e_scaled_sign_out_isInf_T_21; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_23 = activated_data_e_scaled_sign_isSpecial_7 & _activated_data_e_scaled_sign_out_isInf_T_22; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_7_isInf = _activated_data_e_scaled_sign_out_isInf_T_23; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_7 = _activated_data_e_scaled_muladder_7_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_7_sign = _activated_data_e_scaled_sign_out_sign_T_7; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_7 = {1'h0, activated_data_e_scaled_sign_exp_7}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_7_sExp = _activated_data_e_scaled_sign_out_sExp_T_7; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_28 = ~activated_data_e_scaled_sign_isZero_7; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_29 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_28}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_30 = _activated_data_e_scaled_muladder_7_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_31 = {_activated_data_e_scaled_sign_out_sig_T_29, _activated_data_e_scaled_sign_out_sig_T_30}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_7_sig = _activated_data_e_scaled_sign_out_sig_T_31; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_7 = activated_data_e_scaled_sign_out_7_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_87; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_39 = _activated_data_e_scaled_T_87; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_7 = activated_data_e_scaled_overflow_7 ? activated_data_e_scaled_sat_7 : _activated_data_e_scaled_WIRE_39; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_35 = $signed(activated_data_e_scaled_7) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_36 = $signed(activated_data_e_scaled_7) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_37 = _activated_data_e_clipped_T_36 ? 32'hFFFFFF80 : activated_data_e_scaled_7; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_38 = _activated_data_e_clipped_T_35 ? 32'h7F : _activated_data_e_clipped_T_37; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_39 = _activated_data_e_clipped_T_38[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_7 = _activated_data_e_clipped_T_39; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_7_0 = activated_data_e_clipped_7; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_7_0 = _activated_data_WIRE_7_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_257 = _activated_data_e_act_T_256; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_258 = $signed(io_in_bits_acc_read_resp_data_8_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_259 = _activated_data_e_act_T_258 ? io_in_bits_acc_read_resp_data_8_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_41 = {io_in_bits_acc_read_resp_data_8_0_0[31], io_in_bits_acc_read_resp_data_8_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_263; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_263 = _GEN_41; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_278; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_278 = _GEN_41; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_264 = _activated_data_e_act_T_263[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_265 = _activated_data_e_act_T_264; // @[Arithmetic.scala:95:38]
wire _GEN_42 = $signed(io_in_bits_acc_read_resp_data_8_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_32; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_32 = _GEN_42; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_32; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_32 = _GEN_42; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_8 = {_activated_data_e_act_q_sign_T_32, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_33 = 33'h0 - _GEN_41; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_34 = _activated_data_e_act_q_abs_T_33[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_35 = _activated_data_e_act_q_abs_T_34; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_8 = _activated_data_e_act_q_abs_T_32 ? _activated_data_e_act_q_abs_T_35 : io_in_bits_acc_read_resp_data_8_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_57 = _activated_data_e_act_q_clipped_T_56[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_58 = _activated_data_e_act_q_clipped_T_57; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_59 = $signed(activated_data_e_act_q_abs_8) > $signed(_activated_data_e_act_q_clipped_T_58); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_61 = _activated_data_e_act_q_clipped_T_60[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_62 = _activated_data_e_act_q_clipped_T_61; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_8 = _activated_data_e_act_q_clipped_T_59 ? _activated_data_e_act_q_clipped_T_62 : activated_data_e_act_q_abs_8; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_43 = {activated_data_e_act_q_clipped_8[31], activated_data_e_act_q_clipped_8} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_88; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_88 = _GEN_43; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_91; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_91 = _GEN_43; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_89 = _activated_data_e_act_q_poly_T_88[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_90 = _activated_data_e_act_q_poly_T_89; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_92 = _activated_data_e_act_q_poly_T_91[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_93 = _activated_data_e_act_q_poly_T_92; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_94 = {{32{_activated_data_e_act_q_poly_T_90[31]}}, _activated_data_e_act_q_poly_T_90} * {{32{_activated_data_e_act_q_poly_T_93[31]}}, _activated_data_e_act_q_poly_T_93}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_95 = {_activated_data_e_act_q_poly_T_94[63], _activated_data_e_act_q_poly_T_94} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_96 = _activated_data_e_act_q_poly_T_95[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_97 = _activated_data_e_act_q_poly_T_96; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_98 = _activated_data_e_act_q_poly_T_97[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_8 = _activated_data_e_act_q_poly_T_98; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_16 = {{32{activated_data_e_act_q_sign_8[1]}}, activated_data_e_act_q_sign_8} * {{2{activated_data_e_act_q_poly_8[31]}}, activated_data_e_act_q_poly_8}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_17 = _activated_data_e_act_q_erf_T_16[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_8 = _activated_data_e_act_q_erf_T_17; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_269 = {activated_data_e_act_q_erf_8[31], activated_data_e_act_q_erf_8} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_270 = _activated_data_e_act_T_269[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_271 = _activated_data_e_act_T_270; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_272 = {{32{io_in_bits_acc_read_resp_data_8_0_0[31]}}, io_in_bits_acc_read_resp_data_8_0_0} * {{32{_activated_data_e_act_T_271[31]}}, _activated_data_e_act_T_271}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_273 = _activated_data_e_act_T_272[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_274 = _activated_data_e_act_T_273; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_279 = _activated_data_e_act_T_278[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_280 = _activated_data_e_act_T_279; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_16 = 33'h0 - {_activated_data_e_act_T_280[31], _activated_data_e_act_T_280}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_17 = _activated_data_e_act_neg_q_iexp_T_16[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_8 = _activated_data_e_act_neg_q_iexp_T_17; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_32 = {{32{activated_data_e_act_neg_q_iexp_8[31]}}, activated_data_e_act_neg_q_iexp_8} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_33 = _activated_data_e_act_z_iexp_T_32; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_34 = _activated_data_e_act_z_iexp_T_33[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_35 = _activated_data_e_act_z_iexp_T_34; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_264 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_266 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_268 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_270 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_272 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_274 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_276 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_278 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_280 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_282 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_284 = activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_8 = _activated_data_e_act_z_iexp_T_35[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_296; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_8; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_282 = activated_data_e_act_z_iexp_saturated_8; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_265 = _activated_data_e_act_z_iexp_saturated_T_264[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_267 = _activated_data_e_act_z_iexp_saturated_T_266[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_269 = _activated_data_e_act_z_iexp_saturated_T_268[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_271 = _activated_data_e_act_z_iexp_saturated_T_270[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_273 = _activated_data_e_act_z_iexp_saturated_T_272[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_275 = _activated_data_e_act_z_iexp_saturated_T_274[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_277 = _activated_data_e_act_z_iexp_saturated_T_276[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_279 = _activated_data_e_act_z_iexp_saturated_T_278[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_281 = _activated_data_e_act_z_iexp_saturated_T_280[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_283 = _activated_data_e_act_z_iexp_saturated_T_282[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_285 = _activated_data_e_act_z_iexp_saturated_T_284[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_286 = _activated_data_e_act_z_iexp_saturated_T_265 | _activated_data_e_act_z_iexp_saturated_T_267; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_287 = _activated_data_e_act_z_iexp_saturated_T_286 | _activated_data_e_act_z_iexp_saturated_T_269; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_288 = _activated_data_e_act_z_iexp_saturated_T_287 | _activated_data_e_act_z_iexp_saturated_T_271; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_289 = _activated_data_e_act_z_iexp_saturated_T_288 | _activated_data_e_act_z_iexp_saturated_T_273; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_290 = _activated_data_e_act_z_iexp_saturated_T_289 | _activated_data_e_act_z_iexp_saturated_T_275; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_291 = _activated_data_e_act_z_iexp_saturated_T_290 | _activated_data_e_act_z_iexp_saturated_T_277; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_292 = _activated_data_e_act_z_iexp_saturated_T_291 | _activated_data_e_act_z_iexp_saturated_T_279; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_293 = _activated_data_e_act_z_iexp_saturated_T_292 | _activated_data_e_act_z_iexp_saturated_T_281; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_294 = _activated_data_e_act_z_iexp_saturated_T_293 | _activated_data_e_act_z_iexp_saturated_T_283; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_295 = _activated_data_e_act_z_iexp_saturated_T_294 | _activated_data_e_act_z_iexp_saturated_T_285; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_296 = _activated_data_e_act_z_iexp_saturated_T_295 ? 32'h20 : activated_data_e_act_z_iexp_8; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_8 = _activated_data_e_act_z_iexp_saturated_T_296; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_40 = {{32{activated_data_e_act_z_iexp_8[31]}}, activated_data_e_act_z_iexp_8} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_41 = {_activated_data_e_act_qp_iexp_T_40[63], _activated_data_e_act_qp_iexp_T_40} + {{33{_activated_data_e_act_T_280[31]}}, _activated_data_e_act_T_280}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_42 = _activated_data_e_act_qp_iexp_T_41[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_43 = _activated_data_e_act_qp_iexp_T_42; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_44 = _activated_data_e_act_qp_iexp_T_43[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_8 = _activated_data_e_act_qp_iexp_T_44; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_44 = {activated_data_e_act_qp_iexp_8[31], activated_data_e_act_qp_iexp_8} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_88; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_88 = _GEN_44; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_91; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_91 = _GEN_44; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_89 = _activated_data_e_act_q_poly_iexp_T_88[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_90 = _activated_data_e_act_q_poly_iexp_T_89; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_92 = _activated_data_e_act_q_poly_iexp_T_91[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_93 = _activated_data_e_act_q_poly_iexp_T_92; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_94 = {{32{_activated_data_e_act_q_poly_iexp_T_90[31]}}, _activated_data_e_act_q_poly_iexp_T_90} * {{32{_activated_data_e_act_q_poly_iexp_T_93[31]}}, _activated_data_e_act_q_poly_iexp_T_93}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_95 = {_activated_data_e_act_q_poly_iexp_T_94[63], _activated_data_e_act_q_poly_iexp_T_94} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_96 = _activated_data_e_act_q_poly_iexp_T_95[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_97 = _activated_data_e_act_q_poly_iexp_T_96; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_98 = _activated_data_e_act_q_poly_iexp_T_97[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_8 = _activated_data_e_act_q_poly_iexp_T_98; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_281 = activated_data_e_act_q_poly_iexp_8; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_283 = _activated_data_e_act_T_281 >> _activated_data_e_act_T_282; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_284 = _activated_data_e_act_T_283; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_8 = _activated_data_e_act_T_284; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_286 = _activated_data_e_act_T_285; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_287 = _activated_data_e_act_T_286; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_8 = _activated_data_e_act_T_257 ? _activated_data_e_act_T_259 : _activated_data_e_act_T_287; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_8 = activated_data_e_act_8; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_96_bits = _activated_data_e_scaled_T_95_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_43 = _activated_data_e_scaled_T_96_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_97; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_97 = _activated_data_e_scaled_WIRE_43; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_42_bits = _activated_data_e_scaled_T_97; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_8 = _activated_data_e_scaled_WIRE_42_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_8_sign = activated_data_e_scaled_f_rec_rawIn_sign_8; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_8 = _activated_data_e_scaled_WIRE_42_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_8 = _activated_data_e_scaled_WIRE_42_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 = activated_data_e_scaled_f_rec_rawIn_expIn_8 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8 = activated_data_e_scaled_f_rec_rawIn_fractIn_8 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_352 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_353 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_354 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_355 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_356 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_357 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_358 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_359 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_360 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_361 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_362 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_363 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_364 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_365 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_366 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_367 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_368 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_369 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_370 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_371 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_372 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_373 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_374 = activated_data_e_scaled_f_rec_rawIn_fractIn_8[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_375 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_353 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_376 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_354 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_375; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_377 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_355 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_376; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_378 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_356 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_377; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_379 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_357 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_378; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_380 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_358 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_379; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_381 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_359 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_380; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_382 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_360 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_381; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_383 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_361 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_382; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_384 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_362 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_383; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_385 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_363 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_384; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_386 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_364 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_385; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_387 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_365 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_386; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_388 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_366 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_387; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_389 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_367 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_388; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_390 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_368 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_389; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_391 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_369 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_390; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_392 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_370 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_391; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_393 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_371 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_392; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_394 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_372 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_393; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_395 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_373 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_394; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_8 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_374 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_395; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_16 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_8} << activated_data_e_scaled_f_rec_rawIn_normDist_8; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_17 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_16[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_8 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_17, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_40 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_8}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_41 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_40 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_8}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_42 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_43 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_42}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_44 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_41} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_43}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_8 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_44[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_16 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_8; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_8 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_8_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_8 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_8[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_8 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_8; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_66 = activated_data_e_scaled_f_rec_rawIn_8_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_8_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_8_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_8_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_16 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_17 = activated_data_e_scaled_f_rec_rawIn_isSpecial_8 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_16; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_8_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_17; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_8 = activated_data_e_scaled_f_rec_rawIn_isSpecial_8 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_8; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_8_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_8; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_17 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_16}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_8_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_17; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_32 = ~activated_data_e_scaled_f_rec_rawIn_isZero_8; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_33 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_32}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_34 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_8 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_8 : activated_data_e_scaled_f_rec_rawIn_fractIn_8; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_35 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_33, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_34}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_8_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_35; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_64 = activated_data_e_scaled_f_rec_rawIn_8_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_65 = activated_data_e_scaled_f_rec_rawIn_8_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_64; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_67 = {_activated_data_e_scaled_f_rec_T_65[2:1], _activated_data_e_scaled_f_rec_T_65[0] | _activated_data_e_scaled_f_rec_T_66}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_68 = {activated_data_e_scaled_f_rec_rawIn_8_sign, _activated_data_e_scaled_f_rec_T_67}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_69 = activated_data_e_scaled_f_rec_rawIn_8_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_70 = {_activated_data_e_scaled_f_rec_T_68, _activated_data_e_scaled_f_rec_T_69}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_71 = activated_data_e_scaled_f_rec_rawIn_8_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_8 = {_activated_data_e_scaled_f_rec_T_70, _activated_data_e_scaled_f_rec_T_71}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_8 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_8; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_8 = _activated_data_e_scaled_rec_fn_to_in_8_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_8 = _activated_data_e_scaled_muladder_8_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_8 = activated_data_e_scaled_sign_exp_8[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_8 = _activated_data_e_scaled_sign_isZero_T_8 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_8_isZero = activated_data_e_scaled_sign_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_8 = activated_data_e_scaled_sign_exp_8[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_8 = &_activated_data_e_scaled_sign_isSpecial_T_8; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_26; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_8; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_8; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_35; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_8_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_8_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_8_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_8_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_8_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_16 = activated_data_e_scaled_sign_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_24 = activated_data_e_scaled_sign_exp_8[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_17 = activated_data_e_scaled_sign_isSpecial_8 & _activated_data_e_scaled_sign_out_isNaN_T_16; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_8_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_17; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_25 = ~_activated_data_e_scaled_sign_out_isInf_T_24; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_26 = activated_data_e_scaled_sign_isSpecial_8 & _activated_data_e_scaled_sign_out_isInf_T_25; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_8_isInf = _activated_data_e_scaled_sign_out_isInf_T_26; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_8 = _activated_data_e_scaled_muladder_8_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_8_sign = _activated_data_e_scaled_sign_out_sign_T_8; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_8 = {1'h0, activated_data_e_scaled_sign_exp_8}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_8_sExp = _activated_data_e_scaled_sign_out_sExp_T_8; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_32 = ~activated_data_e_scaled_sign_isZero_8; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_33 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_32}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_34 = _activated_data_e_scaled_muladder_8_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_35 = {_activated_data_e_scaled_sign_out_sig_T_33, _activated_data_e_scaled_sign_out_sig_T_34}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_8_sig = _activated_data_e_scaled_sign_out_sig_T_35; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_8 = activated_data_e_scaled_sign_out_8_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_98; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_44 = _activated_data_e_scaled_T_98; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_8 = activated_data_e_scaled_overflow_8 ? activated_data_e_scaled_sat_8 : _activated_data_e_scaled_WIRE_44; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_40 = $signed(activated_data_e_scaled_8) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_41 = $signed(activated_data_e_scaled_8) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_42 = _activated_data_e_clipped_T_41 ? 32'hFFFFFF80 : activated_data_e_scaled_8; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_43 = _activated_data_e_clipped_T_40 ? 32'h7F : _activated_data_e_clipped_T_42; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_44 = _activated_data_e_clipped_T_43[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_8 = _activated_data_e_clipped_T_44; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_8_0 = activated_data_e_clipped_8; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_8_0 = _activated_data_WIRE_8_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_289 = _activated_data_e_act_T_288; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_290 = $signed(io_in_bits_acc_read_resp_data_9_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_291 = _activated_data_e_act_T_290 ? io_in_bits_acc_read_resp_data_9_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_45 = {io_in_bits_acc_read_resp_data_9_0_0[31], io_in_bits_acc_read_resp_data_9_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_295; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_295 = _GEN_45; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_310; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_310 = _GEN_45; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_296 = _activated_data_e_act_T_295[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_297 = _activated_data_e_act_T_296; // @[Arithmetic.scala:95:38]
wire _GEN_46 = $signed(io_in_bits_acc_read_resp_data_9_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_36; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_36 = _GEN_46; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_36; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_36 = _GEN_46; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_9 = {_activated_data_e_act_q_sign_T_36, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_37 = 33'h0 - _GEN_45; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_38 = _activated_data_e_act_q_abs_T_37[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_39 = _activated_data_e_act_q_abs_T_38; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_9 = _activated_data_e_act_q_abs_T_36 ? _activated_data_e_act_q_abs_T_39 : io_in_bits_acc_read_resp_data_9_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_64 = _activated_data_e_act_q_clipped_T_63[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_65 = _activated_data_e_act_q_clipped_T_64; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_66 = $signed(activated_data_e_act_q_abs_9) > $signed(_activated_data_e_act_q_clipped_T_65); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_68 = _activated_data_e_act_q_clipped_T_67[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_69 = _activated_data_e_act_q_clipped_T_68; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_9 = _activated_data_e_act_q_clipped_T_66 ? _activated_data_e_act_q_clipped_T_69 : activated_data_e_act_q_abs_9; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_47 = {activated_data_e_act_q_clipped_9[31], activated_data_e_act_q_clipped_9} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_99; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_99 = _GEN_47; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_102; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_102 = _GEN_47; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_100 = _activated_data_e_act_q_poly_T_99[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_101 = _activated_data_e_act_q_poly_T_100; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_103 = _activated_data_e_act_q_poly_T_102[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_104 = _activated_data_e_act_q_poly_T_103; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_105 = {{32{_activated_data_e_act_q_poly_T_101[31]}}, _activated_data_e_act_q_poly_T_101} * {{32{_activated_data_e_act_q_poly_T_104[31]}}, _activated_data_e_act_q_poly_T_104}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_106 = {_activated_data_e_act_q_poly_T_105[63], _activated_data_e_act_q_poly_T_105} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_107 = _activated_data_e_act_q_poly_T_106[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_108 = _activated_data_e_act_q_poly_T_107; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_109 = _activated_data_e_act_q_poly_T_108[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_9 = _activated_data_e_act_q_poly_T_109; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_18 = {{32{activated_data_e_act_q_sign_9[1]}}, activated_data_e_act_q_sign_9} * {{2{activated_data_e_act_q_poly_9[31]}}, activated_data_e_act_q_poly_9}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_19 = _activated_data_e_act_q_erf_T_18[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_9 = _activated_data_e_act_q_erf_T_19; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_301 = {activated_data_e_act_q_erf_9[31], activated_data_e_act_q_erf_9} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_302 = _activated_data_e_act_T_301[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_303 = _activated_data_e_act_T_302; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_304 = {{32{io_in_bits_acc_read_resp_data_9_0_0[31]}}, io_in_bits_acc_read_resp_data_9_0_0} * {{32{_activated_data_e_act_T_303[31]}}, _activated_data_e_act_T_303}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_305 = _activated_data_e_act_T_304[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_306 = _activated_data_e_act_T_305; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_311 = _activated_data_e_act_T_310[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_312 = _activated_data_e_act_T_311; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_18 = 33'h0 - {_activated_data_e_act_T_312[31], _activated_data_e_act_T_312}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_19 = _activated_data_e_act_neg_q_iexp_T_18[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_9 = _activated_data_e_act_neg_q_iexp_T_19; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_36 = {{32{activated_data_e_act_neg_q_iexp_9[31]}}, activated_data_e_act_neg_q_iexp_9} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_37 = _activated_data_e_act_z_iexp_T_36; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_38 = _activated_data_e_act_z_iexp_T_37[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_39 = _activated_data_e_act_z_iexp_T_38; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_297 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_299 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_301 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_303 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_305 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_307 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_309 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_311 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_313 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_315 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_317 = activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_9 = _activated_data_e_act_z_iexp_T_39[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_329; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_9; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_314 = activated_data_e_act_z_iexp_saturated_9; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_298 = _activated_data_e_act_z_iexp_saturated_T_297[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_300 = _activated_data_e_act_z_iexp_saturated_T_299[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_302 = _activated_data_e_act_z_iexp_saturated_T_301[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_304 = _activated_data_e_act_z_iexp_saturated_T_303[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_306 = _activated_data_e_act_z_iexp_saturated_T_305[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_308 = _activated_data_e_act_z_iexp_saturated_T_307[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_310 = _activated_data_e_act_z_iexp_saturated_T_309[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_312 = _activated_data_e_act_z_iexp_saturated_T_311[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_314 = _activated_data_e_act_z_iexp_saturated_T_313[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_316 = _activated_data_e_act_z_iexp_saturated_T_315[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_318 = _activated_data_e_act_z_iexp_saturated_T_317[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_319 = _activated_data_e_act_z_iexp_saturated_T_298 | _activated_data_e_act_z_iexp_saturated_T_300; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_320 = _activated_data_e_act_z_iexp_saturated_T_319 | _activated_data_e_act_z_iexp_saturated_T_302; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_321 = _activated_data_e_act_z_iexp_saturated_T_320 | _activated_data_e_act_z_iexp_saturated_T_304; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_322 = _activated_data_e_act_z_iexp_saturated_T_321 | _activated_data_e_act_z_iexp_saturated_T_306; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_323 = _activated_data_e_act_z_iexp_saturated_T_322 | _activated_data_e_act_z_iexp_saturated_T_308; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_324 = _activated_data_e_act_z_iexp_saturated_T_323 | _activated_data_e_act_z_iexp_saturated_T_310; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_325 = _activated_data_e_act_z_iexp_saturated_T_324 | _activated_data_e_act_z_iexp_saturated_T_312; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_326 = _activated_data_e_act_z_iexp_saturated_T_325 | _activated_data_e_act_z_iexp_saturated_T_314; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_327 = _activated_data_e_act_z_iexp_saturated_T_326 | _activated_data_e_act_z_iexp_saturated_T_316; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_328 = _activated_data_e_act_z_iexp_saturated_T_327 | _activated_data_e_act_z_iexp_saturated_T_318; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_329 = _activated_data_e_act_z_iexp_saturated_T_328 ? 32'h20 : activated_data_e_act_z_iexp_9; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_9 = _activated_data_e_act_z_iexp_saturated_T_329; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_45 = {{32{activated_data_e_act_z_iexp_9[31]}}, activated_data_e_act_z_iexp_9} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_46 = {_activated_data_e_act_qp_iexp_T_45[63], _activated_data_e_act_qp_iexp_T_45} + {{33{_activated_data_e_act_T_312[31]}}, _activated_data_e_act_T_312}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_47 = _activated_data_e_act_qp_iexp_T_46[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_48 = _activated_data_e_act_qp_iexp_T_47; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_49 = _activated_data_e_act_qp_iexp_T_48[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_9 = _activated_data_e_act_qp_iexp_T_49; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_48 = {activated_data_e_act_qp_iexp_9[31], activated_data_e_act_qp_iexp_9} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_99; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_99 = _GEN_48; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_102; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_102 = _GEN_48; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_100 = _activated_data_e_act_q_poly_iexp_T_99[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_101 = _activated_data_e_act_q_poly_iexp_T_100; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_103 = _activated_data_e_act_q_poly_iexp_T_102[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_104 = _activated_data_e_act_q_poly_iexp_T_103; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_105 = {{32{_activated_data_e_act_q_poly_iexp_T_101[31]}}, _activated_data_e_act_q_poly_iexp_T_101} * {{32{_activated_data_e_act_q_poly_iexp_T_104[31]}}, _activated_data_e_act_q_poly_iexp_T_104}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_106 = {_activated_data_e_act_q_poly_iexp_T_105[63], _activated_data_e_act_q_poly_iexp_T_105} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_107 = _activated_data_e_act_q_poly_iexp_T_106[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_108 = _activated_data_e_act_q_poly_iexp_T_107; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_109 = _activated_data_e_act_q_poly_iexp_T_108[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_9 = _activated_data_e_act_q_poly_iexp_T_109; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_313 = activated_data_e_act_q_poly_iexp_9; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_315 = _activated_data_e_act_T_313 >> _activated_data_e_act_T_314; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_316 = _activated_data_e_act_T_315; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_9 = _activated_data_e_act_T_316; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_318 = _activated_data_e_act_T_317; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_319 = _activated_data_e_act_T_318; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_9 = _activated_data_e_act_T_289 ? _activated_data_e_act_T_291 : _activated_data_e_act_T_319; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_9 = activated_data_e_act_9; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_107_bits = _activated_data_e_scaled_T_106_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_48 = _activated_data_e_scaled_T_107_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_108; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_108 = _activated_data_e_scaled_WIRE_48; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_47_bits = _activated_data_e_scaled_T_108; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_9 = _activated_data_e_scaled_WIRE_47_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_9_sign = activated_data_e_scaled_f_rec_rawIn_sign_9; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_9 = _activated_data_e_scaled_WIRE_47_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_9 = _activated_data_e_scaled_WIRE_47_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 = activated_data_e_scaled_f_rec_rawIn_expIn_9 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9 = activated_data_e_scaled_f_rec_rawIn_fractIn_9 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_396 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_397 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_398 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_399 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_400 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_401 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_402 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_403 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_404 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_405 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_406 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_407 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_408 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_409 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_410 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_411 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_412 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_413 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_414 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_415 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_416 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_417 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_418 = activated_data_e_scaled_f_rec_rawIn_fractIn_9[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_419 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_397 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_420 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_398 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_419; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_421 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_399 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_420; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_422 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_400 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_421; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_423 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_401 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_422; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_424 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_402 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_423; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_425 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_403 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_424; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_426 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_404 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_425; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_427 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_405 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_426; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_428 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_406 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_427; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_429 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_407 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_428; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_430 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_408 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_429; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_431 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_409 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_430; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_432 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_410 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_431; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_433 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_411 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_432; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_434 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_412 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_433; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_435 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_413 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_434; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_436 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_414 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_435; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_437 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_415 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_436; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_438 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_416 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_437; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_439 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_417 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_438; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_9 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_418 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_439; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_18 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_9} << activated_data_e_scaled_f_rec_rawIn_normDist_9; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_19 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_18[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_9 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_19, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_45 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_9}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_46 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_45 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_9}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_47 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_48 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_47}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_49 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_46} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_48}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_9 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_49[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_18 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_9; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_9 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_9_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_9 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_9[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_9 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_9; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_74 = activated_data_e_scaled_f_rec_rawIn_9_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_9_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_9_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_9_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_18 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_19 = activated_data_e_scaled_f_rec_rawIn_isSpecial_9 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_18; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_9_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_19; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_9 = activated_data_e_scaled_f_rec_rawIn_isSpecial_9 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_9; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_9_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_9; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_19 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_18}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_9_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_19; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_36 = ~activated_data_e_scaled_f_rec_rawIn_isZero_9; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_37 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_36}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_38 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_9 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_9 : activated_data_e_scaled_f_rec_rawIn_fractIn_9; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_39 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_37, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_38}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_9_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_39; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_72 = activated_data_e_scaled_f_rec_rawIn_9_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_73 = activated_data_e_scaled_f_rec_rawIn_9_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_72; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_75 = {_activated_data_e_scaled_f_rec_T_73[2:1], _activated_data_e_scaled_f_rec_T_73[0] | _activated_data_e_scaled_f_rec_T_74}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_76 = {activated_data_e_scaled_f_rec_rawIn_9_sign, _activated_data_e_scaled_f_rec_T_75}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_77 = activated_data_e_scaled_f_rec_rawIn_9_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_78 = {_activated_data_e_scaled_f_rec_T_76, _activated_data_e_scaled_f_rec_T_77}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_79 = activated_data_e_scaled_f_rec_rawIn_9_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_9 = {_activated_data_e_scaled_f_rec_T_78, _activated_data_e_scaled_f_rec_T_79}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_9 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_9; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_9 = _activated_data_e_scaled_rec_fn_to_in_9_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_9 = _activated_data_e_scaled_muladder_9_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_9 = activated_data_e_scaled_sign_exp_9[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_9 = _activated_data_e_scaled_sign_isZero_T_9 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_9_isZero = activated_data_e_scaled_sign_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_9 = activated_data_e_scaled_sign_exp_9[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_9 = &_activated_data_e_scaled_sign_isSpecial_T_9; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_29; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_9; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_9; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_39; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_9_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_9_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_9_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_9_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_9_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_18 = activated_data_e_scaled_sign_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_27 = activated_data_e_scaled_sign_exp_9[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_19 = activated_data_e_scaled_sign_isSpecial_9 & _activated_data_e_scaled_sign_out_isNaN_T_18; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_9_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_19; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_28 = ~_activated_data_e_scaled_sign_out_isInf_T_27; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_29 = activated_data_e_scaled_sign_isSpecial_9 & _activated_data_e_scaled_sign_out_isInf_T_28; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_9_isInf = _activated_data_e_scaled_sign_out_isInf_T_29; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_9 = _activated_data_e_scaled_muladder_9_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_9_sign = _activated_data_e_scaled_sign_out_sign_T_9; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_9 = {1'h0, activated_data_e_scaled_sign_exp_9}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_9_sExp = _activated_data_e_scaled_sign_out_sExp_T_9; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_36 = ~activated_data_e_scaled_sign_isZero_9; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_37 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_36}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_38 = _activated_data_e_scaled_muladder_9_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_39 = {_activated_data_e_scaled_sign_out_sig_T_37, _activated_data_e_scaled_sign_out_sig_T_38}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_9_sig = _activated_data_e_scaled_sign_out_sig_T_39; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_9 = activated_data_e_scaled_sign_out_9_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_109; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_49 = _activated_data_e_scaled_T_109; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_9 = activated_data_e_scaled_overflow_9 ? activated_data_e_scaled_sat_9 : _activated_data_e_scaled_WIRE_49; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_45 = $signed(activated_data_e_scaled_9) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_46 = $signed(activated_data_e_scaled_9) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_47 = _activated_data_e_clipped_T_46 ? 32'hFFFFFF80 : activated_data_e_scaled_9; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_48 = _activated_data_e_clipped_T_45 ? 32'h7F : _activated_data_e_clipped_T_47; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_49 = _activated_data_e_clipped_T_48[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_9 = _activated_data_e_clipped_T_49; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_9_0 = activated_data_e_clipped_9; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_9_0 = _activated_data_WIRE_9_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_321 = _activated_data_e_act_T_320; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_322 = $signed(io_in_bits_acc_read_resp_data_10_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_323 = _activated_data_e_act_T_322 ? io_in_bits_acc_read_resp_data_10_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_49 = {io_in_bits_acc_read_resp_data_10_0_0[31], io_in_bits_acc_read_resp_data_10_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_327; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_327 = _GEN_49; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_342; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_342 = _GEN_49; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_328 = _activated_data_e_act_T_327[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_329 = _activated_data_e_act_T_328; // @[Arithmetic.scala:95:38]
wire _GEN_50 = $signed(io_in_bits_acc_read_resp_data_10_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_40; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_40 = _GEN_50; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_40; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_40 = _GEN_50; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_10 = {_activated_data_e_act_q_sign_T_40, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_41 = 33'h0 - _GEN_49; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_42 = _activated_data_e_act_q_abs_T_41[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_43 = _activated_data_e_act_q_abs_T_42; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_10 = _activated_data_e_act_q_abs_T_40 ? _activated_data_e_act_q_abs_T_43 : io_in_bits_acc_read_resp_data_10_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_71 = _activated_data_e_act_q_clipped_T_70[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_72 = _activated_data_e_act_q_clipped_T_71; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_73 = $signed(activated_data_e_act_q_abs_10) > $signed(_activated_data_e_act_q_clipped_T_72); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_75 = _activated_data_e_act_q_clipped_T_74[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_76 = _activated_data_e_act_q_clipped_T_75; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_10 = _activated_data_e_act_q_clipped_T_73 ? _activated_data_e_act_q_clipped_T_76 : activated_data_e_act_q_abs_10; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_51 = {activated_data_e_act_q_clipped_10[31], activated_data_e_act_q_clipped_10} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_110; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_110 = _GEN_51; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_113; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_113 = _GEN_51; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_111 = _activated_data_e_act_q_poly_T_110[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_112 = _activated_data_e_act_q_poly_T_111; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_114 = _activated_data_e_act_q_poly_T_113[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_115 = _activated_data_e_act_q_poly_T_114; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_116 = {{32{_activated_data_e_act_q_poly_T_112[31]}}, _activated_data_e_act_q_poly_T_112} * {{32{_activated_data_e_act_q_poly_T_115[31]}}, _activated_data_e_act_q_poly_T_115}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_117 = {_activated_data_e_act_q_poly_T_116[63], _activated_data_e_act_q_poly_T_116} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_118 = _activated_data_e_act_q_poly_T_117[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_119 = _activated_data_e_act_q_poly_T_118; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_120 = _activated_data_e_act_q_poly_T_119[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_10 = _activated_data_e_act_q_poly_T_120; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_20 = {{32{activated_data_e_act_q_sign_10[1]}}, activated_data_e_act_q_sign_10} * {{2{activated_data_e_act_q_poly_10[31]}}, activated_data_e_act_q_poly_10}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_21 = _activated_data_e_act_q_erf_T_20[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_10 = _activated_data_e_act_q_erf_T_21; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_333 = {activated_data_e_act_q_erf_10[31], activated_data_e_act_q_erf_10} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_334 = _activated_data_e_act_T_333[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_335 = _activated_data_e_act_T_334; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_336 = {{32{io_in_bits_acc_read_resp_data_10_0_0[31]}}, io_in_bits_acc_read_resp_data_10_0_0} * {{32{_activated_data_e_act_T_335[31]}}, _activated_data_e_act_T_335}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_337 = _activated_data_e_act_T_336[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_338 = _activated_data_e_act_T_337; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_343 = _activated_data_e_act_T_342[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_344 = _activated_data_e_act_T_343; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_20 = 33'h0 - {_activated_data_e_act_T_344[31], _activated_data_e_act_T_344}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_21 = _activated_data_e_act_neg_q_iexp_T_20[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_10 = _activated_data_e_act_neg_q_iexp_T_21; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_40 = {{32{activated_data_e_act_neg_q_iexp_10[31]}}, activated_data_e_act_neg_q_iexp_10} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_41 = _activated_data_e_act_z_iexp_T_40; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_42 = _activated_data_e_act_z_iexp_T_41[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_43 = _activated_data_e_act_z_iexp_T_42; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_330 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_332 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_334 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_336 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_338 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_340 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_342 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_344 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_346 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_348 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_350 = activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_10 = _activated_data_e_act_z_iexp_T_43[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_362; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_10; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_346 = activated_data_e_act_z_iexp_saturated_10; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_331 = _activated_data_e_act_z_iexp_saturated_T_330[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_333 = _activated_data_e_act_z_iexp_saturated_T_332[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_335 = _activated_data_e_act_z_iexp_saturated_T_334[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_337 = _activated_data_e_act_z_iexp_saturated_T_336[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_339 = _activated_data_e_act_z_iexp_saturated_T_338[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_341 = _activated_data_e_act_z_iexp_saturated_T_340[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_343 = _activated_data_e_act_z_iexp_saturated_T_342[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_345 = _activated_data_e_act_z_iexp_saturated_T_344[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_347 = _activated_data_e_act_z_iexp_saturated_T_346[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_349 = _activated_data_e_act_z_iexp_saturated_T_348[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_351 = _activated_data_e_act_z_iexp_saturated_T_350[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_352 = _activated_data_e_act_z_iexp_saturated_T_331 | _activated_data_e_act_z_iexp_saturated_T_333; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_353 = _activated_data_e_act_z_iexp_saturated_T_352 | _activated_data_e_act_z_iexp_saturated_T_335; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_354 = _activated_data_e_act_z_iexp_saturated_T_353 | _activated_data_e_act_z_iexp_saturated_T_337; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_355 = _activated_data_e_act_z_iexp_saturated_T_354 | _activated_data_e_act_z_iexp_saturated_T_339; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_356 = _activated_data_e_act_z_iexp_saturated_T_355 | _activated_data_e_act_z_iexp_saturated_T_341; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_357 = _activated_data_e_act_z_iexp_saturated_T_356 | _activated_data_e_act_z_iexp_saturated_T_343; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_358 = _activated_data_e_act_z_iexp_saturated_T_357 | _activated_data_e_act_z_iexp_saturated_T_345; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_359 = _activated_data_e_act_z_iexp_saturated_T_358 | _activated_data_e_act_z_iexp_saturated_T_347; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_360 = _activated_data_e_act_z_iexp_saturated_T_359 | _activated_data_e_act_z_iexp_saturated_T_349; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_361 = _activated_data_e_act_z_iexp_saturated_T_360 | _activated_data_e_act_z_iexp_saturated_T_351; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_362 = _activated_data_e_act_z_iexp_saturated_T_361 ? 32'h20 : activated_data_e_act_z_iexp_10; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_10 = _activated_data_e_act_z_iexp_saturated_T_362; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_50 = {{32{activated_data_e_act_z_iexp_10[31]}}, activated_data_e_act_z_iexp_10} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_51 = {_activated_data_e_act_qp_iexp_T_50[63], _activated_data_e_act_qp_iexp_T_50} + {{33{_activated_data_e_act_T_344[31]}}, _activated_data_e_act_T_344}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_52 = _activated_data_e_act_qp_iexp_T_51[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_53 = _activated_data_e_act_qp_iexp_T_52; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_54 = _activated_data_e_act_qp_iexp_T_53[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_10 = _activated_data_e_act_qp_iexp_T_54; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_52 = {activated_data_e_act_qp_iexp_10[31], activated_data_e_act_qp_iexp_10} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_110; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_110 = _GEN_52; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_113; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_113 = _GEN_52; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_111 = _activated_data_e_act_q_poly_iexp_T_110[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_112 = _activated_data_e_act_q_poly_iexp_T_111; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_114 = _activated_data_e_act_q_poly_iexp_T_113[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_115 = _activated_data_e_act_q_poly_iexp_T_114; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_116 = {{32{_activated_data_e_act_q_poly_iexp_T_112[31]}}, _activated_data_e_act_q_poly_iexp_T_112} * {{32{_activated_data_e_act_q_poly_iexp_T_115[31]}}, _activated_data_e_act_q_poly_iexp_T_115}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_117 = {_activated_data_e_act_q_poly_iexp_T_116[63], _activated_data_e_act_q_poly_iexp_T_116} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_118 = _activated_data_e_act_q_poly_iexp_T_117[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_119 = _activated_data_e_act_q_poly_iexp_T_118; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_120 = _activated_data_e_act_q_poly_iexp_T_119[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_10 = _activated_data_e_act_q_poly_iexp_T_120; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_345 = activated_data_e_act_q_poly_iexp_10; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_347 = _activated_data_e_act_T_345 >> _activated_data_e_act_T_346; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_348 = _activated_data_e_act_T_347; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_10 = _activated_data_e_act_T_348; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_350 = _activated_data_e_act_T_349; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_351 = _activated_data_e_act_T_350; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_10 = _activated_data_e_act_T_321 ? _activated_data_e_act_T_323 : _activated_data_e_act_T_351; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_10 = activated_data_e_act_10; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_118_bits = _activated_data_e_scaled_T_117_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_53 = _activated_data_e_scaled_T_118_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_119; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_119 = _activated_data_e_scaled_WIRE_53; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_52_bits = _activated_data_e_scaled_T_119; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_10 = _activated_data_e_scaled_WIRE_52_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_10_sign = activated_data_e_scaled_f_rec_rawIn_sign_10; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_10 = _activated_data_e_scaled_WIRE_52_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_10 = _activated_data_e_scaled_WIRE_52_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 = activated_data_e_scaled_f_rec_rawIn_expIn_10 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10 = activated_data_e_scaled_f_rec_rawIn_fractIn_10 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_440 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_441 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_442 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_443 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_444 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_445 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_446 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_447 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_448 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_449 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_450 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_451 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_452 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_453 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_454 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_455 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_456 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_457 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_458 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_459 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_460 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_461 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_462 = activated_data_e_scaled_f_rec_rawIn_fractIn_10[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_463 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_441 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_464 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_442 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_463; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_465 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_443 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_464; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_466 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_444 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_465; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_467 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_445 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_466; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_468 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_446 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_467; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_469 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_447 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_468; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_470 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_448 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_469; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_471 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_449 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_470; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_472 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_450 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_471; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_473 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_451 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_472; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_474 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_452 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_473; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_475 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_453 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_474; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_476 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_454 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_475; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_477 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_455 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_476; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_478 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_456 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_477; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_479 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_457 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_478; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_480 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_458 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_479; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_481 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_459 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_480; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_482 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_460 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_481; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_483 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_461 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_482; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_10 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_462 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_483; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_20 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_10} << activated_data_e_scaled_f_rec_rawIn_normDist_10; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_21 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_20[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_10 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_21, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_50 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_10}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_51 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_50 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_10}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_52 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_53 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_52}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_54 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_51} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_53}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_10 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_54[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_20 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_10; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_10 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_10_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_10 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_10[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_10 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_10; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_82 = activated_data_e_scaled_f_rec_rawIn_10_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_10_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_10_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_10_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_20 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_21 = activated_data_e_scaled_f_rec_rawIn_isSpecial_10 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_20; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_10_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_21; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_10 = activated_data_e_scaled_f_rec_rawIn_isSpecial_10 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_10; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_10_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_10; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_21 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_20}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_10_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_21; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_40 = ~activated_data_e_scaled_f_rec_rawIn_isZero_10; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_41 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_40}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_42 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_10 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_10 : activated_data_e_scaled_f_rec_rawIn_fractIn_10; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_43 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_41, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_42}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_10_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_43; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_80 = activated_data_e_scaled_f_rec_rawIn_10_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_81 = activated_data_e_scaled_f_rec_rawIn_10_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_80; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_83 = {_activated_data_e_scaled_f_rec_T_81[2:1], _activated_data_e_scaled_f_rec_T_81[0] | _activated_data_e_scaled_f_rec_T_82}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_84 = {activated_data_e_scaled_f_rec_rawIn_10_sign, _activated_data_e_scaled_f_rec_T_83}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_85 = activated_data_e_scaled_f_rec_rawIn_10_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_86 = {_activated_data_e_scaled_f_rec_T_84, _activated_data_e_scaled_f_rec_T_85}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_87 = activated_data_e_scaled_f_rec_rawIn_10_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_10 = {_activated_data_e_scaled_f_rec_T_86, _activated_data_e_scaled_f_rec_T_87}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_10 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_10; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_10 = _activated_data_e_scaled_rec_fn_to_in_10_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_10 = _activated_data_e_scaled_muladder_10_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_10 = activated_data_e_scaled_sign_exp_10[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_10 = _activated_data_e_scaled_sign_isZero_T_10 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_10_isZero = activated_data_e_scaled_sign_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_10 = activated_data_e_scaled_sign_exp_10[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_10 = &_activated_data_e_scaled_sign_isSpecial_T_10; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_32; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_10; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_10; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_43; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_10_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_10_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_10_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_10_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_10_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_20 = activated_data_e_scaled_sign_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_30 = activated_data_e_scaled_sign_exp_10[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_21 = activated_data_e_scaled_sign_isSpecial_10 & _activated_data_e_scaled_sign_out_isNaN_T_20; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_10_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_21; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_31 = ~_activated_data_e_scaled_sign_out_isInf_T_30; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_32 = activated_data_e_scaled_sign_isSpecial_10 & _activated_data_e_scaled_sign_out_isInf_T_31; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_10_isInf = _activated_data_e_scaled_sign_out_isInf_T_32; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_10 = _activated_data_e_scaled_muladder_10_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_10_sign = _activated_data_e_scaled_sign_out_sign_T_10; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_10 = {1'h0, activated_data_e_scaled_sign_exp_10}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_10_sExp = _activated_data_e_scaled_sign_out_sExp_T_10; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_40 = ~activated_data_e_scaled_sign_isZero_10; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_41 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_40}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_42 = _activated_data_e_scaled_muladder_10_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_43 = {_activated_data_e_scaled_sign_out_sig_T_41, _activated_data_e_scaled_sign_out_sig_T_42}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_10_sig = _activated_data_e_scaled_sign_out_sig_T_43; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_10 = activated_data_e_scaled_sign_out_10_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_120; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_54 = _activated_data_e_scaled_T_120; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_10 = activated_data_e_scaled_overflow_10 ? activated_data_e_scaled_sat_10 : _activated_data_e_scaled_WIRE_54; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_50 = $signed(activated_data_e_scaled_10) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_51 = $signed(activated_data_e_scaled_10) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_52 = _activated_data_e_clipped_T_51 ? 32'hFFFFFF80 : activated_data_e_scaled_10; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_53 = _activated_data_e_clipped_T_50 ? 32'h7F : _activated_data_e_clipped_T_52; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_54 = _activated_data_e_clipped_T_53[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_10 = _activated_data_e_clipped_T_54; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_10_0 = activated_data_e_clipped_10; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_10_0 = _activated_data_WIRE_10_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_353 = _activated_data_e_act_T_352; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_354 = $signed(io_in_bits_acc_read_resp_data_11_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_355 = _activated_data_e_act_T_354 ? io_in_bits_acc_read_resp_data_11_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_53 = {io_in_bits_acc_read_resp_data_11_0_0[31], io_in_bits_acc_read_resp_data_11_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_359; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_359 = _GEN_53; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_374; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_374 = _GEN_53; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_360 = _activated_data_e_act_T_359[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_361 = _activated_data_e_act_T_360; // @[Arithmetic.scala:95:38]
wire _GEN_54 = $signed(io_in_bits_acc_read_resp_data_11_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_44; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_44 = _GEN_54; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_44; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_44 = _GEN_54; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_11 = {_activated_data_e_act_q_sign_T_44, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_45 = 33'h0 - _GEN_53; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_46 = _activated_data_e_act_q_abs_T_45[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_47 = _activated_data_e_act_q_abs_T_46; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_11 = _activated_data_e_act_q_abs_T_44 ? _activated_data_e_act_q_abs_T_47 : io_in_bits_acc_read_resp_data_11_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_78 = _activated_data_e_act_q_clipped_T_77[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_79 = _activated_data_e_act_q_clipped_T_78; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_80 = $signed(activated_data_e_act_q_abs_11) > $signed(_activated_data_e_act_q_clipped_T_79); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_82 = _activated_data_e_act_q_clipped_T_81[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_83 = _activated_data_e_act_q_clipped_T_82; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_11 = _activated_data_e_act_q_clipped_T_80 ? _activated_data_e_act_q_clipped_T_83 : activated_data_e_act_q_abs_11; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_55 = {activated_data_e_act_q_clipped_11[31], activated_data_e_act_q_clipped_11} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_121; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_121 = _GEN_55; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_124; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_124 = _GEN_55; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_122 = _activated_data_e_act_q_poly_T_121[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_123 = _activated_data_e_act_q_poly_T_122; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_125 = _activated_data_e_act_q_poly_T_124[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_126 = _activated_data_e_act_q_poly_T_125; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_127 = {{32{_activated_data_e_act_q_poly_T_123[31]}}, _activated_data_e_act_q_poly_T_123} * {{32{_activated_data_e_act_q_poly_T_126[31]}}, _activated_data_e_act_q_poly_T_126}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_128 = {_activated_data_e_act_q_poly_T_127[63], _activated_data_e_act_q_poly_T_127} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_129 = _activated_data_e_act_q_poly_T_128[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_130 = _activated_data_e_act_q_poly_T_129; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_131 = _activated_data_e_act_q_poly_T_130[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_11 = _activated_data_e_act_q_poly_T_131; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_22 = {{32{activated_data_e_act_q_sign_11[1]}}, activated_data_e_act_q_sign_11} * {{2{activated_data_e_act_q_poly_11[31]}}, activated_data_e_act_q_poly_11}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_23 = _activated_data_e_act_q_erf_T_22[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_11 = _activated_data_e_act_q_erf_T_23; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_365 = {activated_data_e_act_q_erf_11[31], activated_data_e_act_q_erf_11} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_366 = _activated_data_e_act_T_365[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_367 = _activated_data_e_act_T_366; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_368 = {{32{io_in_bits_acc_read_resp_data_11_0_0[31]}}, io_in_bits_acc_read_resp_data_11_0_0} * {{32{_activated_data_e_act_T_367[31]}}, _activated_data_e_act_T_367}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_369 = _activated_data_e_act_T_368[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_370 = _activated_data_e_act_T_369; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_375 = _activated_data_e_act_T_374[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_376 = _activated_data_e_act_T_375; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_22 = 33'h0 - {_activated_data_e_act_T_376[31], _activated_data_e_act_T_376}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_23 = _activated_data_e_act_neg_q_iexp_T_22[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_11 = _activated_data_e_act_neg_q_iexp_T_23; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_44 = {{32{activated_data_e_act_neg_q_iexp_11[31]}}, activated_data_e_act_neg_q_iexp_11} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_45 = _activated_data_e_act_z_iexp_T_44; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_46 = _activated_data_e_act_z_iexp_T_45[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_47 = _activated_data_e_act_z_iexp_T_46; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_363 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_365 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_367 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_369 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_371 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_373 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_375 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_377 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_379 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_381 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_383 = activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_11 = _activated_data_e_act_z_iexp_T_47[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_395; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_11; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_378 = activated_data_e_act_z_iexp_saturated_11; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_364 = _activated_data_e_act_z_iexp_saturated_T_363[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_366 = _activated_data_e_act_z_iexp_saturated_T_365[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_368 = _activated_data_e_act_z_iexp_saturated_T_367[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_370 = _activated_data_e_act_z_iexp_saturated_T_369[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_372 = _activated_data_e_act_z_iexp_saturated_T_371[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_374 = _activated_data_e_act_z_iexp_saturated_T_373[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_376 = _activated_data_e_act_z_iexp_saturated_T_375[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_378 = _activated_data_e_act_z_iexp_saturated_T_377[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_380 = _activated_data_e_act_z_iexp_saturated_T_379[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_382 = _activated_data_e_act_z_iexp_saturated_T_381[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_384 = _activated_data_e_act_z_iexp_saturated_T_383[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_385 = _activated_data_e_act_z_iexp_saturated_T_364 | _activated_data_e_act_z_iexp_saturated_T_366; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_386 = _activated_data_e_act_z_iexp_saturated_T_385 | _activated_data_e_act_z_iexp_saturated_T_368; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_387 = _activated_data_e_act_z_iexp_saturated_T_386 | _activated_data_e_act_z_iexp_saturated_T_370; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_388 = _activated_data_e_act_z_iexp_saturated_T_387 | _activated_data_e_act_z_iexp_saturated_T_372; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_389 = _activated_data_e_act_z_iexp_saturated_T_388 | _activated_data_e_act_z_iexp_saturated_T_374; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_390 = _activated_data_e_act_z_iexp_saturated_T_389 | _activated_data_e_act_z_iexp_saturated_T_376; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_391 = _activated_data_e_act_z_iexp_saturated_T_390 | _activated_data_e_act_z_iexp_saturated_T_378; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_392 = _activated_data_e_act_z_iexp_saturated_T_391 | _activated_data_e_act_z_iexp_saturated_T_380; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_393 = _activated_data_e_act_z_iexp_saturated_T_392 | _activated_data_e_act_z_iexp_saturated_T_382; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_394 = _activated_data_e_act_z_iexp_saturated_T_393 | _activated_data_e_act_z_iexp_saturated_T_384; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_395 = _activated_data_e_act_z_iexp_saturated_T_394 ? 32'h20 : activated_data_e_act_z_iexp_11; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_11 = _activated_data_e_act_z_iexp_saturated_T_395; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_55 = {{32{activated_data_e_act_z_iexp_11[31]}}, activated_data_e_act_z_iexp_11} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_56 = {_activated_data_e_act_qp_iexp_T_55[63], _activated_data_e_act_qp_iexp_T_55} + {{33{_activated_data_e_act_T_376[31]}}, _activated_data_e_act_T_376}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_57 = _activated_data_e_act_qp_iexp_T_56[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_58 = _activated_data_e_act_qp_iexp_T_57; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_59 = _activated_data_e_act_qp_iexp_T_58[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_11 = _activated_data_e_act_qp_iexp_T_59; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_56 = {activated_data_e_act_qp_iexp_11[31], activated_data_e_act_qp_iexp_11} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_121; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_121 = _GEN_56; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_124; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_124 = _GEN_56; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_122 = _activated_data_e_act_q_poly_iexp_T_121[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_123 = _activated_data_e_act_q_poly_iexp_T_122; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_125 = _activated_data_e_act_q_poly_iexp_T_124[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_126 = _activated_data_e_act_q_poly_iexp_T_125; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_127 = {{32{_activated_data_e_act_q_poly_iexp_T_123[31]}}, _activated_data_e_act_q_poly_iexp_T_123} * {{32{_activated_data_e_act_q_poly_iexp_T_126[31]}}, _activated_data_e_act_q_poly_iexp_T_126}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_128 = {_activated_data_e_act_q_poly_iexp_T_127[63], _activated_data_e_act_q_poly_iexp_T_127} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_129 = _activated_data_e_act_q_poly_iexp_T_128[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_130 = _activated_data_e_act_q_poly_iexp_T_129; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_131 = _activated_data_e_act_q_poly_iexp_T_130[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_11 = _activated_data_e_act_q_poly_iexp_T_131; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_377 = activated_data_e_act_q_poly_iexp_11; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_379 = _activated_data_e_act_T_377 >> _activated_data_e_act_T_378; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_380 = _activated_data_e_act_T_379; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_11 = _activated_data_e_act_T_380; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_382 = _activated_data_e_act_T_381; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_383 = _activated_data_e_act_T_382; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_11 = _activated_data_e_act_T_353 ? _activated_data_e_act_T_355 : _activated_data_e_act_T_383; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_11 = activated_data_e_act_11; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_129_bits = _activated_data_e_scaled_T_128_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_58 = _activated_data_e_scaled_T_129_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_130; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_130 = _activated_data_e_scaled_WIRE_58; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_57_bits = _activated_data_e_scaled_T_130; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_11 = _activated_data_e_scaled_WIRE_57_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_11_sign = activated_data_e_scaled_f_rec_rawIn_sign_11; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_11 = _activated_data_e_scaled_WIRE_57_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_11 = _activated_data_e_scaled_WIRE_57_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 = activated_data_e_scaled_f_rec_rawIn_expIn_11 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11 = activated_data_e_scaled_f_rec_rawIn_fractIn_11 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_484 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_485 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_486 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_487 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_488 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_489 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_490 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_491 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_492 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_493 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_494 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_495 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_496 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_497 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_498 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_499 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_500 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_501 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_502 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_503 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_504 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_505 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_506 = activated_data_e_scaled_f_rec_rawIn_fractIn_11[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_507 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_485 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_508 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_486 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_507; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_509 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_487 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_508; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_510 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_488 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_509; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_511 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_489 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_510; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_512 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_490 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_511; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_513 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_491 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_512; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_514 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_492 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_513; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_515 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_493 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_514; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_516 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_494 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_515; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_517 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_495 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_516; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_518 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_496 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_517; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_519 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_497 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_518; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_520 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_498 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_519; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_521 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_499 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_520; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_522 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_500 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_521; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_523 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_501 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_522; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_524 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_502 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_523; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_525 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_503 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_524; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_526 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_504 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_525; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_527 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_505 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_526; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_11 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_506 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_527; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_22 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_11} << activated_data_e_scaled_f_rec_rawIn_normDist_11; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_23 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_22[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_11 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_23, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_55 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_11}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_56 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_55 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_11}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_57 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_58 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_57}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_59 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_56} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_58}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_11 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_59[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_22 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_11; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_11 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_11_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_11 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_11[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_11 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_11; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_90 = activated_data_e_scaled_f_rec_rawIn_11_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_11_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_11_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_11_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_22 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_23 = activated_data_e_scaled_f_rec_rawIn_isSpecial_11 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_22; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_11_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_23; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_11 = activated_data_e_scaled_f_rec_rawIn_isSpecial_11 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_11; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_11_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_11; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_23 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_22}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_11_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_23; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_44 = ~activated_data_e_scaled_f_rec_rawIn_isZero_11; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_45 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_44}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_46 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_11 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_11 : activated_data_e_scaled_f_rec_rawIn_fractIn_11; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_47 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_45, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_46}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_11_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_47; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_88 = activated_data_e_scaled_f_rec_rawIn_11_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_89 = activated_data_e_scaled_f_rec_rawIn_11_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_88; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_91 = {_activated_data_e_scaled_f_rec_T_89[2:1], _activated_data_e_scaled_f_rec_T_89[0] | _activated_data_e_scaled_f_rec_T_90}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_92 = {activated_data_e_scaled_f_rec_rawIn_11_sign, _activated_data_e_scaled_f_rec_T_91}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_93 = activated_data_e_scaled_f_rec_rawIn_11_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_94 = {_activated_data_e_scaled_f_rec_T_92, _activated_data_e_scaled_f_rec_T_93}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_95 = activated_data_e_scaled_f_rec_rawIn_11_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_11 = {_activated_data_e_scaled_f_rec_T_94, _activated_data_e_scaled_f_rec_T_95}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_11 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_11; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_11 = _activated_data_e_scaled_rec_fn_to_in_11_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_11 = _activated_data_e_scaled_muladder_11_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_11 = activated_data_e_scaled_sign_exp_11[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_11 = _activated_data_e_scaled_sign_isZero_T_11 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_11_isZero = activated_data_e_scaled_sign_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_11 = activated_data_e_scaled_sign_exp_11[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_11 = &_activated_data_e_scaled_sign_isSpecial_T_11; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_35; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_11; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_11; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_47; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_11_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_11_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_11_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_11_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_11_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_22 = activated_data_e_scaled_sign_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_33 = activated_data_e_scaled_sign_exp_11[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_23 = activated_data_e_scaled_sign_isSpecial_11 & _activated_data_e_scaled_sign_out_isNaN_T_22; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_11_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_23; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_34 = ~_activated_data_e_scaled_sign_out_isInf_T_33; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_35 = activated_data_e_scaled_sign_isSpecial_11 & _activated_data_e_scaled_sign_out_isInf_T_34; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_11_isInf = _activated_data_e_scaled_sign_out_isInf_T_35; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_11 = _activated_data_e_scaled_muladder_11_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_11_sign = _activated_data_e_scaled_sign_out_sign_T_11; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_11 = {1'h0, activated_data_e_scaled_sign_exp_11}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_11_sExp = _activated_data_e_scaled_sign_out_sExp_T_11; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_44 = ~activated_data_e_scaled_sign_isZero_11; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_45 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_44}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_46 = _activated_data_e_scaled_muladder_11_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_47 = {_activated_data_e_scaled_sign_out_sig_T_45, _activated_data_e_scaled_sign_out_sig_T_46}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_11_sig = _activated_data_e_scaled_sign_out_sig_T_47; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_11 = activated_data_e_scaled_sign_out_11_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_131; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_59 = _activated_data_e_scaled_T_131; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_11 = activated_data_e_scaled_overflow_11 ? activated_data_e_scaled_sat_11 : _activated_data_e_scaled_WIRE_59; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_55 = $signed(activated_data_e_scaled_11) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_56 = $signed(activated_data_e_scaled_11) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_57 = _activated_data_e_clipped_T_56 ? 32'hFFFFFF80 : activated_data_e_scaled_11; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_58 = _activated_data_e_clipped_T_55 ? 32'h7F : _activated_data_e_clipped_T_57; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_59 = _activated_data_e_clipped_T_58[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_11 = _activated_data_e_clipped_T_59; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_11_0 = activated_data_e_clipped_11; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_11_0 = _activated_data_WIRE_11_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_385 = _activated_data_e_act_T_384; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_386 = $signed(io_in_bits_acc_read_resp_data_12_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_387 = _activated_data_e_act_T_386 ? io_in_bits_acc_read_resp_data_12_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_57 = {io_in_bits_acc_read_resp_data_12_0_0[31], io_in_bits_acc_read_resp_data_12_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_391; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_391 = _GEN_57; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_406; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_406 = _GEN_57; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_392 = _activated_data_e_act_T_391[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_393 = _activated_data_e_act_T_392; // @[Arithmetic.scala:95:38]
wire _GEN_58 = $signed(io_in_bits_acc_read_resp_data_12_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_48; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_48 = _GEN_58; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_48; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_48 = _GEN_58; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_12 = {_activated_data_e_act_q_sign_T_48, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_49 = 33'h0 - _GEN_57; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_50 = _activated_data_e_act_q_abs_T_49[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_51 = _activated_data_e_act_q_abs_T_50; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_12 = _activated_data_e_act_q_abs_T_48 ? _activated_data_e_act_q_abs_T_51 : io_in_bits_acc_read_resp_data_12_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_85 = _activated_data_e_act_q_clipped_T_84[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_86 = _activated_data_e_act_q_clipped_T_85; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_87 = $signed(activated_data_e_act_q_abs_12) > $signed(_activated_data_e_act_q_clipped_T_86); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_89 = _activated_data_e_act_q_clipped_T_88[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_90 = _activated_data_e_act_q_clipped_T_89; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_12 = _activated_data_e_act_q_clipped_T_87 ? _activated_data_e_act_q_clipped_T_90 : activated_data_e_act_q_abs_12; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_59 = {activated_data_e_act_q_clipped_12[31], activated_data_e_act_q_clipped_12} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_132; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_132 = _GEN_59; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_135; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_135 = _GEN_59; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_133 = _activated_data_e_act_q_poly_T_132[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_134 = _activated_data_e_act_q_poly_T_133; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_136 = _activated_data_e_act_q_poly_T_135[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_137 = _activated_data_e_act_q_poly_T_136; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_138 = {{32{_activated_data_e_act_q_poly_T_134[31]}}, _activated_data_e_act_q_poly_T_134} * {{32{_activated_data_e_act_q_poly_T_137[31]}}, _activated_data_e_act_q_poly_T_137}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_139 = {_activated_data_e_act_q_poly_T_138[63], _activated_data_e_act_q_poly_T_138} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_140 = _activated_data_e_act_q_poly_T_139[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_141 = _activated_data_e_act_q_poly_T_140; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_142 = _activated_data_e_act_q_poly_T_141[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_12 = _activated_data_e_act_q_poly_T_142; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_24 = {{32{activated_data_e_act_q_sign_12[1]}}, activated_data_e_act_q_sign_12} * {{2{activated_data_e_act_q_poly_12[31]}}, activated_data_e_act_q_poly_12}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_25 = _activated_data_e_act_q_erf_T_24[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_12 = _activated_data_e_act_q_erf_T_25; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_397 = {activated_data_e_act_q_erf_12[31], activated_data_e_act_q_erf_12} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_398 = _activated_data_e_act_T_397[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_399 = _activated_data_e_act_T_398; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_400 = {{32{io_in_bits_acc_read_resp_data_12_0_0[31]}}, io_in_bits_acc_read_resp_data_12_0_0} * {{32{_activated_data_e_act_T_399[31]}}, _activated_data_e_act_T_399}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_401 = _activated_data_e_act_T_400[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_402 = _activated_data_e_act_T_401; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_407 = _activated_data_e_act_T_406[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_408 = _activated_data_e_act_T_407; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_24 = 33'h0 - {_activated_data_e_act_T_408[31], _activated_data_e_act_T_408}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_25 = _activated_data_e_act_neg_q_iexp_T_24[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_12 = _activated_data_e_act_neg_q_iexp_T_25; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_48 = {{32{activated_data_e_act_neg_q_iexp_12[31]}}, activated_data_e_act_neg_q_iexp_12} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_49 = _activated_data_e_act_z_iexp_T_48; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_50 = _activated_data_e_act_z_iexp_T_49[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_51 = _activated_data_e_act_z_iexp_T_50; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_396 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_398 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_400 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_402 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_404 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_406 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_408 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_410 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_412 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_414 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_416 = activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_12 = _activated_data_e_act_z_iexp_T_51[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_428; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_12; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_410 = activated_data_e_act_z_iexp_saturated_12; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_397 = _activated_data_e_act_z_iexp_saturated_T_396[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_399 = _activated_data_e_act_z_iexp_saturated_T_398[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_401 = _activated_data_e_act_z_iexp_saturated_T_400[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_403 = _activated_data_e_act_z_iexp_saturated_T_402[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_405 = _activated_data_e_act_z_iexp_saturated_T_404[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_407 = _activated_data_e_act_z_iexp_saturated_T_406[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_409 = _activated_data_e_act_z_iexp_saturated_T_408[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_411 = _activated_data_e_act_z_iexp_saturated_T_410[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_413 = _activated_data_e_act_z_iexp_saturated_T_412[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_415 = _activated_data_e_act_z_iexp_saturated_T_414[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_417 = _activated_data_e_act_z_iexp_saturated_T_416[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_418 = _activated_data_e_act_z_iexp_saturated_T_397 | _activated_data_e_act_z_iexp_saturated_T_399; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_419 = _activated_data_e_act_z_iexp_saturated_T_418 | _activated_data_e_act_z_iexp_saturated_T_401; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_420 = _activated_data_e_act_z_iexp_saturated_T_419 | _activated_data_e_act_z_iexp_saturated_T_403; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_421 = _activated_data_e_act_z_iexp_saturated_T_420 | _activated_data_e_act_z_iexp_saturated_T_405; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_422 = _activated_data_e_act_z_iexp_saturated_T_421 | _activated_data_e_act_z_iexp_saturated_T_407; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_423 = _activated_data_e_act_z_iexp_saturated_T_422 | _activated_data_e_act_z_iexp_saturated_T_409; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_424 = _activated_data_e_act_z_iexp_saturated_T_423 | _activated_data_e_act_z_iexp_saturated_T_411; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_425 = _activated_data_e_act_z_iexp_saturated_T_424 | _activated_data_e_act_z_iexp_saturated_T_413; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_426 = _activated_data_e_act_z_iexp_saturated_T_425 | _activated_data_e_act_z_iexp_saturated_T_415; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_427 = _activated_data_e_act_z_iexp_saturated_T_426 | _activated_data_e_act_z_iexp_saturated_T_417; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_428 = _activated_data_e_act_z_iexp_saturated_T_427 ? 32'h20 : activated_data_e_act_z_iexp_12; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_12 = _activated_data_e_act_z_iexp_saturated_T_428; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_60 = {{32{activated_data_e_act_z_iexp_12[31]}}, activated_data_e_act_z_iexp_12} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_61 = {_activated_data_e_act_qp_iexp_T_60[63], _activated_data_e_act_qp_iexp_T_60} + {{33{_activated_data_e_act_T_408[31]}}, _activated_data_e_act_T_408}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_62 = _activated_data_e_act_qp_iexp_T_61[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_63 = _activated_data_e_act_qp_iexp_T_62; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_64 = _activated_data_e_act_qp_iexp_T_63[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_12 = _activated_data_e_act_qp_iexp_T_64; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_60 = {activated_data_e_act_qp_iexp_12[31], activated_data_e_act_qp_iexp_12} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_132; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_132 = _GEN_60; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_135; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_135 = _GEN_60; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_133 = _activated_data_e_act_q_poly_iexp_T_132[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_134 = _activated_data_e_act_q_poly_iexp_T_133; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_136 = _activated_data_e_act_q_poly_iexp_T_135[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_137 = _activated_data_e_act_q_poly_iexp_T_136; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_138 = {{32{_activated_data_e_act_q_poly_iexp_T_134[31]}}, _activated_data_e_act_q_poly_iexp_T_134} * {{32{_activated_data_e_act_q_poly_iexp_T_137[31]}}, _activated_data_e_act_q_poly_iexp_T_137}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_139 = {_activated_data_e_act_q_poly_iexp_T_138[63], _activated_data_e_act_q_poly_iexp_T_138} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_140 = _activated_data_e_act_q_poly_iexp_T_139[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_141 = _activated_data_e_act_q_poly_iexp_T_140; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_142 = _activated_data_e_act_q_poly_iexp_T_141[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_12 = _activated_data_e_act_q_poly_iexp_T_142; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_409 = activated_data_e_act_q_poly_iexp_12; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_411 = _activated_data_e_act_T_409 >> _activated_data_e_act_T_410; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_412 = _activated_data_e_act_T_411; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_12 = _activated_data_e_act_T_412; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_414 = _activated_data_e_act_T_413; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_415 = _activated_data_e_act_T_414; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_12 = _activated_data_e_act_T_385 ? _activated_data_e_act_T_387 : _activated_data_e_act_T_415; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_12 = activated_data_e_act_12; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_140_bits = _activated_data_e_scaled_T_139_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_63 = _activated_data_e_scaled_T_140_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_141; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_141 = _activated_data_e_scaled_WIRE_63; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_62_bits = _activated_data_e_scaled_T_141; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_12 = _activated_data_e_scaled_WIRE_62_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_12_sign = activated_data_e_scaled_f_rec_rawIn_sign_12; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_12 = _activated_data_e_scaled_WIRE_62_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_12 = _activated_data_e_scaled_WIRE_62_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 = activated_data_e_scaled_f_rec_rawIn_expIn_12 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12 = activated_data_e_scaled_f_rec_rawIn_fractIn_12 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_528 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_529 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_530 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_531 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_532 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_533 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_534 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_535 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_536 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_537 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_538 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_539 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_540 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_541 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_542 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_543 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_544 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_545 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_546 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_547 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_548 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_549 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_550 = activated_data_e_scaled_f_rec_rawIn_fractIn_12[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_551 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_529 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_552 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_530 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_551; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_553 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_531 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_552; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_554 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_532 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_553; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_555 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_533 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_554; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_556 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_534 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_555; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_557 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_535 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_556; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_558 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_536 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_557; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_559 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_537 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_558; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_560 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_538 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_559; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_561 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_539 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_560; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_562 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_540 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_561; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_563 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_541 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_562; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_564 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_542 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_563; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_565 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_543 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_564; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_566 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_544 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_565; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_567 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_545 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_566; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_568 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_546 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_567; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_569 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_547 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_568; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_570 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_548 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_569; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_571 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_549 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_570; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_12 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_550 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_571; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_24 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_12} << activated_data_e_scaled_f_rec_rawIn_normDist_12; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_25 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_24[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_12 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_25, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_60 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_12}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_61 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_60 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_12}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_62 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_63 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_62}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_64 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_61} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_63}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_12 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_64[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_24 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_12; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_12 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_12_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_12 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_12[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_12 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_12; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_98 = activated_data_e_scaled_f_rec_rawIn_12_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_12_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_12_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_12_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_24 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_25 = activated_data_e_scaled_f_rec_rawIn_isSpecial_12 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_24; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_12_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_25; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_12 = activated_data_e_scaled_f_rec_rawIn_isSpecial_12 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_12; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_12_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_12; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_25 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_24}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_12_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_25; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_48 = ~activated_data_e_scaled_f_rec_rawIn_isZero_12; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_49 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_48}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_50 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_12 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_12 : activated_data_e_scaled_f_rec_rawIn_fractIn_12; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_51 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_49, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_50}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_12_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_51; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_96 = activated_data_e_scaled_f_rec_rawIn_12_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_97 = activated_data_e_scaled_f_rec_rawIn_12_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_96; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_99 = {_activated_data_e_scaled_f_rec_T_97[2:1], _activated_data_e_scaled_f_rec_T_97[0] | _activated_data_e_scaled_f_rec_T_98}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_100 = {activated_data_e_scaled_f_rec_rawIn_12_sign, _activated_data_e_scaled_f_rec_T_99}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_101 = activated_data_e_scaled_f_rec_rawIn_12_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_102 = {_activated_data_e_scaled_f_rec_T_100, _activated_data_e_scaled_f_rec_T_101}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_103 = activated_data_e_scaled_f_rec_rawIn_12_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_12 = {_activated_data_e_scaled_f_rec_T_102, _activated_data_e_scaled_f_rec_T_103}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_12 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_12; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_12 = _activated_data_e_scaled_rec_fn_to_in_12_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_12 = _activated_data_e_scaled_muladder_12_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_12 = activated_data_e_scaled_sign_exp_12[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_12 = _activated_data_e_scaled_sign_isZero_T_12 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_12_isZero = activated_data_e_scaled_sign_isZero_12; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_12 = activated_data_e_scaled_sign_exp_12[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_12 = &_activated_data_e_scaled_sign_isSpecial_T_12; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_25; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_38; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_12; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_12; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_51; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_12_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_12_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_12_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_12_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_12_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_24 = activated_data_e_scaled_sign_exp_12[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_36 = activated_data_e_scaled_sign_exp_12[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_25 = activated_data_e_scaled_sign_isSpecial_12 & _activated_data_e_scaled_sign_out_isNaN_T_24; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_12_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_25; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_37 = ~_activated_data_e_scaled_sign_out_isInf_T_36; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_38 = activated_data_e_scaled_sign_isSpecial_12 & _activated_data_e_scaled_sign_out_isInf_T_37; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_12_isInf = _activated_data_e_scaled_sign_out_isInf_T_38; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_12 = _activated_data_e_scaled_muladder_12_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_12_sign = _activated_data_e_scaled_sign_out_sign_T_12; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_12 = {1'h0, activated_data_e_scaled_sign_exp_12}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_12_sExp = _activated_data_e_scaled_sign_out_sExp_T_12; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_48 = ~activated_data_e_scaled_sign_isZero_12; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_49 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_48}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_50 = _activated_data_e_scaled_muladder_12_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_51 = {_activated_data_e_scaled_sign_out_sig_T_49, _activated_data_e_scaled_sign_out_sig_T_50}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_12_sig = _activated_data_e_scaled_sign_out_sig_T_51; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_12 = activated_data_e_scaled_sign_out_12_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_142; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_64 = _activated_data_e_scaled_T_142; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_12 = activated_data_e_scaled_overflow_12 ? activated_data_e_scaled_sat_12 : _activated_data_e_scaled_WIRE_64; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_60 = $signed(activated_data_e_scaled_12) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_61 = $signed(activated_data_e_scaled_12) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_62 = _activated_data_e_clipped_T_61 ? 32'hFFFFFF80 : activated_data_e_scaled_12; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_63 = _activated_data_e_clipped_T_60 ? 32'h7F : _activated_data_e_clipped_T_62; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_64 = _activated_data_e_clipped_T_63[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_12 = _activated_data_e_clipped_T_64; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_12_0 = activated_data_e_clipped_12; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_12_0 = _activated_data_WIRE_12_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_417 = _activated_data_e_act_T_416; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_418 = $signed(io_in_bits_acc_read_resp_data_13_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_419 = _activated_data_e_act_T_418 ? io_in_bits_acc_read_resp_data_13_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_61 = {io_in_bits_acc_read_resp_data_13_0_0[31], io_in_bits_acc_read_resp_data_13_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_423; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_423 = _GEN_61; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_438; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_438 = _GEN_61; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_424 = _activated_data_e_act_T_423[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_425 = _activated_data_e_act_T_424; // @[Arithmetic.scala:95:38]
wire _GEN_62 = $signed(io_in_bits_acc_read_resp_data_13_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_52; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_52 = _GEN_62; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_52; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_52 = _GEN_62; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_13 = {_activated_data_e_act_q_sign_T_52, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_53 = 33'h0 - _GEN_61; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_54 = _activated_data_e_act_q_abs_T_53[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_55 = _activated_data_e_act_q_abs_T_54; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_13 = _activated_data_e_act_q_abs_T_52 ? _activated_data_e_act_q_abs_T_55 : io_in_bits_acc_read_resp_data_13_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_92 = _activated_data_e_act_q_clipped_T_91[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_93 = _activated_data_e_act_q_clipped_T_92; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_94 = $signed(activated_data_e_act_q_abs_13) > $signed(_activated_data_e_act_q_clipped_T_93); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_96 = _activated_data_e_act_q_clipped_T_95[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_97 = _activated_data_e_act_q_clipped_T_96; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_13 = _activated_data_e_act_q_clipped_T_94 ? _activated_data_e_act_q_clipped_T_97 : activated_data_e_act_q_abs_13; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_63 = {activated_data_e_act_q_clipped_13[31], activated_data_e_act_q_clipped_13} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_143; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_143 = _GEN_63; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_146; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_146 = _GEN_63; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_144 = _activated_data_e_act_q_poly_T_143[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_145 = _activated_data_e_act_q_poly_T_144; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_147 = _activated_data_e_act_q_poly_T_146[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_148 = _activated_data_e_act_q_poly_T_147; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_149 = {{32{_activated_data_e_act_q_poly_T_145[31]}}, _activated_data_e_act_q_poly_T_145} * {{32{_activated_data_e_act_q_poly_T_148[31]}}, _activated_data_e_act_q_poly_T_148}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_150 = {_activated_data_e_act_q_poly_T_149[63], _activated_data_e_act_q_poly_T_149} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_151 = _activated_data_e_act_q_poly_T_150[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_152 = _activated_data_e_act_q_poly_T_151; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_153 = _activated_data_e_act_q_poly_T_152[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_13 = _activated_data_e_act_q_poly_T_153; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_26 = {{32{activated_data_e_act_q_sign_13[1]}}, activated_data_e_act_q_sign_13} * {{2{activated_data_e_act_q_poly_13[31]}}, activated_data_e_act_q_poly_13}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_27 = _activated_data_e_act_q_erf_T_26[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_13 = _activated_data_e_act_q_erf_T_27; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_429 = {activated_data_e_act_q_erf_13[31], activated_data_e_act_q_erf_13} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_430 = _activated_data_e_act_T_429[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_431 = _activated_data_e_act_T_430; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_432 = {{32{io_in_bits_acc_read_resp_data_13_0_0[31]}}, io_in_bits_acc_read_resp_data_13_0_0} * {{32{_activated_data_e_act_T_431[31]}}, _activated_data_e_act_T_431}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_433 = _activated_data_e_act_T_432[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_434 = _activated_data_e_act_T_433; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_439 = _activated_data_e_act_T_438[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_440 = _activated_data_e_act_T_439; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_26 = 33'h0 - {_activated_data_e_act_T_440[31], _activated_data_e_act_T_440}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_27 = _activated_data_e_act_neg_q_iexp_T_26[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_13 = _activated_data_e_act_neg_q_iexp_T_27; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_52 = {{32{activated_data_e_act_neg_q_iexp_13[31]}}, activated_data_e_act_neg_q_iexp_13} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_53 = _activated_data_e_act_z_iexp_T_52; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_54 = _activated_data_e_act_z_iexp_T_53[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_55 = _activated_data_e_act_z_iexp_T_54; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_429 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_431 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_433 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_435 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_437 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_439 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_441 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_443 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_445 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_447 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_449 = activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_13 = _activated_data_e_act_z_iexp_T_55[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_461; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_13; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_442 = activated_data_e_act_z_iexp_saturated_13; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_430 = _activated_data_e_act_z_iexp_saturated_T_429[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_432 = _activated_data_e_act_z_iexp_saturated_T_431[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_434 = _activated_data_e_act_z_iexp_saturated_T_433[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_436 = _activated_data_e_act_z_iexp_saturated_T_435[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_438 = _activated_data_e_act_z_iexp_saturated_T_437[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_440 = _activated_data_e_act_z_iexp_saturated_T_439[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_442 = _activated_data_e_act_z_iexp_saturated_T_441[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_444 = _activated_data_e_act_z_iexp_saturated_T_443[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_446 = _activated_data_e_act_z_iexp_saturated_T_445[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_448 = _activated_data_e_act_z_iexp_saturated_T_447[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_450 = _activated_data_e_act_z_iexp_saturated_T_449[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_451 = _activated_data_e_act_z_iexp_saturated_T_430 | _activated_data_e_act_z_iexp_saturated_T_432; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_452 = _activated_data_e_act_z_iexp_saturated_T_451 | _activated_data_e_act_z_iexp_saturated_T_434; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_453 = _activated_data_e_act_z_iexp_saturated_T_452 | _activated_data_e_act_z_iexp_saturated_T_436; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_454 = _activated_data_e_act_z_iexp_saturated_T_453 | _activated_data_e_act_z_iexp_saturated_T_438; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_455 = _activated_data_e_act_z_iexp_saturated_T_454 | _activated_data_e_act_z_iexp_saturated_T_440; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_456 = _activated_data_e_act_z_iexp_saturated_T_455 | _activated_data_e_act_z_iexp_saturated_T_442; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_457 = _activated_data_e_act_z_iexp_saturated_T_456 | _activated_data_e_act_z_iexp_saturated_T_444; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_458 = _activated_data_e_act_z_iexp_saturated_T_457 | _activated_data_e_act_z_iexp_saturated_T_446; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_459 = _activated_data_e_act_z_iexp_saturated_T_458 | _activated_data_e_act_z_iexp_saturated_T_448; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_460 = _activated_data_e_act_z_iexp_saturated_T_459 | _activated_data_e_act_z_iexp_saturated_T_450; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_461 = _activated_data_e_act_z_iexp_saturated_T_460 ? 32'h20 : activated_data_e_act_z_iexp_13; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_13 = _activated_data_e_act_z_iexp_saturated_T_461; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_65 = {{32{activated_data_e_act_z_iexp_13[31]}}, activated_data_e_act_z_iexp_13} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_66 = {_activated_data_e_act_qp_iexp_T_65[63], _activated_data_e_act_qp_iexp_T_65} + {{33{_activated_data_e_act_T_440[31]}}, _activated_data_e_act_T_440}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_67 = _activated_data_e_act_qp_iexp_T_66[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_68 = _activated_data_e_act_qp_iexp_T_67; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_69 = _activated_data_e_act_qp_iexp_T_68[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_13 = _activated_data_e_act_qp_iexp_T_69; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_64 = {activated_data_e_act_qp_iexp_13[31], activated_data_e_act_qp_iexp_13} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_143; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_143 = _GEN_64; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_146; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_146 = _GEN_64; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_144 = _activated_data_e_act_q_poly_iexp_T_143[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_145 = _activated_data_e_act_q_poly_iexp_T_144; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_147 = _activated_data_e_act_q_poly_iexp_T_146[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_148 = _activated_data_e_act_q_poly_iexp_T_147; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_149 = {{32{_activated_data_e_act_q_poly_iexp_T_145[31]}}, _activated_data_e_act_q_poly_iexp_T_145} * {{32{_activated_data_e_act_q_poly_iexp_T_148[31]}}, _activated_data_e_act_q_poly_iexp_T_148}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_150 = {_activated_data_e_act_q_poly_iexp_T_149[63], _activated_data_e_act_q_poly_iexp_T_149} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_151 = _activated_data_e_act_q_poly_iexp_T_150[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_152 = _activated_data_e_act_q_poly_iexp_T_151; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_153 = _activated_data_e_act_q_poly_iexp_T_152[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_13 = _activated_data_e_act_q_poly_iexp_T_153; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_441 = activated_data_e_act_q_poly_iexp_13; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_443 = _activated_data_e_act_T_441 >> _activated_data_e_act_T_442; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_444 = _activated_data_e_act_T_443; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_13 = _activated_data_e_act_T_444; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_446 = _activated_data_e_act_T_445; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_447 = _activated_data_e_act_T_446; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_13 = _activated_data_e_act_T_417 ? _activated_data_e_act_T_419 : _activated_data_e_act_T_447; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_13 = activated_data_e_act_13; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_151_bits = _activated_data_e_scaled_T_150_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_68 = _activated_data_e_scaled_T_151_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_152; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_152 = _activated_data_e_scaled_WIRE_68; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_67_bits = _activated_data_e_scaled_T_152; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_13 = _activated_data_e_scaled_WIRE_67_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_13_sign = activated_data_e_scaled_f_rec_rawIn_sign_13; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_13 = _activated_data_e_scaled_WIRE_67_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_13 = _activated_data_e_scaled_WIRE_67_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 = activated_data_e_scaled_f_rec_rawIn_expIn_13 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13 = activated_data_e_scaled_f_rec_rawIn_fractIn_13 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_572 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_573 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_574 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_575 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_576 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_577 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_578 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_579 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_580 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_581 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_582 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_583 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_584 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_585 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_586 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_587 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_588 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_589 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_590 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_591 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_592 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_593 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_594 = activated_data_e_scaled_f_rec_rawIn_fractIn_13[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_595 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_573 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_596 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_574 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_595; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_597 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_575 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_596; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_598 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_576 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_597; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_599 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_577 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_598; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_600 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_578 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_599; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_601 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_579 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_600; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_602 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_580 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_601; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_603 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_581 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_602; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_604 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_582 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_603; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_605 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_583 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_604; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_606 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_584 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_605; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_607 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_585 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_606; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_608 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_586 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_607; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_609 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_587 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_608; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_610 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_588 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_609; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_611 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_589 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_610; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_612 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_590 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_611; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_613 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_591 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_612; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_614 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_592 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_613; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_615 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_593 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_614; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_13 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_594 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_615; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_26 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_13} << activated_data_e_scaled_f_rec_rawIn_normDist_13; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_27 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_26[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_13 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_27, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_65 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_13}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_66 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_65 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_13}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_67 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_68 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_67}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_69 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_66} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_68}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_13 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_69[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_26 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_13; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_13 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_13_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_13 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_13[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_13 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_13; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_106 = activated_data_e_scaled_f_rec_rawIn_13_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_13_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_13_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_13_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_26 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_27 = activated_data_e_scaled_f_rec_rawIn_isSpecial_13 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_26; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_13_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_27; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_13 = activated_data_e_scaled_f_rec_rawIn_isSpecial_13 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_13; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_13_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_13; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_27 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_26}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_13_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_27; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_52 = ~activated_data_e_scaled_f_rec_rawIn_isZero_13; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_53 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_52}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_54 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_13 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_13 : activated_data_e_scaled_f_rec_rawIn_fractIn_13; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_55 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_53, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_54}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_13_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_55; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_104 = activated_data_e_scaled_f_rec_rawIn_13_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_105 = activated_data_e_scaled_f_rec_rawIn_13_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_104; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_107 = {_activated_data_e_scaled_f_rec_T_105[2:1], _activated_data_e_scaled_f_rec_T_105[0] | _activated_data_e_scaled_f_rec_T_106}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_108 = {activated_data_e_scaled_f_rec_rawIn_13_sign, _activated_data_e_scaled_f_rec_T_107}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_109 = activated_data_e_scaled_f_rec_rawIn_13_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_110 = {_activated_data_e_scaled_f_rec_T_108, _activated_data_e_scaled_f_rec_T_109}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_111 = activated_data_e_scaled_f_rec_rawIn_13_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_13 = {_activated_data_e_scaled_f_rec_T_110, _activated_data_e_scaled_f_rec_T_111}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_13 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_13; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_13 = _activated_data_e_scaled_rec_fn_to_in_13_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_13 = _activated_data_e_scaled_muladder_13_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_13 = activated_data_e_scaled_sign_exp_13[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_13 = _activated_data_e_scaled_sign_isZero_T_13 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_13_isZero = activated_data_e_scaled_sign_isZero_13; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_13 = activated_data_e_scaled_sign_exp_13[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_13 = &_activated_data_e_scaled_sign_isSpecial_T_13; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_27; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_41; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_13; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_13; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_55; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_13_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_13_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_13_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_13_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_13_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_26 = activated_data_e_scaled_sign_exp_13[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_39 = activated_data_e_scaled_sign_exp_13[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_27 = activated_data_e_scaled_sign_isSpecial_13 & _activated_data_e_scaled_sign_out_isNaN_T_26; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_13_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_27; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_40 = ~_activated_data_e_scaled_sign_out_isInf_T_39; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_41 = activated_data_e_scaled_sign_isSpecial_13 & _activated_data_e_scaled_sign_out_isInf_T_40; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_13_isInf = _activated_data_e_scaled_sign_out_isInf_T_41; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_13 = _activated_data_e_scaled_muladder_13_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_13_sign = _activated_data_e_scaled_sign_out_sign_T_13; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_13 = {1'h0, activated_data_e_scaled_sign_exp_13}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_13_sExp = _activated_data_e_scaled_sign_out_sExp_T_13; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_52 = ~activated_data_e_scaled_sign_isZero_13; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_53 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_52}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_54 = _activated_data_e_scaled_muladder_13_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_55 = {_activated_data_e_scaled_sign_out_sig_T_53, _activated_data_e_scaled_sign_out_sig_T_54}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_13_sig = _activated_data_e_scaled_sign_out_sig_T_55; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_13 = activated_data_e_scaled_sign_out_13_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_153; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_69 = _activated_data_e_scaled_T_153; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_13 = activated_data_e_scaled_overflow_13 ? activated_data_e_scaled_sat_13 : _activated_data_e_scaled_WIRE_69; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_65 = $signed(activated_data_e_scaled_13) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_66 = $signed(activated_data_e_scaled_13) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_67 = _activated_data_e_clipped_T_66 ? 32'hFFFFFF80 : activated_data_e_scaled_13; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_68 = _activated_data_e_clipped_T_65 ? 32'h7F : _activated_data_e_clipped_T_67; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_69 = _activated_data_e_clipped_T_68[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_13 = _activated_data_e_clipped_T_69; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_13_0 = activated_data_e_clipped_13; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_13_0 = _activated_data_WIRE_13_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_449 = _activated_data_e_act_T_448; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_450 = $signed(io_in_bits_acc_read_resp_data_14_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_451 = _activated_data_e_act_T_450 ? io_in_bits_acc_read_resp_data_14_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_65 = {io_in_bits_acc_read_resp_data_14_0_0[31], io_in_bits_acc_read_resp_data_14_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_455; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_455 = _GEN_65; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_470; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_470 = _GEN_65; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_456 = _activated_data_e_act_T_455[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_457 = _activated_data_e_act_T_456; // @[Arithmetic.scala:95:38]
wire _GEN_66 = $signed(io_in_bits_acc_read_resp_data_14_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_56; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_56 = _GEN_66; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_56; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_56 = _GEN_66; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_14 = {_activated_data_e_act_q_sign_T_56, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_57 = 33'h0 - _GEN_65; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_58 = _activated_data_e_act_q_abs_T_57[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_59 = _activated_data_e_act_q_abs_T_58; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_14 = _activated_data_e_act_q_abs_T_56 ? _activated_data_e_act_q_abs_T_59 : io_in_bits_acc_read_resp_data_14_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_99 = _activated_data_e_act_q_clipped_T_98[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_100 = _activated_data_e_act_q_clipped_T_99; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_101 = $signed(activated_data_e_act_q_abs_14) > $signed(_activated_data_e_act_q_clipped_T_100); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_103 = _activated_data_e_act_q_clipped_T_102[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_104 = _activated_data_e_act_q_clipped_T_103; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_14 = _activated_data_e_act_q_clipped_T_101 ? _activated_data_e_act_q_clipped_T_104 : activated_data_e_act_q_abs_14; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_67 = {activated_data_e_act_q_clipped_14[31], activated_data_e_act_q_clipped_14} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_154; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_154 = _GEN_67; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_157; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_157 = _GEN_67; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_155 = _activated_data_e_act_q_poly_T_154[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_156 = _activated_data_e_act_q_poly_T_155; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_158 = _activated_data_e_act_q_poly_T_157[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_159 = _activated_data_e_act_q_poly_T_158; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_160 = {{32{_activated_data_e_act_q_poly_T_156[31]}}, _activated_data_e_act_q_poly_T_156} * {{32{_activated_data_e_act_q_poly_T_159[31]}}, _activated_data_e_act_q_poly_T_159}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_161 = {_activated_data_e_act_q_poly_T_160[63], _activated_data_e_act_q_poly_T_160} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_162 = _activated_data_e_act_q_poly_T_161[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_163 = _activated_data_e_act_q_poly_T_162; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_164 = _activated_data_e_act_q_poly_T_163[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_14 = _activated_data_e_act_q_poly_T_164; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_28 = {{32{activated_data_e_act_q_sign_14[1]}}, activated_data_e_act_q_sign_14} * {{2{activated_data_e_act_q_poly_14[31]}}, activated_data_e_act_q_poly_14}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_29 = _activated_data_e_act_q_erf_T_28[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_14 = _activated_data_e_act_q_erf_T_29; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_461 = {activated_data_e_act_q_erf_14[31], activated_data_e_act_q_erf_14} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_462 = _activated_data_e_act_T_461[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_463 = _activated_data_e_act_T_462; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_464 = {{32{io_in_bits_acc_read_resp_data_14_0_0[31]}}, io_in_bits_acc_read_resp_data_14_0_0} * {{32{_activated_data_e_act_T_463[31]}}, _activated_data_e_act_T_463}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_465 = _activated_data_e_act_T_464[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_466 = _activated_data_e_act_T_465; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_471 = _activated_data_e_act_T_470[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_472 = _activated_data_e_act_T_471; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_28 = 33'h0 - {_activated_data_e_act_T_472[31], _activated_data_e_act_T_472}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_29 = _activated_data_e_act_neg_q_iexp_T_28[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_14 = _activated_data_e_act_neg_q_iexp_T_29; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_56 = {{32{activated_data_e_act_neg_q_iexp_14[31]}}, activated_data_e_act_neg_q_iexp_14} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_57 = _activated_data_e_act_z_iexp_T_56; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_58 = _activated_data_e_act_z_iexp_T_57[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_59 = _activated_data_e_act_z_iexp_T_58; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_462 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_464 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_466 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_468 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_470 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_472 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_474 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_476 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_478 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_480 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_482 = activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_14 = _activated_data_e_act_z_iexp_T_59[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_494; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_14; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_474 = activated_data_e_act_z_iexp_saturated_14; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_463 = _activated_data_e_act_z_iexp_saturated_T_462[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_465 = _activated_data_e_act_z_iexp_saturated_T_464[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_467 = _activated_data_e_act_z_iexp_saturated_T_466[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_469 = _activated_data_e_act_z_iexp_saturated_T_468[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_471 = _activated_data_e_act_z_iexp_saturated_T_470[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_473 = _activated_data_e_act_z_iexp_saturated_T_472[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_475 = _activated_data_e_act_z_iexp_saturated_T_474[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_477 = _activated_data_e_act_z_iexp_saturated_T_476[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_479 = _activated_data_e_act_z_iexp_saturated_T_478[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_481 = _activated_data_e_act_z_iexp_saturated_T_480[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_483 = _activated_data_e_act_z_iexp_saturated_T_482[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_484 = _activated_data_e_act_z_iexp_saturated_T_463 | _activated_data_e_act_z_iexp_saturated_T_465; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_485 = _activated_data_e_act_z_iexp_saturated_T_484 | _activated_data_e_act_z_iexp_saturated_T_467; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_486 = _activated_data_e_act_z_iexp_saturated_T_485 | _activated_data_e_act_z_iexp_saturated_T_469; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_487 = _activated_data_e_act_z_iexp_saturated_T_486 | _activated_data_e_act_z_iexp_saturated_T_471; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_488 = _activated_data_e_act_z_iexp_saturated_T_487 | _activated_data_e_act_z_iexp_saturated_T_473; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_489 = _activated_data_e_act_z_iexp_saturated_T_488 | _activated_data_e_act_z_iexp_saturated_T_475; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_490 = _activated_data_e_act_z_iexp_saturated_T_489 | _activated_data_e_act_z_iexp_saturated_T_477; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_491 = _activated_data_e_act_z_iexp_saturated_T_490 | _activated_data_e_act_z_iexp_saturated_T_479; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_492 = _activated_data_e_act_z_iexp_saturated_T_491 | _activated_data_e_act_z_iexp_saturated_T_481; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_493 = _activated_data_e_act_z_iexp_saturated_T_492 | _activated_data_e_act_z_iexp_saturated_T_483; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_494 = _activated_data_e_act_z_iexp_saturated_T_493 ? 32'h20 : activated_data_e_act_z_iexp_14; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_14 = _activated_data_e_act_z_iexp_saturated_T_494; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_70 = {{32{activated_data_e_act_z_iexp_14[31]}}, activated_data_e_act_z_iexp_14} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_71 = {_activated_data_e_act_qp_iexp_T_70[63], _activated_data_e_act_qp_iexp_T_70} + {{33{_activated_data_e_act_T_472[31]}}, _activated_data_e_act_T_472}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_72 = _activated_data_e_act_qp_iexp_T_71[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_73 = _activated_data_e_act_qp_iexp_T_72; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_74 = _activated_data_e_act_qp_iexp_T_73[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_14 = _activated_data_e_act_qp_iexp_T_74; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_68 = {activated_data_e_act_qp_iexp_14[31], activated_data_e_act_qp_iexp_14} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_154; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_154 = _GEN_68; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_157; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_157 = _GEN_68; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_155 = _activated_data_e_act_q_poly_iexp_T_154[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_156 = _activated_data_e_act_q_poly_iexp_T_155; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_158 = _activated_data_e_act_q_poly_iexp_T_157[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_159 = _activated_data_e_act_q_poly_iexp_T_158; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_160 = {{32{_activated_data_e_act_q_poly_iexp_T_156[31]}}, _activated_data_e_act_q_poly_iexp_T_156} * {{32{_activated_data_e_act_q_poly_iexp_T_159[31]}}, _activated_data_e_act_q_poly_iexp_T_159}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_161 = {_activated_data_e_act_q_poly_iexp_T_160[63], _activated_data_e_act_q_poly_iexp_T_160} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_162 = _activated_data_e_act_q_poly_iexp_T_161[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_163 = _activated_data_e_act_q_poly_iexp_T_162; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_164 = _activated_data_e_act_q_poly_iexp_T_163[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_14 = _activated_data_e_act_q_poly_iexp_T_164; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_473 = activated_data_e_act_q_poly_iexp_14; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_475 = _activated_data_e_act_T_473 >> _activated_data_e_act_T_474; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_476 = _activated_data_e_act_T_475; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_14 = _activated_data_e_act_T_476; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_478 = _activated_data_e_act_T_477; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_479 = _activated_data_e_act_T_478; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_14 = _activated_data_e_act_T_449 ? _activated_data_e_act_T_451 : _activated_data_e_act_T_479; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_14 = activated_data_e_act_14; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_162_bits = _activated_data_e_scaled_T_161_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_73 = _activated_data_e_scaled_T_162_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_163; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_163 = _activated_data_e_scaled_WIRE_73; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_72_bits = _activated_data_e_scaled_T_163; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_14 = _activated_data_e_scaled_WIRE_72_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_14_sign = activated_data_e_scaled_f_rec_rawIn_sign_14; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_14 = _activated_data_e_scaled_WIRE_72_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_14 = _activated_data_e_scaled_WIRE_72_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 = activated_data_e_scaled_f_rec_rawIn_expIn_14 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14 = activated_data_e_scaled_f_rec_rawIn_fractIn_14 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_616 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_617 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_618 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_619 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_620 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_621 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_622 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_623 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_624 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_625 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_626 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_627 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_628 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_629 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_630 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_631 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_632 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_633 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_634 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_635 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_636 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_637 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_638 = activated_data_e_scaled_f_rec_rawIn_fractIn_14[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_639 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_617 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_640 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_618 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_639; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_641 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_619 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_640; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_642 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_620 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_641; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_643 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_621 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_642; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_644 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_622 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_643; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_645 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_623 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_644; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_646 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_624 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_645; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_647 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_625 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_646; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_648 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_626 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_647; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_649 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_627 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_648; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_650 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_628 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_649; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_651 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_629 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_650; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_652 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_630 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_651; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_653 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_631 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_652; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_654 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_632 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_653; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_655 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_633 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_654; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_656 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_634 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_655; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_657 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_635 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_656; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_658 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_636 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_657; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_659 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_637 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_658; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_14 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_638 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_659; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_28 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_14} << activated_data_e_scaled_f_rec_rawIn_normDist_14; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_29 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_28[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_14 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_29, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_70 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_14}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_71 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_70 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_14}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_72 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_73 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_72}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_74 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_71} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_73}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_14 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_74[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_28 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_14; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_14 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_14_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_14 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_14[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_14 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_14; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_114 = activated_data_e_scaled_f_rec_rawIn_14_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_14_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_14_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_14_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_28 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_29 = activated_data_e_scaled_f_rec_rawIn_isSpecial_14 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_28; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_14_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_29; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_14 = activated_data_e_scaled_f_rec_rawIn_isSpecial_14 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_14; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_14_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_14; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_29 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_28}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_14_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_29; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_56 = ~activated_data_e_scaled_f_rec_rawIn_isZero_14; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_57 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_56}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_58 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_14 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_14 : activated_data_e_scaled_f_rec_rawIn_fractIn_14; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_59 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_57, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_58}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_14_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_59; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_112 = activated_data_e_scaled_f_rec_rawIn_14_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_113 = activated_data_e_scaled_f_rec_rawIn_14_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_112; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_115 = {_activated_data_e_scaled_f_rec_T_113[2:1], _activated_data_e_scaled_f_rec_T_113[0] | _activated_data_e_scaled_f_rec_T_114}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_116 = {activated_data_e_scaled_f_rec_rawIn_14_sign, _activated_data_e_scaled_f_rec_T_115}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_117 = activated_data_e_scaled_f_rec_rawIn_14_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_118 = {_activated_data_e_scaled_f_rec_T_116, _activated_data_e_scaled_f_rec_T_117}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_119 = activated_data_e_scaled_f_rec_rawIn_14_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_14 = {_activated_data_e_scaled_f_rec_T_118, _activated_data_e_scaled_f_rec_T_119}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_14 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_14; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_14 = _activated_data_e_scaled_rec_fn_to_in_14_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_14 = _activated_data_e_scaled_muladder_14_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_14 = activated_data_e_scaled_sign_exp_14[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_14 = _activated_data_e_scaled_sign_isZero_T_14 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_14_isZero = activated_data_e_scaled_sign_isZero_14; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_14 = activated_data_e_scaled_sign_exp_14[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_14 = &_activated_data_e_scaled_sign_isSpecial_T_14; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_29; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_44; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_14; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_14; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_59; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_14_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_14_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_14_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_14_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_14_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_28 = activated_data_e_scaled_sign_exp_14[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_42 = activated_data_e_scaled_sign_exp_14[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_29 = activated_data_e_scaled_sign_isSpecial_14 & _activated_data_e_scaled_sign_out_isNaN_T_28; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_14_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_29; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_43 = ~_activated_data_e_scaled_sign_out_isInf_T_42; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_44 = activated_data_e_scaled_sign_isSpecial_14 & _activated_data_e_scaled_sign_out_isInf_T_43; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_14_isInf = _activated_data_e_scaled_sign_out_isInf_T_44; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_14 = _activated_data_e_scaled_muladder_14_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_14_sign = _activated_data_e_scaled_sign_out_sign_T_14; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_14 = {1'h0, activated_data_e_scaled_sign_exp_14}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_14_sExp = _activated_data_e_scaled_sign_out_sExp_T_14; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_56 = ~activated_data_e_scaled_sign_isZero_14; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_57 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_56}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_58 = _activated_data_e_scaled_muladder_14_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_59 = {_activated_data_e_scaled_sign_out_sig_T_57, _activated_data_e_scaled_sign_out_sig_T_58}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_14_sig = _activated_data_e_scaled_sign_out_sig_T_59; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_14 = activated_data_e_scaled_sign_out_14_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_164; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_74 = _activated_data_e_scaled_T_164; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_14 = activated_data_e_scaled_overflow_14 ? activated_data_e_scaled_sat_14 : _activated_data_e_scaled_WIRE_74; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_70 = $signed(activated_data_e_scaled_14) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_71 = $signed(activated_data_e_scaled_14) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_72 = _activated_data_e_clipped_T_71 ? 32'hFFFFFF80 : activated_data_e_scaled_14; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_73 = _activated_data_e_clipped_T_70 ? 32'h7F : _activated_data_e_clipped_T_72; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_74 = _activated_data_e_clipped_T_73[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_14 = _activated_data_e_clipped_T_74; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_14_0 = activated_data_e_clipped_14; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_14_0 = _activated_data_WIRE_14_0; // @[AccumulatorScale.scala:116:{33,55}]
wire _activated_data_e_act_T_481 = _activated_data_e_act_T_480; // @[AccumulatorScale.scala:118:{38,45}]
wire _activated_data_e_act_T_482 = $signed(io_in_bits_acc_read_resp_data_15_0_0) > -32'sh1; // @[Arithmetic.scala:128:42]
wire [31:0] _activated_data_e_act_T_483 = _activated_data_e_act_T_482 ? io_in_bits_acc_read_resp_data_15_0_0 : 32'h0; // @[Arithmetic.scala:128:{36,42}]
wire [32:0] _GEN_69 = {io_in_bits_acc_read_resp_data_15_0_0[31], io_in_bits_acc_read_resp_data_15_0_0}; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_487; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_487 = _GEN_69; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_T_502; // @[Arithmetic.scala:95:38]
assign _activated_data_e_act_T_502 = _GEN_69; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_488 = _activated_data_e_act_T_487[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_489 = _activated_data_e_act_T_488; // @[Arithmetic.scala:95:38]
wire _GEN_70 = $signed(io_in_bits_acc_read_resp_data_15_0_0) < 32'sh0; // @[Arithmetic.scala:110:44, :128:42]
wire _activated_data_e_act_q_sign_T_60; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_sign_T_60 = _GEN_70; // @[Arithmetic.scala:110:44]
wire _activated_data_e_act_q_abs_T_60; // @[Arithmetic.scala:110:44]
assign _activated_data_e_act_q_abs_T_60 = _GEN_70; // @[Arithmetic.scala:110:44]
wire [1:0] activated_data_e_act_q_sign_15 = {_activated_data_e_act_q_sign_T_60, 1'h1}; // @[Arithmetic.scala:110:44]
wire [32:0] _activated_data_e_act_q_abs_T_61 = 33'h0 - _GEN_69; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_q_abs_T_62 = _activated_data_e_act_q_abs_T_61[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_abs_T_63 = _activated_data_e_act_q_abs_T_62; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_abs_15 = _activated_data_e_act_q_abs_T_60 ? _activated_data_e_act_q_abs_T_63 : io_in_bits_acc_read_resp_data_15_0_0; // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_106 = _activated_data_e_act_q_clipped_T_105[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_107 = _activated_data_e_act_q_clipped_T_106; // @[Arithmetic.scala:95:38]
wire _activated_data_e_act_q_clipped_T_108 = $signed(activated_data_e_act_q_abs_15) > $signed(_activated_data_e_act_q_clipped_T_107); // @[Arithmetic.scala:95:38, :110:44]
wire [31:0] _activated_data_e_act_q_clipped_T_110 = _activated_data_e_act_q_clipped_T_109[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_q_clipped_T_111 = _activated_data_e_act_q_clipped_T_110; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_q_clipped_15 = _activated_data_e_act_q_clipped_T_108 ? _activated_data_e_act_q_clipped_T_111 : activated_data_e_act_q_abs_15; // @[Arithmetic.scala:95:38, :110:44]
wire [32:0] _GEN_71 = {activated_data_e_act_q_clipped_15[31], activated_data_e_act_q_clipped_15} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :128:42]
wire [32:0] _activated_data_e_act_q_poly_T_165; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_165 = _GEN_71; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_T_168; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_T_168 = _GEN_71; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_166 = _activated_data_e_act_q_poly_T_165[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_167 = _activated_data_e_act_q_poly_T_166; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_169 = _activated_data_e_act_q_poly_T_168[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_T_170 = _activated_data_e_act_q_poly_T_169; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_T_171 = {{32{_activated_data_e_act_q_poly_T_167[31]}}, _activated_data_e_act_q_poly_T_167} * {{32{_activated_data_e_act_q_poly_T_170[31]}}, _activated_data_e_act_q_poly_T_170}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_T_172 = {_activated_data_e_act_q_poly_T_171[63], _activated_data_e_act_q_poly_T_171} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_T_173 = _activated_data_e_act_q_poly_T_172[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_T_174 = _activated_data_e_act_q_poly_T_173; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_T_175 = _activated_data_e_act_q_poly_T_174[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_15 = _activated_data_e_act_q_poly_T_175; // @[Arithmetic.scala:114:{15,33}]
wire [33:0] _activated_data_e_act_q_erf_T_30 = {{32{activated_data_e_act_q_sign_15[1]}}, activated_data_e_act_q_sign_15} * {{2{activated_data_e_act_q_poly_15[31]}}, activated_data_e_act_q_poly_15}; // @[Arithmetic.scala:92:38, :114:33]
wire [31:0] _activated_data_e_act_q_erf_T_31 = _activated_data_e_act_q_erf_T_30[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] activated_data_e_act_q_erf_15 = _activated_data_e_act_q_erf_T_31; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _activated_data_e_act_T_493 = {activated_data_e_act_q_erf_15[31], activated_data_e_act_q_erf_15} + _GEN_8; // @[Arithmetic.scala:94:38, :114:33]
wire [31:0] _activated_data_e_act_T_494 = _activated_data_e_act_T_493[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_T_495 = _activated_data_e_act_T_494; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_T_496 = {{32{io_in_bits_acc_read_resp_data_15_0_0[31]}}, io_in_bits_acc_read_resp_data_15_0_0} * {{32{_activated_data_e_act_T_495[31]}}, _activated_data_e_act_T_495}; // @[Arithmetic.scala:92:38, :94:38, :95:38]
wire [31:0] _activated_data_e_act_T_497 = _activated_data_e_act_T_496[31:0]; // @[Arithmetic.scala:92:38, :114:15]
wire [31:0] _activated_data_e_act_T_498 = _activated_data_e_act_T_497; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_503 = _activated_data_e_act_T_502[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] _activated_data_e_act_T_504 = _activated_data_e_act_T_503; // @[Arithmetic.scala:95:38]
wire [32:0] _activated_data_e_act_neg_q_iexp_T_30 = 33'h0 - {_activated_data_e_act_T_504[31], _activated_data_e_act_T_504}; // @[Arithmetic.scala:95:38, :128:42]
wire [31:0] _activated_data_e_act_neg_q_iexp_T_31 = _activated_data_e_act_neg_q_iexp_T_30[31:0]; // @[Arithmetic.scala:95:38]
wire [31:0] activated_data_e_act_neg_q_iexp_15 = _activated_data_e_act_neg_q_iexp_T_31; // @[Arithmetic.scala:95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_60 = {{32{activated_data_e_act_neg_q_iexp_15[31]}}, activated_data_e_act_neg_q_iexp_15} * _GEN_10; // @[Arithmetic.scala:92:38, :95:38]
wire [63:0] _activated_data_e_act_z_iexp_T_61 = _activated_data_e_act_z_iexp_T_60; // @[Arithmetic.scala:92:38]
wire [47:0] _activated_data_e_act_z_iexp_T_62 = _activated_data_e_act_z_iexp_T_61[63:16]; // @[AccumulatorScale.scala:398:{42,54}]
wire [47:0] _activated_data_e_act_z_iexp_T_63 = _activated_data_e_act_z_iexp_T_62; // @[AccumulatorScale.scala:398:{54,67}]
wire [31:0] activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_495 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_497 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_499 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_501 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_503 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_505 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_507 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_509 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_511 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_513 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_515 = activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:53]
assign activated_data_e_act_z_iexp_15 = _activated_data_e_act_z_iexp_T_63[31:0]; // @[AccumulatorScale.scala:398:67]
wire [31:0] _activated_data_e_act_z_iexp_saturated_T_527; // @[AccumulatorScale.scala:400:28]
wire [31:0] activated_data_e_act_z_iexp_saturated_15; // @[AccumulatorScale.scala:399:32]
wire [31:0] _activated_data_e_act_T_506 = activated_data_e_act_z_iexp_saturated_15; // @[AccumulatorScale.scala:399:32, :405:48]
wire _activated_data_e_act_z_iexp_saturated_T_496 = _activated_data_e_act_z_iexp_saturated_T_495[5]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_498 = _activated_data_e_act_z_iexp_saturated_T_497[6]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_500 = _activated_data_e_act_z_iexp_saturated_T_499[7]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_502 = _activated_data_e_act_z_iexp_saturated_T_501[8]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_504 = _activated_data_e_act_z_iexp_saturated_T_503[9]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_506 = _activated_data_e_act_z_iexp_saturated_T_505[10]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_508 = _activated_data_e_act_z_iexp_saturated_T_507[11]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_510 = _activated_data_e_act_z_iexp_saturated_T_509[12]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_512 = _activated_data_e_act_z_iexp_saturated_T_511[13]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_514 = _activated_data_e_act_z_iexp_saturated_T_513[14]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_516 = _activated_data_e_act_z_iexp_saturated_T_515[15]; // @[AccumulatorScale.scala:400:{53,59}]
wire _activated_data_e_act_z_iexp_saturated_T_517 = _activated_data_e_act_z_iexp_saturated_T_496 | _activated_data_e_act_z_iexp_saturated_T_498; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_518 = _activated_data_e_act_z_iexp_saturated_T_517 | _activated_data_e_act_z_iexp_saturated_T_500; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_519 = _activated_data_e_act_z_iexp_saturated_T_518 | _activated_data_e_act_z_iexp_saturated_T_502; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_520 = _activated_data_e_act_z_iexp_saturated_T_519 | _activated_data_e_act_z_iexp_saturated_T_504; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_521 = _activated_data_e_act_z_iexp_saturated_T_520 | _activated_data_e_act_z_iexp_saturated_T_506; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_522 = _activated_data_e_act_z_iexp_saturated_T_521 | _activated_data_e_act_z_iexp_saturated_T_508; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_523 = _activated_data_e_act_z_iexp_saturated_T_522 | _activated_data_e_act_z_iexp_saturated_T_510; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_524 = _activated_data_e_act_z_iexp_saturated_T_523 | _activated_data_e_act_z_iexp_saturated_T_512; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_525 = _activated_data_e_act_z_iexp_saturated_T_524 | _activated_data_e_act_z_iexp_saturated_T_514; // @[AccumulatorScale.scala:400:{59,73}]
wire _activated_data_e_act_z_iexp_saturated_T_526 = _activated_data_e_act_z_iexp_saturated_T_525 | _activated_data_e_act_z_iexp_saturated_T_516; // @[AccumulatorScale.scala:400:{59,73}]
assign _activated_data_e_act_z_iexp_saturated_T_527 = _activated_data_e_act_z_iexp_saturated_T_526 ? 32'h20 : activated_data_e_act_z_iexp_15; // @[AccumulatorScale.scala:398:67, :400:{28,73}]
assign activated_data_e_act_z_iexp_saturated_15 = _activated_data_e_act_z_iexp_saturated_T_527; // @[AccumulatorScale.scala:399:32, :400:28]
wire [63:0] _activated_data_e_act_qp_iexp_T_75 = {{32{activated_data_e_act_z_iexp_15[31]}}, activated_data_e_act_z_iexp_15} * _GEN_11; // @[Arithmetic.scala:93:49]
wire [64:0] _activated_data_e_act_qp_iexp_T_76 = {_activated_data_e_act_qp_iexp_T_75[63], _activated_data_e_act_qp_iexp_T_75} + {{33{_activated_data_e_act_T_504[31]}}, _activated_data_e_act_T_504}; // @[Arithmetic.scala:93:{49,54}, :95:38, :128:42]
wire [63:0] _activated_data_e_act_qp_iexp_T_77 = _activated_data_e_act_qp_iexp_T_76[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_qp_iexp_T_78 = _activated_data_e_act_qp_iexp_T_77; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_qp_iexp_T_79 = _activated_data_e_act_qp_iexp_T_78[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_qp_iexp_15 = _activated_data_e_act_qp_iexp_T_79; // @[Arithmetic.scala:114:{15,33}]
wire [32:0] _GEN_72 = {activated_data_e_act_qp_iexp_15[31], activated_data_e_act_qp_iexp_15} + _GEN_4; // @[Arithmetic.scala:94:38, :95:38, :114:33, :128:42]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_165; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_165 = _GEN_72; // @[Arithmetic.scala:94:38]
wire [32:0] _activated_data_e_act_q_poly_iexp_T_168; // @[Arithmetic.scala:94:38]
assign _activated_data_e_act_q_poly_iexp_T_168 = _GEN_72; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_166 = _activated_data_e_act_q_poly_iexp_T_165[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_167 = _activated_data_e_act_q_poly_iexp_T_166; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_169 = _activated_data_e_act_q_poly_iexp_T_168[31:0]; // @[Arithmetic.scala:94:38]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_170 = _activated_data_e_act_q_poly_iexp_T_169; // @[Arithmetic.scala:94:38]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_171 = {{32{_activated_data_e_act_q_poly_iexp_T_167[31]}}, _activated_data_e_act_q_poly_iexp_T_167} * {{32{_activated_data_e_act_q_poly_iexp_T_170[31]}}, _activated_data_e_act_q_poly_iexp_T_170}; // @[Arithmetic.scala:93:49, :94:38]
wire [64:0] _activated_data_e_act_q_poly_iexp_T_172 = {_activated_data_e_act_q_poly_iexp_T_171[63], _activated_data_e_act_q_poly_iexp_T_171} + _GEN_7; // @[Arithmetic.scala:93:{49,54}]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_173 = _activated_data_e_act_q_poly_iexp_T_172[63:0]; // @[Arithmetic.scala:93:54]
wire [63:0] _activated_data_e_act_q_poly_iexp_T_174 = _activated_data_e_act_q_poly_iexp_T_173; // @[Arithmetic.scala:93:54]
wire [31:0] _activated_data_e_act_q_poly_iexp_T_175 = _activated_data_e_act_q_poly_iexp_T_174[31:0]; // @[Arithmetic.scala:93:54, :114:15]
wire [31:0] activated_data_e_act_q_poly_iexp_15 = _activated_data_e_act_q_poly_iexp_T_175; // @[Arithmetic.scala:114:{15,33}]
wire [31:0] _activated_data_e_act_T_505 = activated_data_e_act_q_poly_iexp_15; // @[Arithmetic.scala:114:33]
wire [31:0] _activated_data_e_act_T_507 = _activated_data_e_act_T_505 >> _activated_data_e_act_T_506; // @[AccumulatorScale.scala:405:{18,30,48}]
wire [31:0] _activated_data_e_act_T_508 = _activated_data_e_act_T_507; // @[AccumulatorScale.scala:405:{30,65}]
wire [31:0] _activated_data_e_act_WIRE_15 = _activated_data_e_act_T_508; // @[AccumulatorScale.scala:405:65]
wire [31:0] _activated_data_e_act_T_510 = _activated_data_e_act_T_509; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_act_T_511 = _activated_data_e_act_T_510; // @[Mux.scala:126:16]
wire [31:0] activated_data_e_act_15 = _activated_data_e_act_T_481 ? _activated_data_e_act_T_483 : _activated_data_e_act_T_511; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_T_15 = activated_data_e_act_15; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_173_bits = _activated_data_e_scaled_T_172_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_WIRE_78 = _activated_data_e_scaled_T_173_bits; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_scaled_T_174; // @[AccumulatorScale.scala:132:18]
assign _activated_data_e_scaled_T_174 = _activated_data_e_scaled_WIRE_78; // @[AccumulatorScale.scala:132:18]
wire [31:0] _activated_data_e_scaled_WIRE_77_bits = _activated_data_e_scaled_T_174; // @[AccumulatorScale.scala:132:18]
wire activated_data_e_scaled_f_rec_rawIn_sign_15 = _activated_data_e_scaled_WIRE_77_bits[31]; // @[rawFloatFromFN.scala:44:18]
wire activated_data_e_scaled_f_rec_rawIn_15_sign = activated_data_e_scaled_f_rec_rawIn_sign_15; // @[rawFloatFromFN.scala:44:18, :63:19]
wire [7:0] activated_data_e_scaled_f_rec_rawIn_expIn_15 = _activated_data_e_scaled_WIRE_77_bits[30:23]; // @[rawFloatFromFN.scala:45:19]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_fractIn_15 = _activated_data_e_scaled_WIRE_77_bits[22:0]; // @[rawFloatFromFN.scala:46:21]
wire activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 = activated_data_e_scaled_f_rec_rawIn_expIn_15 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30]
wire activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15 = activated_data_e_scaled_f_rec_rawIn_fractIn_15 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_660 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[0]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_661 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[1]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_662 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[2]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_663 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[3]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_664 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[4]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_665 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[5]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_666 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[6]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_667 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[7]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_668 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[8]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_669 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[9]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_670 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[10]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_671 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[11]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_672 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[12]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_673 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[13]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_674 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[14]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_675 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[15]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_676 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[16]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_677 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[17]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_678 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[18]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_679 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[19]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_680 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[20]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_681 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[21]; // @[rawFloatFromFN.scala:46:21]
wire _activated_data_e_scaled_f_rec_rawIn_normDist_T_682 = activated_data_e_scaled_f_rec_rawIn_fractIn_15[22]; // @[rawFloatFromFN.scala:46:21]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_683 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_661 ? 5'h15 : 5'h16; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_684 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_662 ? 5'h14 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_683; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_685 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_663 ? 5'h13 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_684; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_686 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_664 ? 5'h12 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_685; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_687 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_665 ? 5'h11 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_686; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_688 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_666 ? 5'h10 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_687; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_689 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_667 ? 5'hF : _activated_data_e_scaled_f_rec_rawIn_normDist_T_688; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_690 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_668 ? 5'hE : _activated_data_e_scaled_f_rec_rawIn_normDist_T_689; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_691 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_669 ? 5'hD : _activated_data_e_scaled_f_rec_rawIn_normDist_T_690; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_692 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_670 ? 5'hC : _activated_data_e_scaled_f_rec_rawIn_normDist_T_691; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_693 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_671 ? 5'hB : _activated_data_e_scaled_f_rec_rawIn_normDist_T_692; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_694 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_672 ? 5'hA : _activated_data_e_scaled_f_rec_rawIn_normDist_T_693; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_695 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_673 ? 5'h9 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_694; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_696 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_674 ? 5'h8 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_695; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_697 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_675 ? 5'h7 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_696; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_698 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_676 ? 5'h6 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_697; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_699 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_677 ? 5'h5 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_698; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_700 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_678 ? 5'h4 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_699; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_701 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_679 ? 5'h3 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_700; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_702 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_680 ? 5'h2 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_701; // @[Mux.scala:50:70]
wire [4:0] _activated_data_e_scaled_f_rec_rawIn_normDist_T_703 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_681 ? 5'h1 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_702; // @[Mux.scala:50:70]
wire [4:0] activated_data_e_scaled_f_rec_rawIn_normDist_15 = _activated_data_e_scaled_f_rec_rawIn_normDist_T_682 ? 5'h0 : _activated_data_e_scaled_f_rec_rawIn_normDist_T_703; // @[Mux.scala:50:70]
wire [53:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_30 = {31'h0, activated_data_e_scaled_f_rec_rawIn_fractIn_15} << activated_data_e_scaled_f_rec_rawIn_normDist_15; // @[Mux.scala:50:70]
wire [21:0] _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_31 = _activated_data_e_scaled_f_rec_rawIn_subnormFract_T_30[21:0]; // @[rawFloatFromFN.scala:52:{33,46}]
wire [22:0] activated_data_e_scaled_f_rec_rawIn_subnormFract_15 = {_activated_data_e_scaled_f_rec_rawIn_subnormFract_T_31, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_75 = {4'hF, ~activated_data_e_scaled_f_rec_rawIn_normDist_15}; // @[Mux.scala:50:70]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_76 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 ? _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_75 : {1'h0, activated_data_e_scaled_f_rec_rawIn_expIn_15}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_77 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14]
wire [7:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_78 = {6'h20, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_77}; // @[rawFloatFromFN.scala:58:{9,14}]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_79 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_76} + {2'h0, _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_78}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9]
wire [8:0] activated_data_e_scaled_f_rec_rawIn_adjustedExp_15 = _activated_data_e_scaled_f_rec_rawIn_adjustedExp_T_79[8:0]; // @[rawFloatFromFN.scala:57:9]
wire [8:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_30 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_15; // @[rawFloatFromFN.scala:57:9, :68:28]
wire activated_data_e_scaled_f_rec_rawIn_isZero_15 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30]
wire activated_data_e_scaled_f_rec_rawIn_15_isZero = activated_data_e_scaled_f_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :63:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_isSpecial_T_15 = activated_data_e_scaled_f_rec_rawIn_adjustedExp_15[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32]
wire activated_data_e_scaled_f_rec_rawIn_isSpecial_15 = &_activated_data_e_scaled_f_rec_rawIn_isSpecial_T_15; // @[rawFloatFromFN.scala:61:{32,57}]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:64:28]
wire _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:65:28]
wire _activated_data_e_scaled_f_rec_T_122 = activated_data_e_scaled_f_rec_rawIn_15_isNaN; // @[recFNFromFN.scala:49:20]
wire [9:0] _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:68:42]
wire [24:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:70:27]
wire activated_data_e_scaled_f_rec_rawIn_15_isInf; // @[rawFloatFromFN.scala:63:19]
wire [9:0] activated_data_e_scaled_f_rec_rawIn_15_sExp; // @[rawFloatFromFN.scala:63:19]
wire [24:0] activated_data_e_scaled_f_rec_rawIn_15_sig; // @[rawFloatFromFN.scala:63:19]
wire _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_30 = ~activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :64:31]
assign _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_31 = activated_data_e_scaled_f_rec_rawIn_isSpecial_15 & _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_30; // @[rawFloatFromFN.scala:61:57, :64:{28,31}]
assign activated_data_e_scaled_f_rec_rawIn_15_isNaN = _activated_data_e_scaled_f_rec_rawIn_out_isNaN_T_31; // @[rawFloatFromFN.scala:63:19, :64:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_15 = activated_data_e_scaled_f_rec_rawIn_isSpecial_15 & activated_data_e_scaled_f_rec_rawIn_isZeroFractIn_15; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28]
assign activated_data_e_scaled_f_rec_rawIn_15_isInf = _activated_data_e_scaled_f_rec_rawIn_out_isInf_T_15; // @[rawFloatFromFN.scala:63:19, :65:28]
assign _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_31 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_30}; // @[rawFloatFromFN.scala:68:{28,42}]
assign activated_data_e_scaled_f_rec_rawIn_15_sExp = _activated_data_e_scaled_f_rec_rawIn_out_sExp_T_31; // @[rawFloatFromFN.scala:63:19, :68:42]
wire _activated_data_e_scaled_f_rec_rawIn_out_sig_T_60 = ~activated_data_e_scaled_f_rec_rawIn_isZero_15; // @[rawFloatFromFN.scala:60:30, :70:19]
wire [1:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_61 = {1'h0, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_60}; // @[rawFloatFromFN.scala:70:{16,19}]
wire [22:0] _activated_data_e_scaled_f_rec_rawIn_out_sig_T_62 = activated_data_e_scaled_f_rec_rawIn_isZeroExpIn_15 ? activated_data_e_scaled_f_rec_rawIn_subnormFract_15 : activated_data_e_scaled_f_rec_rawIn_fractIn_15; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33]
assign _activated_data_e_scaled_f_rec_rawIn_out_sig_T_63 = {_activated_data_e_scaled_f_rec_rawIn_out_sig_T_61, _activated_data_e_scaled_f_rec_rawIn_out_sig_T_62}; // @[rawFloatFromFN.scala:70:{16,27,33}]
assign activated_data_e_scaled_f_rec_rawIn_15_sig = _activated_data_e_scaled_f_rec_rawIn_out_sig_T_63; // @[rawFloatFromFN.scala:63:19, :70:27]
wire [2:0] _activated_data_e_scaled_f_rec_T_120 = activated_data_e_scaled_f_rec_rawIn_15_sExp[8:6]; // @[recFNFromFN.scala:48:50]
wire [2:0] _activated_data_e_scaled_f_rec_T_121 = activated_data_e_scaled_f_rec_rawIn_15_isZero ? 3'h0 : _activated_data_e_scaled_f_rec_T_120; // @[recFNFromFN.scala:48:{15,50}]
wire [2:0] _activated_data_e_scaled_f_rec_T_123 = {_activated_data_e_scaled_f_rec_T_121[2:1], _activated_data_e_scaled_f_rec_T_121[0] | _activated_data_e_scaled_f_rec_T_122}; // @[recFNFromFN.scala:48:{15,76}, :49:20]
wire [3:0] _activated_data_e_scaled_f_rec_T_124 = {activated_data_e_scaled_f_rec_rawIn_15_sign, _activated_data_e_scaled_f_rec_T_123}; // @[recFNFromFN.scala:47:20, :48:76]
wire [5:0] _activated_data_e_scaled_f_rec_T_125 = activated_data_e_scaled_f_rec_rawIn_15_sExp[5:0]; // @[recFNFromFN.scala:50:23]
wire [9:0] _activated_data_e_scaled_f_rec_T_126 = {_activated_data_e_scaled_f_rec_T_124, _activated_data_e_scaled_f_rec_T_125}; // @[recFNFromFN.scala:47:20, :49:45, :50:23]
wire [22:0] _activated_data_e_scaled_f_rec_T_127 = activated_data_e_scaled_f_rec_rawIn_15_sig[22:0]; // @[recFNFromFN.scala:51:22]
wire [32:0] activated_data_e_scaled_f_rec_15 = {_activated_data_e_scaled_f_rec_T_126, _activated_data_e_scaled_f_rec_T_127}; // @[recFNFromFN.scala:49:45, :50:41, :51:22]
wire [31:0] _activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_15 = _activated_data_e_scaled_in_to_rec_fn_io_in_T_15; // @[Configs.scala:120:41]
wire activated_data_e_scaled_overflow_15 = _activated_data_e_scaled_rec_fn_to_in_15_io_intExceptionFlags[1]; // @[Configs.scala:135:34, :140:57]
wire [8:0] activated_data_e_scaled_sign_exp_15 = _activated_data_e_scaled_muladder_15_io_out[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _activated_data_e_scaled_sign_isZero_T_15 = activated_data_e_scaled_sign_exp_15[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire activated_data_e_scaled_sign_isZero_15 = _activated_data_e_scaled_sign_isZero_T_15 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire activated_data_e_scaled_sign_out_15_isZero = activated_data_e_scaled_sign_isZero_15; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _activated_data_e_scaled_sign_isSpecial_T_15 = activated_data_e_scaled_sign_exp_15[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire activated_data_e_scaled_sign_isSpecial_15 = &_activated_data_e_scaled_sign_isSpecial_T_15; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _activated_data_e_scaled_sign_out_isNaN_T_31; // @[rawFloatFromRecFN.scala:56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_47; // @[rawFloatFromRecFN.scala:57:33]
wire _activated_data_e_scaled_sign_out_sign_T_15; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _activated_data_e_scaled_sign_out_sExp_T_15; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _activated_data_e_scaled_sign_out_sig_T_63; // @[rawFloatFromRecFN.scala:61:44]
wire activated_data_e_scaled_sign_out_15_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_15_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire activated_data_e_scaled_sign_out_15_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] activated_data_e_scaled_sign_out_15_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] activated_data_e_scaled_sign_out_15_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _activated_data_e_scaled_sign_out_isNaN_T_30 = activated_data_e_scaled_sign_exp_15[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _activated_data_e_scaled_sign_out_isInf_T_45 = activated_data_e_scaled_sign_exp_15[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _activated_data_e_scaled_sign_out_isNaN_T_31 = activated_data_e_scaled_sign_isSpecial_15 & _activated_data_e_scaled_sign_out_isNaN_T_30; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign activated_data_e_scaled_sign_out_15_isNaN = _activated_data_e_scaled_sign_out_isNaN_T_31; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _activated_data_e_scaled_sign_out_isInf_T_46 = ~_activated_data_e_scaled_sign_out_isInf_T_45; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _activated_data_e_scaled_sign_out_isInf_T_47 = activated_data_e_scaled_sign_isSpecial_15 & _activated_data_e_scaled_sign_out_isInf_T_46; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign activated_data_e_scaled_sign_out_15_isInf = _activated_data_e_scaled_sign_out_isInf_T_47; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _activated_data_e_scaled_sign_out_sign_T_15 = _activated_data_e_scaled_muladder_15_io_out[32]; // @[rawFloatFromRecFN.scala:59:25]
assign activated_data_e_scaled_sign_out_15_sign = _activated_data_e_scaled_sign_out_sign_T_15; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _activated_data_e_scaled_sign_out_sExp_T_15 = {1'h0, activated_data_e_scaled_sign_exp_15}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign activated_data_e_scaled_sign_out_15_sExp = _activated_data_e_scaled_sign_out_sExp_T_15; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _activated_data_e_scaled_sign_out_sig_T_60 = ~activated_data_e_scaled_sign_isZero_15; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _activated_data_e_scaled_sign_out_sig_T_61 = {1'h0, _activated_data_e_scaled_sign_out_sig_T_60}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _activated_data_e_scaled_sign_out_sig_T_62 = _activated_data_e_scaled_muladder_15_io_out[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _activated_data_e_scaled_sign_out_sig_T_63 = {_activated_data_e_scaled_sign_out_sig_T_61, _activated_data_e_scaled_sign_out_sig_T_62}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign activated_data_e_scaled_sign_out_15_sig = _activated_data_e_scaled_sign_out_sig_T_63; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [31:0] activated_data_e_scaled_sat_15 = activated_data_e_scaled_sign_out_15_sign ? 32'h80000000 : 32'h7FFFFFFF; // @[rawFloatFromRecFN.scala:55:23]
wire [31:0] _activated_data_e_scaled_T_175; // @[Configs.scala:146:56]
wire [31:0] _activated_data_e_scaled_WIRE_79 = _activated_data_e_scaled_T_175; // @[Configs.scala:146:56]
wire [31:0] activated_data_e_scaled_15 = activated_data_e_scaled_overflow_15 ? activated_data_e_scaled_sat_15 : _activated_data_e_scaled_WIRE_79; // @[Configs.scala:140:57, :144:22, :146:{12,56}]
wire _activated_data_e_clipped_T_75 = $signed(activated_data_e_scaled_15) > 32'sh7F; // @[Configs.scala:146:12]
wire _activated_data_e_clipped_T_76 = $signed(activated_data_e_scaled_15) < -32'sh80; // @[Configs.scala:146:12]
wire [31:0] _activated_data_e_clipped_T_77 = _activated_data_e_clipped_T_76 ? 32'hFFFFFF80 : activated_data_e_scaled_15; // @[Mux.scala:126:16]
wire [31:0] _activated_data_e_clipped_T_78 = _activated_data_e_clipped_T_75 ? 32'h7F : _activated_data_e_clipped_T_77; // @[Mux.scala:126:16]
wire [7:0] _activated_data_e_clipped_T_79 = _activated_data_e_clipped_T_78[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_data_e_clipped_15 = _activated_data_e_clipped_T_79; // @[Arithmetic.scala:125:{81,99}]
wire [7:0] _activated_data_WIRE_15_0 = activated_data_e_clipped_15; // @[Arithmetic.scala:125:99]
wire [7:0] activated_data_15_0 = _activated_data_WIRE_15_0; // @[AccumulatorScale.scala:116:{33,55}]
assign io_in_ready_0 = in_ready; // @[AccumulatorScale.scala:88:7, :139:18]
wire [31:0] in_bits_resp_data_0_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_1_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_2_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_3_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_4_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_5_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_6_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_7_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_8_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_9_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_10_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_11_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_12_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_13_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_14_0; // @[AccumulatorScale.scala:139:18]
wire [31:0] in_bits_resp_data_15_0; // @[AccumulatorScale.scala:139:18]
assign in_bits_resp_data_0_0 = {{24{activated_data_0_0[7]}}, activated_data_0_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_1_0 = {{24{activated_data_1_0[7]}}, activated_data_1_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_2_0 = {{24{activated_data_2_0[7]}}, activated_data_2_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_3_0 = {{24{activated_data_3_0[7]}}, activated_data_3_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_4_0 = {{24{activated_data_4_0[7]}}, activated_data_4_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_5_0 = {{24{activated_data_5_0[7]}}, activated_data_5_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_6_0 = {{24{activated_data_6_0[7]}}, activated_data_6_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_7_0 = {{24{activated_data_7_0[7]}}, activated_data_7_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_8_0 = {{24{activated_data_8_0[7]}}, activated_data_8_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_9_0 = {{24{activated_data_9_0[7]}}, activated_data_9_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_10_0 = {{24{activated_data_10_0[7]}}, activated_data_10_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_11_0 = {{24{activated_data_11_0[7]}}, activated_data_11_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_12_0 = {{24{activated_data_12_0[7]}}, activated_data_12_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_13_0 = {{24{activated_data_13_0[7]}}, activated_data_13_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_14_0 = {{24{activated_data_14_0[7]}}, activated_data_14_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign in_bits_resp_data_15_0 = {{24{activated_data_15_0[7]}}, activated_data_15_0}; // @[AccumulatorScale.scala:116:33, :139:18, :144:23]
assign out_bits_data_0_0 = _pipe_out_p_io_out_bits_resp_data_0_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_1_0 = _pipe_out_p_io_out_bits_resp_data_1_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_2_0 = _pipe_out_p_io_out_bits_resp_data_2_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_3_0 = _pipe_out_p_io_out_bits_resp_data_3_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_4_0 = _pipe_out_p_io_out_bits_resp_data_4_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_5_0 = _pipe_out_p_io_out_bits_resp_data_5_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_6_0 = _pipe_out_p_io_out_bits_resp_data_6_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_7_0 = _pipe_out_p_io_out_bits_resp_data_7_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_8_0 = _pipe_out_p_io_out_bits_resp_data_8_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_9_0 = _pipe_out_p_io_out_bits_resp_data_9_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_10_0 = _pipe_out_p_io_out_bits_resp_data_10_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_11_0 = _pipe_out_p_io_out_bits_resp_data_11_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_12_0 = _pipe_out_p_io_out_bits_resp_data_12_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_13_0 = _pipe_out_p_io_out_bits_resp_data_13_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_14_0 = _pipe_out_p_io_out_bits_resp_data_14_0[7:0]; // @[Pipeline.scala:75:19]
assign out_bits_data_15_0 = _pipe_out_p_io_out_bits_resp_data_15_0[7:0]; // @[Pipeline.scala:75:19]
INToRecFN_i32_e8_s24 activated_data_e_scaled_in_to_rec_fn ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_4 activated_data_e_scaled_muladder ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32 activated_data_e_scaled_rec_fn_to_in ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_10),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_1 activated_data_e_scaled_in_to_rec_fn_1 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_1), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_1_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_5 activated_data_e_scaled_muladder_1 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_1_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_1), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_1_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_1 activated_data_e_scaled_rec_fn_to_in_1 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_1_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_21),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_1_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_2 activated_data_e_scaled_in_to_rec_fn_2 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_2), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_2_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_6 activated_data_e_scaled_muladder_2 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_2_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_2), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_2_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_2 activated_data_e_scaled_rec_fn_to_in_2 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_2_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_32),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_2_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_3 activated_data_e_scaled_in_to_rec_fn_3 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_3), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_3_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_7 activated_data_e_scaled_muladder_3 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_3_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_3), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_3_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_3 activated_data_e_scaled_rec_fn_to_in_3 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_3_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_43),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_3_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_4 activated_data_e_scaled_in_to_rec_fn_4 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_4), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_4_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_8 activated_data_e_scaled_muladder_4 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_4_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_4), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_4_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_4 activated_data_e_scaled_rec_fn_to_in_4 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_4_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_54),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_4_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_5 activated_data_e_scaled_in_to_rec_fn_5 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_5), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_5_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_9 activated_data_e_scaled_muladder_5 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_5_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_5), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_5_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_5 activated_data_e_scaled_rec_fn_to_in_5 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_5_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_65),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_5_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_6 activated_data_e_scaled_in_to_rec_fn_6 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_6), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_6_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_10 activated_data_e_scaled_muladder_6 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_6_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_6), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_6_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_6 activated_data_e_scaled_rec_fn_to_in_6 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_6_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_76),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_6_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_7 activated_data_e_scaled_in_to_rec_fn_7 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_7), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_7_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_11 activated_data_e_scaled_muladder_7 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_7_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_7), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_7_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_7 activated_data_e_scaled_rec_fn_to_in_7 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_7_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_87),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_7_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_8 activated_data_e_scaled_in_to_rec_fn_8 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_8), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_8_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_12 activated_data_e_scaled_muladder_8 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_8_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_8), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_8_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_8 activated_data_e_scaled_rec_fn_to_in_8 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_8_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_98),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_8_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_9 activated_data_e_scaled_in_to_rec_fn_9 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_9), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_9_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_13 activated_data_e_scaled_muladder_9 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_9_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_9), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_9_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_9 activated_data_e_scaled_rec_fn_to_in_9 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_9_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_109),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_9_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_10 activated_data_e_scaled_in_to_rec_fn_10 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_10), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_10_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_14 activated_data_e_scaled_muladder_10 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_10_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_10), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_10_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_10 activated_data_e_scaled_rec_fn_to_in_10 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_10_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_120),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_10_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_11 activated_data_e_scaled_in_to_rec_fn_11 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_11), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_11_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_15 activated_data_e_scaled_muladder_11 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_11_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_11), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_11_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_11 activated_data_e_scaled_rec_fn_to_in_11 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_11_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_131),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_11_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_12 activated_data_e_scaled_in_to_rec_fn_12 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_12), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_12_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_16 activated_data_e_scaled_muladder_12 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_12_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_12), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_12_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_12 activated_data_e_scaled_rec_fn_to_in_12 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_12_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_142),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_12_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_13 activated_data_e_scaled_in_to_rec_fn_13 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_13), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_13_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_17 activated_data_e_scaled_muladder_13 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_13_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_13), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_13_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_13 activated_data_e_scaled_rec_fn_to_in_13 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_13_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_153),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_13_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_14 activated_data_e_scaled_in_to_rec_fn_14 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_14), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_14_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_18 activated_data_e_scaled_muladder_14 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_14_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_14), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_14_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_14 activated_data_e_scaled_rec_fn_to_in_14 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_14_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_164),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_14_io_intExceptionFlags)
); // @[Configs.scala:135:34]
INToRecFN_i32_e8_s24_15 activated_data_e_scaled_in_to_rec_fn_15 ( // @[Configs.scala:118:34]
.io_in (_activated_data_e_scaled_in_to_rec_fn_io_in_WIRE_15), // @[Configs.scala:120:41]
.io_out (_activated_data_e_scaled_in_to_rec_fn_15_io_out)
); // @[Configs.scala:118:34]
MulAddRecFN_e8_s24_19 activated_data_e_scaled_muladder_15 ( // @[Configs.scala:126:30]
.io_a (_activated_data_e_scaled_in_to_rec_fn_15_io_out), // @[Configs.scala:118:34]
.io_b (activated_data_e_scaled_f_rec_15), // @[recFNFromFN.scala:50:41]
.io_out (_activated_data_e_scaled_muladder_15_io_out)
); // @[Configs.scala:126:30]
RecFNToIN_e8_s24_i32_15 activated_data_e_scaled_rec_fn_to_in_15 ( // @[Configs.scala:135:34]
.clock (clock),
.reset (reset),
.io_in (_activated_data_e_scaled_muladder_15_io_out), // @[Configs.scala:126:30]
.io_out (_activated_data_e_scaled_T_175),
.io_intExceptionFlags (_activated_data_e_scaled_rec_fn_to_in_15_io_intExceptionFlags)
); // @[Configs.scala:135:34]
Pipeline_9 pipe_out_p ( // @[Pipeline.scala:75:19]
.clock (clock),
.reset (reset),
.io_in_ready (in_ready),
.io_in_valid (in_valid), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_0_0 (in_bits_resp_data_0_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_1_0 (in_bits_resp_data_1_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_2_0 (in_bits_resp_data_2_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_3_0 (in_bits_resp_data_3_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_4_0 (in_bits_resp_data_4_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_5_0 (in_bits_resp_data_5_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_6_0 (in_bits_resp_data_6_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_7_0 (in_bits_resp_data_7_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_8_0 (in_bits_resp_data_8_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_9_0 (in_bits_resp_data_9_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_10_0 (in_bits_resp_data_10_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_11_0 (in_bits_resp_data_11_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_12_0 (in_bits_resp_data_12_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_13_0 (in_bits_resp_data_13_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_14_0 (in_bits_resp_data_14_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_data_15_0 (in_bits_resp_data_15_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_fromDMA (in_bits_resp_fromDMA), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_scale_bits (in_bits_resp_scale_bits), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_igelu_qb (in_bits_resp_igelu_qb), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_igelu_qc (in_bits_resp_igelu_qc), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_iexp_qln2 (in_bits_resp_iexp_qln2), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_iexp_qln2_inv (in_bits_resp_iexp_qln2_inv), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_act (in_bits_resp_act), // @[AccumulatorScale.scala:139:18]
.io_in_bits_resp_acc_bank_id (in_bits_resp_acc_bank_id), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_0_0 (in_bits_full_data_0_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_1_0 (in_bits_full_data_1_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_2_0 (in_bits_full_data_2_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_3_0 (in_bits_full_data_3_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_4_0 (in_bits_full_data_4_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_5_0 (in_bits_full_data_5_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_6_0 (in_bits_full_data_6_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_7_0 (in_bits_full_data_7_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_8_0 (in_bits_full_data_8_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_9_0 (in_bits_full_data_9_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_10_0 (in_bits_full_data_10_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_11_0 (in_bits_full_data_11_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_12_0 (in_bits_full_data_12_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_13_0 (in_bits_full_data_13_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_14_0 (in_bits_full_data_14_0), // @[AccumulatorScale.scala:139:18]
.io_in_bits_full_data_15_0 (in_bits_full_data_15_0), // @[AccumulatorScale.scala:139:18]
.io_out_ready (out_ready), // @[AccumulatorScale.scala:104:17]
.io_out_valid (out_valid),
.io_out_bits_resp_data_0_0 (_pipe_out_p_io_out_bits_resp_data_0_0),
.io_out_bits_resp_data_1_0 (_pipe_out_p_io_out_bits_resp_data_1_0),
.io_out_bits_resp_data_2_0 (_pipe_out_p_io_out_bits_resp_data_2_0),
.io_out_bits_resp_data_3_0 (_pipe_out_p_io_out_bits_resp_data_3_0),
.io_out_bits_resp_data_4_0 (_pipe_out_p_io_out_bits_resp_data_4_0),
.io_out_bits_resp_data_5_0 (_pipe_out_p_io_out_bits_resp_data_5_0),
.io_out_bits_resp_data_6_0 (_pipe_out_p_io_out_bits_resp_data_6_0),
.io_out_bits_resp_data_7_0 (_pipe_out_p_io_out_bits_resp_data_7_0),
.io_out_bits_resp_data_8_0 (_pipe_out_p_io_out_bits_resp_data_8_0),
.io_out_bits_resp_data_9_0 (_pipe_out_p_io_out_bits_resp_data_9_0),
.io_out_bits_resp_data_10_0 (_pipe_out_p_io_out_bits_resp_data_10_0),
.io_out_bits_resp_data_11_0 (_pipe_out_p_io_out_bits_resp_data_11_0),
.io_out_bits_resp_data_12_0 (_pipe_out_p_io_out_bits_resp_data_12_0),
.io_out_bits_resp_data_13_0 (_pipe_out_p_io_out_bits_resp_data_13_0),
.io_out_bits_resp_data_14_0 (_pipe_out_p_io_out_bits_resp_data_14_0),
.io_out_bits_resp_data_15_0 (_pipe_out_p_io_out_bits_resp_data_15_0),
.io_out_bits_resp_fromDMA (out_bits_fromDMA),
.io_out_bits_resp_acc_bank_id (out_bits_acc_bank_id),
.io_out_bits_full_data_0_0 (out_bits_full_data_0_0),
.io_out_bits_full_data_1_0 (out_bits_full_data_1_0),
.io_out_bits_full_data_2_0 (out_bits_full_data_2_0),
.io_out_bits_full_data_3_0 (out_bits_full_data_3_0),
.io_out_bits_full_data_4_0 (out_bits_full_data_4_0),
.io_out_bits_full_data_5_0 (out_bits_full_data_5_0),
.io_out_bits_full_data_6_0 (out_bits_full_data_6_0),
.io_out_bits_full_data_7_0 (out_bits_full_data_7_0),
.io_out_bits_full_data_8_0 (out_bits_full_data_8_0),
.io_out_bits_full_data_9_0 (out_bits_full_data_9_0),
.io_out_bits_full_data_10_0 (out_bits_full_data_10_0),
.io_out_bits_full_data_11_0 (out_bits_full_data_11_0),
.io_out_bits_full_data_12_0 (out_bits_full_data_12_0),
.io_out_bits_full_data_13_0 (out_bits_full_data_13_0),
.io_out_bits_full_data_14_0 (out_bits_full_data_14_0),
.io_out_bits_full_data_15_0 (out_bits_full_data_15_0)
); // @[Pipeline.scala:75:19]
assign io_in_ready = io_in_ready_0; // @[AccumulatorScale.scala:88:7]
assign io_out_valid = io_out_valid_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_0_0 = io_out_bits_data_0_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_1_0 = io_out_bits_data_1_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_2_0 = io_out_bits_data_2_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_3_0 = io_out_bits_data_3_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_4_0 = io_out_bits_data_4_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_5_0 = io_out_bits_data_5_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_6_0 = io_out_bits_data_6_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_7_0 = io_out_bits_data_7_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_8_0 = io_out_bits_data_8_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_9_0 = io_out_bits_data_9_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_10_0 = io_out_bits_data_10_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_11_0 = io_out_bits_data_11_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_12_0 = io_out_bits_data_12_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_13_0 = io_out_bits_data_13_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_14_0 = io_out_bits_data_14_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_data_15_0 = io_out_bits_data_15_0_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_acc_bank_id = io_out_bits_acc_bank_id_0; // @[AccumulatorScale.scala:88:7]
assign io_out_bits_fromDMA = io_out_bits_fromDMA_0; // @[AccumulatorScale.scala:88:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File PMA.scala:
// See LICENSE.SiFive for license details.
// See LICENSE.Berkeley for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import freechips.rocketchip.devices.debug.DebugModuleKey
import freechips.rocketchip.diplomacy.RegionType
import freechips.rocketchip.subsystem.CacheBlockBytes
import freechips.rocketchip.tile.{CoreModule, CoreBundle}
import freechips.rocketchip.tilelink.{TLSlavePortParameters, TLManagerParameters}
class PMAChecker(manager: TLSlavePortParameters)(implicit p: Parameters) extends CoreModule()(p) {
val io = IO(new Bundle {
val paddr = Input(UInt())
val resp = Output(new Bundle {
val cacheable = Bool()
val r = Bool()
val w = Bool()
val pp = Bool()
val al = Bool()
val aa = Bool()
val x = Bool()
val eff = Bool()
})
})
// PMA
// check exist a slave can consume this address.
val legal_address = manager.findSafe(io.paddr).reduce(_||_)
// check utility to help check SoC property.
def fastCheck(member: TLManagerParameters => Boolean) =
legal_address && manager.fastProperty(io.paddr, member, (b:Boolean) => b.B)
io.resp.cacheable := fastCheck(_.supportsAcquireB)
io.resp.r := fastCheck(_.supportsGet)
io.resp.w := fastCheck(_.supportsPutFull)
io.resp.pp := fastCheck(_.supportsPutPartial)
io.resp.al := fastCheck(_.supportsLogical)
io.resp.aa := fastCheck(_.supportsArithmetic)
io.resp.x := fastCheck(_.executable)
io.resp.eff := fastCheck(Seq(RegionType.PUT_EFFECTS, RegionType.GET_EFFECTS) contains _.regionType)
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
|
module PMAChecker_17( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46]
wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73]
wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19]
wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_49; // @[PMA.scala:39:19]
wire _io_resp_pp_T_49; // @[PMA.scala:39:19]
wire _io_resp_al_T_49; // @[PMA.scala:39:19]
wire _io_resp_aa_T_49; // @[PMA.scala:39:19]
wire _io_resp_x_T_67; // @[PMA.scala:39:19]
wire _io_resp_eff_T_61; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31]
assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31]
assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31]
assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31]
assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31]
assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31]
assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31]
assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31]
assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89]
wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46]
wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89]
wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46]
wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73]
assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73]
assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46]
wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89]
wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46]
wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73]
assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73]
assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73]
assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73]
wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73]
assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File PMP.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.rocket
import chisel3._
import chisel3.util.{Cat, log2Ceil}
import org.chipsalliance.cde.config._
import freechips.rocketchip.tile._
import freechips.rocketchip.util._
class PMPConfig extends Bundle {
val l = Bool()
val res = UInt(2.W)
val a = UInt(2.W)
val x = Bool()
val w = Bool()
val r = Bool()
}
object PMP {
def lgAlign = 2
def apply(reg: PMPReg): PMP = {
val pmp = Wire(new PMP()(reg.p))
pmp.cfg := reg.cfg
pmp.addr := reg.addr
pmp.mask := pmp.computeMask
pmp
}
}
class PMPReg(implicit p: Parameters) extends CoreBundle()(p) {
val cfg = new PMPConfig
val addr = UInt((paddrBits - PMP.lgAlign).W)
def reset(): Unit = {
cfg.a := 0.U
cfg.l := 0.U
}
def readAddr = if (pmpGranularity.log2 == PMP.lgAlign) addr else {
val mask = ((BigInt(1) << (pmpGranularity.log2 - PMP.lgAlign)) - 1).U
Mux(napot, addr | (mask >> 1), ~(~addr | mask))
}
def napot = cfg.a(1)
def torNotNAPOT = cfg.a(0)
def tor = !napot && torNotNAPOT
def cfgLocked = cfg.l
def addrLocked(next: PMPReg) = cfgLocked || next.cfgLocked && next.tor
}
class PMP(implicit p: Parameters) extends PMPReg {
val mask = UInt(paddrBits.W)
import PMP._
def computeMask = {
val base = Cat(addr, cfg.a(0)) | ((pmpGranularity - 1).U >> lgAlign)
Cat(base & ~(base + 1.U), ((1 << lgAlign) - 1).U)
}
private def comparand = ~(~(addr << lgAlign) | (pmpGranularity - 1).U)
private def pow2Match(x: UInt, lgSize: UInt, lgMaxSize: Int) = {
def eval(a: UInt, b: UInt, m: UInt) = ((a ^ b) & ~m) === 0.U
if (lgMaxSize <= pmpGranularity.log2) {
eval(x, comparand, mask)
} else {
// break up the circuit; the MSB part will be CSE'd
val lsbMask = mask | UIntToOH1(lgSize, lgMaxSize)
val msbMatch = eval(x >> lgMaxSize, comparand >> lgMaxSize, mask >> lgMaxSize)
val lsbMatch = eval(x(lgMaxSize-1, 0), comparand(lgMaxSize-1, 0), lsbMask(lgMaxSize-1, 0))
msbMatch && lsbMatch
}
}
private def boundMatch(x: UInt, lsbMask: UInt, lgMaxSize: Int) = {
if (lgMaxSize <= pmpGranularity.log2) {
x < comparand
} else {
// break up the circuit; the MSB part will be CSE'd
val msbsLess = (x >> lgMaxSize) < (comparand >> lgMaxSize)
val msbsEqual = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U
val lsbsLess = (x(lgMaxSize-1, 0) | lsbMask) < comparand(lgMaxSize-1, 0)
msbsLess || (msbsEqual && lsbsLess)
}
}
private def lowerBoundMatch(x: UInt, lgSize: UInt, lgMaxSize: Int) =
!boundMatch(x, UIntToOH1(lgSize, lgMaxSize), lgMaxSize)
private def upperBoundMatch(x: UInt, lgMaxSize: Int) =
boundMatch(x, 0.U, lgMaxSize)
private def rangeMatch(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP) =
prev.lowerBoundMatch(x, lgSize, lgMaxSize) && upperBoundMatch(x, lgMaxSize)
private def pow2Homogeneous(x: UInt, pgLevel: UInt) = {
val maskHomogeneous = pgLevelMap { idxBits => if (idxBits > paddrBits) false.B else mask(idxBits - 1) } (pgLevel)
maskHomogeneous || (pgLevelMap { idxBits => ((x ^ comparand) >> idxBits) =/= 0.U } (pgLevel))
}
private def pgLevelMap[T](f: Int => T) = (0 until pgLevels).map { i =>
f(pgIdxBits + (pgLevels - 1 - i) * pgLevelBits)
}
private def rangeHomogeneous(x: UInt, pgLevel: UInt, prev: PMP) = {
val beginsAfterLower = !(x < prev.comparand)
val beginsAfterUpper = !(x < comparand)
val pgMask = pgLevelMap { idxBits => (((BigInt(1) << paddrBits) - (BigInt(1) << idxBits)) max 0).U } (pgLevel)
val endsBeforeLower = (x & pgMask) < (prev.comparand & pgMask)
val endsBeforeUpper = (x & pgMask) < (comparand & pgMask)
endsBeforeLower || beginsAfterUpper || (beginsAfterLower && endsBeforeUpper)
}
// returns whether this PMP completely contains, or contains none of, a page
def homogeneous(x: UInt, pgLevel: UInt, prev: PMP): Bool =
Mux(napot, pow2Homogeneous(x, pgLevel), !torNotNAPOT || rangeHomogeneous(x, pgLevel, prev))
// returns whether this matching PMP fully contains the access
def aligned(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool = if (lgMaxSize <= pmpGranularity.log2) true.B else {
val lsbMask = UIntToOH1(lgSize, lgMaxSize)
val straddlesLowerBound = ((x >> lgMaxSize) ^ (prev.comparand >> lgMaxSize)) === 0.U && (prev.comparand(lgMaxSize-1, 0) & ~x(lgMaxSize-1, 0)) =/= 0.U
val straddlesUpperBound = ((x >> lgMaxSize) ^ (comparand >> lgMaxSize)) === 0.U && (comparand(lgMaxSize-1, 0) & (x(lgMaxSize-1, 0) | lsbMask)) =/= 0.U
val rangeAligned = !(straddlesLowerBound || straddlesUpperBound)
val pow2Aligned = (lsbMask & ~mask(lgMaxSize-1, 0)) === 0.U
Mux(napot, pow2Aligned, rangeAligned)
}
// returns whether this PMP matches at least one byte of the access
def hit(x: UInt, lgSize: UInt, lgMaxSize: Int, prev: PMP): Bool =
Mux(napot, pow2Match(x, lgSize, lgMaxSize), torNotNAPOT && rangeMatch(x, lgSize, lgMaxSize, prev))
}
class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) {
def apply(addr: UInt, pgLevel: UInt): Bool = {
pmps.foldLeft((true.B, 0.U.asTypeOf(new PMP))) { case ((h, prev), pmp) =>
(h && pmp.homogeneous(addr, pgLevel, prev), pmp)
}._1
}
}
class PMPChecker(lgMaxSize: Int)(implicit val p: Parameters) extends Module
with HasCoreParameters {
override def desiredName = s"PMPChecker_s${lgMaxSize}"
val io = IO(new Bundle {
val prv = Input(UInt(PRV.SZ.W))
val pmp = Input(Vec(nPMPs, new PMP))
val addr = Input(UInt(paddrBits.W))
val size = Input(UInt(log2Ceil(lgMaxSize + 1).W))
val r = Output(Bool())
val w = Output(Bool())
val x = Output(Bool())
})
val default = if (io.pmp.isEmpty) true.B else io.prv > PRV.S.U
val pmp0 = WireInit(0.U.asTypeOf(new PMP))
pmp0.cfg.r := default
pmp0.cfg.w := default
pmp0.cfg.x := default
val res = (io.pmp zip (pmp0 +: io.pmp)).reverse.foldLeft(pmp0) { case (prev, (pmp, prevPMP)) =>
val hit = pmp.hit(io.addr, io.size, lgMaxSize, prevPMP)
val ignore = default && !pmp.cfg.l
val aligned = pmp.aligned(io.addr, io.size, lgMaxSize, prevPMP)
for ((name, idx) <- Seq("no", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty)
property.cover(pmp.cfg.a === idx.U, s"The cfg access is set to ${name} access ", "Cover PMP access mode setting")
property.cover(pmp.cfg.l === 0x1.U, s"The cfg lock is set to high ", "Cover PMP lock mode setting")
// Not including Write and no Read permission as the combination is reserved
for ((name, idx) <- Seq("no", "RO", "", "RW", "X", "RX", "", "RWX").zipWithIndex; if name.nonEmpty)
property.cover((Cat(pmp.cfg.x, pmp.cfg.w, pmp.cfg.r) === idx.U), s"The permission is set to ${name} access ", "Cover PMP access permission setting")
for ((name, idx) <- Seq("", "TOR", if (pmpGranularity <= 4) "NA4" else "", "NAPOT").zipWithIndex; if name.nonEmpty) {
property.cover(!ignore && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode ", "Cover PMP access")
property.cover(pmp.cfg.l && hit && aligned && pmp.cfg.a === idx.U, s"The access matches ${name} mode with lock bit high", "Cover PMP access with lock bit")
}
val cur = WireInit(pmp)
cur.cfg.r := aligned && (pmp.cfg.r || ignore)
cur.cfg.w := aligned && (pmp.cfg.w || ignore)
cur.cfg.x := aligned && (pmp.cfg.x || ignore)
Mux(hit, cur, prev)
}
io.r := res.cfg.r
io.w := res.cfg.w
io.x := res.cfg.x
}
|
module PMPChecker_s3_15( // @[PMP.scala:143:7]
input clock, // @[PMP.scala:143:7]
input reset, // @[PMP.scala:143:7]
input [1:0] io_prv, // @[PMP.scala:146:14]
input io_pmp_0_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_0_cfg_a, // @[PMP.scala:146:14]
input io_pmp_0_cfg_x, // @[PMP.scala:146:14]
input io_pmp_0_cfg_w, // @[PMP.scala:146:14]
input io_pmp_0_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_0_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_0_mask, // @[PMP.scala:146:14]
input io_pmp_1_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_1_cfg_a, // @[PMP.scala:146:14]
input io_pmp_1_cfg_x, // @[PMP.scala:146:14]
input io_pmp_1_cfg_w, // @[PMP.scala:146:14]
input io_pmp_1_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_1_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_1_mask, // @[PMP.scala:146:14]
input io_pmp_2_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_2_cfg_a, // @[PMP.scala:146:14]
input io_pmp_2_cfg_x, // @[PMP.scala:146:14]
input io_pmp_2_cfg_w, // @[PMP.scala:146:14]
input io_pmp_2_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_2_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_2_mask, // @[PMP.scala:146:14]
input io_pmp_3_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_3_cfg_a, // @[PMP.scala:146:14]
input io_pmp_3_cfg_x, // @[PMP.scala:146:14]
input io_pmp_3_cfg_w, // @[PMP.scala:146:14]
input io_pmp_3_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_3_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_3_mask, // @[PMP.scala:146:14]
input io_pmp_4_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_4_cfg_a, // @[PMP.scala:146:14]
input io_pmp_4_cfg_x, // @[PMP.scala:146:14]
input io_pmp_4_cfg_w, // @[PMP.scala:146:14]
input io_pmp_4_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_4_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_4_mask, // @[PMP.scala:146:14]
input io_pmp_5_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_5_cfg_a, // @[PMP.scala:146:14]
input io_pmp_5_cfg_x, // @[PMP.scala:146:14]
input io_pmp_5_cfg_w, // @[PMP.scala:146:14]
input io_pmp_5_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_5_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_5_mask, // @[PMP.scala:146:14]
input io_pmp_6_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_6_cfg_a, // @[PMP.scala:146:14]
input io_pmp_6_cfg_x, // @[PMP.scala:146:14]
input io_pmp_6_cfg_w, // @[PMP.scala:146:14]
input io_pmp_6_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_6_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_6_mask, // @[PMP.scala:146:14]
input io_pmp_7_cfg_l, // @[PMP.scala:146:14]
input [1:0] io_pmp_7_cfg_a, // @[PMP.scala:146:14]
input io_pmp_7_cfg_x, // @[PMP.scala:146:14]
input io_pmp_7_cfg_w, // @[PMP.scala:146:14]
input io_pmp_7_cfg_r, // @[PMP.scala:146:14]
input [29:0] io_pmp_7_addr, // @[PMP.scala:146:14]
input [31:0] io_pmp_7_mask, // @[PMP.scala:146:14]
input [31:0] io_addr, // @[PMP.scala:146:14]
input [1:0] io_size, // @[PMP.scala:146:14]
output io_r, // @[PMP.scala:146:14]
output io_w, // @[PMP.scala:146:14]
output io_x // @[PMP.scala:146:14]
);
wire [1:0] io_prv_0 = io_prv; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_l_0 = io_pmp_0_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_0_cfg_a_0 = io_pmp_0_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_x_0 = io_pmp_0_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_w_0 = io_pmp_0_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_0_cfg_r_0 = io_pmp_0_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_0_addr_0 = io_pmp_0_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_0_mask_0 = io_pmp_0_mask; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_l_0 = io_pmp_1_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_a_0 = io_pmp_1_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_x_0 = io_pmp_1_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_w_0 = io_pmp_1_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_1_cfg_r_0 = io_pmp_1_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_1_addr_0 = io_pmp_1_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_1_mask_0 = io_pmp_1_mask; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_l_0 = io_pmp_2_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_a_0 = io_pmp_2_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_x_0 = io_pmp_2_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_w_0 = io_pmp_2_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_2_cfg_r_0 = io_pmp_2_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_2_addr_0 = io_pmp_2_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_2_mask_0 = io_pmp_2_mask; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_l_0 = io_pmp_3_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_a_0 = io_pmp_3_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_x_0 = io_pmp_3_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_w_0 = io_pmp_3_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_3_cfg_r_0 = io_pmp_3_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_3_addr_0 = io_pmp_3_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_3_mask_0 = io_pmp_3_mask; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_l_0 = io_pmp_4_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_a_0 = io_pmp_4_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_x_0 = io_pmp_4_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_w_0 = io_pmp_4_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_4_cfg_r_0 = io_pmp_4_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_4_addr_0 = io_pmp_4_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_4_mask_0 = io_pmp_4_mask; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_l_0 = io_pmp_5_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_a_0 = io_pmp_5_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_x_0 = io_pmp_5_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_w_0 = io_pmp_5_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_5_cfg_r_0 = io_pmp_5_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_5_addr_0 = io_pmp_5_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_5_mask_0 = io_pmp_5_mask; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_l_0 = io_pmp_6_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_a_0 = io_pmp_6_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_x_0 = io_pmp_6_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_w_0 = io_pmp_6_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_6_cfg_r_0 = io_pmp_6_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_6_addr_0 = io_pmp_6_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_6_mask_0 = io_pmp_6_mask; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_l_0 = io_pmp_7_cfg_l; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_a_0 = io_pmp_7_cfg_a; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_x_0 = io_pmp_7_cfg_x; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_w_0 = io_pmp_7_cfg_w; // @[PMP.scala:143:7]
wire io_pmp_7_cfg_r_0 = io_pmp_7_cfg_r; // @[PMP.scala:143:7]
wire [29:0] io_pmp_7_addr_0 = io_pmp_7_addr; // @[PMP.scala:143:7]
wire [31:0] io_pmp_7_mask_0 = io_pmp_7_mask; // @[PMP.scala:143:7]
wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7]
wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7]
wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35]
wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22]
wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5]
wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:80:52, :81:54, :123:67]
wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}]
wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35]
wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22]
wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27]
wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27]
wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:82:64, :123:{108,125}]
wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35]
wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35]
wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22]
wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39]
wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53]
wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30]
wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16]
wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147]
wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7]
wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35]
wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35]
wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22]
wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22]
wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23]
wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8]
wire _res_T_319 = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_7_cfg_l = io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_7_cfg_a = io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_7_addr = io_pmp_0_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_7_mask = io_pmp_0_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_274 = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_6_cfg_l = io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_6_cfg_a = io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_6_addr = io_pmp_1_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_6_mask = io_pmp_1_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_229 = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_5_cfg_l = io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_5_cfg_a = io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_5_addr = io_pmp_2_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_5_mask = io_pmp_2_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_184 = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_4_cfg_l = io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_4_cfg_a = io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_4_addr = io_pmp_3_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_4_mask = io_pmp_3_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_139 = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_3_cfg_l = io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_3_cfg_a = io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_3_addr = io_pmp_4_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_3_mask = io_pmp_4_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_94 = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_2_cfg_l = io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_2_cfg_a = io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_2_addr = io_pmp_5_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_2_mask = io_pmp_5_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_49 = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_1_cfg_l = io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_1_cfg_a = io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_1_addr = io_pmp_6_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_1_mask = io_pmp_6_mask_0; // @[PMP.scala:143:7, :181:23]
wire _res_T_4 = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :170:30]
wire res_cur_cfg_l = io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :181:23]
wire [1:0] res_cur_cfg_a = io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :181:23]
wire [29:0] res_cur_addr = io_pmp_7_addr_0; // @[PMP.scala:143:7, :181:23]
wire [31:0] res_cur_mask = io_pmp_7_mask_0; // @[PMP.scala:143:7, :181:23]
wire res_cfg_r; // @[PMP.scala:185:8]
wire res_cfg_w; // @[PMP.scala:185:8]
wire res_cfg_x; // @[PMP.scala:185:8]
wire io_r_0; // @[PMP.scala:143:7]
wire io_w_0; // @[PMP.scala:143:7]
wire io_x_0; // @[PMP.scala:143:7]
wire default_0 = io_prv_0[1]; // @[PMP.scala:143:7, :156:56]
wire pmp0_cfg_x = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_w = default_0; // @[PMP.scala:156:56, :157:22]
wire pmp0_cfg_r = default_0; // @[PMP.scala:156:56, :157:22]
wire _res_hit_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T = io_pmp_7_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71]
assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_3; // @[package.scala:243:71]
assign _res_hit_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_16; // @[package.scala:243:71]
assign _res_hit_T_16 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_29; // @[package.scala:243:71]
assign _res_hit_T_29 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_42; // @[package.scala:243:71]
assign _res_hit_T_42 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_55; // @[package.scala:243:71]
assign _res_hit_T_55 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_68; // @[package.scala:243:71]
assign _res_hit_T_68 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_81; // @[package.scala:243:71]
assign _res_hit_T_81 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71]
assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_hit_T_94; // @[package.scala:243:71]
assign _res_hit_T_94 = _GEN; // @[package.scala:243:71]
wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71]
assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71]
wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_6 = io_pmp_7_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T = io_pmp_7_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask = {_res_hit_msbMatch_T_6, _res_aligned_pow2Aligned_T | _res_hit_lsbMask_T_2}; // @[package.scala:243:46]
wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7]
wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7]
wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7]
wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7]
wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7]
wire [31:0] _GEN_0 = {io_pmp_7_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_1; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_7; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_7 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_8; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_9; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_9 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_1 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_8 = _GEN_0; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_2 = ~_res_hit_msbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_3 = {_res_hit_msbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_4 = ~_res_hit_msbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_5 = _res_hit_msbMatch_T_4[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T ^ _res_hit_msbMatch_T_5; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_8 = ~_res_hit_msbMatch_T_6; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7 & _res_hit_msbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7]
wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7]
wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7]
wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7]
wire [31:0] _res_hit_lsbMatch_T_2 = ~_res_hit_lsbMatch_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_3 = {_res_hit_lsbMatch_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_4 = ~_res_hit_lsbMatch_T_3; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_5 = _res_hit_lsbMatch_T_4[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T ^ _res_hit_lsbMatch_T_5; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_2 = io_pmp_7_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_1 = {io_pmp_6_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_1; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_2; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_2 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_1 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_8 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_11; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_11 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_19; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_19 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_22; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_22 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_23; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_23 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_18 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_25 = _GEN_1; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_2 = ~_res_hit_msbsLess_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_3 = {_res_hit_msbsLess_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_4 = ~_res_hit_msbsLess_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_5 = _res_hit_msbsLess_T_4[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess = _res_hit_msbsLess_T < _res_hit_msbsLess_T_5; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_2 = ~_res_hit_msbsEqual_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_3 = {_res_hit_msbsEqual_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_4 = ~_res_hit_msbsEqual_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_5 = _res_hit_msbsEqual_T_4[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T ^ _res_hit_msbsEqual_T_5; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_3 = ~_res_hit_lsbsLess_T_2; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_4 = {_res_hit_lsbsLess_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_5 = ~_res_hit_lsbsLess_T_4; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_6 = _res_hit_lsbsLess_T_5[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess = _res_hit_lsbsLess_T_1 < _res_hit_lsbsLess_T_6; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_6 = res_hit_msbsEqual & res_hit_lsbsLess; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_7 = res_hit_msbsLess | _res_hit_T_6; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_8 = ~_res_hit_T_7; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_8 = ~_res_hit_msbsLess_T_7; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_9 = {_res_hit_msbsLess_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_10 = ~_res_hit_msbsLess_T_9; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_11 = _res_hit_msbsLess_T_10[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_1 = _res_hit_msbsLess_T_6 < _res_hit_msbsLess_T_11; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_9 = ~_res_hit_msbsEqual_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_10 = {_res_hit_msbsEqual_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_11 = ~_res_hit_msbsEqual_T_10; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_12 = _res_hit_msbsEqual_T_11[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7 ^ _res_hit_msbsEqual_T_12; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_10 = ~_res_hit_lsbsLess_T_9; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_11 = {_res_hit_lsbsLess_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_12 = ~_res_hit_lsbsLess_T_11; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_13 = _res_hit_lsbsLess_T_12[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_1 = _res_hit_lsbsLess_T_8 < _res_hit_lsbsLess_T_13; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_9 = res_hit_msbsEqual_1 & res_hit_lsbsLess_1; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_10 = res_hit_msbsLess_1 | _res_hit_T_9; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_11 = _res_hit_T_8 & _res_hit_T_10; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_12 = _res_hit_T_2 & _res_hit_T_11; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit = _res_hit_T ? _res_hit_T_1 : _res_hit_T_12; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T = ~io_pmp_7_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore = default_0 & _res_ignore_T; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_2 = ~_res_aligned_straddlesLowerBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_3 = {_res_aligned_straddlesLowerBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_4 = ~_res_aligned_straddlesLowerBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_5 = _res_aligned_straddlesLowerBound_T_4[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T ^ _res_aligned_straddlesLowerBound_T_5; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_9 = ~_res_aligned_straddlesLowerBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_10 = {_res_aligned_straddlesLowerBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_11 = ~_res_aligned_straddlesLowerBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_12 = _res_aligned_straddlesLowerBound_T_11[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_15 = _res_aligned_straddlesLowerBound_T_12 & _res_aligned_straddlesLowerBound_T_14; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_16 = |_res_aligned_straddlesLowerBound_T_15; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound = _res_aligned_straddlesLowerBound_T_7 & _res_aligned_straddlesLowerBound_T_16; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_2 = ~_res_aligned_straddlesUpperBound_T_1; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_3 = {_res_aligned_straddlesUpperBound_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_4 = ~_res_aligned_straddlesUpperBound_T_3; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_5 = _res_aligned_straddlesUpperBound_T_4[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T ^ _res_aligned_straddlesUpperBound_T_5; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_9 = ~_res_aligned_straddlesUpperBound_T_8; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_10 = {_res_aligned_straddlesUpperBound_T_9[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_11 = ~_res_aligned_straddlesUpperBound_T_10; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_12 = _res_aligned_straddlesUpperBound_T_11[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_15 = _res_aligned_straddlesUpperBound_T_12 & _res_aligned_straddlesUpperBound_T_14; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_16 = |_res_aligned_straddlesUpperBound_T_15; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound = _res_aligned_straddlesUpperBound_T_7 & _res_aligned_straddlesUpperBound_T_16; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T = res_aligned_straddlesLowerBound | res_aligned_straddlesUpperBound; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned = ~_res_aligned_rangeAligned_T; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_1 = ~_res_aligned_pow2Aligned_T; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask & _res_aligned_pow2Aligned_T_1; // @[package.scala:243:46]
wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned = _res_aligned_T ? res_aligned_pow2Aligned : res_aligned_rangeAligned; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T = io_pmp_7_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_2 = io_pmp_7_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_1; // @[PMP.scala:168:32]
assign _res_T_1 = _GEN_2; // @[PMP.scala:168:32]
wire _res_T_20; // @[PMP.scala:177:61]
assign _res_T_20 = _GEN_2; // @[PMP.scala:168:32, :177:61]
wire _res_T_24; // @[PMP.scala:178:63]
assign _res_T_24 = _GEN_2; // @[PMP.scala:168:32, :178:63]
wire _GEN_3 = io_pmp_7_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_2; // @[PMP.scala:168:32]
assign _res_T_2 = _GEN_3; // @[PMP.scala:168:32]
wire _res_T_29; // @[PMP.scala:177:61]
assign _res_T_29 = _GEN_3; // @[PMP.scala:168:32, :177:61]
wire _res_T_33; // @[PMP.scala:178:63]
assign _res_T_33 = _GEN_3; // @[PMP.scala:168:32, :178:63]
wire _res_T_3 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_4 = {io_pmp_7_cfg_x_0, io_pmp_7_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi; // @[PMP.scala:174:26]
assign res_hi = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_1; // @[PMP.scala:174:26]
assign res_hi_1 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_2; // @[PMP.scala:174:26]
assign res_hi_2 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_3; // @[PMP.scala:174:26]
assign res_hi_3 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_4; // @[PMP.scala:174:26]
assign res_hi_4 = _GEN_4; // @[PMP.scala:174:26]
wire [1:0] res_hi_5; // @[PMP.scala:174:26]
assign res_hi_5 = _GEN_4; // @[PMP.scala:174:26]
wire [2:0] _res_T_5 = {res_hi, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_6 = _res_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_7 = {res_hi_1, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_8 = _res_T_7 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_9 = {res_hi_2, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_10 = _res_T_9 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_11 = {res_hi_3, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_12 = _res_T_11 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_13 = {res_hi_4, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_14 = _res_T_13 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_15 = {res_hi_5, io_pmp_7_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_16 = &_res_T_15; // @[PMP.scala:174:{26,60}]
wire _res_T_17 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_18 = _res_T_17 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_19 = _res_T_18 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_21 = _res_T_19 & _res_T_20; // @[PMP.scala:177:{37,48,61}]
wire _GEN_5 = io_pmp_7_cfg_l_0 & res_hit; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_22; // @[PMP.scala:178:32]
assign _res_T_22 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_31; // @[PMP.scala:178:32]
assign _res_T_31 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_40; // @[PMP.scala:178:32]
assign _res_T_40 = _GEN_5; // @[PMP.scala:178:32]
wire _res_T_23 = _res_T_22 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_25 = _res_T_23 & _res_T_24; // @[PMP.scala:178:{39,50,63}]
wire _res_T_26 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_27 = _res_T_26 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_28 = _res_T_27 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_30 = _res_T_28 & _res_T_29; // @[PMP.scala:177:{37,48,61}]
wire _res_T_32 = _res_T_31 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_34 = _res_T_32 & _res_T_33; // @[PMP.scala:178:{39,50,63}]
wire _res_T_35 = ~res_ignore; // @[PMP.scala:164:26, :177:22]
wire _res_T_36 = _res_T_35 & res_hit; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_37 = _res_T_36 & res_aligned; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_38 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_39 = _res_T_37 & _res_T_38; // @[PMP.scala:177:{37,48,61}]
wire _res_T_41 = _res_T_40 & res_aligned; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_42 = &io_pmp_7_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_43 = _res_T_41 & _res_T_42; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_1; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_1; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_1; // @[PMP.scala:182:26]
wire res_cur_cfg_x; // @[PMP.scala:181:23]
wire res_cur_cfg_w; // @[PMP.scala:181:23]
wire res_cur_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T = io_pmp_7_cfg_r_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_1 = res_aligned & _res_cur_cfg_r_T; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_cfg_r = _res_cur_cfg_r_T_1; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T = io_pmp_7_cfg_w_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_1 = res_aligned & _res_cur_cfg_w_T; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_cfg_w = _res_cur_cfg_w_T_1; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T = io_pmp_7_cfg_x_0 | res_ignore; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_1 = res_aligned & _res_cur_cfg_x_T; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_cfg_x = _res_cur_cfg_x_T_1; // @[PMP.scala:181:23, :184:26]
wire _res_T_44_cfg_l = res_hit & res_cur_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_44_cfg_a = res_hit ? res_cur_cfg_a : 2'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_44_cfg_x = res_hit ? res_cur_cfg_x : pmp0_cfg_x; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_w = res_hit ? res_cur_cfg_w : pmp0_cfg_w; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire _res_T_44_cfg_r = res_hit ? res_cur_cfg_r : pmp0_cfg_r; // @[PMP.scala:132:8, :157:22, :181:23, :185:8]
wire [29:0] _res_T_44_addr = res_hit ? res_cur_addr : 30'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_44_mask = res_hit ? res_cur_mask : 32'h0; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_13 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_1 = io_pmp_6_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_16 = io_pmp_6_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_3 = io_pmp_6_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_1 = {_res_hit_msbMatch_T_16, _res_aligned_pow2Aligned_T_3 | _res_hit_lsbMask_T_5}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_12 = ~_res_hit_msbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_13 = {_res_hit_msbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_14 = ~_res_hit_msbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_15 = _res_hit_msbMatch_T_14[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10 ^ _res_hit_msbMatch_T_15; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_18 = ~_res_hit_msbMatch_T_16; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17 & _res_hit_msbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_12 = ~_res_hit_lsbMatch_T_11; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_13 = {_res_hit_lsbMatch_T_12[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_14 = ~_res_hit_lsbMatch_T_13; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_15 = _res_hit_lsbMatch_T_14[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10 ^ _res_hit_lsbMatch_T_15; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_15 = io_pmp_6_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_6 = {io_pmp_5_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_13; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_13 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_15; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_15 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_16; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_16 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_18 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_25 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_21; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_21 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_31 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_36; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_36 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_37 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_35 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_42 = _GEN_6; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_14 = ~_res_hit_msbsLess_T_13; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_15 = {_res_hit_msbsLess_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_16 = ~_res_hit_msbsLess_T_15; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_17 = _res_hit_msbsLess_T_16[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_2 = _res_hit_msbsLess_T_12 < _res_hit_msbsLess_T_17; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_16 = ~_res_hit_msbsEqual_T_15; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_17 = {_res_hit_msbsEqual_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_18 = ~_res_hit_msbsEqual_T_17; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_19 = _res_hit_msbsEqual_T_18[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14 ^ _res_hit_msbsEqual_T_19; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_17 = ~_res_hit_lsbsLess_T_16; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_18 = {_res_hit_lsbsLess_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_19 = ~_res_hit_lsbsLess_T_18; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_20 = _res_hit_lsbsLess_T_19[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_2 = _res_hit_lsbsLess_T_15 < _res_hit_lsbsLess_T_20; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_19 = res_hit_msbsEqual_2 & res_hit_lsbsLess_2; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_20 = res_hit_msbsLess_2 | _res_hit_T_19; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_21 = ~_res_hit_T_20; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_20 = ~_res_hit_msbsLess_T_19; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_21 = {_res_hit_msbsLess_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_22 = ~_res_hit_msbsLess_T_21; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_23 = _res_hit_msbsLess_T_22[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_3 = _res_hit_msbsLess_T_18 < _res_hit_msbsLess_T_23; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_23 = ~_res_hit_msbsEqual_T_22; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_24 = {_res_hit_msbsEqual_T_23[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_25 = ~_res_hit_msbsEqual_T_24; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_26 = _res_hit_msbsEqual_T_25[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21 ^ _res_hit_msbsEqual_T_26; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_24 = ~_res_hit_lsbsLess_T_23; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_25 = {_res_hit_lsbsLess_T_24[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_26 = ~_res_hit_lsbsLess_T_25; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_27 = _res_hit_lsbsLess_T_26[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_3 = _res_hit_lsbsLess_T_22 < _res_hit_lsbsLess_T_27; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_22 = res_hit_msbsEqual_3 & res_hit_lsbsLess_3; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_23 = res_hit_msbsLess_3 | _res_hit_T_22; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_24 = _res_hit_T_21 & _res_hit_T_23; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_25 = _res_hit_T_15 & _res_hit_T_24; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_1 = _res_hit_T_13 ? _res_hit_T_14 : _res_hit_T_25; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_1 = ~io_pmp_6_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_1 = default_0 & _res_ignore_T_1; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_19 = ~_res_aligned_straddlesLowerBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_20 = {_res_aligned_straddlesLowerBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_21 = ~_res_aligned_straddlesLowerBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_22 = _res_aligned_straddlesLowerBound_T_21[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17 ^ _res_aligned_straddlesLowerBound_T_22; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_26 = ~_res_aligned_straddlesLowerBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_27 = {_res_aligned_straddlesLowerBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_28 = ~_res_aligned_straddlesLowerBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_29 = _res_aligned_straddlesLowerBound_T_28[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_32 = _res_aligned_straddlesLowerBound_T_29 & _res_aligned_straddlesLowerBound_T_31; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_33 = |_res_aligned_straddlesLowerBound_T_32; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_1 = _res_aligned_straddlesLowerBound_T_24 & _res_aligned_straddlesLowerBound_T_33; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_19 = ~_res_aligned_straddlesUpperBound_T_18; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_20 = {_res_aligned_straddlesUpperBound_T_19[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_21 = ~_res_aligned_straddlesUpperBound_T_20; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_22 = _res_aligned_straddlesUpperBound_T_21[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17 ^ _res_aligned_straddlesUpperBound_T_22; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_26 = ~_res_aligned_straddlesUpperBound_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_27 = {_res_aligned_straddlesUpperBound_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_28 = ~_res_aligned_straddlesUpperBound_T_27; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_29 = _res_aligned_straddlesUpperBound_T_28[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_32 = _res_aligned_straddlesUpperBound_T_29 & _res_aligned_straddlesUpperBound_T_31; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_33 = |_res_aligned_straddlesUpperBound_T_32; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_1 = _res_aligned_straddlesUpperBound_T_24 & _res_aligned_straddlesUpperBound_T_33; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_1 = res_aligned_straddlesLowerBound_1 | res_aligned_straddlesUpperBound_1; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_1 = ~_res_aligned_rangeAligned_T_1; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_4 = ~_res_aligned_pow2Aligned_T_3; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1 & _res_aligned_pow2Aligned_T_4; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_1 = _res_aligned_T_1 ? res_aligned_pow2Aligned_1 : res_aligned_rangeAligned_1; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_45 = io_pmp_6_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_7 = io_pmp_6_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_46; // @[PMP.scala:168:32]
assign _res_T_46 = _GEN_7; // @[PMP.scala:168:32]
wire _res_T_65; // @[PMP.scala:177:61]
assign _res_T_65 = _GEN_7; // @[PMP.scala:168:32, :177:61]
wire _res_T_69; // @[PMP.scala:178:63]
assign _res_T_69 = _GEN_7; // @[PMP.scala:168:32, :178:63]
wire _GEN_8 = io_pmp_6_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_47; // @[PMP.scala:168:32]
assign _res_T_47 = _GEN_8; // @[PMP.scala:168:32]
wire _res_T_74; // @[PMP.scala:177:61]
assign _res_T_74 = _GEN_8; // @[PMP.scala:168:32, :177:61]
wire _res_T_78; // @[PMP.scala:178:63]
assign _res_T_78 = _GEN_8; // @[PMP.scala:168:32, :178:63]
wire _res_T_48 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_9 = {io_pmp_6_cfg_x_0, io_pmp_6_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_6; // @[PMP.scala:174:26]
assign res_hi_6 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_7; // @[PMP.scala:174:26]
assign res_hi_7 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_8; // @[PMP.scala:174:26]
assign res_hi_8 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_9; // @[PMP.scala:174:26]
assign res_hi_9 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_10; // @[PMP.scala:174:26]
assign res_hi_10 = _GEN_9; // @[PMP.scala:174:26]
wire [1:0] res_hi_11; // @[PMP.scala:174:26]
assign res_hi_11 = _GEN_9; // @[PMP.scala:174:26]
wire [2:0] _res_T_50 = {res_hi_6, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_51 = _res_T_50 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_52 = {res_hi_7, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_53 = _res_T_52 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_54 = {res_hi_8, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_55 = _res_T_54 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_56 = {res_hi_9, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_57 = _res_T_56 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_58 = {res_hi_10, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_59 = _res_T_58 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_60 = {res_hi_11, io_pmp_6_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_61 = &_res_T_60; // @[PMP.scala:174:{26,60}]
wire _res_T_62 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_63 = _res_T_62 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_64 = _res_T_63 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_66 = _res_T_64 & _res_T_65; // @[PMP.scala:177:{37,48,61}]
wire _GEN_10 = io_pmp_6_cfg_l_0 & res_hit_1; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_67; // @[PMP.scala:178:32]
assign _res_T_67 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_76; // @[PMP.scala:178:32]
assign _res_T_76 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_85; // @[PMP.scala:178:32]
assign _res_T_85 = _GEN_10; // @[PMP.scala:178:32]
wire _res_T_68 = _res_T_67 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_70 = _res_T_68 & _res_T_69; // @[PMP.scala:178:{39,50,63}]
wire _res_T_71 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_72 = _res_T_71 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_73 = _res_T_72 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_75 = _res_T_73 & _res_T_74; // @[PMP.scala:177:{37,48,61}]
wire _res_T_77 = _res_T_76 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_79 = _res_T_77 & _res_T_78; // @[PMP.scala:178:{39,50,63}]
wire _res_T_80 = ~res_ignore_1; // @[PMP.scala:164:26, :177:22]
wire _res_T_81 = _res_T_80 & res_hit_1; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_82 = _res_T_81 & res_aligned_1; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_83 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_84 = _res_T_82 & _res_T_83; // @[PMP.scala:177:{37,48,61}]
wire _res_T_86 = _res_T_85 & res_aligned_1; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_87 = &io_pmp_6_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_88 = _res_T_86 & _res_T_87; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_3; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_3; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_3; // @[PMP.scala:182:26]
wire res_cur_1_cfg_x; // @[PMP.scala:181:23]
wire res_cur_1_cfg_w; // @[PMP.scala:181:23]
wire res_cur_1_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_2 = io_pmp_6_cfg_r_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_3 = res_aligned_1 & _res_cur_cfg_r_T_2; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_1_cfg_r = _res_cur_cfg_r_T_3; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_2 = io_pmp_6_cfg_w_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_3 = res_aligned_1 & _res_cur_cfg_w_T_2; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_1_cfg_w = _res_cur_cfg_w_T_3; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_2 = io_pmp_6_cfg_x_0 | res_ignore_1; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_3 = res_aligned_1 & _res_cur_cfg_x_T_2; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_1_cfg_x = _res_cur_cfg_x_T_3; // @[PMP.scala:181:23, :184:26]
wire _res_T_89_cfg_l = res_hit_1 ? res_cur_1_cfg_l : _res_T_44_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_89_cfg_a = res_hit_1 ? res_cur_1_cfg_a : _res_T_44_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_x = res_hit_1 ? res_cur_1_cfg_x : _res_T_44_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_w = res_hit_1 ? res_cur_1_cfg_w : _res_T_44_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_89_cfg_r = res_hit_1 ? res_cur_1_cfg_r : _res_T_44_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_89_addr = res_hit_1 ? res_cur_1_addr : _res_T_44_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_89_mask = res_hit_1 ? res_cur_1_mask : _res_T_44_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_26 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_2 = io_pmp_5_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_26 = io_pmp_5_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_6 = io_pmp_5_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_2 = {_res_hit_msbMatch_T_26, _res_aligned_pow2Aligned_T_6 | _res_hit_lsbMask_T_8}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_22 = ~_res_hit_msbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_23 = {_res_hit_msbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_24 = ~_res_hit_msbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_25 = _res_hit_msbMatch_T_24[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20 ^ _res_hit_msbMatch_T_25; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_28 = ~_res_hit_msbMatch_T_26; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27 & _res_hit_msbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_22 = ~_res_hit_lsbMatch_T_21; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_23 = {_res_hit_lsbMatch_T_22[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_24 = ~_res_hit_lsbMatch_T_23; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_25 = _res_hit_lsbMatch_T_24[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20 ^ _res_hit_lsbMatch_T_25; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_28 = io_pmp_5_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_11 = {io_pmp_4_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_25; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_25 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_29; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_29 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_30; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_30 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_35 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_42 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_31; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_31 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_43 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_50; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_50 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_51 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_52 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_59 = _GEN_11; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_26 = ~_res_hit_msbsLess_T_25; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_27 = {_res_hit_msbsLess_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_28 = ~_res_hit_msbsLess_T_27; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_29 = _res_hit_msbsLess_T_28[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_4 = _res_hit_msbsLess_T_24 < _res_hit_msbsLess_T_29; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_30 = ~_res_hit_msbsEqual_T_29; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_31 = {_res_hit_msbsEqual_T_30[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_32 = ~_res_hit_msbsEqual_T_31; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_33 = _res_hit_msbsEqual_T_32[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28 ^ _res_hit_msbsEqual_T_33; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_31 = ~_res_hit_lsbsLess_T_30; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_32 = {_res_hit_lsbsLess_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_33 = ~_res_hit_lsbsLess_T_32; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_34 = _res_hit_lsbsLess_T_33[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_4 = _res_hit_lsbsLess_T_29 < _res_hit_lsbsLess_T_34; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_32 = res_hit_msbsEqual_4 & res_hit_lsbsLess_4; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_33 = res_hit_msbsLess_4 | _res_hit_T_32; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_34 = ~_res_hit_T_33; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_32 = ~_res_hit_msbsLess_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_33 = {_res_hit_msbsLess_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_34 = ~_res_hit_msbsLess_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_35 = _res_hit_msbsLess_T_34[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_5 = _res_hit_msbsLess_T_30 < _res_hit_msbsLess_T_35; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_37 = ~_res_hit_msbsEqual_T_36; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_38 = {_res_hit_msbsEqual_T_37[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_39 = ~_res_hit_msbsEqual_T_38; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_40 = _res_hit_msbsEqual_T_39[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35 ^ _res_hit_msbsEqual_T_40; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_38 = ~_res_hit_lsbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_39 = {_res_hit_lsbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_40 = ~_res_hit_lsbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_41 = _res_hit_lsbsLess_T_40[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_5 = _res_hit_lsbsLess_T_36 < _res_hit_lsbsLess_T_41; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_35 = res_hit_msbsEqual_5 & res_hit_lsbsLess_5; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_36 = res_hit_msbsLess_5 | _res_hit_T_35; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_37 = _res_hit_T_34 & _res_hit_T_36; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_38 = _res_hit_T_28 & _res_hit_T_37; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_2 = _res_hit_T_26 ? _res_hit_T_27 : _res_hit_T_38; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_2 = ~io_pmp_5_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_2 = default_0 & _res_ignore_T_2; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_36 = ~_res_aligned_straddlesLowerBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_37 = {_res_aligned_straddlesLowerBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_38 = ~_res_aligned_straddlesLowerBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_39 = _res_aligned_straddlesLowerBound_T_38[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34 ^ _res_aligned_straddlesLowerBound_T_39; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_43 = ~_res_aligned_straddlesLowerBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_44 = {_res_aligned_straddlesLowerBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_45 = ~_res_aligned_straddlesLowerBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_46 = _res_aligned_straddlesLowerBound_T_45[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_49 = _res_aligned_straddlesLowerBound_T_46 & _res_aligned_straddlesLowerBound_T_48; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_50 = |_res_aligned_straddlesLowerBound_T_49; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_2 = _res_aligned_straddlesLowerBound_T_41 & _res_aligned_straddlesLowerBound_T_50; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_36 = ~_res_aligned_straddlesUpperBound_T_35; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_37 = {_res_aligned_straddlesUpperBound_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_38 = ~_res_aligned_straddlesUpperBound_T_37; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_39 = _res_aligned_straddlesUpperBound_T_38[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34 ^ _res_aligned_straddlesUpperBound_T_39; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_43 = ~_res_aligned_straddlesUpperBound_T_42; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_44 = {_res_aligned_straddlesUpperBound_T_43[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_45 = ~_res_aligned_straddlesUpperBound_T_44; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_46 = _res_aligned_straddlesUpperBound_T_45[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_49 = _res_aligned_straddlesUpperBound_T_46 & _res_aligned_straddlesUpperBound_T_48; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_50 = |_res_aligned_straddlesUpperBound_T_49; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_2 = _res_aligned_straddlesUpperBound_T_41 & _res_aligned_straddlesUpperBound_T_50; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_2 = res_aligned_straddlesLowerBound_2 | res_aligned_straddlesUpperBound_2; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_2 = ~_res_aligned_rangeAligned_T_2; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_7 = ~_res_aligned_pow2Aligned_T_6; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2 & _res_aligned_pow2Aligned_T_7; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_2 = _res_aligned_T_2 ? res_aligned_pow2Aligned_2 : res_aligned_rangeAligned_2; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_90 = io_pmp_5_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_12 = io_pmp_5_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_91; // @[PMP.scala:168:32]
assign _res_T_91 = _GEN_12; // @[PMP.scala:168:32]
wire _res_T_110; // @[PMP.scala:177:61]
assign _res_T_110 = _GEN_12; // @[PMP.scala:168:32, :177:61]
wire _res_T_114; // @[PMP.scala:178:63]
assign _res_T_114 = _GEN_12; // @[PMP.scala:168:32, :178:63]
wire _GEN_13 = io_pmp_5_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_92; // @[PMP.scala:168:32]
assign _res_T_92 = _GEN_13; // @[PMP.scala:168:32]
wire _res_T_119; // @[PMP.scala:177:61]
assign _res_T_119 = _GEN_13; // @[PMP.scala:168:32, :177:61]
wire _res_T_123; // @[PMP.scala:178:63]
assign _res_T_123 = _GEN_13; // @[PMP.scala:168:32, :178:63]
wire _res_T_93 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_14 = {io_pmp_5_cfg_x_0, io_pmp_5_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_12; // @[PMP.scala:174:26]
assign res_hi_12 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_13; // @[PMP.scala:174:26]
assign res_hi_13 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_14; // @[PMP.scala:174:26]
assign res_hi_14 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_15; // @[PMP.scala:174:26]
assign res_hi_15 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_16; // @[PMP.scala:174:26]
assign res_hi_16 = _GEN_14; // @[PMP.scala:174:26]
wire [1:0] res_hi_17; // @[PMP.scala:174:26]
assign res_hi_17 = _GEN_14; // @[PMP.scala:174:26]
wire [2:0] _res_T_95 = {res_hi_12, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_96 = _res_T_95 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_97 = {res_hi_13, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_98 = _res_T_97 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_99 = {res_hi_14, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_100 = _res_T_99 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_101 = {res_hi_15, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_102 = _res_T_101 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_103 = {res_hi_16, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_104 = _res_T_103 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_105 = {res_hi_17, io_pmp_5_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_106 = &_res_T_105; // @[PMP.scala:174:{26,60}]
wire _res_T_107 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_108 = _res_T_107 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_109 = _res_T_108 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_111 = _res_T_109 & _res_T_110; // @[PMP.scala:177:{37,48,61}]
wire _GEN_15 = io_pmp_5_cfg_l_0 & res_hit_2; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_112; // @[PMP.scala:178:32]
assign _res_T_112 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_121; // @[PMP.scala:178:32]
assign _res_T_121 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_130; // @[PMP.scala:178:32]
assign _res_T_130 = _GEN_15; // @[PMP.scala:178:32]
wire _res_T_113 = _res_T_112 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_115 = _res_T_113 & _res_T_114; // @[PMP.scala:178:{39,50,63}]
wire _res_T_116 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_117 = _res_T_116 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_118 = _res_T_117 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_120 = _res_T_118 & _res_T_119; // @[PMP.scala:177:{37,48,61}]
wire _res_T_122 = _res_T_121 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_124 = _res_T_122 & _res_T_123; // @[PMP.scala:178:{39,50,63}]
wire _res_T_125 = ~res_ignore_2; // @[PMP.scala:164:26, :177:22]
wire _res_T_126 = _res_T_125 & res_hit_2; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_127 = _res_T_126 & res_aligned_2; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_128 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_129 = _res_T_127 & _res_T_128; // @[PMP.scala:177:{37,48,61}]
wire _res_T_131 = _res_T_130 & res_aligned_2; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_132 = &io_pmp_5_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_133 = _res_T_131 & _res_T_132; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_5; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_5; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_5; // @[PMP.scala:182:26]
wire res_cur_2_cfg_x; // @[PMP.scala:181:23]
wire res_cur_2_cfg_w; // @[PMP.scala:181:23]
wire res_cur_2_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_4 = io_pmp_5_cfg_r_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_5 = res_aligned_2 & _res_cur_cfg_r_T_4; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_2_cfg_r = _res_cur_cfg_r_T_5; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_4 = io_pmp_5_cfg_w_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_5 = res_aligned_2 & _res_cur_cfg_w_T_4; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_2_cfg_w = _res_cur_cfg_w_T_5; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_4 = io_pmp_5_cfg_x_0 | res_ignore_2; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_5 = res_aligned_2 & _res_cur_cfg_x_T_4; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_2_cfg_x = _res_cur_cfg_x_T_5; // @[PMP.scala:181:23, :184:26]
wire _res_T_134_cfg_l = res_hit_2 ? res_cur_2_cfg_l : _res_T_89_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_134_cfg_a = res_hit_2 ? res_cur_2_cfg_a : _res_T_89_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_x = res_hit_2 ? res_cur_2_cfg_x : _res_T_89_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_w = res_hit_2 ? res_cur_2_cfg_w : _res_T_89_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_134_cfg_r = res_hit_2 ? res_cur_2_cfg_r : _res_T_89_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_134_addr = res_hit_2 ? res_cur_2_addr : _res_T_89_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_134_mask = res_hit_2 ? res_cur_2_mask : _res_T_89_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_39 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_3 = io_pmp_4_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_36 = io_pmp_4_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_9 = io_pmp_4_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_3 = {_res_hit_msbMatch_T_36, _res_aligned_pow2Aligned_T_9 | _res_hit_lsbMask_T_11}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_32 = ~_res_hit_msbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_33 = {_res_hit_msbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_34 = ~_res_hit_msbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_35 = _res_hit_msbMatch_T_34[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30 ^ _res_hit_msbMatch_T_35; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_38 = ~_res_hit_msbMatch_T_36; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37 & _res_hit_msbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_32 = ~_res_hit_lsbMatch_T_31; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_33 = {_res_hit_lsbMatch_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_34 = ~_res_hit_lsbMatch_T_33; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_35 = _res_hit_lsbMatch_T_34[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30 ^ _res_hit_lsbMatch_T_35; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_41 = io_pmp_4_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_16 = {io_pmp_3_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_37; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_37 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_43; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_43 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_44; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_44 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_52 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_59 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_41; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_41 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_55; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_55 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_64; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_64 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_65; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_65 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_69 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_76 = _GEN_16; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_38 = ~_res_hit_msbsLess_T_37; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_39 = {_res_hit_msbsLess_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_40 = ~_res_hit_msbsLess_T_39; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_41 = _res_hit_msbsLess_T_40[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_6 = _res_hit_msbsLess_T_36 < _res_hit_msbsLess_T_41; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_44 = ~_res_hit_msbsEqual_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_45 = {_res_hit_msbsEqual_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_46 = ~_res_hit_msbsEqual_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_47 = _res_hit_msbsEqual_T_46[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42 ^ _res_hit_msbsEqual_T_47; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_45 = ~_res_hit_lsbsLess_T_44; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_46 = {_res_hit_lsbsLess_T_45[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_47 = ~_res_hit_lsbsLess_T_46; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_48 = _res_hit_lsbsLess_T_47[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_6 = _res_hit_lsbsLess_T_43 < _res_hit_lsbsLess_T_48; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_45 = res_hit_msbsEqual_6 & res_hit_lsbsLess_6; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_46 = res_hit_msbsLess_6 | _res_hit_T_45; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_47 = ~_res_hit_T_46; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_44 = ~_res_hit_msbsLess_T_43; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_45 = {_res_hit_msbsLess_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_46 = ~_res_hit_msbsLess_T_45; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_47 = _res_hit_msbsLess_T_46[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_7 = _res_hit_msbsLess_T_42 < _res_hit_msbsLess_T_47; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_51 = ~_res_hit_msbsEqual_T_50; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_52 = {_res_hit_msbsEqual_T_51[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_53 = ~_res_hit_msbsEqual_T_52; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_54 = _res_hit_msbsEqual_T_53[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49 ^ _res_hit_msbsEqual_T_54; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_52 = ~_res_hit_lsbsLess_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_53 = {_res_hit_lsbsLess_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_54 = ~_res_hit_lsbsLess_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_55 = _res_hit_lsbsLess_T_54[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_7 = _res_hit_lsbsLess_T_50 < _res_hit_lsbsLess_T_55; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_48 = res_hit_msbsEqual_7 & res_hit_lsbsLess_7; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_49 = res_hit_msbsLess_7 | _res_hit_T_48; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_50 = _res_hit_T_47 & _res_hit_T_49; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_51 = _res_hit_T_41 & _res_hit_T_50; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_3 = _res_hit_T_39 ? _res_hit_T_40 : _res_hit_T_51; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_3 = ~io_pmp_4_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_3 = default_0 & _res_ignore_T_3; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_53 = ~_res_aligned_straddlesLowerBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_54 = {_res_aligned_straddlesLowerBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_55 = ~_res_aligned_straddlesLowerBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_56 = _res_aligned_straddlesLowerBound_T_55[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51 ^ _res_aligned_straddlesLowerBound_T_56; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_60 = ~_res_aligned_straddlesLowerBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_61 = {_res_aligned_straddlesLowerBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_62 = ~_res_aligned_straddlesLowerBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_63 = _res_aligned_straddlesLowerBound_T_62[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_66 = _res_aligned_straddlesLowerBound_T_63 & _res_aligned_straddlesLowerBound_T_65; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_67 = |_res_aligned_straddlesLowerBound_T_66; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_3 = _res_aligned_straddlesLowerBound_T_58 & _res_aligned_straddlesLowerBound_T_67; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_53 = ~_res_aligned_straddlesUpperBound_T_52; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_54 = {_res_aligned_straddlesUpperBound_T_53[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_55 = ~_res_aligned_straddlesUpperBound_T_54; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_56 = _res_aligned_straddlesUpperBound_T_55[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51 ^ _res_aligned_straddlesUpperBound_T_56; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_60 = ~_res_aligned_straddlesUpperBound_T_59; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_61 = {_res_aligned_straddlesUpperBound_T_60[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_62 = ~_res_aligned_straddlesUpperBound_T_61; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_63 = _res_aligned_straddlesUpperBound_T_62[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_66 = _res_aligned_straddlesUpperBound_T_63 & _res_aligned_straddlesUpperBound_T_65; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_67 = |_res_aligned_straddlesUpperBound_T_66; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_3 = _res_aligned_straddlesUpperBound_T_58 & _res_aligned_straddlesUpperBound_T_67; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_3 = res_aligned_straddlesLowerBound_3 | res_aligned_straddlesUpperBound_3; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_3 = ~_res_aligned_rangeAligned_T_3; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_10 = ~_res_aligned_pow2Aligned_T_9; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3 & _res_aligned_pow2Aligned_T_10; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_3 = _res_aligned_T_3 ? res_aligned_pow2Aligned_3 : res_aligned_rangeAligned_3; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_135 = io_pmp_4_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_17 = io_pmp_4_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_136; // @[PMP.scala:168:32]
assign _res_T_136 = _GEN_17; // @[PMP.scala:168:32]
wire _res_T_155; // @[PMP.scala:177:61]
assign _res_T_155 = _GEN_17; // @[PMP.scala:168:32, :177:61]
wire _res_T_159; // @[PMP.scala:178:63]
assign _res_T_159 = _GEN_17; // @[PMP.scala:168:32, :178:63]
wire _GEN_18 = io_pmp_4_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_137; // @[PMP.scala:168:32]
assign _res_T_137 = _GEN_18; // @[PMP.scala:168:32]
wire _res_T_164; // @[PMP.scala:177:61]
assign _res_T_164 = _GEN_18; // @[PMP.scala:168:32, :177:61]
wire _res_T_168; // @[PMP.scala:178:63]
assign _res_T_168 = _GEN_18; // @[PMP.scala:168:32, :178:63]
wire _res_T_138 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_19 = {io_pmp_4_cfg_x_0, io_pmp_4_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_18; // @[PMP.scala:174:26]
assign res_hi_18 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_19; // @[PMP.scala:174:26]
assign res_hi_19 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_20; // @[PMP.scala:174:26]
assign res_hi_20 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_21; // @[PMP.scala:174:26]
assign res_hi_21 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_22; // @[PMP.scala:174:26]
assign res_hi_22 = _GEN_19; // @[PMP.scala:174:26]
wire [1:0] res_hi_23; // @[PMP.scala:174:26]
assign res_hi_23 = _GEN_19; // @[PMP.scala:174:26]
wire [2:0] _res_T_140 = {res_hi_18, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_141 = _res_T_140 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_142 = {res_hi_19, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_143 = _res_T_142 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_144 = {res_hi_20, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_145 = _res_T_144 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_146 = {res_hi_21, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_147 = _res_T_146 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_148 = {res_hi_22, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_149 = _res_T_148 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_150 = {res_hi_23, io_pmp_4_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_151 = &_res_T_150; // @[PMP.scala:174:{26,60}]
wire _res_T_152 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_153 = _res_T_152 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_154 = _res_T_153 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_156 = _res_T_154 & _res_T_155; // @[PMP.scala:177:{37,48,61}]
wire _GEN_20 = io_pmp_4_cfg_l_0 & res_hit_3; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_157; // @[PMP.scala:178:32]
assign _res_T_157 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_166; // @[PMP.scala:178:32]
assign _res_T_166 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_175; // @[PMP.scala:178:32]
assign _res_T_175 = _GEN_20; // @[PMP.scala:178:32]
wire _res_T_158 = _res_T_157 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_160 = _res_T_158 & _res_T_159; // @[PMP.scala:178:{39,50,63}]
wire _res_T_161 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_162 = _res_T_161 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_163 = _res_T_162 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_165 = _res_T_163 & _res_T_164; // @[PMP.scala:177:{37,48,61}]
wire _res_T_167 = _res_T_166 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_169 = _res_T_167 & _res_T_168; // @[PMP.scala:178:{39,50,63}]
wire _res_T_170 = ~res_ignore_3; // @[PMP.scala:164:26, :177:22]
wire _res_T_171 = _res_T_170 & res_hit_3; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_172 = _res_T_171 & res_aligned_3; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_173 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_174 = _res_T_172 & _res_T_173; // @[PMP.scala:177:{37,48,61}]
wire _res_T_176 = _res_T_175 & res_aligned_3; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_177 = &io_pmp_4_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_178 = _res_T_176 & _res_T_177; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_7; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_7; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_7; // @[PMP.scala:182:26]
wire res_cur_3_cfg_x; // @[PMP.scala:181:23]
wire res_cur_3_cfg_w; // @[PMP.scala:181:23]
wire res_cur_3_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_6 = io_pmp_4_cfg_r_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_7 = res_aligned_3 & _res_cur_cfg_r_T_6; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_3_cfg_r = _res_cur_cfg_r_T_7; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_6 = io_pmp_4_cfg_w_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_7 = res_aligned_3 & _res_cur_cfg_w_T_6; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_3_cfg_w = _res_cur_cfg_w_T_7; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_6 = io_pmp_4_cfg_x_0 | res_ignore_3; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_7 = res_aligned_3 & _res_cur_cfg_x_T_6; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_3_cfg_x = _res_cur_cfg_x_T_7; // @[PMP.scala:181:23, :184:26]
wire _res_T_179_cfg_l = res_hit_3 ? res_cur_3_cfg_l : _res_T_134_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_179_cfg_a = res_hit_3 ? res_cur_3_cfg_a : _res_T_134_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_x = res_hit_3 ? res_cur_3_cfg_x : _res_T_134_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_w = res_hit_3 ? res_cur_3_cfg_w : _res_T_134_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_179_cfg_r = res_hit_3 ? res_cur_3_cfg_r : _res_T_134_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_179_addr = res_hit_3 ? res_cur_3_addr : _res_T_134_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_179_mask = res_hit_3 ? res_cur_3_mask : _res_T_134_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_52 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_4 = io_pmp_3_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_46 = io_pmp_3_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_12 = io_pmp_3_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_4 = {_res_hit_msbMatch_T_46, _res_aligned_pow2Aligned_T_12 | _res_hit_lsbMask_T_14}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_42 = ~_res_hit_msbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_43 = {_res_hit_msbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_44 = ~_res_hit_msbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_45 = _res_hit_msbMatch_T_44[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40 ^ _res_hit_msbMatch_T_45; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_48 = ~_res_hit_msbMatch_T_46; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47 & _res_hit_msbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_42 = ~_res_hit_lsbMatch_T_41; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_43 = {_res_hit_lsbMatch_T_42[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_44 = ~_res_hit_lsbMatch_T_43; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_45 = _res_hit_lsbMatch_T_44[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40 ^ _res_hit_lsbMatch_T_45; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_54 = io_pmp_3_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_21 = {io_pmp_2_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_49; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_49 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_57; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_57 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_58; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_58 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_69 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_76 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_51; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_51 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_67; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_67 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_78; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_78 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_79 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_86 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_93 = _GEN_21; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_50 = ~_res_hit_msbsLess_T_49; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_51 = {_res_hit_msbsLess_T_50[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_52 = ~_res_hit_msbsLess_T_51; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_53 = _res_hit_msbsLess_T_52[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_8 = _res_hit_msbsLess_T_48 < _res_hit_msbsLess_T_53; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_58 = ~_res_hit_msbsEqual_T_57; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_59 = {_res_hit_msbsEqual_T_58[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_60 = ~_res_hit_msbsEqual_T_59; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_61 = _res_hit_msbsEqual_T_60[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56 ^ _res_hit_msbsEqual_T_61; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_59 = ~_res_hit_lsbsLess_T_58; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_60 = {_res_hit_lsbsLess_T_59[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_61 = ~_res_hit_lsbsLess_T_60; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_62 = _res_hit_lsbsLess_T_61[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_8 = _res_hit_lsbsLess_T_57 < _res_hit_lsbsLess_T_62; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_58 = res_hit_msbsEqual_8 & res_hit_lsbsLess_8; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_59 = res_hit_msbsLess_8 | _res_hit_T_58; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_60 = ~_res_hit_T_59; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_56 = ~_res_hit_msbsLess_T_55; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_57 = {_res_hit_msbsLess_T_56[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_58 = ~_res_hit_msbsLess_T_57; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_59 = _res_hit_msbsLess_T_58[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_9 = _res_hit_msbsLess_T_54 < _res_hit_msbsLess_T_59; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_65 = ~_res_hit_msbsEqual_T_64; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_66 = {_res_hit_msbsEqual_T_65[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_67 = ~_res_hit_msbsEqual_T_66; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_68 = _res_hit_msbsEqual_T_67[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63 ^ _res_hit_msbsEqual_T_68; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_66 = ~_res_hit_lsbsLess_T_65; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_67 = {_res_hit_lsbsLess_T_66[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_68 = ~_res_hit_lsbsLess_T_67; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_69 = _res_hit_lsbsLess_T_68[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_9 = _res_hit_lsbsLess_T_64 < _res_hit_lsbsLess_T_69; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_61 = res_hit_msbsEqual_9 & res_hit_lsbsLess_9; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_62 = res_hit_msbsLess_9 | _res_hit_T_61; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_63 = _res_hit_T_60 & _res_hit_T_62; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_64 = _res_hit_T_54 & _res_hit_T_63; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_4 = _res_hit_T_52 ? _res_hit_T_53 : _res_hit_T_64; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_4 = ~io_pmp_3_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_4 = default_0 & _res_ignore_T_4; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_70 = ~_res_aligned_straddlesLowerBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_71 = {_res_aligned_straddlesLowerBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_72 = ~_res_aligned_straddlesLowerBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_73 = _res_aligned_straddlesLowerBound_T_72[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68 ^ _res_aligned_straddlesLowerBound_T_73; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_77 = ~_res_aligned_straddlesLowerBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_78 = {_res_aligned_straddlesLowerBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_79 = ~_res_aligned_straddlesLowerBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_80 = _res_aligned_straddlesLowerBound_T_79[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_83 = _res_aligned_straddlesLowerBound_T_80 & _res_aligned_straddlesLowerBound_T_82; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_84 = |_res_aligned_straddlesLowerBound_T_83; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_4 = _res_aligned_straddlesLowerBound_T_75 & _res_aligned_straddlesLowerBound_T_84; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_70 = ~_res_aligned_straddlesUpperBound_T_69; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_71 = {_res_aligned_straddlesUpperBound_T_70[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_72 = ~_res_aligned_straddlesUpperBound_T_71; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_73 = _res_aligned_straddlesUpperBound_T_72[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68 ^ _res_aligned_straddlesUpperBound_T_73; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_77 = ~_res_aligned_straddlesUpperBound_T_76; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_78 = {_res_aligned_straddlesUpperBound_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_79 = ~_res_aligned_straddlesUpperBound_T_78; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_80 = _res_aligned_straddlesUpperBound_T_79[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_83 = _res_aligned_straddlesUpperBound_T_80 & _res_aligned_straddlesUpperBound_T_82; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_84 = |_res_aligned_straddlesUpperBound_T_83; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_4 = _res_aligned_straddlesUpperBound_T_75 & _res_aligned_straddlesUpperBound_T_84; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_4 = res_aligned_straddlesLowerBound_4 | res_aligned_straddlesUpperBound_4; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_4 = ~_res_aligned_rangeAligned_T_4; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_13 = ~_res_aligned_pow2Aligned_T_12; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4 & _res_aligned_pow2Aligned_T_13; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_4 = _res_aligned_T_4 ? res_aligned_pow2Aligned_4 : res_aligned_rangeAligned_4; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_180 = io_pmp_3_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_22 = io_pmp_3_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_181; // @[PMP.scala:168:32]
assign _res_T_181 = _GEN_22; // @[PMP.scala:168:32]
wire _res_T_200; // @[PMP.scala:177:61]
assign _res_T_200 = _GEN_22; // @[PMP.scala:168:32, :177:61]
wire _res_T_204; // @[PMP.scala:178:63]
assign _res_T_204 = _GEN_22; // @[PMP.scala:168:32, :178:63]
wire _GEN_23 = io_pmp_3_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_182; // @[PMP.scala:168:32]
assign _res_T_182 = _GEN_23; // @[PMP.scala:168:32]
wire _res_T_209; // @[PMP.scala:177:61]
assign _res_T_209 = _GEN_23; // @[PMP.scala:168:32, :177:61]
wire _res_T_213; // @[PMP.scala:178:63]
assign _res_T_213 = _GEN_23; // @[PMP.scala:168:32, :178:63]
wire _res_T_183 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_24 = {io_pmp_3_cfg_x_0, io_pmp_3_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_24; // @[PMP.scala:174:26]
assign res_hi_24 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_25; // @[PMP.scala:174:26]
assign res_hi_25 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_26; // @[PMP.scala:174:26]
assign res_hi_26 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_27; // @[PMP.scala:174:26]
assign res_hi_27 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_28; // @[PMP.scala:174:26]
assign res_hi_28 = _GEN_24; // @[PMP.scala:174:26]
wire [1:0] res_hi_29; // @[PMP.scala:174:26]
assign res_hi_29 = _GEN_24; // @[PMP.scala:174:26]
wire [2:0] _res_T_185 = {res_hi_24, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_186 = _res_T_185 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_187 = {res_hi_25, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_188 = _res_T_187 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_189 = {res_hi_26, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_190 = _res_T_189 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_191 = {res_hi_27, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_192 = _res_T_191 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_193 = {res_hi_28, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_194 = _res_T_193 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_195 = {res_hi_29, io_pmp_3_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_196 = &_res_T_195; // @[PMP.scala:174:{26,60}]
wire _res_T_197 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_198 = _res_T_197 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_199 = _res_T_198 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_201 = _res_T_199 & _res_T_200; // @[PMP.scala:177:{37,48,61}]
wire _GEN_25 = io_pmp_3_cfg_l_0 & res_hit_4; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_202; // @[PMP.scala:178:32]
assign _res_T_202 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_211; // @[PMP.scala:178:32]
assign _res_T_211 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_220; // @[PMP.scala:178:32]
assign _res_T_220 = _GEN_25; // @[PMP.scala:178:32]
wire _res_T_203 = _res_T_202 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_205 = _res_T_203 & _res_T_204; // @[PMP.scala:178:{39,50,63}]
wire _res_T_206 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_207 = _res_T_206 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_208 = _res_T_207 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_210 = _res_T_208 & _res_T_209; // @[PMP.scala:177:{37,48,61}]
wire _res_T_212 = _res_T_211 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_214 = _res_T_212 & _res_T_213; // @[PMP.scala:178:{39,50,63}]
wire _res_T_215 = ~res_ignore_4; // @[PMP.scala:164:26, :177:22]
wire _res_T_216 = _res_T_215 & res_hit_4; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_217 = _res_T_216 & res_aligned_4; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_218 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_219 = _res_T_217 & _res_T_218; // @[PMP.scala:177:{37,48,61}]
wire _res_T_221 = _res_T_220 & res_aligned_4; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_222 = &io_pmp_3_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_223 = _res_T_221 & _res_T_222; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_9; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_9; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_9; // @[PMP.scala:182:26]
wire res_cur_4_cfg_x; // @[PMP.scala:181:23]
wire res_cur_4_cfg_w; // @[PMP.scala:181:23]
wire res_cur_4_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_8 = io_pmp_3_cfg_r_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_9 = res_aligned_4 & _res_cur_cfg_r_T_8; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_4_cfg_r = _res_cur_cfg_r_T_9; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_8 = io_pmp_3_cfg_w_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_9 = res_aligned_4 & _res_cur_cfg_w_T_8; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_4_cfg_w = _res_cur_cfg_w_T_9; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_8 = io_pmp_3_cfg_x_0 | res_ignore_4; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_9 = res_aligned_4 & _res_cur_cfg_x_T_8; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_4_cfg_x = _res_cur_cfg_x_T_9; // @[PMP.scala:181:23, :184:26]
wire _res_T_224_cfg_l = res_hit_4 ? res_cur_4_cfg_l : _res_T_179_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_224_cfg_a = res_hit_4 ? res_cur_4_cfg_a : _res_T_179_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_x = res_hit_4 ? res_cur_4_cfg_x : _res_T_179_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_w = res_hit_4 ? res_cur_4_cfg_w : _res_T_179_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_224_cfg_r = res_hit_4 ? res_cur_4_cfg_r : _res_T_179_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_224_addr = res_hit_4 ? res_cur_4_addr : _res_T_179_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_224_mask = res_hit_4 ? res_cur_4_mask : _res_T_179_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_65 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_5 = io_pmp_2_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_56 = io_pmp_2_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_15 = io_pmp_2_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_5 = {_res_hit_msbMatch_T_56, _res_aligned_pow2Aligned_T_15 | _res_hit_lsbMask_T_17}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_52 = ~_res_hit_msbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_53 = {_res_hit_msbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_54 = ~_res_hit_msbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_55 = _res_hit_msbMatch_T_54[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50 ^ _res_hit_msbMatch_T_55; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_58 = ~_res_hit_msbMatch_T_56; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57 & _res_hit_msbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_52 = ~_res_hit_lsbMatch_T_51; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_53 = {_res_hit_lsbMatch_T_52[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_54 = ~_res_hit_lsbMatch_T_53; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_55 = _res_hit_lsbMatch_T_54[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50 ^ _res_hit_lsbMatch_T_55; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_67 = io_pmp_2_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_26 = {io_pmp_1_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_71 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_72; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_72 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_86 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_61; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_61 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_79; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_79 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_92; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_92 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_93; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_93 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_103 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_110 = _GEN_26; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_62 = ~_res_hit_msbsLess_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_63 = {_res_hit_msbsLess_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_64 = ~_res_hit_msbsLess_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_65 = _res_hit_msbsLess_T_64[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_10 = _res_hit_msbsLess_T_60 < _res_hit_msbsLess_T_65; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_72 = ~_res_hit_msbsEqual_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_73 = {_res_hit_msbsEqual_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_74 = ~_res_hit_msbsEqual_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_75 = _res_hit_msbsEqual_T_74[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70 ^ _res_hit_msbsEqual_T_75; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_73 = ~_res_hit_lsbsLess_T_72; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_74 = {_res_hit_lsbsLess_T_73[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_75 = ~_res_hit_lsbsLess_T_74; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_76 = _res_hit_lsbsLess_T_75[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_10 = _res_hit_lsbsLess_T_71 < _res_hit_lsbsLess_T_76; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_71 = res_hit_msbsEqual_10 & res_hit_lsbsLess_10; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_72 = res_hit_msbsLess_10 | _res_hit_T_71; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_73 = ~_res_hit_T_72; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_68 = ~_res_hit_msbsLess_T_67; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_69 = {_res_hit_msbsLess_T_68[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_70 = ~_res_hit_msbsLess_T_69; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_71 = _res_hit_msbsLess_T_70[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_11 = _res_hit_msbsLess_T_66 < _res_hit_msbsLess_T_71; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_79 = ~_res_hit_msbsEqual_T_78; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_80 = {_res_hit_msbsEqual_T_79[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_81 = ~_res_hit_msbsEqual_T_80; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_82 = _res_hit_msbsEqual_T_81[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77 ^ _res_hit_msbsEqual_T_82; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_80 = ~_res_hit_lsbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_81 = {_res_hit_lsbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_82 = ~_res_hit_lsbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_83 = _res_hit_lsbsLess_T_82[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_11 = _res_hit_lsbsLess_T_78 < _res_hit_lsbsLess_T_83; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_74 = res_hit_msbsEqual_11 & res_hit_lsbsLess_11; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_75 = res_hit_msbsLess_11 | _res_hit_T_74; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_76 = _res_hit_T_73 & _res_hit_T_75; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_77 = _res_hit_T_67 & _res_hit_T_76; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_5 = _res_hit_T_65 ? _res_hit_T_66 : _res_hit_T_77; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_5 = ~io_pmp_2_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_5 = default_0 & _res_ignore_T_5; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_87 = ~_res_aligned_straddlesLowerBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_88 = {_res_aligned_straddlesLowerBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_89 = ~_res_aligned_straddlesLowerBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_90 = _res_aligned_straddlesLowerBound_T_89[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85 ^ _res_aligned_straddlesLowerBound_T_90; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_94 = ~_res_aligned_straddlesLowerBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_95 = {_res_aligned_straddlesLowerBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_96 = ~_res_aligned_straddlesLowerBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_97 = _res_aligned_straddlesLowerBound_T_96[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_100 = _res_aligned_straddlesLowerBound_T_97 & _res_aligned_straddlesLowerBound_T_99; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_101 = |_res_aligned_straddlesLowerBound_T_100; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_5 = _res_aligned_straddlesLowerBound_T_92 & _res_aligned_straddlesLowerBound_T_101; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_87 = ~_res_aligned_straddlesUpperBound_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_88 = {_res_aligned_straddlesUpperBound_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_89 = ~_res_aligned_straddlesUpperBound_T_88; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_90 = _res_aligned_straddlesUpperBound_T_89[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85 ^ _res_aligned_straddlesUpperBound_T_90; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_94 = ~_res_aligned_straddlesUpperBound_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_95 = {_res_aligned_straddlesUpperBound_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_96 = ~_res_aligned_straddlesUpperBound_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_97 = _res_aligned_straddlesUpperBound_T_96[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_100 = _res_aligned_straddlesUpperBound_T_97 & _res_aligned_straddlesUpperBound_T_99; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_101 = |_res_aligned_straddlesUpperBound_T_100; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_5 = _res_aligned_straddlesUpperBound_T_92 & _res_aligned_straddlesUpperBound_T_101; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_5 = res_aligned_straddlesLowerBound_5 | res_aligned_straddlesUpperBound_5; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_5 = ~_res_aligned_rangeAligned_T_5; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_16 = ~_res_aligned_pow2Aligned_T_15; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5 & _res_aligned_pow2Aligned_T_16; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_5 = _res_aligned_T_5 ? res_aligned_pow2Aligned_5 : res_aligned_rangeAligned_5; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_225 = io_pmp_2_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_27 = io_pmp_2_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_226; // @[PMP.scala:168:32]
assign _res_T_226 = _GEN_27; // @[PMP.scala:168:32]
wire _res_T_245; // @[PMP.scala:177:61]
assign _res_T_245 = _GEN_27; // @[PMP.scala:168:32, :177:61]
wire _res_T_249; // @[PMP.scala:178:63]
assign _res_T_249 = _GEN_27; // @[PMP.scala:168:32, :178:63]
wire _GEN_28 = io_pmp_2_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_227; // @[PMP.scala:168:32]
assign _res_T_227 = _GEN_28; // @[PMP.scala:168:32]
wire _res_T_254; // @[PMP.scala:177:61]
assign _res_T_254 = _GEN_28; // @[PMP.scala:168:32, :177:61]
wire _res_T_258; // @[PMP.scala:178:63]
assign _res_T_258 = _GEN_28; // @[PMP.scala:168:32, :178:63]
wire _res_T_228 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_29 = {io_pmp_2_cfg_x_0, io_pmp_2_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_30; // @[PMP.scala:174:26]
assign res_hi_30 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_31; // @[PMP.scala:174:26]
assign res_hi_31 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_32; // @[PMP.scala:174:26]
assign res_hi_32 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_33; // @[PMP.scala:174:26]
assign res_hi_33 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_34; // @[PMP.scala:174:26]
assign res_hi_34 = _GEN_29; // @[PMP.scala:174:26]
wire [1:0] res_hi_35; // @[PMP.scala:174:26]
assign res_hi_35 = _GEN_29; // @[PMP.scala:174:26]
wire [2:0] _res_T_230 = {res_hi_30, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_231 = _res_T_230 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_232 = {res_hi_31, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_233 = _res_T_232 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_234 = {res_hi_32, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_235 = _res_T_234 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_236 = {res_hi_33, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_237 = _res_T_236 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_238 = {res_hi_34, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_239 = _res_T_238 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_240 = {res_hi_35, io_pmp_2_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_241 = &_res_T_240; // @[PMP.scala:174:{26,60}]
wire _res_T_242 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_243 = _res_T_242 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_244 = _res_T_243 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_246 = _res_T_244 & _res_T_245; // @[PMP.scala:177:{37,48,61}]
wire _GEN_30 = io_pmp_2_cfg_l_0 & res_hit_5; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_247; // @[PMP.scala:178:32]
assign _res_T_247 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_256; // @[PMP.scala:178:32]
assign _res_T_256 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_265; // @[PMP.scala:178:32]
assign _res_T_265 = _GEN_30; // @[PMP.scala:178:32]
wire _res_T_248 = _res_T_247 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_250 = _res_T_248 & _res_T_249; // @[PMP.scala:178:{39,50,63}]
wire _res_T_251 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_252 = _res_T_251 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_253 = _res_T_252 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_255 = _res_T_253 & _res_T_254; // @[PMP.scala:177:{37,48,61}]
wire _res_T_257 = _res_T_256 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_259 = _res_T_257 & _res_T_258; // @[PMP.scala:178:{39,50,63}]
wire _res_T_260 = ~res_ignore_5; // @[PMP.scala:164:26, :177:22]
wire _res_T_261 = _res_T_260 & res_hit_5; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_262 = _res_T_261 & res_aligned_5; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_263 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_264 = _res_T_262 & _res_T_263; // @[PMP.scala:177:{37,48,61}]
wire _res_T_266 = _res_T_265 & res_aligned_5; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_267 = &io_pmp_2_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_268 = _res_T_266 & _res_T_267; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_11; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_11; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_11; // @[PMP.scala:182:26]
wire res_cur_5_cfg_x; // @[PMP.scala:181:23]
wire res_cur_5_cfg_w; // @[PMP.scala:181:23]
wire res_cur_5_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_10 = io_pmp_2_cfg_r_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_11 = res_aligned_5 & _res_cur_cfg_r_T_10; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_5_cfg_r = _res_cur_cfg_r_T_11; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_10 = io_pmp_2_cfg_w_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_11 = res_aligned_5 & _res_cur_cfg_w_T_10; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_5_cfg_w = _res_cur_cfg_w_T_11; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_10 = io_pmp_2_cfg_x_0 | res_ignore_5; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_11 = res_aligned_5 & _res_cur_cfg_x_T_10; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_5_cfg_x = _res_cur_cfg_x_T_11; // @[PMP.scala:181:23, :184:26]
wire _res_T_269_cfg_l = res_hit_5 ? res_cur_5_cfg_l : _res_T_224_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_269_cfg_a = res_hit_5 ? res_cur_5_cfg_a : _res_T_224_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_x = res_hit_5 ? res_cur_5_cfg_x : _res_T_224_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_w = res_hit_5 ? res_cur_5_cfg_w : _res_T_224_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_269_cfg_r = res_hit_5 ? res_cur_5_cfg_r : _res_T_224_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_269_addr = res_hit_5 ? res_cur_5_addr : _res_T_224_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_269_mask = res_hit_5 ? res_cur_5_mask : _res_T_224_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_78 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_6 = io_pmp_1_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_66 = io_pmp_1_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_18 = io_pmp_1_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_6 = {_res_hit_msbMatch_T_66, _res_aligned_pow2Aligned_T_18 | _res_hit_lsbMask_T_20}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_62 = ~_res_hit_msbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_63 = {_res_hit_msbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_64 = ~_res_hit_msbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_65 = _res_hit_msbMatch_T_64[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60 ^ _res_hit_msbMatch_T_65; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_68 = ~_res_hit_msbMatch_T_66; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67 & _res_hit_msbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_62 = ~_res_hit_lsbMatch_T_61; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_63 = {_res_hit_lsbMatch_T_62[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_64 = ~_res_hit_lsbMatch_T_63; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_65 = _res_hit_lsbMatch_T_64[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60 ^ _res_hit_lsbMatch_T_65; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_80 = io_pmp_1_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}]
wire [31:0] _GEN_31 = {io_pmp_0_addr_0, 2'h0}; // @[PMP.scala:60:36, :143:7]
wire [31:0] _res_hit_msbsLess_T_73; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_73 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_85; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_85 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_86; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_86 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_103 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:36]
assign _res_aligned_straddlesLowerBound_T_110 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_msbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbMatch_T_71; // @[PMP.scala:60:36]
assign _res_hit_lsbMatch_T_71 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_91; // @[PMP.scala:60:36]
assign _res_hit_msbsLess_T_91 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsEqual_T_106; // @[PMP.scala:60:36]
assign _res_hit_msbsEqual_T_106 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_lsbsLess_T_107; // @[PMP.scala:60:36]
assign _res_hit_lsbsLess_T_107 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_120 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:36]
assign _res_aligned_straddlesUpperBound_T_127 = _GEN_31; // @[PMP.scala:60:36]
wire [31:0] _res_hit_msbsLess_T_74 = ~_res_hit_msbsLess_T_73; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_75 = {_res_hit_msbsLess_T_74[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_76 = ~_res_hit_msbsLess_T_75; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_77 = _res_hit_msbsLess_T_76[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_12 = _res_hit_msbsLess_T_72 < _res_hit_msbsLess_T_77; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_86 = ~_res_hit_msbsEqual_T_85; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_87 = {_res_hit_msbsEqual_T_86[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_88 = ~_res_hit_msbsEqual_T_87; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_89 = _res_hit_msbsEqual_T_88[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84 ^ _res_hit_msbsEqual_T_89; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46]
wire [31:0] _res_hit_lsbsLess_T_87 = ~_res_hit_lsbsLess_T_86; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_88 = {_res_hit_lsbsLess_T_87[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_89 = ~_res_hit_lsbsLess_T_88; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_90 = _res_hit_lsbsLess_T_89[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_12 = _res_hit_lsbsLess_T_85 < _res_hit_lsbsLess_T_90; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_84 = res_hit_msbsEqual_12 & res_hit_lsbsLess_12; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_85 = res_hit_msbsLess_12 | _res_hit_T_84; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_86 = ~_res_hit_T_85; // @[PMP.scala:83:16, :88:5]
wire [31:0] _res_hit_msbsLess_T_80 = ~_res_hit_msbsLess_T_79; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_81 = {_res_hit_msbsLess_T_80[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_82 = ~_res_hit_msbsLess_T_81; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_83 = _res_hit_msbsLess_T_82[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_13 = _res_hit_msbsLess_T_78 < _res_hit_msbsLess_T_83; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_93 = ~_res_hit_msbsEqual_T_92; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_94 = {_res_hit_msbsEqual_T_93[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_95 = ~_res_hit_msbsEqual_T_94; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_96 = _res_hit_msbsEqual_T_95[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91 ^ _res_hit_msbsEqual_T_96; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_94 = ~_res_hit_lsbsLess_T_93; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_95 = {_res_hit_lsbsLess_T_94[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_96 = ~_res_hit_lsbsLess_T_95; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_97 = _res_hit_lsbsLess_T_96[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_13 = _res_hit_lsbsLess_T_92 < _res_hit_lsbsLess_T_97; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_87 = res_hit_msbsEqual_13 & res_hit_lsbsLess_13; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_88 = res_hit_msbsLess_13 | _res_hit_T_87; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_89 = _res_hit_T_86 & _res_hit_T_88; // @[PMP.scala:83:16, :88:5, :94:48]
wire _res_hit_T_90 = _res_hit_T_80 & _res_hit_T_89; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_6 = _res_hit_T_78 ? _res_hit_T_79 : _res_hit_T_90; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_6 = ~io_pmp_1_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_6 = default_0 & _res_ignore_T_6; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}]
wire [31:0] _res_aligned_straddlesLowerBound_T_104 = ~_res_aligned_straddlesLowerBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_105 = {_res_aligned_straddlesLowerBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_106 = ~_res_aligned_straddlesLowerBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesLowerBound_T_107 = _res_aligned_straddlesLowerBound_T_106[31:3]; // @[PMP.scala:60:27, :123:67]
wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102 ^ _res_aligned_straddlesLowerBound_T_107; // @[PMP.scala:123:{35,49,67}]
wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [31:0] _res_aligned_straddlesLowerBound_T_111 = ~_res_aligned_straddlesLowerBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesLowerBound_T_112 = {_res_aligned_straddlesLowerBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesLowerBound_T_113 = ~_res_aligned_straddlesLowerBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesLowerBound_T_114 = _res_aligned_straddlesLowerBound_T_113[2:0]; // @[PMP.scala:60:27, :123:108]
wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}]
wire [2:0] _res_aligned_straddlesLowerBound_T_117 = _res_aligned_straddlesLowerBound_T_114 & _res_aligned_straddlesLowerBound_T_116; // @[PMP.scala:123:{108,125,127}]
wire _res_aligned_straddlesLowerBound_T_118 = |_res_aligned_straddlesLowerBound_T_117; // @[PMP.scala:123:{125,147}]
wire res_aligned_straddlesLowerBound_6 = _res_aligned_straddlesLowerBound_T_109 & _res_aligned_straddlesLowerBound_T_118; // @[PMP.scala:123:{82,90,147}]
wire [31:0] _res_aligned_straddlesUpperBound_T_104 = ~_res_aligned_straddlesUpperBound_T_103; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_105 = {_res_aligned_straddlesUpperBound_T_104[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_106 = ~_res_aligned_straddlesUpperBound_T_105; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_107 = _res_aligned_straddlesUpperBound_T_106[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102 ^ _res_aligned_straddlesUpperBound_T_107; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_111 = ~_res_aligned_straddlesUpperBound_T_110; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_112 = {_res_aligned_straddlesUpperBound_T_111[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_113 = ~_res_aligned_straddlesUpperBound_T_112; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_114 = _res_aligned_straddlesUpperBound_T_113[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_117 = _res_aligned_straddlesUpperBound_T_114 & _res_aligned_straddlesUpperBound_T_116; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_118 = |_res_aligned_straddlesUpperBound_T_117; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_6 = _res_aligned_straddlesUpperBound_T_109 & _res_aligned_straddlesUpperBound_T_118; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_6 = res_aligned_straddlesLowerBound_6 | res_aligned_straddlesUpperBound_6; // @[PMP.scala:123:90, :124:85, :125:46]
wire res_aligned_rangeAligned_6 = ~_res_aligned_rangeAligned_T_6; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_19 = ~_res_aligned_pow2Aligned_T_18; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6 & _res_aligned_pow2Aligned_T_19; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_6 = _res_aligned_T_6 ? res_aligned_pow2Aligned_6 : res_aligned_rangeAligned_6; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_270 = io_pmp_1_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_32 = io_pmp_1_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_271; // @[PMP.scala:168:32]
assign _res_T_271 = _GEN_32; // @[PMP.scala:168:32]
wire _res_T_290; // @[PMP.scala:177:61]
assign _res_T_290 = _GEN_32; // @[PMP.scala:168:32, :177:61]
wire _res_T_294; // @[PMP.scala:178:63]
assign _res_T_294 = _GEN_32; // @[PMP.scala:168:32, :178:63]
wire _GEN_33 = io_pmp_1_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_272; // @[PMP.scala:168:32]
assign _res_T_272 = _GEN_33; // @[PMP.scala:168:32]
wire _res_T_299; // @[PMP.scala:177:61]
assign _res_T_299 = _GEN_33; // @[PMP.scala:168:32, :177:61]
wire _res_T_303; // @[PMP.scala:178:63]
assign _res_T_303 = _GEN_33; // @[PMP.scala:168:32, :178:63]
wire _res_T_273 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_34 = {io_pmp_1_cfg_x_0, io_pmp_1_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_36; // @[PMP.scala:174:26]
assign res_hi_36 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_37; // @[PMP.scala:174:26]
assign res_hi_37 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_38; // @[PMP.scala:174:26]
assign res_hi_38 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_39; // @[PMP.scala:174:26]
assign res_hi_39 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_40; // @[PMP.scala:174:26]
assign res_hi_40 = _GEN_34; // @[PMP.scala:174:26]
wire [1:0] res_hi_41; // @[PMP.scala:174:26]
assign res_hi_41 = _GEN_34; // @[PMP.scala:174:26]
wire [2:0] _res_T_275 = {res_hi_36, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_276 = _res_T_275 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_277 = {res_hi_37, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_278 = _res_T_277 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_279 = {res_hi_38, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_280 = _res_T_279 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_281 = {res_hi_39, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_282 = _res_T_281 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_283 = {res_hi_40, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_284 = _res_T_283 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_285 = {res_hi_41, io_pmp_1_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_286 = &_res_T_285; // @[PMP.scala:174:{26,60}]
wire _res_T_287 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_288 = _res_T_287 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_289 = _res_T_288 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_291 = _res_T_289 & _res_T_290; // @[PMP.scala:177:{37,48,61}]
wire _GEN_35 = io_pmp_1_cfg_l_0 & res_hit_6; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_292; // @[PMP.scala:178:32]
assign _res_T_292 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_301; // @[PMP.scala:178:32]
assign _res_T_301 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_310; // @[PMP.scala:178:32]
assign _res_T_310 = _GEN_35; // @[PMP.scala:178:32]
wire _res_T_293 = _res_T_292 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_295 = _res_T_293 & _res_T_294; // @[PMP.scala:178:{39,50,63}]
wire _res_T_296 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_297 = _res_T_296 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_298 = _res_T_297 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_300 = _res_T_298 & _res_T_299; // @[PMP.scala:177:{37,48,61}]
wire _res_T_302 = _res_T_301 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_304 = _res_T_302 & _res_T_303; // @[PMP.scala:178:{39,50,63}]
wire _res_T_305 = ~res_ignore_6; // @[PMP.scala:164:26, :177:22]
wire _res_T_306 = _res_T_305 & res_hit_6; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_307 = _res_T_306 & res_aligned_6; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_308 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_309 = _res_T_307 & _res_T_308; // @[PMP.scala:177:{37,48,61}]
wire _res_T_311 = _res_T_310 & res_aligned_6; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_312 = &io_pmp_1_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_313 = _res_T_311 & _res_T_312; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_13; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_13; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_13; // @[PMP.scala:182:26]
wire res_cur_6_cfg_x; // @[PMP.scala:181:23]
wire res_cur_6_cfg_w; // @[PMP.scala:181:23]
wire res_cur_6_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_12 = io_pmp_1_cfg_r_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_13 = res_aligned_6 & _res_cur_cfg_r_T_12; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_6_cfg_r = _res_cur_cfg_r_T_13; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_12 = io_pmp_1_cfg_w_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_13 = res_aligned_6 & _res_cur_cfg_w_T_12; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_6_cfg_w = _res_cur_cfg_w_T_13; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_12 = io_pmp_1_cfg_x_0 | res_ignore_6; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_13 = res_aligned_6 & _res_cur_cfg_x_T_12; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_6_cfg_x = _res_cur_cfg_x_T_13; // @[PMP.scala:181:23, :184:26]
wire _res_T_314_cfg_l = res_hit_6 ? res_cur_6_cfg_l : _res_T_269_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] _res_T_314_cfg_a = res_hit_6 ? res_cur_6_cfg_a : _res_T_269_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_x = res_hit_6 ? res_cur_6_cfg_x : _res_T_269_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_w = res_hit_6 ? res_cur_6_cfg_w : _res_T_269_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_T_314_cfg_r = res_hit_6 ? res_cur_6_cfg_r : _res_T_269_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] _res_T_314_addr = res_hit_6 ? res_cur_6_addr : _res_T_269_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] _res_T_314_mask = res_hit_6 ? res_cur_6_mask : _res_T_269_mask; // @[PMP.scala:132:8, :181:23, :185:8]
wire _res_hit_T_91 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire _res_aligned_T_7 = io_pmp_0_cfg_a_0[1]; // @[PMP.scala:45:20, :143:7]
wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbMatch_T_76 = io_pmp_0_mask_0[31:3]; // @[PMP.scala:68:26, :69:72, :143:7]
wire [2:0] _res_aligned_pow2Aligned_T_21 = io_pmp_0_mask_0[2:0]; // @[PMP.scala:68:26, :126:39, :143:7]
wire [31:0] res_hit_lsbMask_7 = {_res_hit_msbMatch_T_76, _res_aligned_pow2Aligned_T_21 | _res_hit_lsbMask_T_23}; // @[package.scala:243:46]
wire [31:0] _res_hit_msbMatch_T_72 = ~_res_hit_msbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbMatch_T_73 = {_res_hit_msbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbMatch_T_74 = ~_res_hit_msbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbMatch_T_75 = _res_hit_msbMatch_T_74[31:3]; // @[PMP.scala:60:27, :69:53]
wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70 ^ _res_hit_msbMatch_T_75; // @[PMP.scala:63:47, :69:{29,53}]
wire [28:0] _res_hit_msbMatch_T_78 = ~_res_hit_msbMatch_T_76; // @[PMP.scala:63:54, :69:72]
wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77 & _res_hit_msbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :80:52, :81:54, :123:67]
wire [31:0] _res_hit_lsbMatch_T_72 = ~_res_hit_lsbMatch_T_71; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbMatch_T_73 = {_res_hit_lsbMatch_T_72[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbMatch_T_74 = ~_res_hit_lsbMatch_T_73; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbMatch_T_75 = _res_hit_lsbMatch_T_74[2:0]; // @[PMP.scala:60:27, :70:55]
wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80]
wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70 ^ _res_hit_lsbMatch_T_75; // @[PMP.scala:63:47, :70:{28,55}]
wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80]
wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}]
wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :82:64, :123:{108,125}]
wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16]
wire _res_hit_T_93 = io_pmp_0_cfg_a_0[0]; // @[PMP.scala:46:26, :143:7]
wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}]
wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}]
wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46]
wire [31:0] _res_hit_msbsLess_T_92 = ~_res_hit_msbsLess_T_91; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsLess_T_93 = {_res_hit_msbsLess_T_92[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsLess_T_94 = ~_res_hit_msbsLess_T_93; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsLess_T_95 = _res_hit_msbsLess_T_94[31:3]; // @[PMP.scala:60:27, :80:52]
wire res_hit_msbsLess_15 = _res_hit_msbsLess_T_90 < _res_hit_msbsLess_T_95; // @[PMP.scala:80:{25,39,52}]
wire [31:0] _res_hit_msbsEqual_T_107 = ~_res_hit_msbsEqual_T_106; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_msbsEqual_T_108 = {_res_hit_msbsEqual_T_107[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_msbsEqual_T_109 = ~_res_hit_msbsEqual_T_108; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_hit_msbsEqual_T_110 = _res_hit_msbsEqual_T_109[31:3]; // @[PMP.scala:60:27, :81:54]
wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105 ^ _res_hit_msbsEqual_T_110; // @[PMP.scala:81:{27,41,54}]
wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:80:52, :81:{41,54,69}, :123:67]
wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}]
wire [31:0] _res_hit_lsbsLess_T_108 = ~_res_hit_lsbsLess_T_107; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_hit_lsbsLess_T_109 = {_res_hit_lsbsLess_T_108[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_hit_lsbsLess_T_110 = ~_res_hit_lsbsLess_T_109; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_hit_lsbsLess_T_111 = _res_hit_lsbsLess_T_110[2:0]; // @[PMP.scala:60:27, :82:64]
wire res_hit_lsbsLess_15 = _res_hit_lsbsLess_T_106 < _res_hit_lsbsLess_T_111; // @[PMP.scala:82:{42,53,64}]
wire _res_hit_T_100 = res_hit_msbsEqual_15 & res_hit_lsbsLess_15; // @[PMP.scala:81:69, :82:53, :83:30]
wire _res_hit_T_101 = res_hit_msbsLess_15 | _res_hit_T_100; // @[PMP.scala:80:39, :83:{16,30}]
wire _res_hit_T_102 = _res_hit_T_101; // @[PMP.scala:83:16, :94:48]
wire _res_hit_T_103 = _res_hit_T_93 & _res_hit_T_102; // @[PMP.scala:46:26, :94:48, :132:61]
wire res_hit_7 = _res_hit_T_91 ? _res_hit_T_92 : _res_hit_T_103; // @[PMP.scala:45:20, :71:16, :132:{8,61}]
wire _res_ignore_T_7 = ~io_pmp_0_cfg_l_0; // @[PMP.scala:143:7, :164:29]
wire res_ignore_7 = default_0 & _res_ignore_T_7; // @[PMP.scala:156:56, :164:{26,29}]
wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}]
wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}]
wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:{49,67,82}]
wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}]
wire [31:0] _res_aligned_straddlesUpperBound_T_121 = ~_res_aligned_straddlesUpperBound_T_120; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_122 = {_res_aligned_straddlesUpperBound_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_123 = ~_res_aligned_straddlesUpperBound_T_122; // @[PMP.scala:60:{27,48}]
wire [28:0] _res_aligned_straddlesUpperBound_T_124 = _res_aligned_straddlesUpperBound_T_123[31:3]; // @[PMP.scala:60:27, :124:62]
wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119 ^ _res_aligned_straddlesUpperBound_T_124; // @[PMP.scala:124:{35,49,62}]
wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:80:52, :81:54, :123:67, :124:{49,77}]
wire [31:0] _res_aligned_straddlesUpperBound_T_128 = ~_res_aligned_straddlesUpperBound_T_127; // @[PMP.scala:60:{29,36}]
wire [31:0] _res_aligned_straddlesUpperBound_T_129 = {_res_aligned_straddlesUpperBound_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}]
wire [31:0] _res_aligned_straddlesUpperBound_T_130 = ~_res_aligned_straddlesUpperBound_T_129; // @[PMP.scala:60:{27,48}]
wire [2:0] _res_aligned_straddlesUpperBound_T_131 = _res_aligned_straddlesUpperBound_T_130[2:0]; // @[PMP.scala:60:27, :124:98]
wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46]
wire [2:0] _res_aligned_straddlesUpperBound_T_134 = _res_aligned_straddlesUpperBound_T_131 & _res_aligned_straddlesUpperBound_T_133; // @[PMP.scala:124:{98,115,136}]
wire _res_aligned_straddlesUpperBound_T_135 = |_res_aligned_straddlesUpperBound_T_134; // @[PMP.scala:124:{115,148}]
wire res_aligned_straddlesUpperBound_7 = _res_aligned_straddlesUpperBound_T_126 & _res_aligned_straddlesUpperBound_T_135; // @[PMP.scala:124:{77,85,148}]
wire _res_aligned_rangeAligned_T_7 = res_aligned_straddlesUpperBound_7; // @[PMP.scala:124:85, :125:46]
wire res_aligned_rangeAligned_7 = ~_res_aligned_rangeAligned_T_7; // @[PMP.scala:125:{24,46}]
wire [2:0] _res_aligned_pow2Aligned_T_22 = ~_res_aligned_pow2Aligned_T_21; // @[PMP.scala:126:{34,39}]
wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7 & _res_aligned_pow2Aligned_T_22; // @[package.scala:243:46]
wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :126:{32,57}]
wire res_aligned_7 = _res_aligned_T_7 ? res_aligned_pow2Aligned_7 : res_aligned_rangeAligned_7; // @[PMP.scala:45:20, :125:24, :126:57, :127:8]
wire _res_T_315 = io_pmp_0_cfg_a_0 == 2'h0; // @[PMP.scala:143:7, :168:32]
wire _GEN_36 = io_pmp_0_cfg_a_0 == 2'h1; // @[PMP.scala:143:7, :168:32]
wire _res_T_316; // @[PMP.scala:168:32]
assign _res_T_316 = _GEN_36; // @[PMP.scala:168:32]
wire _res_T_335; // @[PMP.scala:177:61]
assign _res_T_335 = _GEN_36; // @[PMP.scala:168:32, :177:61]
wire _res_T_339; // @[PMP.scala:178:63]
assign _res_T_339 = _GEN_36; // @[PMP.scala:168:32, :178:63]
wire _GEN_37 = io_pmp_0_cfg_a_0 == 2'h2; // @[PMP.scala:143:7, :168:32]
wire _res_T_317; // @[PMP.scala:168:32]
assign _res_T_317 = _GEN_37; // @[PMP.scala:168:32]
wire _res_T_344; // @[PMP.scala:177:61]
assign _res_T_344 = _GEN_37; // @[PMP.scala:168:32, :177:61]
wire _res_T_348; // @[PMP.scala:178:63]
assign _res_T_348 = _GEN_37; // @[PMP.scala:168:32, :178:63]
wire _res_T_318 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32]
wire [1:0] _GEN_38 = {io_pmp_0_cfg_x_0, io_pmp_0_cfg_w_0}; // @[PMP.scala:143:7, :174:26]
wire [1:0] res_hi_42; // @[PMP.scala:174:26]
assign res_hi_42 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_43; // @[PMP.scala:174:26]
assign res_hi_43 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_44; // @[PMP.scala:174:26]
assign res_hi_44 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_45; // @[PMP.scala:174:26]
assign res_hi_45 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_46; // @[PMP.scala:174:26]
assign res_hi_46 = _GEN_38; // @[PMP.scala:174:26]
wire [1:0] res_hi_47; // @[PMP.scala:174:26]
assign res_hi_47 = _GEN_38; // @[PMP.scala:174:26]
wire [2:0] _res_T_320 = {res_hi_42, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_321 = _res_T_320 == 3'h0; // @[PMP.scala:82:64, :123:{108,125}, :174:{26,60}]
wire [2:0] _res_T_322 = {res_hi_43, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_323 = _res_T_322 == 3'h1; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_324 = {res_hi_44, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_325 = _res_T_324 == 3'h3; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_326 = {res_hi_45, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_327 = _res_T_326 == 3'h4; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_328 = {res_hi_46, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_329 = _res_T_328 == 3'h5; // @[PMP.scala:174:{26,60}]
wire [2:0] _res_T_330 = {res_hi_47, io_pmp_0_cfg_r_0}; // @[PMP.scala:143:7, :174:26]
wire _res_T_331 = &_res_T_330; // @[PMP.scala:174:{26,60}]
wire _res_T_332 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_333 = _res_T_332 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_334 = _res_T_333 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_336 = _res_T_334 & _res_T_335; // @[PMP.scala:177:{37,48,61}]
wire _GEN_39 = io_pmp_0_cfg_l_0 & res_hit_7; // @[PMP.scala:132:8, :143:7, :178:32]
wire _res_T_337; // @[PMP.scala:178:32]
assign _res_T_337 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_346; // @[PMP.scala:178:32]
assign _res_T_346 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_355; // @[PMP.scala:178:32]
assign _res_T_355 = _GEN_39; // @[PMP.scala:178:32]
wire _res_T_338 = _res_T_337 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_340 = _res_T_338 & _res_T_339; // @[PMP.scala:178:{39,50,63}]
wire _res_T_341 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_342 = _res_T_341 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_343 = _res_T_342 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_345 = _res_T_343 & _res_T_344; // @[PMP.scala:177:{37,48,61}]
wire _res_T_347 = _res_T_346 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_349 = _res_T_347 & _res_T_348; // @[PMP.scala:178:{39,50,63}]
wire _res_T_350 = ~res_ignore_7; // @[PMP.scala:164:26, :177:22]
wire _res_T_351 = _res_T_350 & res_hit_7; // @[PMP.scala:132:8, :177:{22,30}]
wire _res_T_352 = _res_T_351 & res_aligned_7; // @[PMP.scala:127:8, :177:{30,37}]
wire _res_T_353 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :177:61]
wire _res_T_354 = _res_T_352 & _res_T_353; // @[PMP.scala:177:{37,48,61}]
wire _res_T_356 = _res_T_355 & res_aligned_7; // @[PMP.scala:127:8, :178:{32,39}]
wire _res_T_357 = &io_pmp_0_cfg_a_0; // @[PMP.scala:143:7, :168:32, :178:63]
wire _res_T_358 = _res_T_356 & _res_T_357; // @[PMP.scala:178:{39,50,63}]
wire _res_cur_cfg_x_T_15; // @[PMP.scala:184:26]
wire _res_cur_cfg_w_T_15; // @[PMP.scala:183:26]
wire _res_cur_cfg_r_T_15; // @[PMP.scala:182:26]
wire res_cur_7_cfg_x; // @[PMP.scala:181:23]
wire res_cur_7_cfg_w; // @[PMP.scala:181:23]
wire res_cur_7_cfg_r; // @[PMP.scala:181:23]
wire _res_cur_cfg_r_T_14 = io_pmp_0_cfg_r_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :182:40]
assign _res_cur_cfg_r_T_15 = res_aligned_7 & _res_cur_cfg_r_T_14; // @[PMP.scala:127:8, :182:{26,40}]
assign res_cur_7_cfg_r = _res_cur_cfg_r_T_15; // @[PMP.scala:181:23, :182:26]
wire _res_cur_cfg_w_T_14 = io_pmp_0_cfg_w_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :183:40]
assign _res_cur_cfg_w_T_15 = res_aligned_7 & _res_cur_cfg_w_T_14; // @[PMP.scala:127:8, :183:{26,40}]
assign res_cur_7_cfg_w = _res_cur_cfg_w_T_15; // @[PMP.scala:181:23, :183:26]
wire _res_cur_cfg_x_T_14 = io_pmp_0_cfg_x_0 | res_ignore_7; // @[PMP.scala:143:7, :164:26, :184:40]
assign _res_cur_cfg_x_T_15 = res_aligned_7 & _res_cur_cfg_x_T_14; // @[PMP.scala:127:8, :184:{26,40}]
assign res_cur_7_cfg_x = _res_cur_cfg_x_T_15; // @[PMP.scala:181:23, :184:26]
wire res_cfg_l = res_hit_7 ? res_cur_7_cfg_l : _res_T_314_cfg_l; // @[PMP.scala:132:8, :181:23, :185:8]
wire [1:0] res_cfg_a = res_hit_7 ? res_cur_7_cfg_a : _res_T_314_cfg_a; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_x = res_hit_7 ? res_cur_7_cfg_x : _res_T_314_cfg_x; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_w = res_hit_7 ? res_cur_7_cfg_w : _res_T_314_cfg_w; // @[PMP.scala:132:8, :181:23, :185:8]
assign res_cfg_r = res_hit_7 ? res_cur_7_cfg_r : _res_T_314_cfg_r; // @[PMP.scala:132:8, :181:23, :185:8]
wire [29:0] res_addr = res_hit_7 ? res_cur_7_addr : _res_T_314_addr; // @[PMP.scala:132:8, :181:23, :185:8]
wire [31:0] res_mask = res_hit_7 ? res_cur_7_mask : _res_T_314_mask; // @[PMP.scala:132:8, :181:23, :185:8]
assign io_x_0 = res_cfg_x; // @[PMP.scala:143:7, :185:8]
assign io_w_0 = res_cfg_w; // @[PMP.scala:143:7, :185:8]
assign io_r_0 = res_cfg_r; // @[PMP.scala:143:7, :185:8]
assign io_r = io_r_0; // @[PMP.scala:143:7]
assign io_w = io_w_0; // @[PMP.scala:143:7]
assign io_x = io_x_0; // @[PMP.scala:143:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v4.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val grant = Input(Bool())
val iss_uop = Output(new MicroOp())
val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val squash_grant = Input(Bool())
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup)))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val child_rebusys = Input(UInt(aluWidth.W))
}
class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters)
extends BoomModule
{
val io = IO(new IssueSlotIO(numWakeupPorts))
val slot_valid = RegInit(false.B)
val slot_uop = Reg(new MicroOp())
val next_valid = WireInit(slot_valid)
val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop))
val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop)
io.valid := slot_valid
io.out_uop := next_uop
io.will_be_valid := next_valid && !killed
when (io.kill) {
slot_valid := false.B
} .elsewhen (io.in_uop.valid) {
slot_valid := true.B
} .elsewhen (io.clear) {
slot_valid := false.B
} .otherwise {
slot_valid := next_valid && !killed
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (!slot_valid || io.clear || io.kill)
} .otherwise {
slot_uop := next_uop
}
// Wakeups
next_uop.iw_p1_bypass_hint := false.B
next_uop.iw_p2_bypass_hint := false.B
next_uop.iw_p3_bypass_hint := false.B
next_uop.iw_p1_speculative_child := 0.U
next_uop.iw_p2_speculative_child := 0.U
val rebusied_prs1 = WireInit(false.B)
val rebusied_prs2 = WireInit(false.B)
val rebusied = rebusied_prs1 || rebusied_prs2
val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 }
val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 }
val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 }
val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m }
val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m }
val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m }
val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m }
val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m }
val bypassables = io.wakeup_ports.map { w => w.bits.bypassable }
val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask }
when (prs1_wakeups.reduce(_||_)) {
next_uop.prs1_busy := false.B
next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks)
next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables)
}
when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) &&
slot_uop.lrs1_rtype === RT_FIX) {
next_uop.prs1_busy := true.B
rebusied_prs1 := true.B
}
when (prs2_wakeups.reduce(_||_)) {
next_uop.prs2_busy := false.B
next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks)
next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables)
}
when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) &&
slot_uop.lrs2_rtype === RT_FIX) {
next_uop.prs2_busy := true.B
rebusied_prs2 := true.B
}
when (prs3_wakeups.reduce(_||_)) {
next_uop.prs3_busy := false.B
next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables)
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) {
next_uop.ppred_busy := false.B
}
val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B)
val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
io.request := slot_valid && !slot_uop.iw_issued && (
iss_ready || agen_ready || dgen_ready
)
io.iss_uop := slot_uop
// Update state for current micro-op based on grant
next_uop.iw_issued := false.B
next_uop.iw_issued_partial_agen := false.B
next_uop.iw_issued_partial_dgen := false.B
when (io.grant && !io.squash_grant) {
next_uop.iw_issued := true.B
}
if (isMem) {
when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) {
when (agen_ready) {
// Issue the AGEN, next slot entry is a DGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_agen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := true.B
io.iss_uop.fu_code(FC_DGEN) := false.B
} .otherwise {
// Issue the DGEN, next slot entry is the AGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_dgen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := false.B
io.iss_uop.fu_code(FC_DGEN) := true.B
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
} .elsewhen (slot_uop.fu_code(FC_DGEN)) {
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
io.iss_uop.lrs2_rtype := RT_X
io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE
}
when (slot_valid && slot_uop.iw_issued) {
next_valid := rebusied
if (isMem) {
when (slot_uop.iw_issued_partial_agen) {
next_valid := true.B
when (!rebusied_prs1) {
next_uop.fu_code(FC_AGEN) := false.B
next_uop.fu_code(FC_DGEN) := true.B
}
} .elsewhen (slot_uop.iw_issued_partial_dgen) {
next_valid := true.B
when (!rebusied_prs2) {
next_uop.fu_code(FC_AGEN) := true.B
next_uop.fu_code(FC_DGEN) := false.B
}
}
}
}
}
|
module IssueSlot_3( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31]
wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31]
wire rebusied = 1'h0; // @[issue-slot.scala:94:32]
wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] next_uop_iw_p1_speculative_child = 2'h0; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child = 2'h0; // @[issue-slot.scala:59:28]
wire [1:0] _next_uop_iw_p1_speculative_child_T = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p1_speculative_child_T_2 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p1_speculative_child_WIRE = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_2 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_WIRE = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_226( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
|
module TLBuffer_a32d128s3k4z4c( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire _nodeOut_e_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _nodeOut_c_q_io_enq_ready; // @[Decoupled.scala:362:21]
wire _nodeIn_b_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_b_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_b_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [3:0] _nodeIn_b_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_b_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [31:0] _nodeIn_b_q_io_deq_bits_address; // @[Decoupled.scala:362:21]
wire [15:0] _nodeIn_b_q_io_deq_bits_mask; // @[Decoupled.scala:362:21]
wire _nodeIn_b_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
wire [2:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
wire [3:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
TLMonitor_45 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_a_valid (auto_in_a_valid),
.io_in_a_bits_opcode (auto_in_a_bits_opcode),
.io_in_a_bits_param (auto_in_a_bits_param),
.io_in_a_bits_size (auto_in_a_bits_size),
.io_in_a_bits_source (auto_in_a_bits_source),
.io_in_a_bits_address (auto_in_a_bits_address),
.io_in_a_bits_mask (auto_in_a_bits_mask),
.io_in_b_ready (auto_in_b_ready),
.io_in_b_valid (_nodeIn_b_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_b_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_b_bits_param (_nodeIn_b_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_b_bits_size (_nodeIn_b_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_b_bits_source (_nodeIn_b_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_b_bits_address (_nodeIn_b_q_io_deq_bits_address), // @[Decoupled.scala:362:21]
.io_in_b_bits_mask (_nodeIn_b_q_io_deq_bits_mask), // @[Decoupled.scala:362:21]
.io_in_b_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt), // @[Decoupled.scala:362:21]
.io_in_c_ready (_nodeOut_c_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_c_valid (auto_in_c_valid),
.io_in_c_bits_opcode (auto_in_c_bits_opcode),
.io_in_c_bits_param (auto_in_c_bits_param),
.io_in_c_bits_size (auto_in_c_bits_size),
.io_in_c_bits_source (auto_in_c_bits_source),
.io_in_c_bits_address (auto_in_c_bits_address),
.io_in_d_ready (auto_in_d_ready),
.io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21]
.io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21]
.io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21]
.io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21]
.io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21]
.io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21]
.io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21]
.io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt), // @[Decoupled.scala:362:21]
.io_in_e_ready (_nodeOut_e_q_io_enq_ready), // @[Decoupled.scala:362:21]
.io_in_e_valid (auto_in_e_valid),
.io_in_e_bits_sink (auto_in_e_bits_sink)
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d128s3k4z4c nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_a_q_io_enq_ready),
.io_enq_valid (auto_in_a_valid),
.io_enq_bits_opcode (auto_in_a_bits_opcode),
.io_enq_bits_param (auto_in_a_bits_param),
.io_enq_bits_size (auto_in_a_bits_size),
.io_enq_bits_source (auto_in_a_bits_source),
.io_enq_bits_address (auto_in_a_bits_address),
.io_enq_bits_mask (auto_in_a_bits_mask),
.io_enq_bits_data (auto_in_a_bits_data),
.io_deq_ready (auto_out_a_ready),
.io_deq_valid (auto_out_a_valid),
.io_deq_bits_opcode (auto_out_a_bits_opcode),
.io_deq_bits_param (auto_out_a_bits_param),
.io_deq_bits_size (auto_out_a_bits_size),
.io_deq_bits_source (auto_out_a_bits_source),
.io_deq_bits_address (auto_out_a_bits_address),
.io_deq_bits_mask (auto_out_a_bits_mask),
.io_deq_bits_data (auto_out_a_bits_data),
.io_deq_bits_corrupt (auto_out_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d128s3k4z4c nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_d_ready),
.io_enq_valid (auto_out_d_valid),
.io_enq_bits_opcode (auto_out_d_bits_opcode),
.io_enq_bits_param (auto_out_d_bits_param),
.io_enq_bits_size (auto_out_d_bits_size),
.io_enq_bits_source (auto_out_d_bits_source),
.io_enq_bits_sink (auto_out_d_bits_sink),
.io_enq_bits_denied (auto_out_d_bits_denied),
.io_enq_bits_data (auto_out_d_bits_data),
.io_enq_bits_corrupt (auto_out_d_bits_corrupt),
.io_deq_ready (auto_in_d_ready),
.io_deq_valid (_nodeIn_d_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source),
.io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink),
.io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied),
.io_deq_bits_data (auto_in_d_bits_data),
.io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d128s3k4z4c nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (auto_out_b_ready),
.io_enq_valid (auto_out_b_valid),
.io_enq_bits_opcode (auto_out_b_bits_opcode),
.io_enq_bits_param (auto_out_b_bits_param),
.io_enq_bits_size (auto_out_b_bits_size),
.io_enq_bits_source (auto_out_b_bits_source),
.io_enq_bits_address (auto_out_b_bits_address),
.io_enq_bits_mask (auto_out_b_bits_mask),
.io_enq_bits_data (auto_out_b_bits_data),
.io_enq_bits_corrupt (auto_out_b_bits_corrupt),
.io_deq_ready (auto_in_b_ready),
.io_deq_valid (_nodeIn_b_q_io_deq_valid),
.io_deq_bits_opcode (_nodeIn_b_q_io_deq_bits_opcode),
.io_deq_bits_param (_nodeIn_b_q_io_deq_bits_param),
.io_deq_bits_size (_nodeIn_b_q_io_deq_bits_size),
.io_deq_bits_source (_nodeIn_b_q_io_deq_bits_source),
.io_deq_bits_address (_nodeIn_b_q_io_deq_bits_address),
.io_deq_bits_mask (_nodeIn_b_q_io_deq_bits_mask),
.io_deq_bits_corrupt (_nodeIn_b_q_io_deq_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d128s3k4z4c nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_c_q_io_enq_ready),
.io_enq_valid (auto_in_c_valid),
.io_enq_bits_opcode (auto_in_c_bits_opcode),
.io_enq_bits_param (auto_in_c_bits_param),
.io_enq_bits_size (auto_in_c_bits_size),
.io_enq_bits_source (auto_in_c_bits_source),
.io_enq_bits_address (auto_in_c_bits_address),
.io_enq_bits_data (auto_in_c_bits_data),
.io_deq_ready (auto_out_c_ready),
.io_deq_valid (auto_out_c_valid),
.io_deq_bits_opcode (auto_out_c_bits_opcode),
.io_deq_bits_param (auto_out_c_bits_param),
.io_deq_bits_size (auto_out_c_bits_size),
.io_deq_bits_source (auto_out_c_bits_source),
.io_deq_bits_address (auto_out_c_bits_address),
.io_deq_bits_data (auto_out_c_bits_data),
.io_deq_bits_corrupt (auto_out_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d128s3k4z4c nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (_nodeOut_e_q_io_enq_ready),
.io_enq_valid (auto_in_e_valid),
.io_enq_bits_sink (auto_in_e_bits_sink),
.io_deq_ready (auto_out_e_ready),
.io_deq_valid (auto_out_e_valid),
.io_deq_bits_sink (auto_out_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_b_valid = _nodeIn_b_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_opcode = _nodeIn_b_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_param = _nodeIn_b_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_size = _nodeIn_b_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_source = _nodeIn_b_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_address = _nodeIn_b_q_io_deq_bits_address; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_mask = _nodeIn_b_q_io_deq_bits_mask; // @[Decoupled.scala:362:21]
assign auto_in_b_bits_corrupt = _nodeIn_b_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
assign auto_in_c_ready = _nodeOut_c_q_io_enq_ready; // @[Decoupled.scala:362:21]
assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
assign auto_in_e_ready = _nodeOut_e_q_io_enq_ready; // @[Decoupled.scala:362:21]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Transposer.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
trait Transposer[T <: Data] extends Module {
def dim: Int
def dataType: T
val io = IO(new Bundle {
val inRow = Flipped(Decoupled(Vec(dim, dataType)))
val outCol = Decoupled(Vec(dim, dataType))
})
}
class PipelinedTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
val sMoveUp :: sMoveLeft :: Nil = Enum(2)
val state = RegInit(sMoveUp)
val leftCounter = RegInit(0.U(log2Ceil(dim+1).W)) //(io.inRow.fire && state === sMoveLeft, dim+1)
val upCounter = RegInit(0.U(log2Ceil(dim+1).W)) //Counter(io.inRow.fire && state === sMoveUp, dim+1)
io.outCol.valid := 0.U
io.inRow.ready := 0.U
switch(state) {
is(sMoveUp) {
io.inRow.ready := upCounter <= dim.U
io.outCol.valid := leftCounter > 0.U
when(io.inRow.fire) {
upCounter := upCounter + 1.U
}
when(upCounter === (dim-1).U) {
state := sMoveLeft
leftCounter := 0.U
}
when(io.outCol.fire) {
leftCounter := leftCounter - 1.U
}
}
is(sMoveLeft) {
io.inRow.ready := leftCounter <= dim.U // TODO: this is naive
io.outCol.valid := upCounter > 0.U
when(leftCounter === (dim-1).U) {
state := sMoveUp
}
when(io.inRow.fire) {
leftCounter := leftCounter + 1.U
upCounter := 0.U
}
when(io.outCol.fire) {
upCounter := upCounter - 1.U
}
}
}
// Propagate input from bottom row to top row systolically in the move up phase
// TODO: need to iterate over columns to connect Chisel values of type T
// Should be able to operate directly on the Vec, but Seq and Vec don't mix (try Array?)
for (colIdx <- 0 until dim) {
regArray.foldRight(io.inRow.bits(colIdx)) {
case (regRow, prevReg) =>
when (state === sMoveUp) {
regRow(colIdx) := prevReg
}
regRow(colIdx)
}
}
// Propagate input from right side to left side systolically in the move left phase
for (rowIdx <- 0 until dim) {
regArrayT.foldRight(io.inRow.bits(rowIdx)) {
case (regCol, prevReg) =>
when (state === sMoveLeft) {
regCol(rowIdx) := prevReg
}
regCol(rowIdx)
}
}
// Pull from the left side or the top side based on the state
for (idx <- 0 until dim) {
when (state === sMoveUp) {
io.outCol.bits(idx) := regArray(0)(idx)
}.elsewhen(state === sMoveLeft) {
io.outCol.bits(idx) := regArrayT(0)(idx)
}.otherwise {
io.outCol.bits(idx) := DontCare
}
}
}
class AlwaysOutTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
require(isPow2(dim))
val LEFT_DIR = 0.U(1.W)
val UP_DIR = 1.U(1.W)
class PE extends Module {
val io = IO(new Bundle {
val inR = Input(dataType)
val inD = Input(dataType)
val outL = Output(dataType)
val outU = Output(dataType)
val dir = Input(UInt(1.W))
val en = Input(Bool())
})
val reg = RegEnable(Mux(io.dir === LEFT_DIR, io.inR, io.inD), io.en)
io.outU := reg
io.outL := reg
}
val pes = Seq.fill(dim,dim)(Module(new PE))
val counter = RegInit(0.U((log2Ceil(dim) max 1).W)) // TODO replace this with a standard Chisel counter
val dir = RegInit(LEFT_DIR)
// Wire up horizontal signals
for (row <- 0 until dim; col <- 0 until dim) {
val right_in = if (col == dim-1) io.inRow.bits(row) else pes(row)(col+1).io.outL
pes(row)(col).io.inR := right_in
}
// Wire up vertical signals
for (row <- 0 until dim; col <- 0 until dim) {
val down_in = if (row == dim-1) io.inRow.bits(col) else pes(row+1)(col).io.outU
pes(row)(col).io.inD := down_in
}
// Wire up global signals
pes.flatten.foreach(_.io.dir := dir)
pes.flatten.foreach(_.io.en := io.inRow.fire)
io.outCol.valid := true.B
io.inRow.ready := true.B
val left_out = VecInit(pes.transpose.head.map(_.io.outL))
val up_out = VecInit(pes.head.map(_.io.outU))
io.outCol.bits := Mux(dir === LEFT_DIR, left_out, up_out)
when (io.inRow.fire) {
counter := wrappingAdd(counter, 1.U, dim)
}
when (counter === (dim-1).U && io.inRow.fire) {
dir := ~dir
}
}
class NaiveTransposer[T <: Data](val dim: Int, val dataType: T) extends Transposer[T] {
val regArray = Seq.fill(dim, dim)(Reg(dataType))
val regArrayT = regArray.transpose
// state = 0 => filling regArray row-wise, state = 1 => draining regArray column-wise
val state = RegInit(0.U(1.W))
val countInc = io.inRow.fire || io.outCol.fire
val (countValue, countWrap) = Counter(countInc, dim)
io.inRow.ready := state === 0.U
io.outCol.valid := state === 1.U
for (i <- 0 until dim) {
for (j <- 0 until dim) {
when(countValue === i.U && io.inRow.fire) {
regArray(i)(j) := io.inRow.bits(j)
}
}
}
for (i <- 0 until dim) {
io.outCol.bits(i) := 0.U
for (j <- 0 until dim) {
when(countValue === j.U) {
io.outCol.bits(i) := regArrayT(j)(i)
}
}
}
when (io.inRow.fire && countWrap) {
state := 1.U
}
when (io.outCol.fire && countWrap) {
state := 0.U
}
assert(!(state === 0.U) || !io.outCol.fire)
assert(!(state === 1.U) || !io.inRow.fire)
}
|
module PE_56( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File MulRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (ported from Verilog to
Chisel by Andrew Waterman).
Copyright 2019, 2020 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
import consts._
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulFullRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth*2 - 1))
})
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
val notSigNaN_invalidExc = (io.a.isInf && io.b.isZero) || (io.a.isZero && io.b.isInf)
val notNaN_isInfOut = io.a.isInf || io.b.isInf
val notNaN_isZeroOut = io.a.isZero || io.b.isZero
val notNaN_signOut = io.a.sign ^ io.b.sign
val common_sExpOut = io.a.sExp + io.b.sExp - (1<<expWidth).S
val common_sigOut = (io.a.sig * io.b.sig)(sigWidth*2 - 1, 0)
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
io.invalidExc := isSigNaNRawFloat(io.a) || isSigNaNRawFloat(io.b) || notSigNaN_invalidExc
io.rawOut.isInf := notNaN_isInfOut
io.rawOut.isZero := notNaN_isZeroOut
io.rawOut.sExp := common_sExpOut
io.rawOut.isNaN := io.a.isNaN || io.b.isNaN
io.rawOut.sign := notNaN_signOut
io.rawOut.sig := common_sigOut
}
class MulRawFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(new RawFloat(expWidth, sigWidth))
val b = Input(new RawFloat(expWidth, sigWidth))
val invalidExc = Output(Bool())
val rawOut = Output(new RawFloat(expWidth, sigWidth + 2))
})
val mulFullRaw = Module(new MulFullRawFN(expWidth, sigWidth))
mulFullRaw.io.a := io.a
mulFullRaw.io.b := io.b
io.invalidExc := mulFullRaw.io.invalidExc
io.rawOut := mulFullRaw.io.rawOut
io.rawOut.sig := {
val sig = mulFullRaw.io.rawOut.sig
Cat(sig >> (sigWidth - 2), sig(sigWidth - 3, 0).orR)
}
}
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
class MulRecFN(expWidth: Int, sigWidth: Int) extends chisel3.RawModule
{
val io = IO(new Bundle {
val a = Input(UInt((expWidth + sigWidth + 1).W))
val b = Input(UInt((expWidth + sigWidth + 1).W))
val roundingMode = Input(UInt(3.W))
val detectTininess = Input(Bool())
val out = Output(UInt((expWidth + sigWidth + 1).W))
val exceptionFlags = Output(UInt(5.W))
})
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val mulRawFN = Module(new MulRawFN(expWidth, sigWidth))
mulRawFN.io.a := rawFloatFromRecFN(expWidth, sigWidth, io.a)
mulRawFN.io.b := rawFloatFromRecFN(expWidth, sigWidth, io.b)
//------------------------------------------------------------------------
//------------------------------------------------------------------------
val roundRawFNToRecFN =
Module(new RoundRawFNToRecFN(expWidth, sigWidth, 0))
roundRawFNToRecFN.io.invalidExc := mulRawFN.io.invalidExc
roundRawFNToRecFN.io.infiniteExc := false.B
roundRawFNToRecFN.io.in := mulRawFN.io.rawOut
roundRawFNToRecFN.io.roundingMode := io.roundingMode
roundRawFNToRecFN.io.detectTininess := io.detectTininess
io.out := roundRawFNToRecFN.io.out
io.exceptionFlags := roundRawFNToRecFN.io.exceptionFlags
}
File rawFloatFromRecFN.scala:
/*============================================================================
This Chisel source file is part of a pre-release version of the HardFloat IEEE
Floating-Point Arithmetic Package, by John R. Hauser (with some contributions
from Yunsup Lee and Andrew Waterman, mainly concerning testing).
Copyright 2010, 2011, 2012, 2013, 2014, 2015, 2016 The Regents of the
University of California. All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
package hardfloat
import chisel3._
import chisel3.util._
/*----------------------------------------------------------------------------
| In the result, no more than one of 'isNaN', 'isInf', and 'isZero' will be
| set.
*----------------------------------------------------------------------------*/
object rawFloatFromRecFN
{
def apply(expWidth: Int, sigWidth: Int, in: Bits): RawFloat =
{
val exp = in(expWidth + sigWidth - 1, sigWidth - 1)
val isZero = exp(expWidth, expWidth - 2) === 0.U
val isSpecial = exp(expWidth, expWidth - 1) === 3.U
val out = Wire(new RawFloat(expWidth, sigWidth))
out.isNaN := isSpecial && exp(expWidth - 2)
out.isInf := isSpecial && ! exp(expWidth - 2)
out.isZero := isZero
out.sign := in(expWidth + sigWidth)
out.sExp := exp.zext
out.sig := 0.U(1.W) ## ! isZero ## in(sigWidth - 2, 0)
out
}
}
|
module MulRecFN_48( // @[MulRecFN.scala:100:7]
input [32:0] io_a, // @[MulRecFN.scala:102:16]
input [32:0] io_b, // @[MulRecFN.scala:102:16]
output [32:0] io_out // @[MulRecFN.scala:102:16]
);
wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26]
wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26]
wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26]
wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7]
wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7]
wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [32:0] io_out_0; // @[MulRecFN.scala:100:7]
wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7]
wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
MulRawFN_48 mulRawFN ( // @[MulRecFN.scala:113:26]
.io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_invalidExc (_mulRawFN_io_invalidExc),
.io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN),
.io_rawOut_isInf (_mulRawFN_io_rawOut_isInf),
.io_rawOut_isZero (_mulRawFN_io_rawOut_isZero),
.io_rawOut_sign (_mulRawFN_io_rawOut_sign),
.io_rawOut_sExp (_mulRawFN_io_rawOut_sExp),
.io_rawOut_sig (_mulRawFN_io_rawOut_sig)
); // @[MulRecFN.scala:113:26]
RoundRawFNToRecFN_e8_s24_125 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15]
.io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26]
.io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26]
.io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26]
.io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26]
.io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26]
.io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26]
.io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulRecFN.scala:121:15]
assign io_out = io_out_0; // @[MulRecFN.scala:100:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Buffer.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.BufferParams
class TLBufferNode (
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit valName: ValName) extends TLAdapterNode(
clientFn = { p => p.v1copy(minLatency = p.minLatency + b.latency + c.latency) },
managerFn = { p => p.v1copy(minLatency = p.minLatency + a.latency + d.latency) }
) {
override lazy val nodedebugstring = s"a:${a.toString}, b:${b.toString}, c:${c.toString}, d:${d.toString}, e:${e.toString}"
override def circuitIdentity = List(a,b,c,d,e).forall(_ == BufferParams.none)
}
class TLBuffer(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters) extends LazyModule
{
def this(ace: BufferParams, bd: BufferParams)(implicit p: Parameters) = this(ace, bd, ace, bd, ace)
def this(abcde: BufferParams)(implicit p: Parameters) = this(abcde, abcde)
def this()(implicit p: Parameters) = this(BufferParams.default)
val node = new TLBufferNode(a, b, c, d, e)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
def headBundle = node.out.head._2.bundle
override def desiredName = (Seq("TLBuffer") ++ node.out.headOption.map(_._2.bundle.shortName)).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
out.a <> a(in .a)
in .d <> d(out.d)
if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
in .b <> b(out.b)
out.c <> c(in .c)
out.e <> e(in .e)
} else {
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLBuffer
{
def apply() (implicit p: Parameters): TLNode = apply(BufferParams.default)
def apply(abcde: BufferParams) (implicit p: Parameters): TLNode = apply(abcde, abcde)
def apply(ace: BufferParams, bd: BufferParams)(implicit p: Parameters): TLNode = apply(ace, bd, ace, bd, ace)
def apply(
a: BufferParams,
b: BufferParams,
c: BufferParams,
d: BufferParams,
e: BufferParams)(implicit p: Parameters): TLNode =
{
val buffer = LazyModule(new TLBuffer(a, b, c, d, e))
buffer.node
}
def chain(depth: Int, name: Option[String] = None)(implicit p: Parameters): Seq[TLNode] = {
val buffers = Seq.fill(depth) { LazyModule(new TLBuffer()) }
name.foreach { n => buffers.zipWithIndex.foreach { case (b, i) => b.suggestName(s"${n}_${i}") } }
buffers.map(_.node)
}
def chainNode(depth: Int, name: Option[String] = None)(implicit p: Parameters): TLNode = {
chain(depth, name)
.reduceLeftOption(_ :*=* _)
.getOrElse(TLNameNode("no_buffer"))
}
}
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
|
module TLBuffer_a21d64s8k1z3u( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [20:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [20:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [7:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [20:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [20:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [20:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_30 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a21d64s8k1z3u nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a21d64s8k1z3u nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v3.common.{MicroOp}
import boom.v3.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v3.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v3.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U}
def apply(ip: UInt, isel: UInt): SInt = {
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0).asSInt
}
}
/**
* Object to get the FP rounding mode out of a packed immediate.
*/
object ImmGenRm { def apply(ip: UInt): UInt = { return ip(2,0) } }
/**
* Object to get the FP function fype from a packed immediate.
* Note: only works if !(IS_B or IS_S)
*/
object ImmGenTyp { def apply(ip: UInt): UInt = { return ip(9,8) } }
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v3.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v3.common.MicroOp => Bool = u => true.B, flow: Boolean = true)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v3.common.BoomModule()(p)
with boom.v3.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire)
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B //!IsKilledByBranch(io.brupdate, io.enq.bits.uop)
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value) && !IsKilledByBranch(io.brupdate, out.uop) && !(io.flush && flush_fn(out.uop))
io.deq.bits := out
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, out.uop)
// For flow queue behavior.
if (flow) {
when (io.empty) {
io.deq.valid := io.enq.valid //&& !IsKilledByBranch(io.brupdate, io.enq.bits.uop)
io.deq.bits := io.enq.bits
io.deq.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
do_deq := false.B
when (io.deq.ready) { do_enq := false.B }
}
}
private val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
File functional-unit.scala:
//******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Functional Units
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// If regfile bypassing is disabled, then the functional unit must do its own
// bypassing in here on the WB stage (i.e., bypassing the io.resp.data)
//
// TODO: explore possibility of conditional IO fields? if a branch unit... how to add extra to IO in subclass?
package boom.v3.exu
import chisel3._
import chisel3.util._
import chisel3.experimental.dataview._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import freechips.rocketchip.tile
import freechips.rocketchip.rocket.{PipelinedMultiplier,BP,BreakpointUnit,Causes,CSR}
import boom.v3.common._
import boom.v3.ifu._
import boom.v3.util._
/**t
* Functional unit constants
*/
object FUConstants
{
// bit mask, since a given execution pipeline may support multiple functional units
val FUC_SZ = 10
val FU_X = BitPat.dontCare(FUC_SZ)
val FU_ALU = 1.U(FUC_SZ.W)
val FU_JMP = 2.U(FUC_SZ.W)
val FU_MEM = 4.U(FUC_SZ.W)
val FU_MUL = 8.U(FUC_SZ.W)
val FU_DIV = 16.U(FUC_SZ.W)
val FU_CSR = 32.U(FUC_SZ.W)
val FU_FPU = 64.U(FUC_SZ.W)
val FU_FDV = 128.U(FUC_SZ.W)
val FU_I2F = 256.U(FUC_SZ.W)
val FU_F2I = 512.U(FUC_SZ.W)
// FP stores generate data through FP F2I, and generate address through MemAddrCalc
val FU_F2IMEM = 516.U(FUC_SZ.W)
}
import FUConstants._
/**
* Class to tell the FUDecoders what units it needs to support
*
* @param alu support alu unit?
* @param bru support br unit?
* @param mem support mem unit?
* @param muld support multiple div unit?
* @param fpu support FP unit?
* @param csr support csr writing unit?
* @param fdiv support FP div unit?
* @param ifpu support int to FP unit?
*/
class SupportedFuncUnits(
val alu: Boolean = false,
val jmp: Boolean = false,
val mem: Boolean = false,
val muld: Boolean = false,
val fpu: Boolean = false,
val csr: Boolean = false,
val fdiv: Boolean = false,
val ifpu: Boolean = false)
{
}
/**
* Bundle for signals sent to the functional unit
*
* @param dataWidth width of the data sent to the functional unit
*/
class FuncUnitReq(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val numOperands = 3
val rs1_data = UInt(dataWidth.W)
val rs2_data = UInt(dataWidth.W)
val rs3_data = UInt(dataWidth.W) // only used for FMA units
val pred_data = Bool()
val kill = Bool() // kill everything
}
/**
* Bundle for the signals sent out of the function unit
*
* @param dataWidth data sent from the functional unit
*/
class FuncUnitResp(val dataWidth: Int)(implicit p: Parameters) extends BoomBundle
with HasBoomUOP
{
val predicated = Bool() // Was this response from a predicated-off instruction
val data = UInt(dataWidth.W)
val fflags = new ValidIO(new FFlagsResp)
val addr = UInt((vaddrBits+1).W) // only for maddr -> LSU
val mxcpt = new ValidIO(UInt((freechips.rocketchip.rocket.Causes.all.max+2).W)) //only for maddr->LSU
val sfence = Valid(new freechips.rocketchip.rocket.SFenceReq) // only for mcalc
}
/**
* Branch resolution information given from the branch unit
*/
class BrResolutionInfo(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp
val valid = Bool()
val mispredict = Bool()
val taken = Bool() // which direction did the branch go?
val cfi_type = UInt(CFI_SZ.W)
// Info for recalculating the pc for this branch
val pc_sel = UInt(2.W)
val jalr_target = UInt(vaddrBitsExtended.W)
val target_offset = SInt()
}
class BrUpdateInfo(implicit p: Parameters) extends BoomBundle
{
// On the first cycle we get masks to kill registers
val b1 = new BrUpdateMasks
// On the second cycle we get indices to reset pointers
val b2 = new BrResolutionInfo
}
class BrUpdateMasks(implicit p: Parameters) extends BoomBundle
{
val resolve_mask = UInt(maxBrCount.W)
val mispredict_mask = UInt(maxBrCount.W)
}
/**
* Abstract top level functional unit class that wraps a lower level hand made functional unit
*
* @param isPipelined is the functional unit pipelined?
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class FunctionalUnit(
val isPipelined: Boolean,
val numStages: Int,
val numBypassStages: Int,
val dataWidth: Int,
val isJmpUnit: Boolean = false,
val isAluUnit: Boolean = false,
val isMemAddrCalcUnit: Boolean = false,
val needsFcsr: Boolean = false)
(implicit p: Parameters) extends BoomModule
{
val io = IO(new Bundle {
val req = Flipped(new DecoupledIO(new FuncUnitReq(dataWidth)))
val resp = (new DecoupledIO(new FuncUnitResp(dataWidth)))
val brupdate = Input(new BrUpdateInfo())
val bypass = Output(Vec(numBypassStages, Valid(new ExeUnitResp(dataWidth))))
// only used by the fpu unit
val fcsr_rm = if (needsFcsr) Input(UInt(tile.FPConstants.RM_SZ.W)) else null
// only used by branch unit
val brinfo = if (isAluUnit) Output(new BrResolutionInfo()) else null
val get_ftq_pc = if (isJmpUnit) Flipped(new GetPCFromFtqIO()) else null
val status = if (isMemAddrCalcUnit) Input(new freechips.rocketchip.rocket.MStatus()) else null
// only used by memaddr calc unit
val bp = if (isMemAddrCalcUnit) Input(Vec(nBreakpoints, new BP)) else null
val mcontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.mcontextWidth.W)) else null
val scontext = if (isMemAddrCalcUnit) Input(UInt(coreParams.scontextWidth.W)) else null
})
io.bypass.foreach { b => b.valid := false.B; b.bits := DontCare }
io.resp.valid := false.B
io.resp.bits := DontCare
if (isJmpUnit) {
io.get_ftq_pc.ftq_idx := DontCare
}
}
/**
* Abstract top level pipelined functional unit
*
* Note: this helps track which uops get killed while in intermediate stages,
* but it is the job of the consumer to check for kills on the same cycle as consumption!!!
*
* @param numStages how many pipeline stages does the functional unit have
* @param numBypassStages how many bypass stages does the function unit have
* @param earliestBypassStage first stage that you can start bypassing from
* @param dataWidth width of the data being operated on in the functional unit
* @param hasBranchUnit does this functional unit have a branch unit?
*/
abstract class PipelinedFunctionalUnit(
numStages: Int,
numBypassStages: Int,
earliestBypassStage: Int,
dataWidth: Int,
isJmpUnit: Boolean = false,
isAluUnit: Boolean = false,
isMemAddrCalcUnit: Boolean = false,
needsFcsr: Boolean = false
)(implicit p: Parameters) extends FunctionalUnit(
isPipelined = true,
numStages = numStages,
numBypassStages = numBypassStages,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit,
isAluUnit = isAluUnit,
isMemAddrCalcUnit = isMemAddrCalcUnit,
needsFcsr = needsFcsr)
{
// Pipelined functional unit is always ready.
io.req.ready := true.B
if (numStages > 0) {
val r_valids = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_uops = Reg(Vec(numStages, new MicroOp()))
// handle incoming request
r_valids(0) := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop) && !io.req.bits.kill
r_uops(0) := io.req.bits.uop
r_uops(0).br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
// handle middle of the pipeline
for (i <- 1 until numStages) {
r_valids(i) := r_valids(i-1) && !IsKilledByBranch(io.brupdate, r_uops(i-1)) && !io.req.bits.kill
r_uops(i) := r_uops(i-1)
r_uops(i).br_mask := GetNewBrMask(io.brupdate, r_uops(i-1))
if (numBypassStages > 0) {
io.bypass(i-1).bits.uop := r_uops(i-1)
}
}
// handle outgoing (branch could still kill it)
// consumer must also check for pipeline flushes (kills)
io.resp.valid := r_valids(numStages-1) && !IsKilledByBranch(io.brupdate, r_uops(numStages-1))
io.resp.bits.predicated := false.B
io.resp.bits.uop := r_uops(numStages-1)
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, r_uops(numStages-1))
// bypassing (TODO allow bypass vector to have a different size from numStages)
if (numBypassStages > 0 && earliestBypassStage == 0) {
io.bypass(0).bits.uop := io.req.bits.uop
for (i <- 1 until numBypassStages) {
io.bypass(i).bits.uop := r_uops(i-1)
}
}
} else {
require (numStages == 0)
// pass req straight through to response
// valid doesn't check kill signals, let consumer deal with it.
// The LSU already handles it and this hurts critical path.
io.resp.valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.req.bits.uop)
io.resp.bits.predicated := false.B
io.resp.bits.uop := io.req.bits.uop
io.resp.bits.uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
}
}
/**
* Functional unit that wraps RocketChips ALU
*
* @param isBranchUnit is this a branch unit?
* @param numStages how many pipeline stages does the functional unit have
* @param dataWidth width of the data being operated on in the functional unit
*/
class ALUUnit(isJmpUnit: Boolean = false, numStages: Int = 1, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = numStages,
isAluUnit = true,
earliestBypassStage = 0,
dataWidth = dataWidth,
isJmpUnit = isJmpUnit)
with boom.v3.ifu.HasBoomFrontendParameters
{
val uop = io.req.bits.uop
// immediate generation
val imm_xprlen = ImmGen(uop.imm_packed, uop.ctrl.imm_sel)
// operand 1 select
var op1_data: UInt = null
if (isJmpUnit) {
// Get the uop PC for jumps
val block_pc = AlignPCToBoundary(io.get_ftq_pc.pc, icBlockBytes)
val uop_pc = (block_pc | uop.pc_lob) - Mux(uop.edge_inst, 2.U, 0.U)
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
Mux(uop.ctrl.op1_sel.asUInt === OP1_PC , Sext(uop_pc, xLen),
0.U))
} else {
op1_data = Mux(uop.ctrl.op1_sel.asUInt === OP1_RS1 , io.req.bits.rs1_data,
0.U)
}
// operand 2 select
val op2_data = Mux(uop.ctrl.op2_sel === OP2_IMM, Sext(imm_xprlen.asUInt, xLen),
Mux(uop.ctrl.op2_sel === OP2_IMMC, io.req.bits.uop.prs1(4,0),
Mux(uop.ctrl.op2_sel === OP2_RS2 , io.req.bits.rs2_data,
Mux(uop.ctrl.op2_sel === OP2_NEXT, Mux(uop.is_rvc, 2.U, 4.U),
0.U))))
val alu = Module(new freechips.rocketchip.rocket.ALU())
alu.io.in1 := op1_data.asUInt
alu.io.in2 := op2_data.asUInt
alu.io.fn := uop.ctrl.op_fcn
alu.io.dw := uop.ctrl.fcn_dw
// Did I just get killed by the previous cycle's branch,
// or by a flush pipeline?
val killed = WireInit(false.B)
when (io.req.bits.kill || IsKilledByBranch(io.brupdate, uop)) {
killed := true.B
}
val rs1 = io.req.bits.rs1_data
val rs2 = io.req.bits.rs2_data
val br_eq = (rs1 === rs2)
val br_ltu = (rs1.asUInt < rs2.asUInt)
val br_lt = (~(rs1(xLen-1) ^ rs2(xLen-1)) & br_ltu |
rs1(xLen-1) & ~rs2(xLen-1)).asBool
val pc_sel = MuxLookup(uop.ctrl.br_type, PC_PLUS4)(
Seq( BR_N -> PC_PLUS4,
BR_NE -> Mux(!br_eq, PC_BRJMP, PC_PLUS4),
BR_EQ -> Mux( br_eq, PC_BRJMP, PC_PLUS4),
BR_GE -> Mux(!br_lt, PC_BRJMP, PC_PLUS4),
BR_GEU -> Mux(!br_ltu, PC_BRJMP, PC_PLUS4),
BR_LT -> Mux( br_lt, PC_BRJMP, PC_PLUS4),
BR_LTU -> Mux( br_ltu, PC_BRJMP, PC_PLUS4),
BR_J -> PC_BRJMP,
BR_JR -> PC_JALR
))
val is_taken = io.req.valid &&
!killed &&
(uop.is_br || uop.is_jalr || uop.is_jal) &&
(pc_sel =/= PC_PLUS4)
// "mispredict" means that a branch has been resolved and it must be killed
val mispredict = WireInit(false.B)
val is_br = io.req.valid && !killed && uop.is_br && !uop.is_sfb
val is_jal = io.req.valid && !killed && uop.is_jal
val is_jalr = io.req.valid && !killed && uop.is_jalr
when (is_br || is_jalr) {
if (!isJmpUnit) {
assert (pc_sel =/= PC_JALR)
}
when (pc_sel === PC_PLUS4) {
mispredict := uop.taken
}
when (pc_sel === PC_BRJMP) {
mispredict := !uop.taken
}
}
val brinfo = Wire(new BrResolutionInfo)
// note: jal doesn't allocate a branch-mask, so don't clear a br-mask bit
brinfo.valid := is_br || is_jalr
brinfo.mispredict := mispredict
brinfo.uop := uop
brinfo.cfi_type := Mux(is_jalr, CFI_JALR,
Mux(is_br , CFI_BR, CFI_X))
brinfo.taken := is_taken
brinfo.pc_sel := pc_sel
brinfo.jalr_target := DontCare
// Branch/Jump Target Calculation
// For jumps we read the FTQ, and can calculate the target
// For branches we emit the offset for the core to redirect if necessary
val target_offset = imm_xprlen(20,0).asSInt
brinfo.jalr_target := DontCare
if (isJmpUnit) {
def encodeVirtualAddress(a0: UInt, ea: UInt) = if (vaddrBitsExtended == vaddrBits) {
ea
} else {
// Efficient means to compress 64-bit VA into vaddrBits+1 bits.
// (VA is bad if VA(vaddrBits) != VA(vaddrBits-1)).
val a = a0.asSInt >> vaddrBits
val msb = Mux(a === 0.S || a === -1.S, ea(vaddrBits), !ea(vaddrBits-1))
Cat(msb, ea(vaddrBits-1,0))
}
val jalr_target_base = io.req.bits.rs1_data.asSInt
val jalr_target_xlen = Wire(UInt(xLen.W))
jalr_target_xlen := (jalr_target_base + target_offset).asUInt
val jalr_target = (encodeVirtualAddress(jalr_target_xlen, jalr_target_xlen).asSInt & -2.S).asUInt
brinfo.jalr_target := jalr_target
val cfi_idx = ((uop.pc_lob ^ Mux(io.get_ftq_pc.entry.start_bank === 1.U, 1.U << log2Ceil(bankBytes), 0.U)))(log2Ceil(fetchWidth),1)
when (pc_sel === PC_JALR) {
mispredict := !io.get_ftq_pc.next_val ||
(io.get_ftq_pc.next_pc =/= jalr_target) ||
!io.get_ftq_pc.entry.cfi_idx.valid ||
(io.get_ftq_pc.entry.cfi_idx.bits =/= cfi_idx)
}
}
brinfo.target_offset := target_offset
io.brinfo := brinfo
// Response
// TODO add clock gate on resp bits from functional units
// io.resp.bits.data := RegEnable(alu.io.out, io.req.valid)
// val reg_data = Reg(outType = Bits(width = xLen))
// reg_data := alu.io.out
// io.resp.bits.data := reg_data
val r_val = RegInit(VecInit(Seq.fill(numStages) { false.B }))
val r_data = Reg(Vec(numStages, UInt(xLen.W)))
val r_pred = Reg(Vec(numStages, Bool()))
val alu_out = Mux(io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data,
Mux(io.req.bits.uop.ldst_is_rs1, io.req.bits.rs1_data, io.req.bits.rs2_data),
Mux(io.req.bits.uop.uopc === uopMOV, io.req.bits.rs2_data, alu.io.out))
r_val (0) := io.req.valid
r_data(0) := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
r_pred(0) := io.req.bits.uop.is_sfb_shadow && io.req.bits.pred_data
for (i <- 1 until numStages) {
r_val(i) := r_val(i-1)
r_data(i) := r_data(i-1)
r_pred(i) := r_pred(i-1)
}
io.resp.bits.data := r_data(numStages-1)
io.resp.bits.predicated := r_pred(numStages-1)
// Bypass
// for the ALU, we can bypass same cycle as compute
require (numStages >= 1)
require (numBypassStages >= 1)
io.bypass(0).valid := io.req.valid
io.bypass(0).bits.data := Mux(io.req.bits.uop.is_sfb_br, pc_sel === PC_BRJMP, alu_out)
for (i <- 1 until numStages) {
io.bypass(i).valid := r_val(i-1)
io.bypass(i).bits.data := r_data(i-1)
}
// Exceptions
io.resp.bits.fflags.valid := false.B
}
/**
* Functional unit that passes in base+imm to calculate addresses, and passes store data
* to the LSU.
* For floating point, 65bit FP store-data needs to be decoded into 64bit FP form
*/
class MemAddrCalcUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = 0,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65, // TODO enable this only if FP is enabled?
isMemAddrCalcUnit = true)
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
// perform address calculation
val sum = (io.req.bits.rs1_data.asSInt + io.req.bits.uop.imm_packed(19,8).asSInt).asUInt
val ea_sign = Mux(sum(vaddrBits-1), ~sum(63,vaddrBits) === 0.U,
sum(63,vaddrBits) =/= 0.U)
val effective_address = Cat(ea_sign, sum(vaddrBits-1,0)).asUInt
val store_data = io.req.bits.rs2_data
io.resp.bits.addr := effective_address
io.resp.bits.data := store_data
if (dataWidth > 63) {
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std &&
io.resp.bits.data(64).asBool === true.B), "65th bit set in MemAddrCalcUnit.")
assert (!(io.req.valid && io.req.bits.uop.ctrl.is_std && io.req.bits.uop.fp_val),
"FP store-data should now be going through a different unit.")
}
assert (!(io.req.bits.uop.fp_val && io.req.valid && io.req.bits.uop.uopc =/=
uopLD && io.req.bits.uop.uopc =/= uopSTA),
"[maddrcalc] assert we never get store data in here.")
// Handle misaligned exceptions
val size = io.req.bits.uop.mem_size
val misaligned =
(size === 1.U && (effective_address(0) =/= 0.U)) ||
(size === 2.U && (effective_address(1,0) =/= 0.U)) ||
(size === 3.U && (effective_address(2,0) =/= 0.U))
val bkptu = Module(new BreakpointUnit(nBreakpoints))
bkptu.io.status := io.status
bkptu.io.bp := io.bp
bkptu.io.pc := DontCare
bkptu.io.ea := effective_address
bkptu.io.mcontext := io.mcontext
bkptu.io.scontext := io.scontext
val ma_ld = io.req.valid && io.req.bits.uop.uopc === uopLD && misaligned
val ma_st = io.req.valid && (io.req.bits.uop.uopc === uopSTA || io.req.bits.uop.uopc === uopAMO_AG) && misaligned
val dbg_bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.debug_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.debug_st))
val bp = io.req.valid && ((io.req.bits.uop.uopc === uopLD && bkptu.io.xcpt_ld) ||
(io.req.bits.uop.uopc === uopSTA && bkptu.io.xcpt_st))
def checkExceptions(x: Seq[(Bool, UInt)]) =
(x.map(_._1).reduce(_||_), PriorityMux(x))
val (xcpt_val, xcpt_cause) = checkExceptions(List(
(ma_ld, (Causes.misaligned_load).U),
(ma_st, (Causes.misaligned_store).U),
(dbg_bp, (CSR.debugTriggerCause).U),
(bp, (Causes.breakpoint).U)))
io.resp.bits.mxcpt.valid := xcpt_val
io.resp.bits.mxcpt.bits := xcpt_cause
assert (!(ma_ld && ma_st), "Mutually-exclusive exceptions are firing.")
io.resp.bits.sfence.valid := io.req.valid && io.req.bits.uop.mem_cmd === M_SFENCE
io.resp.bits.sfence.bits.rs1 := io.req.bits.uop.mem_size(0)
io.resp.bits.sfence.bits.rs2 := io.req.bits.uop.mem_size(1)
io.resp.bits.sfence.bits.addr := io.req.bits.rs1_data
io.resp.bits.sfence.bits.asid := io.req.bits.rs2_data
}
/**
* Functional unit to wrap lower level FPU
*
* Currently, bypassing is unsupported!
* All FP instructions are padded out to the max latency unit for easy
* write-port scheduling.
*/
class FPUUnit(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = p(tile.TileKey).core.fpu.get.dfmaLatency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
{
val fpu = Module(new FPU())
fpu.io.req.valid := io.req.valid
fpu.io.req.bits.uop := io.req.bits.uop
fpu.io.req.bits.rs1_data := io.req.bits.rs1_data
fpu.io.req.bits.rs2_data := io.req.bits.rs2_data
fpu.io.req.bits.rs3_data := io.req.bits.rs3_data
fpu.io.req.bits.fcsr_rm := io.fcsr_rm
io.resp.bits.data := fpu.io.resp.bits.data
io.resp.bits.fflags.valid := fpu.io.resp.bits.fflags.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := fpu.io.resp.bits.fflags.bits.flags // kill me now
}
/**
* Int to FP conversion functional unit
*
* @param latency the amount of stages to delay by
*/
class IntToFPUnit(latency: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = latency,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = 65,
needsFcsr = true)
with tile.HasFPUParameters
{
val fp_decoder = Module(new UOPCodeFPUDecoder) // TODO use a simpler decoder
val io_req = io.req.bits
fp_decoder.io.uopc := io_req.uop.uopc
val fp_ctrl = fp_decoder.io.sigs
val fp_rm = Mux(ImmGenRm(io_req.uop.imm_packed) === 7.U, io.fcsr_rm, ImmGenRm(io_req.uop.imm_packed))
val req = Wire(new tile.FPInput)
val tag = fp_ctrl.typeTagIn
req.viewAsSupertype(new tile.FPUCtrlSigs) := fp_ctrl
req.rm := fp_rm
req.in1 := unbox(io_req.rs1_data, tag, None)
req.in2 := unbox(io_req.rs2_data, tag, None)
req.in3 := DontCare
req.typ := ImmGenTyp(io_req.uop.imm_packed)
req.fmt := DontCare // FIXME: this may not be the right thing to do here
req.fmaCmd := DontCare
assert (!(io.req.valid && fp_ctrl.fromint && req.in1(xLen).asBool),
"[func] IntToFP integer input has 65th high-order bit set!")
assert (!(io.req.valid && !fp_ctrl.fromint),
"[func] Only support fromInt micro-ops.")
val ifpu = Module(new tile.IntToFP(intToFpLatency))
ifpu.io.in.valid := io.req.valid
ifpu.io.in.bits := req
ifpu.io.in.bits.in1 := io_req.rs1_data
val out_double = Pipe(io.req.valid, fp_ctrl.typeTagOut === D, intToFpLatency).bits
//io.resp.bits.data := box(ifpu.io.out.bits.data, !io.resp.bits.uop.fp_single)
io.resp.bits.data := box(ifpu.io.out.bits.data, out_double)
io.resp.bits.fflags.valid := ifpu.io.out.valid
io.resp.bits.fflags.bits.uop := io.resp.bits.uop
io.resp.bits.fflags.bits.flags := ifpu.io.out.bits.exc
}
/**
* Iterative/unpipelined functional unit, can only hold a single MicroOp at a time
* assumes at least one register between request and response
*
* TODO allow up to N micro-ops simultaneously.
*
* @param dataWidth width of the data to be passed into the functional unit
*/
abstract class IterativeFunctionalUnit(dataWidth: Int)(implicit p: Parameters)
extends FunctionalUnit(
isPipelined = false,
numStages = 1,
numBypassStages = 0,
dataWidth = dataWidth)
{
val r_uop = Reg(new MicroOp())
val do_kill = Wire(Bool())
do_kill := io.req.bits.kill // irrelevant default
when (io.req.fire) {
// update incoming uop
do_kill := IsKilledByBranch(io.brupdate, io.req.bits.uop) || io.req.bits.kill
r_uop := io.req.bits.uop
r_uop.br_mask := GetNewBrMask(io.brupdate, io.req.bits.uop)
} .otherwise {
do_kill := IsKilledByBranch(io.brupdate, r_uop) || io.req.bits.kill
r_uop.br_mask := GetNewBrMask(io.brupdate, r_uop)
}
// assumes at least one pipeline register between request and response
io.resp.bits.uop := r_uop
}
/**
* Divide functional unit.
*
* @param dataWidth data to be passed into the functional unit
*/
class DivUnit(dataWidth: Int)(implicit p: Parameters)
extends IterativeFunctionalUnit(dataWidth)
{
// We don't use the iterative multiply functionality here.
// Instead we use the PipelinedMultiplier
val div = Module(new freechips.rocketchip.rocket.MulDiv(mulDivParams, width = dataWidth))
// request
div.io.req.valid := io.req.valid && !this.do_kill
div.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
div.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
div.io.req.bits.in1 := io.req.bits.rs1_data
div.io.req.bits.in2 := io.req.bits.rs2_data
div.io.req.bits.tag := DontCare
io.req.ready := div.io.req.ready
// handle pipeline kills and branch misspeculations
div.io.kill := this.do_kill
// response
io.resp.valid := div.io.resp.valid && !this.do_kill
div.io.resp.ready := io.resp.ready
io.resp.bits.data := div.io.resp.bits.data
}
/**
* Pipelined multiplier functional unit that wraps around the RocketChip pipelined multiplier
*
* @param numStages number of pipeline stages
* @param dataWidth size of the data being passed into the functional unit
*/
class PipelinedMulUnit(numStages: Int, dataWidth: Int)(implicit p: Parameters)
extends PipelinedFunctionalUnit(
numStages = numStages,
numBypassStages = 0,
earliestBypassStage = 0,
dataWidth = dataWidth)
{
val imul = Module(new PipelinedMultiplier(xLen, numStages))
// request
imul.io.req.valid := io.req.valid
imul.io.req.bits.fn := io.req.bits.uop.ctrl.op_fcn
imul.io.req.bits.dw := io.req.bits.uop.ctrl.fcn_dw
imul.io.req.bits.in1 := io.req.bits.rs1_data
imul.io.req.bits.in2 := io.req.bits.rs2_data
imul.io.req.bits.tag := DontCare
// response
io.resp.bits.data := imul.io.resp.bits.data
}
File micro-op.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// MicroOp
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v3.common
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v3.exu.FUConstants
/**
* Extension to BoomBundle to add a MicroOp
*/
abstract trait HasBoomUOP extends BoomBundle
{
val uop = new MicroOp()
}
/**
* MicroOp passing through the pipeline
*/
class MicroOp(implicit p: Parameters) extends BoomBundle
with freechips.rocketchip.rocket.constants.MemoryOpConstants
with freechips.rocketchip.rocket.constants.ScalarOpConstants
{
val uopc = UInt(UOPC_SZ.W) // micro-op code
val inst = UInt(32.W)
val debug_inst = UInt(32.W)
val is_rvc = Bool()
val debug_pc = UInt(coreMaxAddrBits.W)
val iq_type = UInt(IQT_SZ.W) // which issue unit do we use?
val fu_code = UInt(FUConstants.FUC_SZ.W) // which functional unit do we use?
val ctrl = new CtrlSignals
// What is the next state of this uop in the issue window? useful
// for the compacting queue.
val iw_state = UInt(2.W)
// Has operand 1 or 2 been waken speculatively by a load?
// Only integer operands are speculaively woken up,
// so we can ignore p3.
val iw_p1_poisoned = Bool()
val iw_p2_poisoned = Bool()
val is_br = Bool() // is this micro-op a (branch) vs a regular PC+4 inst?
val is_jalr = Bool() // is this a jump? (jal or jalr)
val is_jal = Bool() // is this a JAL (doesn't include JR)? used for branch unit
val is_sfb = Bool() // is this a sfb or in the shadow of a sfb
val br_mask = UInt(maxBrCount.W) // which branches are we being speculated under?
val br_tag = UInt(brTagSz.W)
// Index into FTQ to figure out our fetch PC.
val ftq_idx = UInt(log2Ceil(ftqSz).W)
// This inst straddles two fetch packets
val edge_inst = Bool()
// Low-order bits of our own PC. Combine with ftq[ftq_idx] to get PC.
// Aligned to a cache-line size, as that is the greater fetch granularity.
// TODO: Shouldn't this be aligned to fetch-width size?
val pc_lob = UInt(log2Ceil(icBlockBytes).W)
// Was this a branch that was predicted taken?
val taken = Bool()
val imm_packed = UInt(LONGEST_IMM_SZ.W) // densely pack the imm in decode...
// then translate and sign-extend in execute
val csr_addr = UInt(CSR_ADDR_SZ.W) // only used for critical path reasons in Exe
val rob_idx = UInt(robAddrSz.W)
val ldq_idx = UInt(ldqAddrSz.W)
val stq_idx = UInt(stqAddrSz.W)
val rxq_idx = UInt(log2Ceil(numRxqEntries).W)
val pdst = UInt(maxPregSz.W)
val prs1 = UInt(maxPregSz.W)
val prs2 = UInt(maxPregSz.W)
val prs3 = UInt(maxPregSz.W)
val ppred = UInt(log2Ceil(ftqSz).W)
val prs1_busy = Bool()
val prs2_busy = Bool()
val prs3_busy = Bool()
val ppred_busy = Bool()
val stale_pdst = UInt(maxPregSz.W)
val exception = Bool()
val exc_cause = UInt(xLen.W) // TODO compress this down, xlen is insanity
val bypassable = Bool() // can we bypass ALU results? (doesn't include loads, csr, etc...)
val mem_cmd = UInt(M_SZ.W) // sync primitives/cache flushes
val mem_size = UInt(2.W)
val mem_signed = Bool()
val is_fence = Bool()
val is_fencei = Bool()
val is_amo = Bool()
val uses_ldq = Bool()
val uses_stq = Bool()
val is_sys_pc2epc = Bool() // Is a ECall or Breakpoint -- both set EPC to PC.
val is_unique = Bool() // only allow this instruction in the pipeline, wait for STQ to
// drain, clear fetcha fter it (tell ROB to un-ready until empty)
val flush_on_commit = Bool() // some instructions need to flush the pipeline behind them
// Preditation
def is_sfb_br = is_br && is_sfb && enableSFBOpt.B // Does this write a predicate
def is_sfb_shadow = !is_br && is_sfb && enableSFBOpt.B // Is this predicated
val ldst_is_rs1 = Bool() // If this is set and we are predicated off, copy rs1 to dst,
// else copy rs2 to dst
// logical specifiers (only used in Decode->Rename), except rollback (ldst)
val ldst = UInt(lregSz.W)
val lrs1 = UInt(lregSz.W)
val lrs2 = UInt(lregSz.W)
val lrs3 = UInt(lregSz.W)
val ldst_val = Bool() // is there a destination? invalid for stores, rd==x0, etc.
val dst_rtype = UInt(2.W)
val lrs1_rtype = UInt(2.W)
val lrs2_rtype = UInt(2.W)
val frs3_en = Bool()
// floating point information
val fp_val = Bool() // is a floating-point instruction (F- or D-extension)?
// If it's non-ld/st it will write back exception bits to the fcsr.
val fp_single = Bool() // single-precision floating point instruction (F-extension)
// frontend exception information
val xcpt_pf_if = Bool() // I-TLB page fault.
val xcpt_ae_if = Bool() // I$ access exception.
val xcpt_ma_if = Bool() // Misaligned fetch (jal/brjumping to misaligned addr).
val bp_debug_if = Bool() // Breakpoint
val bp_xcpt_if = Bool() // Breakpoint
// What prediction structure provides the prediction FROM this op
val debug_fsrc = UInt(BSRC_SZ.W)
// What prediction structure provides the prediction TO this op
val debug_tsrc = UInt(BSRC_SZ.W)
// Do we allocate a branch tag for this?
// SFB branches don't get a mask, they get a predicate bit
def allocate_brtag = (is_br && !is_sfb) || is_jalr
// Does this register write-back
def rf_wen = dst_rtype =/= RT_X
// Is it possible for this uop to misspeculate, preventing the commit of subsequent uops?
def unsafe = uses_ldq || (uses_stq && !is_fence) || is_br || is_jalr
def fu_code_is(_fu: UInt) = (fu_code & _fu) =/= 0.U
}
/**
* Control signals within a MicroOp
*
* TODO REFACTOR this, as this should no longer be true, as bypass occurs in stage before branch resolution
*/
class CtrlSignals extends Bundle()
{
val br_type = UInt(BR_N.getWidth.W)
val op1_sel = UInt(OP1_X.getWidth.W)
val op2_sel = UInt(OP2_X.getWidth.W)
val imm_sel = UInt(IS_X.getWidth.W)
val op_fcn = UInt(freechips.rocketchip.rocket.ALU.SZ_ALU_FN.W)
val fcn_dw = Bool()
val csr_cmd = UInt(freechips.rocketchip.rocket.CSR.SZ.W)
val is_load = Bool() // will invoke TLB address lookup
val is_sta = Bool() // will invoke TLB address lookup
val is_std = Bool()
}
|
module ALUUnit_5( // @[functional-unit.scala:290:7]
input clock, // @[functional-unit.scala:290:7]
input reset, // @[functional-unit.scala:290:7]
input io_req_valid, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_req_bits_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_iw_state, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_br, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_jal, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
input [15:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:168:14]
input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_req_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_req_bits_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_req_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_req_bits_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:168:14]
input io_req_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fence, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_amo, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_req_bits_uop_is_unique, // @[functional-unit.scala:168:14]
input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:168:14]
input io_req_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_req_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_val, // @[functional-unit.scala:168:14]
input io_req_bits_uop_fp_single, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:168:14]
input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:168:14]
input io_req_bits_kill, // @[functional-unit.scala:168:14]
output io_resp_valid, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_resp_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [15:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [63:0] io_resp_bits_data, // @[functional-unit.scala:168:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:168:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:168:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[functional-unit.scala:168:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_br, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jalr, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_jal, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:168:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:168:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_taken, // @[functional-unit.scala:168:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:168:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:168:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_exception, // @[functional-unit.scala:168:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bypassable, // @[functional-unit.scala:168:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:168:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_ldst_val, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_fp_single, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:168:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:168:14]
input io_brupdate_b2_valid, // @[functional-unit.scala:168:14]
input io_brupdate_b2_mispredict, // @[functional-unit.scala:168:14]
input io_brupdate_b2_taken, // @[functional-unit.scala:168:14]
input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:168:14]
input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:168:14]
input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:168:14]
input [20:0] io_brupdate_b2_target_offset, // @[functional-unit.scala:168:14]
output io_bypass_0_valid, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_0_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_0_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_0_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_bypass_0_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_bypass_0_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_0_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_0_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [15:0] io_bypass_0_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_0_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_0_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_bypass_0_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_bypass_0_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_0_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_0_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_0_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_0_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_0_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_0_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_0_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_0_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_0_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_0_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_0_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_0_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_bypass_0_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_0_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_0_bits_data, // @[functional-unit.scala:168:14]
output io_bypass_1_valid, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_1_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_1_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_1_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_bypass_1_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_bypass_1_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_1_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_1_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [15:0] io_bypass_1_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_1_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_1_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_bypass_1_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_bypass_1_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_1_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_1_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_1_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_1_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_1_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_1_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_1_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_1_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_1_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_1_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_1_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_1_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_bypass_1_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_1_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_1_bits_data, // @[functional-unit.scala:168:14]
output io_bypass_2_valid, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_2_bits_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_2_bits_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_bypass_2_bits_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_bypass_2_bits_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_bypass_2_bits_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_2_bits_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_2_bits_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_iw_state, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_br, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_jal, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_sfb, // @[functional-unit.scala:168:14]
output [15:0] io_bypass_2_bits_uop_br_mask, // @[functional-unit.scala:168:14]
output [3:0] io_bypass_2_bits_uop_br_tag, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_2_bits_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_bypass_2_bits_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_bypass_2_bits_uop_csr_addr, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_2_bits_uop_rob_idx, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_2_bits_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_2_bits_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_2_bits_uop_pdst, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_2_bits_uop_prs1, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_2_bits_uop_prs2, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_2_bits_uop_prs3, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_2_bits_uop_ppred, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [6:0] io_bypass_2_bits_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_2_bits_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_bypass_2_bits_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_mem_size, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_fence, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_amo, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_is_unique, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_bypass_2_bits_uop_lrs3, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_fp_val, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_fp_single, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_bypass_2_bits_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_bypass_2_bits_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output [63:0] io_bypass_2_bits_data, // @[functional-unit.scala:168:14]
output [6:0] io_brinfo_uop_uopc, // @[functional-unit.scala:168:14]
output [31:0] io_brinfo_uop_inst, // @[functional-unit.scala:168:14]
output [31:0] io_brinfo_uop_debug_inst, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_rvc, // @[functional-unit.scala:168:14]
output [39:0] io_brinfo_uop_debug_pc, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_iq_type, // @[functional-unit.scala:168:14]
output [9:0] io_brinfo_uop_fu_code, // @[functional-unit.scala:168:14]
output [3:0] io_brinfo_uop_ctrl_br_type, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_ctrl_op1_sel, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_ctrl_op2_sel, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_ctrl_imm_sel, // @[functional-unit.scala:168:14]
output [4:0] io_brinfo_uop_ctrl_op_fcn, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ctrl_fcn_dw, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_uop_ctrl_csr_cmd, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ctrl_is_load, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ctrl_is_sta, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ctrl_is_std, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_iw_state, // @[functional-unit.scala:168:14]
output io_brinfo_uop_iw_p1_poisoned, // @[functional-unit.scala:168:14]
output io_brinfo_uop_iw_p2_poisoned, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_br, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_jalr, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_jal, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_sfb, // @[functional-unit.scala:168:14]
output [15:0] io_brinfo_uop_br_mask, // @[functional-unit.scala:168:14]
output [3:0] io_brinfo_uop_br_tag, // @[functional-unit.scala:168:14]
output [4:0] io_brinfo_uop_ftq_idx, // @[functional-unit.scala:168:14]
output io_brinfo_uop_edge_inst, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_pc_lob, // @[functional-unit.scala:168:14]
output io_brinfo_uop_taken, // @[functional-unit.scala:168:14]
output [19:0] io_brinfo_uop_imm_packed, // @[functional-unit.scala:168:14]
output [11:0] io_brinfo_uop_csr_addr, // @[functional-unit.scala:168:14]
output [6:0] io_brinfo_uop_rob_idx, // @[functional-unit.scala:168:14]
output [4:0] io_brinfo_uop_ldq_idx, // @[functional-unit.scala:168:14]
output [4:0] io_brinfo_uop_stq_idx, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_rxq_idx, // @[functional-unit.scala:168:14]
output [6:0] io_brinfo_uop_pdst, // @[functional-unit.scala:168:14]
output [6:0] io_brinfo_uop_prs1, // @[functional-unit.scala:168:14]
output [6:0] io_brinfo_uop_prs2, // @[functional-unit.scala:168:14]
output [6:0] io_brinfo_uop_prs3, // @[functional-unit.scala:168:14]
output [4:0] io_brinfo_uop_ppred, // @[functional-unit.scala:168:14]
output io_brinfo_uop_prs1_busy, // @[functional-unit.scala:168:14]
output io_brinfo_uop_prs2_busy, // @[functional-unit.scala:168:14]
output io_brinfo_uop_prs3_busy, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ppred_busy, // @[functional-unit.scala:168:14]
output [6:0] io_brinfo_uop_stale_pdst, // @[functional-unit.scala:168:14]
output io_brinfo_uop_exception, // @[functional-unit.scala:168:14]
output [63:0] io_brinfo_uop_exc_cause, // @[functional-unit.scala:168:14]
output io_brinfo_uop_bypassable, // @[functional-unit.scala:168:14]
output [4:0] io_brinfo_uop_mem_cmd, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_mem_size, // @[functional-unit.scala:168:14]
output io_brinfo_uop_mem_signed, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_fence, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_fencei, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_amo, // @[functional-unit.scala:168:14]
output io_brinfo_uop_uses_ldq, // @[functional-unit.scala:168:14]
output io_brinfo_uop_uses_stq, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_sys_pc2epc, // @[functional-unit.scala:168:14]
output io_brinfo_uop_is_unique, // @[functional-unit.scala:168:14]
output io_brinfo_uop_flush_on_commit, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ldst_is_rs1, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_ldst, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_lrs1, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_lrs2, // @[functional-unit.scala:168:14]
output [5:0] io_brinfo_uop_lrs3, // @[functional-unit.scala:168:14]
output io_brinfo_uop_ldst_val, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_dst_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_lrs1_rtype, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_lrs2_rtype, // @[functional-unit.scala:168:14]
output io_brinfo_uop_frs3_en, // @[functional-unit.scala:168:14]
output io_brinfo_uop_fp_val, // @[functional-unit.scala:168:14]
output io_brinfo_uop_fp_single, // @[functional-unit.scala:168:14]
output io_brinfo_uop_xcpt_pf_if, // @[functional-unit.scala:168:14]
output io_brinfo_uop_xcpt_ae_if, // @[functional-unit.scala:168:14]
output io_brinfo_uop_xcpt_ma_if, // @[functional-unit.scala:168:14]
output io_brinfo_uop_bp_debug_if, // @[functional-unit.scala:168:14]
output io_brinfo_uop_bp_xcpt_if, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_debug_fsrc, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_uop_debug_tsrc, // @[functional-unit.scala:168:14]
output io_brinfo_valid, // @[functional-unit.scala:168:14]
output io_brinfo_mispredict, // @[functional-unit.scala:168:14]
output io_brinfo_taken, // @[functional-unit.scala:168:14]
output [2:0] io_brinfo_cfi_type, // @[functional-unit.scala:168:14]
output [1:0] io_brinfo_pc_sel, // @[functional-unit.scala:168:14]
output [20:0] io_brinfo_target_offset // @[functional-unit.scala:168:14]
);
wire [63:0] _alu_io_out; // @[functional-unit.scala:327:19]
wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:290:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[functional-unit.scala:290:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:290:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:290:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[functional-unit.scala:290:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[functional-unit.scala:290:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[functional-unit.scala:290:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[functional-unit.scala:290:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:290:7]
wire [15:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:290:7]
wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:290:7]
wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:290:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:290:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[functional-unit.scala:290:7]
wire [6:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:290:7]
wire [4:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:290:7]
wire [4:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:290:7]
wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:290:7]
wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:290:7]
wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:290:7]
wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:290:7]
wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:290:7]
wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:290:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[functional-unit.scala:290:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:290:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:290:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:290:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:290:7]
wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:290:7]
wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:290:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[functional-unit.scala:290:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:290:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:290:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[functional-unit.scala:290:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:290:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:290:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[functional-unit.scala:290:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[functional-unit.scala:290:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[functional-unit.scala:290:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:290:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:290:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:290:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:290:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:290:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[functional-unit.scala:290:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:290:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:290:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:290:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:290:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:290:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:290:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:290:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:290:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:290:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[functional-unit.scala:290:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:290:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:290:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:290:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:290:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:290:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:290:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:290:7]
wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_ready = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_mxcpt_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_bits_rs1 = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_bits_rs2 = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_bits_asid = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_bits_hv = 1'h0; // @[functional-unit.scala:290:7]
wire io_resp_bits_sfence_bits_hg = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_predicated = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_predicated = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_predicated = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_valid = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_rvc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_br = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_jalr = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_jal = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_sfb = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_edge_inst = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_taken = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_exception = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_bypassable = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_mem_signed = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_fence = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_fencei = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_amo = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_uses_stq = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_is_unique = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_ldst_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_frs3_en = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_fp_val = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_fp_single = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[functional-unit.scala:290:7]
wire _r_valids_WIRE_0 = 1'h0; // @[functional-unit.scala:236:35]
wire _r_valids_WIRE_1 = 1'h0; // @[functional-unit.scala:236:35]
wire _r_valids_WIRE_2 = 1'h0; // @[functional-unit.scala:236:35]
wire _r_val_WIRE_0 = 1'h0; // @[functional-unit.scala:446:31]
wire _r_val_WIRE_1 = 1'h0; // @[functional-unit.scala:446:31]
wire _r_val_WIRE_2 = 1'h0; // @[functional-unit.scala:446:31]
wire _alu_out_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire _alu_out_T_3 = 1'h0; // @[functional-unit.scala:449:51]
wire _r_data_0_T_1 = 1'h0; // @[micro-op.scala:109:42]
wire _r_pred_0_T_2 = 1'h0; // @[micro-op.scala:110:43]
wire _r_pred_0_T_3 = 1'h0; // @[functional-unit.scala:454:46]
wire _io_bypass_0_bits_data_T_1 = 1'h0; // @[micro-op.scala:109:42]
wire io_req_ready = 1'h1; // @[functional-unit.scala:290:7]
wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:290:7]
wire [63:0] io_resp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_0_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_1_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_2_bits_fflags_bits_uop_exc_cause = 64'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_fflags_bits_uop_rob_idx = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_fflags_bits_uop_pdst = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs1 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs2 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_fflags_bits_uop_prs3 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_rob_idx = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_pdst = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs1 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs2 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_prs3 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_0_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_rob_idx = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_pdst = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs1 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs2 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_prs3 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_uopc = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_rob_idx = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_pdst = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs1 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs2 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_prs3 = 7'h0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_fflags_bits_uop_stale_pdst = 7'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_resp_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_resp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_0_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_0_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_1_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_1_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_2_bits_fflags_bits_uop_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_2_bits_fflags_bits_uop_debug_inst = 32'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_resp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_resp_bits_addr = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_bypass_0_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_bypass_1_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_bypass_2_bits_fflags_bits_uop_debug_pc = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] io_brinfo_jalr_target = 40'h0; // @[functional-unit.scala:290:7]
wire [39:0] brinfo_jalr_target = 40'h0; // @[functional-unit.scala:385:20]
wire [2:0] io_resp_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_0_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_iq_type = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[functional-unit.scala:290:7]
wire [9:0] io_resp_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7]
wire [9:0] io_bypass_0_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7]
wire [9:0] io_bypass_1_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7]
wire [9:0] io_bypass_2_bits_fflags_bits_uop_fu_code = 10'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_resp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_resp_bits_fflags_bits_uop_br_tag = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_0_bits_fflags_bits_uop_br_tag = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_1_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_1_bits_fflags_bits_uop_br_tag = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_2_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_2_bits_fflags_bits_uop_br_tag = 4'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_0_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_iw_state = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_mem_size = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[functional-unit.scala:290:7]
wire [1:0] _pc_sel_T_10 = 2'h0; // @[functional-unit.scala:349:53]
wire [4:0] io_resp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_fflags_bits_uop_stq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_fflags_bits_uop_ppred = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_stq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_ppred = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_0_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_stq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_ppred = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_ftq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_ldq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_stq_idx = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_ppred = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_fflags_bits_flags = 5'h0; // @[functional-unit.scala:290:7]
wire [15:0] io_resp_bits_fflags_bits_uop_br_mask = 16'h0; // @[functional-unit.scala:290:7]
wire [15:0] io_bypass_0_bits_fflags_bits_uop_br_mask = 16'h0; // @[functional-unit.scala:290:7]
wire [15:0] io_bypass_1_bits_fflags_bits_uop_br_mask = 16'h0; // @[functional-unit.scala:290:7]
wire [15:0] io_bypass_2_bits_fflags_bits_uop_br_mask = 16'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_0_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_pc_lob = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_ldst = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs1 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs2 = 6'h0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_fflags_bits_uop_lrs3 = 6'h0; // @[functional-unit.scala:290:7]
wire [19:0] io_resp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7]
wire [19:0] io_bypass_0_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7]
wire [19:0] io_bypass_1_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7]
wire [19:0] io_bypass_2_bits_fflags_bits_uop_imm_packed = 20'h0; // @[functional-unit.scala:290:7]
wire [11:0] io_resp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7]
wire [11:0] io_bypass_0_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7]
wire [11:0] io_bypass_1_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7]
wire [11:0] io_bypass_2_bits_fflags_bits_uop_csr_addr = 12'h0; // @[functional-unit.scala:290:7]
wire [24:0] io_resp_bits_mxcpt_bits = 25'h0; // @[functional-unit.scala:290:7]
wire [38:0] io_resp_bits_sfence_bits_addr = 39'h0; // @[functional-unit.scala:290:7]
wire io_bypass_0_valid_0 = io_req_valid_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_0_bits_uop_uopc_0 = io_req_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
wire [6:0] brinfo_uop_uopc = io_req_bits_uop_uopc_0; // @[functional-unit.scala:290:7, :385:20]
wire [31:0] io_bypass_0_bits_uop_inst_0 = io_req_bits_uop_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] brinfo_uop_inst = io_req_bits_uop_inst_0; // @[functional-unit.scala:290:7, :385:20]
wire [31:0] io_bypass_0_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] brinfo_uop_debug_inst = io_req_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_rvc = io_req_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7, :385:20]
wire [39:0] io_bypass_0_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
wire [39:0] brinfo_uop_debug_pc = io_req_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_iq_type_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_iq_type = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:290:7, :385:20]
wire [9:0] io_bypass_0_bits_uop_fu_code_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
wire [9:0] brinfo_uop_fu_code = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:290:7, :385:20]
wire [3:0] io_bypass_0_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
wire [3:0] brinfo_uop_ctrl_br_type = io_req_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_ctrl_op1_sel = io_req_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_ctrl_op2_sel = io_req_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_ctrl_imm_sel = io_req_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7, :385:20]
wire [4:0] io_bypass_0_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
wire [4:0] brinfo_uop_ctrl_op_fcn = io_req_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ctrl_fcn_dw = io_req_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7, :385:20]
wire [2:0] io_bypass_0_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
wire [2:0] brinfo_uop_ctrl_csr_cmd = io_req_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ctrl_is_load = io_req_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ctrl_is_sta = io_req_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ctrl_is_std = io_req_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_iw_state_0 = io_req_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_iw_state = io_req_bits_uop_iw_state_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_iw_p1_poisoned = io_req_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_iw_p2_poisoned = io_req_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_br_0 = io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_br = io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_jalr = io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_jal_0 = io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_jal = io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_sfb = io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7, :385:20]
wire [15:0] io_bypass_0_bits_uop_br_mask_0 = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
wire [15:0] brinfo_uop_br_mask = io_req_bits_uop_br_mask_0; // @[functional-unit.scala:290:7, :385:20]
wire [3:0] io_bypass_0_bits_uop_br_tag_0 = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
wire [3:0] brinfo_uop_br_tag = io_req_bits_uop_br_tag_0; // @[functional-unit.scala:290:7, :385:20]
wire [4:0] io_bypass_0_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] brinfo_uop_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_edge_inst = io_req_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_pc_lob = io_req_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_taken_0 = io_req_bits_uop_taken_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_taken = io_req_bits_uop_taken_0; // @[functional-unit.scala:290:7, :385:20]
wire [19:0] io_bypass_0_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
wire [19:0] brinfo_uop_imm_packed = io_req_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7, :385:20]
wire [11:0] io_bypass_0_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
wire [11:0] brinfo_uop_csr_addr = io_req_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7, :385:20]
wire [6:0] io_bypass_0_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
wire [6:0] brinfo_uop_rob_idx = io_req_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7, :385:20]
wire [4:0] io_bypass_0_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] brinfo_uop_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7, :385:20]
wire [4:0] io_bypass_0_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] brinfo_uop_stq_idx = io_req_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7, :385:20]
wire [6:0] io_bypass_0_bits_uop_pdst_0 = io_req_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
wire [6:0] brinfo_uop_pdst = io_req_bits_uop_pdst_0; // @[functional-unit.scala:290:7, :385:20]
wire [6:0] io_bypass_0_bits_uop_prs1_0 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
wire [6:0] brinfo_uop_prs1 = io_req_bits_uop_prs1_0; // @[functional-unit.scala:290:7, :385:20]
wire [6:0] io_bypass_0_bits_uop_prs2_0 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
wire [6:0] brinfo_uop_prs2 = io_req_bits_uop_prs2_0; // @[functional-unit.scala:290:7, :385:20]
wire [6:0] io_bypass_0_bits_uop_prs3_0 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
wire [6:0] brinfo_uop_prs3 = io_req_bits_uop_prs3_0; // @[functional-unit.scala:290:7, :385:20]
wire [4:0] io_bypass_0_bits_uop_ppred_0 = io_req_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
wire [4:0] brinfo_uop_ppred = io_req_bits_uop_ppred_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7, :385:20]
wire [6:0] io_bypass_0_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
wire [6:0] brinfo_uop_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_exception_0 = io_req_bits_uop_exception_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_exception = io_req_bits_uop_exception_0; // @[functional-unit.scala:290:7, :385:20]
wire [63:0] io_bypass_0_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
wire [63:0] brinfo_uop_exc_cause = io_req_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_bypassable_0 = io_req_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_bypassable = io_req_bits_uop_bypassable_0; // @[functional-unit.scala:290:7, :385:20]
wire [4:0] io_bypass_0_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
wire [4:0] brinfo_uop_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_mem_size_0 = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_mem_size = io_req_bits_uop_mem_size_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_mem_signed = io_req_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_fence_0 = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_fence = io_req_bits_uop_is_fence_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_fencei = io_req_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_amo_0 = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_amo = io_req_bits_uop_is_amo_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_uses_stq = io_req_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_is_unique_0 = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_is_unique = io_req_bits_uop_is_unique_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_ldst_0 = io_req_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_ldst = io_req_bits_uop_ldst_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_lrs1_0 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_lrs1 = io_req_bits_uop_lrs1_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_lrs2_0 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_lrs2 = io_req_bits_uop_lrs2_0; // @[functional-unit.scala:290:7, :385:20]
wire [5:0] io_bypass_0_bits_uop_lrs3_0 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
wire [5:0] brinfo_uop_lrs3 = io_req_bits_uop_lrs3_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_ldst_val = io_req_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_frs3_en = io_req_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_fp_val_0 = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_fp_val = io_req_bits_uop_fp_val_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_fp_single_0 = io_req_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_fp_single = io_req_bits_uop_fp_single_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7, :385:20]
wire io_bypass_0_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
wire brinfo_uop_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7, :385:20]
wire [1:0] io_bypass_0_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] brinfo_uop_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7, :385:20]
wire _io_resp_valid_T_3; // @[functional-unit.scala:257:47]
wire [15:0] _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire [63:0] _io_bypass_0_bits_data_T_3; // @[functional-unit.scala:467:32]
wire brinfo_valid; // @[functional-unit.scala:385:20]
wire brinfo_mispredict; // @[functional-unit.scala:385:20]
wire brinfo_taken; // @[functional-unit.scala:385:20]
wire [2:0] brinfo_cfi_type; // @[functional-unit.scala:385:20]
wire [1:0] brinfo_pc_sel; // @[functional-unit.scala:385:20]
wire [20:0] brinfo_target_offset; // @[functional-unit.scala:385:20]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire [15:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:290:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:290:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:290:7]
wire io_resp_valid_0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_0_bits_data_0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_1_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_1_bits_uop_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_1_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
wire [39:0] io_bypass_1_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_1_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
wire [9:0] io_bypass_1_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire [15:0] io_bypass_1_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_1_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_taken_0; // @[functional-unit.scala:290:7]
wire [19:0] io_bypass_1_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
wire [11:0] io_bypass_1_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_1_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_exception_0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_1_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_1_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_1_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_1_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_1_bits_data_0; // @[functional-unit.scala:290:7]
wire io_bypass_1_valid_0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_2_bits_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_uop_uopc_0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_2_bits_uop_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] io_bypass_2_bits_uop_debug_inst_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_rvc_0; // @[functional-unit.scala:290:7]
wire [39:0] io_bypass_2_bits_uop_debug_pc_0; // @[functional-unit.scala:290:7]
wire [2:0] io_bypass_2_bits_uop_iq_type_0; // @[functional-unit.scala:290:7]
wire [9:0] io_bypass_2_bits_uop_fu_code_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_iw_state_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_br_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_jal_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire [15:0] io_bypass_2_bits_uop_br_mask_0; // @[functional-unit.scala:290:7]
wire [3:0] io_bypass_2_bits_uop_br_tag_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_edge_inst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_pc_lob_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_taken_0; // @[functional-unit.scala:290:7]
wire [19:0] io_bypass_2_bits_uop_imm_packed_0; // @[functional-unit.scala:290:7]
wire [11:0] io_bypass_2_bits_uop_csr_addr_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_uop_rob_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_uop_stq_idx_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_uop_pdst_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_uop_prs1_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_uop_prs2_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_uop_prs3_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_uop_ppred_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
wire [6:0] io_bypass_2_bits_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_exception_0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_2_bits_uop_exc_cause_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_bypassable_0; // @[functional-unit.scala:290:7]
wire [4:0] io_bypass_2_bits_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_mem_size_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_mem_signed_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_fence_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_fencei_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_amo_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_uses_stq_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_is_unique_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_ldst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_lrs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_lrs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_bypass_2_bits_uop_lrs3_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_ldst_val_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_frs3_en_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_fp_val_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_fp_single_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] io_bypass_2_bits_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
wire [63:0] io_bypass_2_bits_data_0; // @[functional-unit.scala:290:7]
wire io_bypass_2_valid_0; // @[functional-unit.scala:290:7]
wire [3:0] io_brinfo_uop_ctrl_br_type_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_ctrl_op1_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_ctrl_op2_sel_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_ctrl_imm_sel_0; // @[functional-unit.scala:290:7]
wire [4:0] io_brinfo_uop_ctrl_op_fcn_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ctrl_fcn_dw_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_ctrl_csr_cmd_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ctrl_is_load_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ctrl_is_sta_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ctrl_is_std_0; // @[functional-unit.scala:290:7]
wire [6:0] io_brinfo_uop_uopc_0; // @[functional-unit.scala:290:7]
wire [31:0] io_brinfo_uop_inst_0; // @[functional-unit.scala:290:7]
wire [31:0] io_brinfo_uop_debug_inst_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_rvc_0; // @[functional-unit.scala:290:7]
wire [39:0] io_brinfo_uop_debug_pc_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_uop_iq_type_0; // @[functional-unit.scala:290:7]
wire [9:0] io_brinfo_uop_fu_code_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_iw_state_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_iw_p1_poisoned_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_iw_p2_poisoned_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_br_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_jalr_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_jal_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_sfb_0; // @[functional-unit.scala:290:7]
wire [15:0] io_brinfo_uop_br_mask_0; // @[functional-unit.scala:290:7]
wire [3:0] io_brinfo_uop_br_tag_0; // @[functional-unit.scala:290:7]
wire [4:0] io_brinfo_uop_ftq_idx_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_edge_inst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_pc_lob_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_taken_0; // @[functional-unit.scala:290:7]
wire [19:0] io_brinfo_uop_imm_packed_0; // @[functional-unit.scala:290:7]
wire [11:0] io_brinfo_uop_csr_addr_0; // @[functional-unit.scala:290:7]
wire [6:0] io_brinfo_uop_rob_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] io_brinfo_uop_ldq_idx_0; // @[functional-unit.scala:290:7]
wire [4:0] io_brinfo_uop_stq_idx_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_rxq_idx_0; // @[functional-unit.scala:290:7]
wire [6:0] io_brinfo_uop_pdst_0; // @[functional-unit.scala:290:7]
wire [6:0] io_brinfo_uop_prs1_0; // @[functional-unit.scala:290:7]
wire [6:0] io_brinfo_uop_prs2_0; // @[functional-unit.scala:290:7]
wire [6:0] io_brinfo_uop_prs3_0; // @[functional-unit.scala:290:7]
wire [4:0] io_brinfo_uop_ppred_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_prs1_busy_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_prs2_busy_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_prs3_busy_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ppred_busy_0; // @[functional-unit.scala:290:7]
wire [6:0] io_brinfo_uop_stale_pdst_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_exception_0; // @[functional-unit.scala:290:7]
wire [63:0] io_brinfo_uop_exc_cause_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_bypassable_0; // @[functional-unit.scala:290:7]
wire [4:0] io_brinfo_uop_mem_cmd_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_mem_size_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_mem_signed_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_fence_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_fencei_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_amo_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_uses_ldq_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_uses_stq_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_sys_pc2epc_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_is_unique_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_flush_on_commit_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ldst_is_rs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_ldst_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_lrs1_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_lrs2_0; // @[functional-unit.scala:290:7]
wire [5:0] io_brinfo_uop_lrs3_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_ldst_val_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_dst_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_lrs1_rtype_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_lrs2_rtype_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_frs3_en_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_fp_val_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_fp_single_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_xcpt_pf_if_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_xcpt_ae_if_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_xcpt_ma_if_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_bp_debug_if_0; // @[functional-unit.scala:290:7]
wire io_brinfo_uop_bp_xcpt_if_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_debug_fsrc_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_uop_debug_tsrc_0; // @[functional-unit.scala:290:7]
wire io_brinfo_valid_0; // @[functional-unit.scala:290:7]
wire io_brinfo_mispredict_0; // @[functional-unit.scala:290:7]
wire io_brinfo_taken_0; // @[functional-unit.scala:290:7]
wire [2:0] io_brinfo_cfi_type_0; // @[functional-unit.scala:290:7]
wire [1:0] io_brinfo_pc_sel_0; // @[functional-unit.scala:290:7]
wire [20:0] io_brinfo_target_offset_0; // @[functional-unit.scala:290:7]
reg r_valids_0; // @[functional-unit.scala:236:27]
reg r_valids_1; // @[functional-unit.scala:236:27]
reg r_valids_2; // @[functional-unit.scala:236:27]
reg [6:0] r_uops_0_uopc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_uopc_0 = r_uops_0_uopc; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_0_inst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_inst_0 = r_uops_0_inst; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_0_debug_inst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_debug_inst_0 = r_uops_0_debug_inst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_rvc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_rvc_0 = r_uops_0_is_rvc; // @[functional-unit.scala:237:23, :290:7]
reg [39:0] r_uops_0_debug_pc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_debug_pc_0 = r_uops_0_debug_pc; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_iq_type; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_iq_type_0 = r_uops_0_iq_type; // @[functional-unit.scala:237:23, :290:7]
reg [9:0] r_uops_0_fu_code; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_fu_code_0 = r_uops_0_fu_code; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_br_type_0 = r_uops_0_ctrl_br_type; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_op1_sel_0 = r_uops_0_ctrl_op1_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_op2_sel_0 = r_uops_0_ctrl_op2_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_imm_sel_0 = r_uops_0_ctrl_imm_sel; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_op_fcn_0 = r_uops_0_ctrl_op_fcn; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_fcn_dw_0 = r_uops_0_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_csr_cmd_0 = r_uops_0_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_is_load_0 = r_uops_0_ctrl_is_load; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_is_sta_0 = r_uops_0_ctrl_is_sta; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ctrl_is_std_0 = r_uops_0_ctrl_is_std; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_iw_state; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_iw_state_0 = r_uops_0_iw_state; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_iw_p1_poisoned_0 = r_uops_0_iw_p1_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_iw_p2_poisoned_0 = r_uops_0_iw_p2_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_br; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_br_0 = r_uops_0_is_br; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_jalr; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_jalr_0 = r_uops_0_is_jalr; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_jal; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_jal_0 = r_uops_0_is_jal; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_sfb; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_sfb_0 = r_uops_0_is_sfb; // @[functional-unit.scala:237:23, :290:7]
reg [15:0] r_uops_0_br_mask; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_br_mask_0 = r_uops_0_br_mask; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_0_br_tag; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_br_tag_0 = r_uops_0_br_tag; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_0_ftq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ftq_idx_0 = r_uops_0_ftq_idx; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_edge_inst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_edge_inst_0 = r_uops_0_edge_inst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_pc_lob; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_pc_lob_0 = r_uops_0_pc_lob; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_taken; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_taken_0 = r_uops_0_taken; // @[functional-unit.scala:237:23, :290:7]
reg [19:0] r_uops_0_imm_packed; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_imm_packed_0 = r_uops_0_imm_packed; // @[functional-unit.scala:237:23, :290:7]
reg [11:0] r_uops_0_csr_addr; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_csr_addr_0 = r_uops_0_csr_addr; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_0_rob_idx; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_rob_idx_0 = r_uops_0_rob_idx; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_0_ldq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ldq_idx_0 = r_uops_0_ldq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_0_stq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_stq_idx_0 = r_uops_0_stq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_rxq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_rxq_idx_0 = r_uops_0_rxq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_0_pdst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_pdst_0 = r_uops_0_pdst; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_0_prs1; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs1_0 = r_uops_0_prs1; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_0_prs2; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs2_0 = r_uops_0_prs2; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_0_prs3; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs3_0 = r_uops_0_prs3; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_0_ppred; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ppred_0 = r_uops_0_ppred; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_prs1_busy; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs1_busy_0 = r_uops_0_prs1_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_prs2_busy; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs2_busy_0 = r_uops_0_prs2_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_prs3_busy; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_prs3_busy_0 = r_uops_0_prs3_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ppred_busy; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ppred_busy_0 = r_uops_0_ppred_busy; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_0_stale_pdst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_stale_pdst_0 = r_uops_0_stale_pdst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_exception; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_exception_0 = r_uops_0_exception; // @[functional-unit.scala:237:23, :290:7]
reg [63:0] r_uops_0_exc_cause; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_exc_cause_0 = r_uops_0_exc_cause; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_bypassable; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_bypassable_0 = r_uops_0_bypassable; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_0_mem_cmd; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_mem_cmd_0 = r_uops_0_mem_cmd; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_mem_size; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_mem_size_0 = r_uops_0_mem_size; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_mem_signed; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_mem_signed_0 = r_uops_0_mem_signed; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_fence; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_fence_0 = r_uops_0_is_fence; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_fencei; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_fencei_0 = r_uops_0_is_fencei; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_amo; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_amo_0 = r_uops_0_is_amo; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_uses_ldq; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_uses_ldq_0 = r_uops_0_uses_ldq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_uses_stq; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_uses_stq_0 = r_uops_0_uses_stq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_sys_pc2epc_0 = r_uops_0_is_sys_pc2epc; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_is_unique; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_is_unique_0 = r_uops_0_is_unique; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_flush_on_commit_0 = r_uops_0_flush_on_commit; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ldst_is_rs1_0 = r_uops_0_ldst_is_rs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_ldst; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ldst_0 = r_uops_0_ldst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_lrs1; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_lrs1_0 = r_uops_0_lrs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_lrs2; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_lrs2_0 = r_uops_0_lrs2; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_0_lrs3; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_lrs3_0 = r_uops_0_lrs3; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_ldst_val; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_ldst_val_0 = r_uops_0_ldst_val; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_dst_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_dst_rtype_0 = r_uops_0_dst_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_lrs1_rtype_0 = r_uops_0_lrs1_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_lrs2_rtype_0 = r_uops_0_lrs2_rtype; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_frs3_en; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_frs3_en_0 = r_uops_0_frs3_en; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_fp_val; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_fp_val_0 = r_uops_0_fp_val; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_fp_single; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_fp_single_0 = r_uops_0_fp_single; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_xcpt_pf_if_0 = r_uops_0_xcpt_pf_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_xcpt_ae_if_0 = r_uops_0_xcpt_ae_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_xcpt_ma_if_0 = r_uops_0_xcpt_ma_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_bp_debug_if_0 = r_uops_0_bp_debug_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_bp_xcpt_if_0 = r_uops_0_bp_xcpt_if; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_debug_fsrc_0 = r_uops_0_debug_fsrc; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23]
assign io_bypass_1_bits_uop_debug_tsrc_0 = r_uops_0_debug_tsrc; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_1_uopc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_uopc_0 = r_uops_1_uopc; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_1_inst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_inst_0 = r_uops_1_inst; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_1_debug_inst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_debug_inst_0 = r_uops_1_debug_inst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_rvc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_rvc_0 = r_uops_1_is_rvc; // @[functional-unit.scala:237:23, :290:7]
reg [39:0] r_uops_1_debug_pc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_debug_pc_0 = r_uops_1_debug_pc; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_iq_type; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_iq_type_0 = r_uops_1_iq_type; // @[functional-unit.scala:237:23, :290:7]
reg [9:0] r_uops_1_fu_code; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_fu_code_0 = r_uops_1_fu_code; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_br_type_0 = r_uops_1_ctrl_br_type; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_op1_sel_0 = r_uops_1_ctrl_op1_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_op2_sel_0 = r_uops_1_ctrl_op2_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_imm_sel_0 = r_uops_1_ctrl_imm_sel; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_op_fcn_0 = r_uops_1_ctrl_op_fcn; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_fcn_dw_0 = r_uops_1_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_csr_cmd_0 = r_uops_1_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_is_load_0 = r_uops_1_ctrl_is_load; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_is_sta_0 = r_uops_1_ctrl_is_sta; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ctrl_is_std_0 = r_uops_1_ctrl_is_std; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_iw_state; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_iw_state_0 = r_uops_1_iw_state; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_iw_p1_poisoned_0 = r_uops_1_iw_p1_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_iw_p2_poisoned_0 = r_uops_1_iw_p2_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_br; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_br_0 = r_uops_1_is_br; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_jalr; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_jalr_0 = r_uops_1_is_jalr; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_jal; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_jal_0 = r_uops_1_is_jal; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_sfb; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_sfb_0 = r_uops_1_is_sfb; // @[functional-unit.scala:237:23, :290:7]
reg [15:0] r_uops_1_br_mask; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_br_mask_0 = r_uops_1_br_mask; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_1_br_tag; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_br_tag_0 = r_uops_1_br_tag; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_1_ftq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ftq_idx_0 = r_uops_1_ftq_idx; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_edge_inst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_edge_inst_0 = r_uops_1_edge_inst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_pc_lob; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_pc_lob_0 = r_uops_1_pc_lob; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_taken; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_taken_0 = r_uops_1_taken; // @[functional-unit.scala:237:23, :290:7]
reg [19:0] r_uops_1_imm_packed; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_imm_packed_0 = r_uops_1_imm_packed; // @[functional-unit.scala:237:23, :290:7]
reg [11:0] r_uops_1_csr_addr; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_csr_addr_0 = r_uops_1_csr_addr; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_1_rob_idx; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_rob_idx_0 = r_uops_1_rob_idx; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_1_ldq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ldq_idx_0 = r_uops_1_ldq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_1_stq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_stq_idx_0 = r_uops_1_stq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_rxq_idx; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_rxq_idx_0 = r_uops_1_rxq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_1_pdst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_pdst_0 = r_uops_1_pdst; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_1_prs1; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs1_0 = r_uops_1_prs1; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_1_prs2; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs2_0 = r_uops_1_prs2; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_1_prs3; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs3_0 = r_uops_1_prs3; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_1_ppred; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ppred_0 = r_uops_1_ppred; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_prs1_busy; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs1_busy_0 = r_uops_1_prs1_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_prs2_busy; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs2_busy_0 = r_uops_1_prs2_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_prs3_busy; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_prs3_busy_0 = r_uops_1_prs3_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ppred_busy; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ppred_busy_0 = r_uops_1_ppred_busy; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_1_stale_pdst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_stale_pdst_0 = r_uops_1_stale_pdst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_exception; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_exception_0 = r_uops_1_exception; // @[functional-unit.scala:237:23, :290:7]
reg [63:0] r_uops_1_exc_cause; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_exc_cause_0 = r_uops_1_exc_cause; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_bypassable; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_bypassable_0 = r_uops_1_bypassable; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_1_mem_cmd; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_mem_cmd_0 = r_uops_1_mem_cmd; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_mem_size; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_mem_size_0 = r_uops_1_mem_size; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_mem_signed; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_mem_signed_0 = r_uops_1_mem_signed; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_fence; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_fence_0 = r_uops_1_is_fence; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_fencei; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_fencei_0 = r_uops_1_is_fencei; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_amo; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_amo_0 = r_uops_1_is_amo; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_uses_ldq; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_uses_ldq_0 = r_uops_1_uses_ldq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_uses_stq; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_uses_stq_0 = r_uops_1_uses_stq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_sys_pc2epc_0 = r_uops_1_is_sys_pc2epc; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_is_unique; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_is_unique_0 = r_uops_1_is_unique; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_flush_on_commit_0 = r_uops_1_flush_on_commit; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ldst_is_rs1_0 = r_uops_1_ldst_is_rs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_ldst; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ldst_0 = r_uops_1_ldst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_lrs1; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_lrs1_0 = r_uops_1_lrs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_lrs2; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_lrs2_0 = r_uops_1_lrs2; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_1_lrs3; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_lrs3_0 = r_uops_1_lrs3; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_ldst_val; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_ldst_val_0 = r_uops_1_ldst_val; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_dst_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_dst_rtype_0 = r_uops_1_dst_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_lrs1_rtype_0 = r_uops_1_lrs1_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_lrs2_rtype_0 = r_uops_1_lrs2_rtype; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_frs3_en; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_frs3_en_0 = r_uops_1_frs3_en; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_fp_val; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_fp_val_0 = r_uops_1_fp_val; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_fp_single; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_fp_single_0 = r_uops_1_fp_single; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_xcpt_pf_if_0 = r_uops_1_xcpt_pf_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_xcpt_ae_if_0 = r_uops_1_xcpt_ae_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_xcpt_ma_if_0 = r_uops_1_xcpt_ma_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_bp_debug_if_0 = r_uops_1_bp_debug_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_bp_xcpt_if_0 = r_uops_1_bp_xcpt_if; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_debug_fsrc_0 = r_uops_1_debug_fsrc; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23]
assign io_bypass_2_bits_uop_debug_tsrc_0 = r_uops_1_debug_tsrc; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_2_uopc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_uopc_0 = r_uops_2_uopc; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_2_inst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_inst_0 = r_uops_2_inst; // @[functional-unit.scala:237:23, :290:7]
reg [31:0] r_uops_2_debug_inst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_inst_0 = r_uops_2_debug_inst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_rvc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_rvc_0 = r_uops_2_is_rvc; // @[functional-unit.scala:237:23, :290:7]
reg [39:0] r_uops_2_debug_pc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_pc_0 = r_uops_2_debug_pc; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_2_iq_type; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iq_type_0 = r_uops_2_iq_type; // @[functional-unit.scala:237:23, :290:7]
reg [9:0] r_uops_2_fu_code; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_fu_code_0 = r_uops_2_fu_code; // @[functional-unit.scala:237:23, :290:7]
reg [3:0] r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_br_type_0 = r_uops_2_ctrl_br_type; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_op1_sel_0 = r_uops_2_ctrl_op1_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_op2_sel_0 = r_uops_2_ctrl_op2_sel; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_imm_sel_0 = r_uops_2_ctrl_imm_sel; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_op_fcn_0 = r_uops_2_ctrl_op_fcn; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_fcn_dw_0 = r_uops_2_ctrl_fcn_dw; // @[functional-unit.scala:237:23, :290:7]
reg [2:0] r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_csr_cmd_0 = r_uops_2_ctrl_csr_cmd; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_is_load_0 = r_uops_2_ctrl_is_load; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_is_sta_0 = r_uops_2_ctrl_is_sta; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ctrl_is_std_0 = r_uops_2_ctrl_is_std; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_iw_state; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iw_state_0 = r_uops_2_iw_state; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iw_p1_poisoned_0 = r_uops_2_iw_p1_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_iw_p2_poisoned_0 = r_uops_2_iw_p2_poisoned; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_br; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_br_0 = r_uops_2_is_br; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_jalr; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_jalr_0 = r_uops_2_is_jalr; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_jal; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_jal_0 = r_uops_2_is_jal; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_sfb; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_sfb_0 = r_uops_2_is_sfb; // @[functional-unit.scala:237:23, :290:7]
reg [15:0] r_uops_2_br_mask; // @[functional-unit.scala:237:23]
reg [3:0] r_uops_2_br_tag; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_br_tag_0 = r_uops_2_br_tag; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_2_ftq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ftq_idx_0 = r_uops_2_ftq_idx; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_edge_inst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_edge_inst_0 = r_uops_2_edge_inst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_pc_lob; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_pc_lob_0 = r_uops_2_pc_lob; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_taken; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_taken_0 = r_uops_2_taken; // @[functional-unit.scala:237:23, :290:7]
reg [19:0] r_uops_2_imm_packed; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_imm_packed_0 = r_uops_2_imm_packed; // @[functional-unit.scala:237:23, :290:7]
reg [11:0] r_uops_2_csr_addr; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_csr_addr_0 = r_uops_2_csr_addr; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_2_rob_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_rob_idx_0 = r_uops_2_rob_idx; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_2_ldq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldq_idx_0 = r_uops_2_ldq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_2_stq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_stq_idx_0 = r_uops_2_stq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_rxq_idx; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_rxq_idx_0 = r_uops_2_rxq_idx; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_2_pdst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_pdst_0 = r_uops_2_pdst; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_2_prs1; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs1_0 = r_uops_2_prs1; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_2_prs2; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs2_0 = r_uops_2_prs2; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_2_prs3; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs3_0 = r_uops_2_prs3; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_2_ppred; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ppred_0 = r_uops_2_ppred; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_prs1_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs1_busy_0 = r_uops_2_prs1_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_prs2_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs2_busy_0 = r_uops_2_prs2_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_prs3_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_prs3_busy_0 = r_uops_2_prs3_busy; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ppred_busy; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ppred_busy_0 = r_uops_2_ppred_busy; // @[functional-unit.scala:237:23, :290:7]
reg [6:0] r_uops_2_stale_pdst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_stale_pdst_0 = r_uops_2_stale_pdst; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_exception; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_exception_0 = r_uops_2_exception; // @[functional-unit.scala:237:23, :290:7]
reg [63:0] r_uops_2_exc_cause; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_exc_cause_0 = r_uops_2_exc_cause; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_bypassable; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_bypassable_0 = r_uops_2_bypassable; // @[functional-unit.scala:237:23, :290:7]
reg [4:0] r_uops_2_mem_cmd; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_mem_cmd_0 = r_uops_2_mem_cmd; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_mem_size; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_mem_size_0 = r_uops_2_mem_size; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_mem_signed; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_mem_signed_0 = r_uops_2_mem_signed; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_fence; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_fence_0 = r_uops_2_is_fence; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_fencei; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_fencei_0 = r_uops_2_is_fencei; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_amo; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_amo_0 = r_uops_2_is_amo; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_uses_ldq; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_uses_ldq_0 = r_uops_2_uses_ldq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_uses_stq; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_uses_stq_0 = r_uops_2_uses_stq; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_sys_pc2epc_0 = r_uops_2_is_sys_pc2epc; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_is_unique; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_is_unique_0 = r_uops_2_is_unique; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_flush_on_commit_0 = r_uops_2_flush_on_commit; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldst_is_rs1_0 = r_uops_2_ldst_is_rs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_ldst; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldst_0 = r_uops_2_ldst; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_lrs1; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs1_0 = r_uops_2_lrs1; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_lrs2; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs2_0 = r_uops_2_lrs2; // @[functional-unit.scala:237:23, :290:7]
reg [5:0] r_uops_2_lrs3; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs3_0 = r_uops_2_lrs3; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_ldst_val; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_ldst_val_0 = r_uops_2_ldst_val; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_dst_rtype; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_dst_rtype_0 = r_uops_2_dst_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs1_rtype_0 = r_uops_2_lrs1_rtype; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_lrs2_rtype_0 = r_uops_2_lrs2_rtype; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_frs3_en; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_frs3_en_0 = r_uops_2_frs3_en; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_fp_val; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_fp_val_0 = r_uops_2_fp_val; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_fp_single; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_fp_single_0 = r_uops_2_fp_single; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_xcpt_pf_if_0 = r_uops_2_xcpt_pf_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_xcpt_ae_if_0 = r_uops_2_xcpt_ae_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_xcpt_ma_if_0 = r_uops_2_xcpt_ma_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_bp_debug_if_0 = r_uops_2_bp_debug_if; // @[functional-unit.scala:237:23, :290:7]
reg r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_bp_xcpt_if_0 = r_uops_2_bp_xcpt_if; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_fsrc_0 = r_uops_2_debug_fsrc; // @[functional-unit.scala:237:23, :290:7]
reg [1:0] r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23]
assign io_resp_bits_uop_debug_tsrc_0 = r_uops_2_debug_tsrc; // @[functional-unit.scala:237:23, :290:7]
wire [15:0] _r_valids_0_T = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:118:51]
wire _r_valids_0_T_1 = |_r_valids_0_T; // @[util.scala:118:{51,59}]
wire _r_valids_0_T_2 = ~_r_valids_0_T_1; // @[util.scala:118:59]
wire _r_valids_0_T_3 = io_req_valid_0 & _r_valids_0_T_2; // @[functional-unit.scala:240:{33,36}, :290:7]
wire _r_valids_0_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :290:7]
wire _r_valids_0_T_5 = _r_valids_0_T_3 & _r_valids_0_T_4; // @[functional-unit.scala:240:{33,84,87}]
wire [15:0] _r_uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_uops_0_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _r_uops_0_br_mask_T; // @[util.scala:85:{25,27}]
wire [15:0] _r_valids_1_T = io_brupdate_b1_mispredict_mask_0 & r_uops_0_br_mask; // @[util.scala:118:51]
wire _r_valids_1_T_1 = |_r_valids_1_T; // @[util.scala:118:{51,59}]
wire _r_valids_1_T_2 = ~_r_valids_1_T_1; // @[util.scala:118:59]
wire _r_valids_1_T_3 = r_valids_0 & _r_valids_1_T_2; // @[functional-unit.scala:236:27, :246:{36,39}]
wire _r_valids_1_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :290:7]
wire _r_valids_1_T_5 = _r_valids_1_T_3 & _r_valids_1_T_4; // @[functional-unit.scala:246:{36,83,86}]
wire [15:0] _r_uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_uops_1_br_mask_T_1 = r_uops_0_br_mask & _r_uops_1_br_mask_T; // @[util.scala:85:{25,27}]
wire [15:0] _r_valids_2_T = io_brupdate_b1_mispredict_mask_0 & r_uops_1_br_mask; // @[util.scala:118:51]
wire _r_valids_2_T_1 = |_r_valids_2_T; // @[util.scala:118:{51,59}]
wire _r_valids_2_T_2 = ~_r_valids_2_T_1; // @[util.scala:118:59]
wire _r_valids_2_T_3 = r_valids_1 & _r_valids_2_T_2; // @[functional-unit.scala:236:27, :246:{36,39}]
wire _r_valids_2_T_4 = ~io_req_bits_kill_0; // @[functional-unit.scala:240:87, :246:86, :290:7]
wire _r_valids_2_T_5 = _r_valids_2_T_3 & _r_valids_2_T_4; // @[functional-unit.scala:246:{36,83,86}]
wire [15:0] _r_uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
wire [15:0] _r_uops_2_br_mask_T_1 = r_uops_1_br_mask & _r_uops_2_br_mask_T; // @[util.scala:85:{25,27}]
wire [15:0] _io_resp_valid_T = io_brupdate_b1_mispredict_mask_0 & r_uops_2_br_mask; // @[util.scala:118:51]
wire _io_resp_valid_T_1 = |_io_resp_valid_T; // @[util.scala:118:{51,59}]
wire _io_resp_valid_T_2 = ~_io_resp_valid_T_1; // @[util.scala:118:59]
assign _io_resp_valid_T_3 = r_valids_2 & _io_resp_valid_T_2; // @[functional-unit.scala:236:27, :257:{47,50}]
assign io_resp_valid_0 = _io_resp_valid_T_3; // @[functional-unit.scala:257:47, :290:7]
wire [15:0] _io_resp_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27]
assign _io_resp_bits_uop_br_mask_T_1 = r_uops_2_br_mask & _io_resp_bits_uop_br_mask_T; // @[util.scala:85:{25,27}]
assign io_resp_bits_uop_br_mask_0 = _io_resp_bits_uop_br_mask_T_1; // @[util.scala:85:25]
wire _imm_xprlen_sign_T = io_req_bits_uop_imm_packed_0[19]; // @[util.scala:273:18]
wire imm_xprlen_sign = _imm_xprlen_sign_T; // @[util.scala:273:{18,37}]
wire imm_xprlen_hi_hi_hi = imm_xprlen_sign; // @[util.scala:273:37, :282:15]
wire _GEN = io_req_bits_uop_ctrl_imm_sel_0 == 3'h3; // @[util.scala:274:27]
wire _imm_xprlen_i30_20_T; // @[util.scala:274:27]
assign _imm_xprlen_i30_20_T = _GEN; // @[util.scala:274:27]
wire _imm_xprlen_i19_12_T; // @[util.scala:275:27]
assign _imm_xprlen_i19_12_T = _GEN; // @[util.scala:274:27, :275:27]
wire _imm_xprlen_i11_T; // @[util.scala:276:27]
assign _imm_xprlen_i11_T = _GEN; // @[util.scala:274:27, :276:27]
wire _imm_xprlen_i10_5_T; // @[util.scala:278:27]
assign _imm_xprlen_i10_5_T = _GEN; // @[util.scala:274:27, :278:27]
wire _imm_xprlen_i4_1_T; // @[util.scala:279:27]
assign _imm_xprlen_i4_1_T = _GEN; // @[util.scala:274:27, :279:27]
wire [10:0] _imm_xprlen_i30_20_T_1 = io_req_bits_uop_imm_packed_0[18:8]; // @[util.scala:274:39]
wire [10:0] _imm_xprlen_i30_20_T_2 = _imm_xprlen_i30_20_T_1; // @[util.scala:274:{39,46}]
wire [10:0] imm_xprlen_i30_20 = _imm_xprlen_i30_20_T ? _imm_xprlen_i30_20_T_2 : {11{imm_xprlen_sign}}; // @[util.scala:273:37, :274:{21,27,46}]
wire [10:0] imm_xprlen_hi_hi_lo = imm_xprlen_i30_20; // @[util.scala:274:21, :282:15]
wire _GEN_0 = io_req_bits_uop_ctrl_imm_sel_0 == 3'h4; // @[util.scala:275:44]
wire _imm_xprlen_i19_12_T_1; // @[util.scala:275:44]
assign _imm_xprlen_i19_12_T_1 = _GEN_0; // @[util.scala:275:44]
wire _imm_xprlen_i11_T_1; // @[util.scala:277:27]
assign _imm_xprlen_i11_T_1 = _GEN_0; // @[util.scala:275:44, :277:27]
wire _imm_xprlen_i19_12_T_2 = _imm_xprlen_i19_12_T | _imm_xprlen_i19_12_T_1; // @[util.scala:275:{27,36,44}]
wire [7:0] _imm_xprlen_i19_12_T_3 = io_req_bits_uop_imm_packed_0[7:0]; // @[util.scala:275:56]
wire [7:0] _imm_xprlen_i19_12_T_4 = _imm_xprlen_i19_12_T_3; // @[util.scala:275:{56,62}]
wire [7:0] imm_xprlen_i19_12 = _imm_xprlen_i19_12_T_2 ? _imm_xprlen_i19_12_T_4 : {8{imm_xprlen_sign}}; // @[util.scala:273:37, :275:{21,36,62}]
wire [7:0] imm_xprlen_hi_lo_hi = imm_xprlen_i19_12; // @[util.scala:275:21, :282:15]
wire _imm_xprlen_i11_T_2 = io_req_bits_uop_ctrl_imm_sel_0 == 3'h2; // @[util.scala:277:44]
wire _imm_xprlen_i11_T_3 = _imm_xprlen_i11_T_1 | _imm_xprlen_i11_T_2; // @[util.scala:277:{27,36,44}]
wire _imm_xprlen_i11_T_4 = io_req_bits_uop_imm_packed_0[8]; // @[util.scala:277:56]
wire _imm_xprlen_i0_T_3 = io_req_bits_uop_imm_packed_0[8]; // @[util.scala:277:56, :280:56]
wire _imm_xprlen_i11_T_5 = _imm_xprlen_i11_T_4; // @[util.scala:277:{56,60}]
wire _imm_xprlen_i11_T_6 = _imm_xprlen_i11_T_3 ? _imm_xprlen_i11_T_5 : imm_xprlen_sign; // @[util.scala:273:37, :277:{21,36,60}]
wire imm_xprlen_i11 = ~_imm_xprlen_i11_T & _imm_xprlen_i11_T_6; // @[util.scala:276:{21,27}, :277:21]
wire imm_xprlen_hi_lo_lo = imm_xprlen_i11; // @[util.scala:276:21, :282:15]
wire [4:0] _imm_xprlen_i10_5_T_1 = io_req_bits_uop_imm_packed_0[18:14]; // @[util.scala:278:44]
wire [4:0] _imm_xprlen_i10_5_T_2 = _imm_xprlen_i10_5_T_1; // @[util.scala:278:{44,52}]
wire [4:0] imm_xprlen_i10_5 = _imm_xprlen_i10_5_T ? 5'h0 : _imm_xprlen_i10_5_T_2; // @[util.scala:278:{21,27,52}]
wire [4:0] imm_xprlen_lo_hi_hi = imm_xprlen_i10_5; // @[util.scala:278:21, :282:15]
wire [4:0] _imm_xprlen_i4_1_T_1 = io_req_bits_uop_imm_packed_0[13:9]; // @[util.scala:279:44]
wire [4:0] _imm_xprlen_i4_1_T_2 = _imm_xprlen_i4_1_T_1; // @[util.scala:279:{44,51}]
wire [4:0] imm_xprlen_i4_1 = _imm_xprlen_i4_1_T ? 5'h0 : _imm_xprlen_i4_1_T_2; // @[util.scala:279:{21,27,51}]
wire [4:0] imm_xprlen_lo_hi_lo = imm_xprlen_i4_1; // @[util.scala:279:21, :282:15]
wire _imm_xprlen_i0_T = io_req_bits_uop_ctrl_imm_sel_0 == 3'h1; // @[util.scala:280:27]
wire _imm_xprlen_i0_T_1 = io_req_bits_uop_ctrl_imm_sel_0 == 3'h0; // @[util.scala:280:44]
wire _imm_xprlen_i0_T_2 = _imm_xprlen_i0_T | _imm_xprlen_i0_T_1; // @[util.scala:280:{27,36,44}]
wire _imm_xprlen_i0_T_4 = _imm_xprlen_i0_T_3; // @[util.scala:280:{56,60}]
wire imm_xprlen_i0 = _imm_xprlen_i0_T_2 & _imm_xprlen_i0_T_4; // @[util.scala:280:{21,36,60}]
wire imm_xprlen_lo_lo = imm_xprlen_i0; // @[util.scala:280:21, :282:15]
wire [9:0] imm_xprlen_lo_hi = {imm_xprlen_lo_hi_hi, imm_xprlen_lo_hi_lo}; // @[util.scala:282:15]
wire [10:0] imm_xprlen_lo = {imm_xprlen_lo_hi, imm_xprlen_lo_lo}; // @[util.scala:282:15]
wire [8:0] imm_xprlen_hi_lo = {imm_xprlen_hi_lo_hi, imm_xprlen_hi_lo_lo}; // @[util.scala:282:15]
wire [11:0] imm_xprlen_hi_hi = {imm_xprlen_hi_hi_hi, imm_xprlen_hi_hi_lo}; // @[util.scala:282:15]
wire [20:0] imm_xprlen_hi = {imm_xprlen_hi_hi, imm_xprlen_hi_lo}; // @[util.scala:282:15]
wire [31:0] _imm_xprlen_T = {imm_xprlen_hi, imm_xprlen_lo}; // @[util.scala:282:15]
wire [31:0] imm_xprlen = _imm_xprlen_T; // @[util.scala:282:{15,60}]
wire [31:0] _op2_data_T_1 = imm_xprlen; // @[util.scala:282:60]
wire _op2_data_T = io_req_bits_uop_ctrl_op2_sel_0 == 3'h1; // @[functional-unit.scala:290:7, :321:39]
wire _op2_data_T_2 = _op2_data_T_1[31]; // @[util.scala:261:46]
wire [31:0] _op2_data_T_3 = {32{_op2_data_T_2}}; // @[util.scala:261:{25,46}]
wire [63:0] _op2_data_T_4 = {_op2_data_T_3, _op2_data_T_1}; // @[util.scala:261:{20,25}]
wire _op2_data_T_5 = io_req_bits_uop_ctrl_op2_sel_0 == 3'h4; // @[functional-unit.scala:290:7, :322:39]
wire [4:0] _op2_data_T_6 = io_req_bits_uop_prs1_0[4:0]; // @[functional-unit.scala:290:7, :322:73]
wire _op2_data_T_7 = io_req_bits_uop_ctrl_op2_sel_0 == 3'h0; // @[functional-unit.scala:290:7, :323:39]
wire _op2_data_T_8 = io_req_bits_uop_ctrl_op2_sel_0 == 3'h3; // @[functional-unit.scala:290:7, :324:39]
wire [2:0] _op2_data_T_9 = io_req_bits_uop_is_rvc_0 ? 3'h2 : 3'h4; // @[functional-unit.scala:290:7, :324:56]
wire [2:0] _op2_data_T_10 = _op2_data_T_8 ? _op2_data_T_9 : 3'h0; // @[functional-unit.scala:324:{21,39,56}]
wire [63:0] _op2_data_T_11 = _op2_data_T_7 ? io_req_bits_rs2_data_0 : {61'h0, _op2_data_T_10}; // @[functional-unit.scala:290:7, :323:{21,39}, :324:21]
wire [63:0] _op2_data_T_12 = _op2_data_T_5 ? {59'h0, _op2_data_T_6} : _op2_data_T_11; // @[functional-unit.scala:322:{21,39,73}, :323:21]
wire [63:0] op2_data = _op2_data_T ? _op2_data_T_4 : _op2_data_T_12; // @[util.scala:261:20]
wire killed; // @[functional-unit.scala:337:24]
assign killed = |{io_req_bits_kill_0, _r_valids_0_T}; // @[util.scala:118:{51,59}]
wire br_eq = io_req_bits_rs1_data_0 == io_req_bits_rs2_data_0; // @[functional-unit.scala:290:7, :344:21]
wire br_ltu = io_req_bits_rs1_data_0 < io_req_bits_rs2_data_0; // @[functional-unit.scala:290:7, :345:28]
wire _br_lt_T = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:290:7, :346:22]
wire _br_lt_T_5 = io_req_bits_rs1_data_0[63]; // @[functional-unit.scala:290:7, :346:22, :347:20]
wire _br_lt_T_1 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:290:7, :346:36]
wire _br_lt_T_6 = io_req_bits_rs2_data_0[63]; // @[functional-unit.scala:290:7, :346:36, :347:35]
wire _br_lt_T_2 = _br_lt_T ^ _br_lt_T_1; // @[functional-unit.scala:346:{22,31,36}]
wire _br_lt_T_3 = ~_br_lt_T_2; // @[functional-unit.scala:346:{17,31}]
wire _br_lt_T_4 = _br_lt_T_3 & br_ltu; // @[functional-unit.scala:345:28, :346:{17,46}]
wire _br_lt_T_7 = ~_br_lt_T_6; // @[functional-unit.scala:347:{31,35}]
wire _br_lt_T_8 = _br_lt_T_5 & _br_lt_T_7; // @[functional-unit.scala:347:{20,29,31}]
wire br_lt = _br_lt_T_4 | _br_lt_T_8; // @[functional-unit.scala:346:{46,55}, :347:29]
wire _pc_sel_T = ~br_eq; // @[functional-unit.scala:344:21, :351:39]
wire [1:0] _pc_sel_T_1 = {1'h0, _pc_sel_T}; // @[functional-unit.scala:351:{38,39}]
wire [1:0] _pc_sel_T_2 = {1'h0, br_eq}; // @[functional-unit.scala:344:21, :352:38]
wire _pc_sel_T_3 = ~br_lt; // @[functional-unit.scala:346:55, :353:39]
wire [1:0] _pc_sel_T_4 = {1'h0, _pc_sel_T_3}; // @[functional-unit.scala:353:{38,39}]
wire _pc_sel_T_5 = ~br_ltu; // @[functional-unit.scala:345:28, :354:39]
wire [1:0] _pc_sel_T_6 = {1'h0, _pc_sel_T_5}; // @[functional-unit.scala:354:{38,39}]
wire [1:0] _pc_sel_T_7 = {1'h0, br_lt}; // @[functional-unit.scala:346:55, :355:38]
wire [1:0] _pc_sel_T_8 = {1'h0, br_ltu}; // @[functional-unit.scala:345:28, :356:38]
wire _pc_sel_T_9 = io_req_bits_uop_ctrl_br_type_0 == 4'h0; // @[functional-unit.scala:290:7, :349:53]
wire _pc_sel_T_11 = io_req_bits_uop_ctrl_br_type_0 == 4'h1; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_12 = _pc_sel_T_11 ? _pc_sel_T_1 : 2'h0; // @[functional-unit.scala:349:53, :351:38]
wire _pc_sel_T_13 = io_req_bits_uop_ctrl_br_type_0 == 4'h2; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_14 = _pc_sel_T_13 ? _pc_sel_T_2 : _pc_sel_T_12; // @[functional-unit.scala:349:53, :352:38]
wire _pc_sel_T_15 = io_req_bits_uop_ctrl_br_type_0 == 4'h3; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_16 = _pc_sel_T_15 ? _pc_sel_T_4 : _pc_sel_T_14; // @[functional-unit.scala:349:53, :353:38]
wire _pc_sel_T_17 = io_req_bits_uop_ctrl_br_type_0 == 4'h4; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_18 = _pc_sel_T_17 ? _pc_sel_T_6 : _pc_sel_T_16; // @[functional-unit.scala:349:53, :354:38]
wire _pc_sel_T_19 = io_req_bits_uop_ctrl_br_type_0 == 4'h5; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_20 = _pc_sel_T_19 ? _pc_sel_T_7 : _pc_sel_T_18; // @[functional-unit.scala:349:53, :355:38]
wire _pc_sel_T_21 = io_req_bits_uop_ctrl_br_type_0 == 4'h6; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_22 = _pc_sel_T_21 ? _pc_sel_T_8 : _pc_sel_T_20; // @[functional-unit.scala:349:53, :356:38]
wire _pc_sel_T_23 = io_req_bits_uop_ctrl_br_type_0 == 4'h7; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] _pc_sel_T_24 = _pc_sel_T_23 ? 2'h1 : _pc_sel_T_22; // @[functional-unit.scala:349:53]
wire _pc_sel_T_25 = io_req_bits_uop_ctrl_br_type_0 == 4'h8; // @[functional-unit.scala:290:7, :349:53]
wire [1:0] pc_sel = _pc_sel_T_25 ? 2'h2 : _pc_sel_T_24; // @[functional-unit.scala:349:53]
assign brinfo_pc_sel = pc_sel; // @[functional-unit.scala:349:53, :385:20]
wire _is_taken_T = ~killed; // @[functional-unit.scala:337:24, :362:20]
wire _is_taken_T_1 = io_req_valid_0 & _is_taken_T; // @[functional-unit.scala:290:7, :361:31, :362:20]
wire _is_taken_T_2 = io_req_bits_uop_is_br_0 | io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7, :363:31]
wire _is_taken_T_3 = _is_taken_T_2 | io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7, :363:{31,46}]
wire _is_taken_T_4 = _is_taken_T_1 & _is_taken_T_3; // @[functional-unit.scala:361:31, :362:28, :363:46]
wire _is_taken_T_5 = |pc_sel; // @[functional-unit.scala:349:53, :364:28]
wire is_taken = _is_taken_T_4 & _is_taken_T_5; // @[functional-unit.scala:362:28, :363:61, :364:28]
assign brinfo_taken = is_taken; // @[functional-unit.scala:363:61, :385:20]
wire mispredict; // @[functional-unit.scala:367:28]
assign brinfo_mispredict = mispredict; // @[functional-unit.scala:367:28, :385:20]
wire _is_br_T = ~killed; // @[functional-unit.scala:337:24, :362:20, :369:40]
wire _is_br_T_1 = io_req_valid_0 & _is_br_T; // @[functional-unit.scala:290:7, :369:{37,40}]
wire _is_br_T_2 = _is_br_T_1 & io_req_bits_uop_is_br_0; // @[functional-unit.scala:290:7, :369:{37,48}]
wire _is_br_T_3 = ~io_req_bits_uop_is_sfb_0; // @[functional-unit.scala:290:7, :369:64]
wire is_br = _is_br_T_2 & _is_br_T_3; // @[functional-unit.scala:369:{48,61,64}]
wire _is_jal_T = ~killed; // @[functional-unit.scala:337:24, :362:20, :370:40]
wire _is_jal_T_1 = io_req_valid_0 & _is_jal_T; // @[functional-unit.scala:290:7, :370:{37,40}]
wire is_jal = _is_jal_T_1 & io_req_bits_uop_is_jal_0; // @[functional-unit.scala:290:7, :370:{37,48}]
wire _is_jalr_T = ~killed; // @[functional-unit.scala:337:24, :362:20, :371:40]
wire _is_jalr_T_1 = io_req_valid_0 & _is_jalr_T; // @[functional-unit.scala:290:7, :371:{37,40}]
wire is_jalr = _is_jalr_T_1 & io_req_bits_uop_is_jalr_0; // @[functional-unit.scala:290:7, :371:{37,48}]
wire _brinfo_valid_T = is_br | is_jalr; // @[functional-unit.scala:369:61, :371:48, :373:15, :388:34]
|
Generate the Verilog code corresponding to the following Chisel files.
File HasChipyardPRCI.scala:
package chipyard.clocking
import chisel3._
import scala.collection.mutable.{ArrayBuffer}
import org.chipsalliance.cde.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.prci._
import testchipip.boot.{TLTileResetCtrl}
import testchipip.clocking.{ClockGroupFakeResetSynchronizer}
case class ChipyardPRCIControlParams(
slaveWhere: TLBusWrapperLocation = CBUS,
baseAddress: BigInt = 0x100000,
enableTileClockGating: Boolean = true,
enableTileResetSetting: Boolean = true,
enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems
) {
def generatePRCIXBar = enableTileClockGating || enableTileResetSetting
}
case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams())
trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements =>
require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks")
val prciParams = p(ChipyardPRCIControlKey)
// Set up clock domain
private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
val prci_ctrl_domain = tlbus.generateSynchronousDomain("ChipyardPRCICtrl")
.suggestName("chipyard_prcictrl_domain")
val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar(nameSuffix = Some("prcibus")) } }
prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
:= TLFIFOFixer(TLFIFOFixer.all)
:= TLBuffer()
:= _)
})
// Aggregate all the clock groups into a single node
val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
// The diplomatic clocks in the subsystem are routed to this allClockGroupsNode
val clockNamePrefixer = ClockGroupNamePrefixer()
(allClockGroupsNode
:*= clockNamePrefixer
:*= aggregator)
// Once all the clocks are gathered in the aggregator node, several steps remain
// 1. Assign frequencies to any clock groups which did not specify a frequency.
// 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain)
// 3. Synchronize reset to each clock group
// 4. Clock gate the clock groups corresponding to Tiles (if desired).
// 5. Add reset control registers to the tiles (if desired)
// The final clock group here contains physically distinct clock domains, which some PRCI node in a
// diplomatic IOBinder should drive
val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey))
val clockGroupCombiner = ClockGroupCombiner()
val resetSynchronizer = prci_ctrl_domain {
if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer()
}
val tileClockGater = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
clock_gater.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileClockGater")) := prci_ctrl_bus.get
clock_gater
} }
val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil))
reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes, nameSuffix = Some("TileResetSetter")) := prci_ctrl_bus.get
reset_setter
} }
if (!prciParams.enableResetSynchronizers) {
println(Console.RED + s"""
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
WARNING:
DISABLING THE RESET SYNCHRONIZERS RESULTS IN
A BROKEN DESIGN THAT WILL NOT BEHAVE
PROPERLY AS ASIC OR FPGA.
THESE SHOULD ONLY BE DISABLED TO WORK AROUND
LIMITATIONS IN ASYNC RESET INITIALIZATION IN
RTL SIMULATORS, NAMELY VERILATOR.
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
""" + Console.RESET)
}
// The chiptopClockGroupsNode shouuld be what ClockBinders attach to
val chiptopClockGroupsNode = ClockGroupEphemeralNode()
(aggregator
:= frequencySpecifier
:= clockGroupCombiner
:= resetSynchronizer
:= tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
:= tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
:= chiptopClockGroupsNode)
}
File Fragmenter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressSet, BufferParams, IdRange, TransferSizes}
import freechips.rocketchip.util.{Repeater, OH1ToUInt, UIntToOH1}
import scala.math.min
import freechips.rocketchip.util.DataToAugmentedData
object EarlyAck {
sealed trait T
case object AllPuts extends T
case object PutFulls extends T
case object None extends T
}
// minSize: minimum size of transfers supported by all outward managers
// maxSize: maximum size of transfers supported after the Fragmenter is applied
// alwaysMin: fragment all requests down to minSize (else fragment to maximum supported by manager)
// earlyAck: should a multibeat Put should be acknowledged on the first beat or last beat
// holdFirstDeny: allow the Fragmenter to unsafely combine multibeat Gets by taking the first denied for the whole burst
// nameSuffix: appends a suffix to the module name
// Fragmenter modifies: PutFull, PutPartial, LogicalData, Get, Hint
// Fragmenter passes: ArithmeticData (truncated to minSize if alwaysMin)
// Fragmenter cannot modify acquire (could livelock); thus it is unsafe to put caches on both sides
class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean = false, val earlyAck: EarlyAck.T = EarlyAck.None, val holdFirstDeny: Boolean = false, val nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
require(isPow2 (maxSize), s"TLFragmenter expects pow2(maxSize), but got $maxSize")
require(isPow2 (minSize), s"TLFragmenter expects pow2(minSize), but got $minSize")
require(minSize <= maxSize, s"TLFragmenter expects min <= max, but got $minSize > $maxSize")
val fragmentBits = log2Ceil(maxSize / minSize)
val fullBits = if (earlyAck == EarlyAck.PutFulls) 1 else 0
val toggleBits = 1
val addedBits = fragmentBits + toggleBits + fullBits
def expandTransfer(x: TransferSizes, op: String) = if (!x) x else {
// validate that we can apply the fragmenter correctly
require (x.max >= minSize, s"TLFragmenter (with parent $parent) max transfer size $op(${x.max}) must be >= min transfer size (${minSize})")
TransferSizes(x.min, maxSize)
}
private def noChangeRequired = minSize == maxSize
private def shrinkTransfer(x: TransferSizes) =
if (!alwaysMin) x
else if (x.min <= minSize) TransferSizes(x.min, min(minSize, x.max))
else TransferSizes.none
private def mapManager(m: TLSlaveParameters) = m.v1copy(
supportsArithmetic = shrinkTransfer(m.supportsArithmetic),
supportsLogical = shrinkTransfer(m.supportsLogical),
supportsGet = expandTransfer(m.supportsGet, "Get"),
supportsPutFull = expandTransfer(m.supportsPutFull, "PutFull"),
supportsPutPartial = expandTransfer(m.supportsPutPartial, "PutParital"),
supportsHint = expandTransfer(m.supportsHint, "Hint"))
val node = new TLAdapterNode(
// We require that all the responses are mutually FIFO
// Thus we need to compact all of the masters into one big master
clientFn = { c => (if (noChangeRequired) c else c.v2copy(
masters = Seq(TLMasterParameters.v2(
name = "TLFragmenter",
sourceId = IdRange(0, if (minSize == maxSize) c.endSourceId else (c.endSourceId << addedBits)),
requestFifo = true,
emits = TLMasterToSlaveTransferSizes(
acquireT = shrinkTransfer(c.masters.map(_.emits.acquireT) .reduce(_ mincover _)),
acquireB = shrinkTransfer(c.masters.map(_.emits.acquireB) .reduce(_ mincover _)),
arithmetic = shrinkTransfer(c.masters.map(_.emits.arithmetic).reduce(_ mincover _)),
logical = shrinkTransfer(c.masters.map(_.emits.logical) .reduce(_ mincover _)),
get = shrinkTransfer(c.masters.map(_.emits.get) .reduce(_ mincover _)),
putFull = shrinkTransfer(c.masters.map(_.emits.putFull) .reduce(_ mincover _)),
putPartial = shrinkTransfer(c.masters.map(_.emits.putPartial).reduce(_ mincover _)),
hint = shrinkTransfer(c.masters.map(_.emits.hint) .reduce(_ mincover _))
)
))
))},
managerFn = { m => if (noChangeRequired) m else m.v2copy(slaves = m.slaves.map(mapManager)) }
) {
override def circuitIdentity = noChangeRequired
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
override def desiredName = (Seq("TLFragmenter") ++ nameSuffix).mkString("_")
(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
if (noChangeRequired) {
out <> in
} else {
// All managers must share a common FIFO domain (responses might end up interleaved)
val manager = edgeOut.manager
val managers = manager.managers
val beatBytes = manager.beatBytes
val fifoId = managers(0).fifoId
require (fifoId.isDefined && managers.map(_.fifoId == fifoId).reduce(_ && _))
require (!manager.anySupportAcquireB || !edgeOut.client.anySupportProbe,
s"TLFragmenter (with parent $parent) can't fragment a caching client's requests into a cacheable region")
require (minSize >= beatBytes, s"TLFragmenter (with parent $parent) can't support fragmenting ($minSize) to sub-beat ($beatBytes) accesses")
// We can't support devices which are cached on both sides of us
require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
// We can't support denied because we reassemble fragments
require (!edgeOut.manager.mayDenyGet || holdFirstDeny, s"TLFragmenter (with parent $parent) can't support denials without holdFirstDeny=true")
require (!edgeOut.manager.mayDenyPut || earlyAck == EarlyAck.None)
/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
* max size -- the maximum transfer size possible
* orig size -- the original pre-fragmenter size
* frag size -- the modified post-fragmenter size
* min size -- the threshold below which frag=orig
* beat size -- the amount transfered on any given beat
*
* The relationships are as follows:
* max >= orig >= frag
* max > min >= beat
* It IS possible that orig <= min (then frag=orig; ie: no fragmentation)
*
* The fragment# (sent via TL.source) is measured in multiples of min size.
* Meanwhile, to track the progress, counters measure in multiples of beat size.
*
* Here is an example of a bus with max=256, min=8, beat=4 and a device supporting 16.
*
* in.A out.A (frag#) out.D (frag#) in.D gen# ack#
* get64 get16 6 ackD16 6 ackD64 12 15
* ackD16 6 ackD64 14
* ackD16 6 ackD64 13
* ackD16 6 ackD64 12
* get16 4 ackD16 4 ackD64 8 11
* ackD16 4 ackD64 10
* ackD16 4 ackD64 9
* ackD16 4 ackD64 8
* get16 2 ackD16 2 ackD64 4 7
* ackD16 2 ackD64 6
* ackD16 2 ackD64 5
* ackD16 2 ackD64 4
* get16 0 ackD16 0 ackD64 0 3
* ackD16 0 ackD64 2
* ackD16 0 ackD64 1
* ackD16 0 ackD64 0
*
* get8 get8 0 ackD8 0 ackD8 0 1
* ackD8 0 ackD8 0
*
* get4 get4 0 ackD4 0 ackD4 0 0
* get1 get1 0 ackD1 0 ackD1 0 0
*
* put64 put16 6 15
* put64 put16 6 14
* put64 put16 6 13
* put64 put16 6 ack16 6 12 12
* put64 put16 4 11
* put64 put16 4 10
* put64 put16 4 9
* put64 put16 4 ack16 4 8 8
* put64 put16 2 7
* put64 put16 2 6
* put64 put16 2 5
* put64 put16 2 ack16 2 4 4
* put64 put16 0 3
* put64 put16 0 2
* put64 put16 0 1
* put64 put16 0 ack16 0 ack64 0 0
*
* put8 put8 0 1
* put8 put8 0 ack8 0 ack8 0 0
*
* put4 put4 0 ack4 0 ack4 0 0
* put1 put1 0 ack1 0 ack1 0 0
*/
val counterBits = log2Up(maxSize/beatBytes)
val maxDownSize = if (alwaysMin) minSize else min(manager.maxTransfer, maxSize)
// Consider the following waveform for two 4-beat bursts:
// ---A----A------------
// -------D-----DDD-DDDD
// Under TL rules, the second A can use the same source as the first A,
// because the source is released for reuse on the first response beat.
//
// However, if we fragment the requests, it looks like this:
// ---3210-3210---------
// -------3-----210-3210
// ... now we've broken the rules because 210 are twice inflight.
//
// This phenomenon means we can have essentially 2*maxSize/minSize-1
// fragmented transactions in flight per original transaction source.
//
// To keep the source unique, we encode the beat counter in the low
// bits of the source. To solve the overlap, we use a toggle bit.
// Whatever toggle bit the D is reassembling, A will use the opposite.
// First, handle the return path
val acknum = RegInit(0.U(counterBits.W))
val dOrig = Reg(UInt())
val dToggle = RegInit(false.B)
val dFragnum = out.d.bits.source(fragmentBits-1, 0)
val dFirst = acknum === 0.U
val dLast = dFragnum === 0.U // only for AccessAck (!Data)
val dsizeOH = UIntToOH (out.d.bits.size, log2Ceil(maxDownSize)+1)
val dsizeOH1 = UIntToOH1(out.d.bits.size, log2Up(maxDownSize))
val dHasData = edgeOut.hasData(out.d.bits)
// calculate new acknum
val acknum_fragment = dFragnum << log2Ceil(minSize/beatBytes)
val acknum_size = dsizeOH1 >> log2Ceil(beatBytes)
assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)
val dFirst_acknum = acknum_fragment | Mux(dHasData, acknum_size, 0.U)
val ack_decrement = Mux(dHasData, 1.U, dsizeOH >> log2Ceil(beatBytes))
// calculate the original size
val dFirst_size = OH1ToUInt((dFragnum << log2Ceil(minSize)) | dsizeOH1)
when (out.d.fire) {
acknum := Mux(dFirst, dFirst_acknum, acknum - ack_decrement)
when (dFirst) {
dOrig := dFirst_size
dToggle := out.d.bits.source(fragmentBits)
}
}
// Swallow up non-data ack fragments
val doEarlyAck = earlyAck match {
case EarlyAck.AllPuts => true.B
case EarlyAck.PutFulls => out.d.bits.source(fragmentBits+1)
case EarlyAck.None => false.B
}
val drop = !dHasData && !Mux(doEarlyAck, dFirst, dLast)
out.d.ready := in.d.ready || drop
in.d.valid := out.d.valid && !drop
in.d.bits := out.d.bits // pass most stuff unchanged
in.d.bits.source := out.d.bits.source >> addedBits
in.d.bits.size := Mux(dFirst, dFirst_size, dOrig)
if (edgeOut.manager.mayDenyPut) {
val r_denied = Reg(Bool())
val d_denied = (!dFirst && r_denied) || out.d.bits.denied
when (out.d.fire) { r_denied := d_denied }
in.d.bits.denied := d_denied
}
if (edgeOut.manager.mayDenyGet) {
// Take denied only from the first beat and hold that value
val d_denied = out.d.bits.denied holdUnless dFirst
when (dHasData) {
in.d.bits.denied := d_denied
in.d.bits.corrupt := d_denied || out.d.bits.corrupt
}
}
// What maximum transfer sizes do downstream devices support?
val maxArithmetics = managers.map(_.supportsArithmetic.max)
val maxLogicals = managers.map(_.supportsLogical.max)
val maxGets = managers.map(_.supportsGet.max)
val maxPutFulls = managers.map(_.supportsPutFull.max)
val maxPutPartials = managers.map(_.supportsPutPartial.max)
val maxHints = managers.map(m => if (m.supportsHint) maxDownSize else 0)
// We assume that the request is valid => size 0 is impossible
val lgMinSize = log2Ceil(minSize).U
val maxLgArithmetics = maxArithmetics.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgLogicals = maxLogicals .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgGets = maxGets .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutFulls = maxPutFulls .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgPutPartials = maxPutPartials.map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
val maxLgHints = maxHints .map(m => if (m == 0) lgMinSize else log2Ceil(m).U)
// Make the request repeatable
val repeater = Module(new Repeater(in.a.bits))
repeater.io.enq <> in.a
val in_a = repeater.io.deq
// If this is infront of a single manager, these become constants
val find = manager.findFast(edgeIn.address(in_a.bits))
val maxLgArithmetic = Mux1H(find, maxLgArithmetics)
val maxLgLogical = Mux1H(find, maxLgLogicals)
val maxLgGet = Mux1H(find, maxLgGets)
val maxLgPutFull = Mux1H(find, maxLgPutFulls)
val maxLgPutPartial = Mux1H(find, maxLgPutPartials)
val maxLgHint = Mux1H(find, maxLgHints)
val limit = if (alwaysMin) lgMinSize else
MuxLookup(in_a.bits.opcode, lgMinSize)(Array(
TLMessages.PutFullData -> maxLgPutFull,
TLMessages.PutPartialData -> maxLgPutPartial,
TLMessages.ArithmeticData -> maxLgArithmetic,
TLMessages.LogicalData -> maxLgLogical,
TLMessages.Get -> maxLgGet,
TLMessages.Hint -> maxLgHint))
val aOrig = in_a.bits.size
val aFrag = Mux(aOrig > limit, limit, aOrig)
val aOrigOH1 = UIntToOH1(aOrig, log2Ceil(maxSize))
val aFragOH1 = UIntToOH1(aFrag, log2Up(maxDownSize))
val aHasData = edgeIn.hasData(in_a.bits)
val aMask = Mux(aHasData, 0.U, aFragOH1)
val gennum = RegInit(0.U(counterBits.W))
val aFirst = gennum === 0.U
val old_gennum1 = Mux(aFirst, aOrigOH1 >> log2Ceil(beatBytes), gennum - 1.U)
val new_gennum = ~(~old_gennum1 | (aMask >> log2Ceil(beatBytes))) // ~(~x|y) is width safe
val aFragnum = ~(~(old_gennum1 >> log2Ceil(minSize/beatBytes)) | (aFragOH1 >> log2Ceil(minSize)))
val aLast = aFragnum === 0.U
val aToggle = !Mux(aFirst, dToggle, RegEnable(dToggle, aFirst))
val aFull = if (earlyAck == EarlyAck.PutFulls) Some(in_a.bits.opcode === TLMessages.PutFullData) else None
when (out.a.fire) { gennum := new_gennum }
repeater.io.repeat := !aHasData && aFragnum =/= 0.U
out.a <> in_a
out.a.bits.address := in_a.bits.address | ~(old_gennum1 << log2Ceil(beatBytes) | ~aOrigOH1 | aFragOH1 | (minSize-1).U)
out.a.bits.source := Cat(Seq(in_a.bits.source) ++ aFull ++ Seq(aToggle.asUInt, aFragnum))
out.a.bits.size := aFrag
// Optimize away some of the Repeater's registers
assert (!repeater.io.full || !aHasData)
out.a.bits.data := in.a.bits.data
val fullMask = ((BigInt(1) << beatBytes) - 1).U
assert (!repeater.io.full || in_a.bits.mask === fullMask)
out.a.bits.mask := Mux(repeater.io.full, fullMask, in.a.bits.mask)
out.a.bits.user.waiveAll :<= in.a.bits.user.subset(_.isData)
// Tie off unused channels
in.b.valid := false.B
in.c.ready := true.B
in.e.ready := true.B
out.b.ready := true.B
out.c.valid := false.B
out.e.valid := false.B
}
}
}
}
object TLFragmenter
{
def apply(minSize: Int, maxSize: Int, alwaysMin: Boolean = false, earlyAck: EarlyAck.T = EarlyAck.None, holdFirstDeny: Boolean = false, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
if (minSize <= maxSize) {
val fragmenter = LazyModule(new TLFragmenter(minSize, maxSize, alwaysMin, earlyAck, holdFirstDeny, nameSuffix))
fragmenter.node
} else { TLEphemeralNode()(ValName("no_fragmenter")) }
}
def apply(wrapper: TLBusWrapper, nameSuffix: Option[String])(implicit p: Parameters): TLNode = apply(wrapper.beatBytes, wrapper.blockBytes, nameSuffix = nameSuffix)
def apply(wrapper: TLBusWrapper)(implicit p: Parameters): TLNode = apply(wrapper, None)
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = EarlyAck.AllPuts)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMFragmenterTest(ramBeatBytes: Int, maxSize: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMFragmenter(ramBeatBytes,maxSize,txns)).module)
io.finished := dut.io.finished
dut.io.start := io.start
}
File ClockDomain.scala:
package freechips.rocketchip.prci
import chisel3._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
abstract class Domain(implicit p: Parameters) extends LazyModule with HasDomainCrossing
{
def clockBundle: ClockBundle
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
childClock := clockBundle.clock
childReset := clockBundle.reset
override def provideImplicitClockToLazyChildren = true
// these are just for backwards compatibility with external devices
// that were manually wiring themselves to the domain's clock/reset input:
val clock = IO(Output(chiselTypeOf(clockBundle.clock)))
val reset = IO(Output(chiselTypeOf(clockBundle.reset)))
clock := clockBundle.clock
reset := clockBundle.reset
}
}
abstract class ClockDomain(implicit p: Parameters) extends Domain with HasClockDomainCrossing
class ClockSinkDomain(val clockSinkParams: ClockSinkParameters)(implicit p: Parameters) extends ClockDomain
{
def this(take: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSinkParameters(take = take, name = name))
val clockNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockNode.in.head._1
override lazy val desiredName = (clockSinkParams.name.toSeq :+ "ClockSinkDomain").mkString
}
class ClockSourceDomain(val clockSourceParams: ClockSourceParameters)(implicit p: Parameters) extends ClockDomain
{
def this(give: Option[ClockParameters] = None, name: Option[String] = None)(implicit p: Parameters) = this(ClockSourceParameters(give = give, name = name))
val clockNode = ClockSourceNode(Seq(clockSourceParams))
def clockBundle = clockNode.out.head._1
override lazy val desiredName = (clockSourceParams.name.toSeq :+ "ClockSourceDomain").mkString
}
abstract class ResetDomain(implicit p: Parameters) extends Domain with HasResetDomainCrossing
File ResetSynchronizer.scala:
// See LICENSE for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.ResetCatchAndSync
/**
* Synchronizes the reset of a diplomatic clock-reset pair to its accompanying clock.
*/
class ResetSynchronizer(implicit p: Parameters) extends LazyModule {
val node = ClockAdapterNode()
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
(node.out zip node.in).map { case ((o, _), (i, _)) =>
o.clock := i.clock
o.reset := ResetCatchAndSync(i.clock, i.reset.asBool)
}
}
}
object ResetSynchronizer {
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ResetSynchronizer()).node
}
/**
* Instantiates a reset synchronizer on all clock-reset pairs in a clock group.
*/
class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule {
val node = ClockGroupAdapterNode()
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
(node.out zip node.in).map { case ((oG, _), (iG, _)) =>
(oG.member.data zip iG.member.data).foreach { case (o, i) =>
o.clock := i.clock
o.reset := ResetCatchAndSync(i.clock, i.reset.asBool)
}
}
}
}
object ClockGroupResetSynchronizer {
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File Xbar.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.diplomacy.{AddressDecoder, AddressSet, RegionType, IdRange, TriStateValue}
import freechips.rocketchip.util.BundleField
// Trades off slave port proximity against routing resource cost
object ForceFanout
{
def apply[T](
a: TriStateValue = TriStateValue.unset,
b: TriStateValue = TriStateValue.unset,
c: TriStateValue = TriStateValue.unset,
d: TriStateValue = TriStateValue.unset,
e: TriStateValue = TriStateValue.unset)(body: Parameters => T)(implicit p: Parameters) =
{
body(p.alterPartial {
case ForceFanoutKey => p(ForceFanoutKey) match {
case ForceFanoutParams(pa, pb, pc, pd, pe) =>
ForceFanoutParams(a.update(pa), b.update(pb), c.update(pc), d.update(pd), e.update(pe))
}
})
}
}
private case class ForceFanoutParams(a: Boolean, b: Boolean, c: Boolean, d: Boolean, e: Boolean)
private case object ForceFanoutKey extends Field(ForceFanoutParams(false, false, false, false, false))
class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters) extends LazyModule
{
val node = new TLNexusNode(
clientFn = { seq =>
seq(0).v1copy(
echoFields = BundleField.union(seq.flatMap(_.echoFields)),
requestFields = BundleField.union(seq.flatMap(_.requestFields)),
responseKeys = seq.flatMap(_.responseKeys).distinct,
minLatency = seq.map(_.minLatency).min,
clients = (TLXbar.mapInputIds(seq) zip seq) flatMap { case (range, port) =>
port.clients map { client => client.v1copy(
sourceId = client.sourceId.shift(range.start)
)}
}
)
},
managerFn = { seq =>
val fifoIdFactory = TLXbar.relabeler()
seq(0).v1copy(
responseFields = BundleField.union(seq.flatMap(_.responseFields)),
requestKeys = seq.flatMap(_.requestKeys).distinct,
minLatency = seq.map(_.minLatency).min,
endSinkId = TLXbar.mapOutputIds(seq).map(_.end).max,
managers = seq.flatMap { port =>
require (port.beatBytes == seq(0).beatBytes,
s"Xbar ($name with parent $parent) data widths don't match: ${port.managers.map(_.name)} has ${port.beatBytes}B vs ${seq(0).managers.map(_.name)} has ${seq(0).beatBytes}B")
val fifoIdMapper = fifoIdFactory()
port.managers map { manager => manager.v1copy(
fifoId = manager.fifoId.map(fifoIdMapper(_))
)}
}
)
}
){
override def circuitIdentity = outputs.size == 1 && inputs.size == 1
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) {
if ((node.in.size * node.out.size) > (8*32)) {
println (s"!!! WARNING !!!")
println (s" Your TLXbar ($name with parent $parent) is very large, with ${node.in.size} Masters and ${node.out.size} Slaves.")
println (s"!!! WARNING !!!")
}
val wide_bundle = TLBundleParameters.union((node.in ++ node.out).map(_._2.bundle))
override def desiredName = (Seq("TLXbar") ++ nameSuffix ++ Seq(s"i${node.in.size}_o${node.out.size}_${wide_bundle.shortName}")).mkString("_")
TLXbar.circuit(policy, node.in, node.out)
}
}
object TLXbar
{
def mapInputIds(ports: Seq[TLMasterPortParameters]) = assignRanges(ports.map(_.endSourceId))
def mapOutputIds(ports: Seq[TLSlavePortParameters]) = assignRanges(ports.map(_.endSinkId))
def assignRanges(sizes: Seq[Int]) = {
val pow2Sizes = sizes.map { z => if (z == 0) 0 else 1 << log2Ceil(z) }
val tuples = pow2Sizes.zipWithIndex.sortBy(_._1) // record old index, then sort by increasing size
val starts = tuples.scanRight(0)(_._1 + _).tail // suffix-sum of the sizes = the start positions
val ranges = (tuples zip starts) map { case ((sz, i), st) =>
(if (sz == 0) IdRange(0, 0) else IdRange(st, st + sz), i)
}
ranges.sortBy(_._2).map(_._1) // Restore orignal order
}
def relabeler() = {
var idFactory = 0
() => {
val fifoMap = scala.collection.mutable.HashMap.empty[Int, Int]
(x: Int) => {
if (fifoMap.contains(x)) fifoMap(x) else {
val out = idFactory
idFactory = idFactory + 1
fifoMap += (x -> out)
out
}
}
}
}
def circuit(policy: TLArbiter.Policy, seqIn: Seq[(TLBundle, TLEdge)], seqOut: Seq[(TLBundle, TLEdge)]) {
val (io_in, edgesIn) = seqIn.unzip
val (io_out, edgesOut) = seqOut.unzip
// Not every master need connect to every slave on every channel; determine which connections are necessary
val reachableIO = edgesIn.map { cp => edgesOut.map { mp =>
cp.client.clients.exists { c => mp.manager.managers.exists { m =>
c.visibility.exists { ca => m.address.exists { ma =>
ca.overlaps(ma)}}}}
}.toVector}.toVector
val probeIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.managers.exists(_.regionType >= RegionType.TRACKED)
}.toVector}.toVector
val releaseIO = (edgesIn zip reachableIO).map { case (cp, reachableO) =>
(edgesOut zip reachableO).map { case (mp, reachable) =>
reachable && cp.client.anySupportProbe && mp.manager.anySupportAcquireB
}.toVector}.toVector
val connectAIO = reachableIO
val connectBIO = probeIO
val connectCIO = releaseIO
val connectDIO = reachableIO
val connectEIO = releaseIO
def transpose[T](x: Seq[Seq[T]]) = if (x.isEmpty) Nil else Vector.tabulate(x(0).size) { i => Vector.tabulate(x.size) { j => x(j)(i) } }
val connectAOI = transpose(connectAIO)
val connectBOI = transpose(connectBIO)
val connectCOI = transpose(connectCIO)
val connectDOI = transpose(connectDIO)
val connectEOI = transpose(connectEIO)
// Grab the port ID mapping
val inputIdRanges = TLXbar.mapInputIds(edgesIn.map(_.client))
val outputIdRanges = TLXbar.mapOutputIds(edgesOut.map(_.manager))
// We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = TLBundleParameters.union(io_in.map(_.params) ++ io_out.map(_.params))
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
// Transform input bundle sources (sinks use global namespace on both sides)
val in = Wire(Vec(io_in.size, TLBundle(wide_bundle)))
for (i <- 0 until in.size) {
val r = inputIdRanges(i)
if (connectAIO(i).exists(x=>x)) {
in(i).a.bits.user := DontCare
in(i).a.squeezeAll.waiveAll :<>= io_in(i).a.squeezeAll.waiveAll
in(i).a.bits.source := io_in(i).a.bits.source | r.start.U
} else {
in(i).a := DontCare
io_in(i).a := DontCare
in(i).a.valid := false.B
io_in(i).a.ready := true.B
}
if (connectBIO(i).exists(x=>x)) {
io_in(i).b.squeezeAll :<>= in(i).b.squeezeAll
io_in(i).b.bits.source := trim(in(i).b.bits.source, r.size)
} else {
in(i).b := DontCare
io_in(i).b := DontCare
in(i).b.ready := true.B
io_in(i).b.valid := false.B
}
if (connectCIO(i).exists(x=>x)) {
in(i).c.bits.user := DontCare
in(i).c.squeezeAll.waiveAll :<>= io_in(i).c.squeezeAll.waiveAll
in(i).c.bits.source := io_in(i).c.bits.source | r.start.U
} else {
in(i).c := DontCare
io_in(i).c := DontCare
in(i).c.valid := false.B
io_in(i).c.ready := true.B
}
if (connectDIO(i).exists(x=>x)) {
io_in(i).d.squeezeAll.waiveAll :<>= in(i).d.squeezeAll.waiveAll
io_in(i).d.bits.source := trim(in(i).d.bits.source, r.size)
} else {
in(i).d := DontCare
io_in(i).d := DontCare
in(i).d.ready := true.B
io_in(i).d.valid := false.B
}
if (connectEIO(i).exists(x=>x)) {
in(i).e.squeezeAll :<>= io_in(i).e.squeezeAll
} else {
in(i).e := DontCare
io_in(i).e := DontCare
in(i).e.valid := false.B
io_in(i).e.ready := true.B
}
}
// Transform output bundle sinks (sources use global namespace on both sides)
val out = Wire(Vec(io_out.size, TLBundle(wide_bundle)))
for (o <- 0 until out.size) {
val r = outputIdRanges(o)
if (connectAOI(o).exists(x=>x)) {
out(o).a.bits.user := DontCare
io_out(o).a.squeezeAll.waiveAll :<>= out(o).a.squeezeAll.waiveAll
} else {
out(o).a := DontCare
io_out(o).a := DontCare
out(o).a.ready := true.B
io_out(o).a.valid := false.B
}
if (connectBOI(o).exists(x=>x)) {
out(o).b.squeezeAll :<>= io_out(o).b.squeezeAll
} else {
out(o).b := DontCare
io_out(o).b := DontCare
out(o).b.valid := false.B
io_out(o).b.ready := true.B
}
if (connectCOI(o).exists(x=>x)) {
out(o).c.bits.user := DontCare
io_out(o).c.squeezeAll.waiveAll :<>= out(o).c.squeezeAll.waiveAll
} else {
out(o).c := DontCare
io_out(o).c := DontCare
out(o).c.ready := true.B
io_out(o).c.valid := false.B
}
if (connectDOI(o).exists(x=>x)) {
out(o).d.squeezeAll :<>= io_out(o).d.squeezeAll
out(o).d.bits.sink := io_out(o).d.bits.sink | r.start.U
} else {
out(o).d := DontCare
io_out(o).d := DontCare
out(o).d.valid := false.B
io_out(o).d.ready := true.B
}
if (connectEOI(o).exists(x=>x)) {
io_out(o).e.squeezeAll :<>= out(o).e.squeezeAll
io_out(o).e.bits.sink := trim(out(o).e.bits.sink, r.size)
} else {
out(o).e := DontCare
io_out(o).e := DontCare
out(o).e.ready := true.B
io_out(o).e.valid := false.B
}
}
// Filter a list to only those elements selected
def filter[T](data: Seq[T], mask: Seq[Boolean]) = (data zip mask).filter(_._2).map(_._1)
// Based on input=>output connectivity, create per-input minimal address decode circuits
val requiredAC = (connectAIO ++ connectCIO).distinct
val outputPortFns: Map[Vector[Boolean], Seq[UInt => Bool]] = requiredAC.map { connectO =>
val port_addrs = edgesOut.map(_.manager.managers.flatMap(_.address))
val routingMask = AddressDecoder(filter(port_addrs, connectO))
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
// Print the address mapping
if (false) {
println("Xbar mapping:")
route_addrs.foreach { p =>
print(" ")
p.foreach { a => print(s" ${a}") }
println("")
}
println("--")
}
(connectO, route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)))
}.toMap
// Print the ID mapping
if (false) {
println(s"XBar mapping:")
(edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
val addressA = (in zip edgesIn) map { case (i, e) => e.address(i.a.bits) }
val addressC = (in zip edgesIn) map { case (i, e) => e.address(i.c.bits) }
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
val requestAIO = (connectAIO zip addressA) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestCIO = (connectCIO zip addressC) map { case (c, i) => outputPortFns(c).map { o => unique(c) || o(i) } }
val requestBOI = out.map { o => inputIdRanges.map { i => i.contains(o.b.bits.source) } }
val requestDOI = out.map { o => inputIdRanges.map { i => i.contains(o.d.bits.source) } }
val requestEIO = in.map { i => outputIdRanges.map { o => o.contains(i.e.bits.sink) } }
val beatsAI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.a.bits) }
val beatsBO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.b.bits) }
val beatsCI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.c.bits) }
val beatsDO = (out zip edgesOut) map { case (o, e) => e.numBeats1(o.d.bits) }
val beatsEI = (in zip edgesIn) map { case (i, e) => e.numBeats1(i.e.bits) }
// Fanout the input sources to the output sinks
val portsAOI = transpose((in zip requestAIO) map { case (i, r) => TLXbar.fanout(i.a, r, edgesOut.map(_.params(ForceFanoutKey).a)) })
val portsBIO = transpose((out zip requestBOI) map { case (o, r) => TLXbar.fanout(o.b, r, edgesIn .map(_.params(ForceFanoutKey).b)) })
val portsCOI = transpose((in zip requestCIO) map { case (i, r) => TLXbar.fanout(i.c, r, edgesOut.map(_.params(ForceFanoutKey).c)) })
val portsDIO = transpose((out zip requestDOI) map { case (o, r) => TLXbar.fanout(o.d, r, edgesIn .map(_.params(ForceFanoutKey).d)) })
val portsEOI = transpose((in zip requestEIO) map { case (i, r) => TLXbar.fanout(i.e, r, edgesOut.map(_.params(ForceFanoutKey).e)) })
// Arbitrate amongst the sources
for (o <- 0 until out.size) {
TLArbiter(policy)(out(o).a, filter(beatsAI zip portsAOI(o), connectAOI(o)):_*)
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), connectCOI(o)):_*)
TLArbiter(policy)(out(o).e, filter(beatsEI zip portsEOI(o), connectEOI(o)):_*)
filter(portsAOI(o), connectAOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsCOI(o), connectCOI(o).map(!_)) foreach { r => r.ready := false.B }
filter(portsEOI(o), connectEOI(o).map(!_)) foreach { r => r.ready := false.B }
}
for (i <- 0 until in.size) {
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), connectBIO(i)):_*)
TLArbiter(policy)(in(i).d, filter(beatsDO zip portsDIO(i), connectDIO(i)):_*)
filter(portsBIO(i), connectBIO(i).map(!_)) foreach { r => r.ready := false.B }
filter(portsDIO(i), connectDIO(i).map(!_)) foreach { r => r.ready := false.B }
}
}
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin, nameSuffix: Option[String] = None)(implicit p: Parameters): TLNode =
{
val xbar = LazyModule(new TLXbar(policy, nameSuffix))
xbar.node
}
// Replicate an input port to each output port
def fanout[T <: TLChannel](input: DecoupledIO[T], select: Seq[Bool], force: Seq[Boolean] = Nil): Seq[DecoupledIO[T]] = {
val filtered = Wire(Vec(select.size, chiselTypeOf(input)))
for (i <- 0 until select.size) {
filtered(i).bits := (if (force.lift(i).getOrElse(false)) IdentityModule(input.bits) else input.bits)
filtered(i).valid := input.valid && (select(i) || (select.size == 1).B)
}
input.ready := Mux1H(select, filtered.map(_.ready))
filtered
}
}
// Synthesizable unit tests
import freechips.rocketchip.unittest._
class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
}
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar)
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new Impl
class Impl extends LazyModuleImp(this) with UnitTestModule {
io.finished := fuzzers.last.module.io.finished
}
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
dut.io.start := io.start
io.finished := dut.io.finished
}
|
module ChipyardPRCICtrlClockSinkDomain( // @[ClockDomain.scala:14:9]
input auto_reset_setter_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_reset_setter_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_resetSynchronizer_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_resetSynchronizer_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_xbar_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [9:0] auto_xbar_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_xbar_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_xbar_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_xbar_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_xbar_anon_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_xbar_anon_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_xbar_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [9:0] auto_xbar_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_xbar_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset // @[LazyModuleImp.scala:107:25]
);
wire _fragmenter_1_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34]
wire _fragmenter_1_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_1_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_1_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34]
wire [9:0] _fragmenter_1_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34]
wire _fragmenter_1_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_1_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_1_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34]
wire [1:0] _fragmenter_1_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34]
wire [13:0] _fragmenter_1_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34]
wire [20:0] _fragmenter_1_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_1_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_1_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_1_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34]
wire _fragmenter_1_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34]
wire _reset_setter_auto_clock_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:78:34]
wire _reset_setter_auto_clock_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:78:34]
wire _reset_setter_auto_tl_in_a_ready; // @[HasChipyardPRCI.scala:78:34]
wire _reset_setter_auto_tl_in_d_valid; // @[HasChipyardPRCI.scala:78:34]
wire [2:0] _reset_setter_auto_tl_in_d_bits_opcode; // @[HasChipyardPRCI.scala:78:34]
wire [1:0] _reset_setter_auto_tl_in_d_bits_size; // @[HasChipyardPRCI.scala:78:34]
wire [13:0] _reset_setter_auto_tl_in_d_bits_source; // @[HasChipyardPRCI.scala:78:34]
wire _fragmenter_auto_anon_in_a_ready; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_in_d_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_in_d_bits_size; // @[Fragmenter.scala:345:34]
wire [9:0] _fragmenter_auto_anon_in_d_bits_source; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_in_d_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_valid; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_opcode; // @[Fragmenter.scala:345:34]
wire [2:0] _fragmenter_auto_anon_out_a_bits_param; // @[Fragmenter.scala:345:34]
wire [1:0] _fragmenter_auto_anon_out_a_bits_size; // @[Fragmenter.scala:345:34]
wire [13:0] _fragmenter_auto_anon_out_a_bits_source; // @[Fragmenter.scala:345:34]
wire [20:0] _fragmenter_auto_anon_out_a_bits_address; // @[Fragmenter.scala:345:34]
wire [7:0] _fragmenter_auto_anon_out_a_bits_mask; // @[Fragmenter.scala:345:34]
wire [63:0] _fragmenter_auto_anon_out_a_bits_data; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_a_bits_corrupt; // @[Fragmenter.scala:345:34]
wire _fragmenter_auto_anon_out_d_ready; // @[Fragmenter.scala:345:34]
wire _clock_gater_auto_clock_gater_in_1_a_ready; // @[HasChipyardPRCI.scala:73:33]
wire _clock_gater_auto_clock_gater_in_1_d_valid; // @[HasChipyardPRCI.scala:73:33]
wire [2:0] _clock_gater_auto_clock_gater_in_1_d_bits_opcode; // @[HasChipyardPRCI.scala:73:33]
wire [1:0] _clock_gater_auto_clock_gater_in_1_d_bits_size; // @[HasChipyardPRCI.scala:73:33]
wire [13:0] _clock_gater_auto_clock_gater_in_1_d_bits_source; // @[HasChipyardPRCI.scala:73:33]
wire [63:0] _clock_gater_auto_clock_gater_in_1_d_bits_data; // @[HasChipyardPRCI.scala:73:33]
wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock; // @[HasChipyardPRCI.scala:73:33]
wire _clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset; // @[HasChipyardPRCI.scala:73:33]
wire _xbar_auto_anon_out_1_a_valid; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_1_a_bits_opcode; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_1_a_bits_param; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_1_a_bits_size; // @[Xbar.scala:346:26]
wire [9:0] _xbar_auto_anon_out_1_a_bits_source; // @[Xbar.scala:346:26]
wire [20:0] _xbar_auto_anon_out_1_a_bits_address; // @[Xbar.scala:346:26]
wire [7:0] _xbar_auto_anon_out_1_a_bits_mask; // @[Xbar.scala:346:26]
wire [63:0] _xbar_auto_anon_out_1_a_bits_data; // @[Xbar.scala:346:26]
wire _xbar_auto_anon_out_1_a_bits_corrupt; // @[Xbar.scala:346:26]
wire _xbar_auto_anon_out_1_d_ready; // @[Xbar.scala:346:26]
wire _xbar_auto_anon_out_0_a_valid; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_0_a_bits_opcode; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_0_a_bits_param; // @[Xbar.scala:346:26]
wire [2:0] _xbar_auto_anon_out_0_a_bits_size; // @[Xbar.scala:346:26]
wire [9:0] _xbar_auto_anon_out_0_a_bits_source; // @[Xbar.scala:346:26]
wire [20:0] _xbar_auto_anon_out_0_a_bits_address; // @[Xbar.scala:346:26]
wire [7:0] _xbar_auto_anon_out_0_a_bits_mask; // @[Xbar.scala:346:26]
wire [63:0] _xbar_auto_anon_out_0_a_bits_data; // @[Xbar.scala:346:26]
wire _xbar_auto_anon_out_0_a_bits_corrupt; // @[Xbar.scala:346:26]
wire _xbar_auto_anon_out_0_d_ready; // @[Xbar.scala:346:26]
wire auto_reset_setter_clock_in_member_allClocks_uncore_clock_0 = auto_reset_setter_clock_in_member_allClocks_uncore_clock; // @[ClockDomain.scala:14:9]
wire auto_reset_setter_clock_in_member_allClocks_uncore_reset_0 = auto_reset_setter_clock_in_member_allClocks_uncore_reset; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_valid_0 = auto_xbar_anon_in_a_valid; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_opcode_0 = auto_xbar_anon_in_a_bits_opcode; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_param_0 = auto_xbar_anon_in_a_bits_param; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_a_bits_size_0 = auto_xbar_anon_in_a_bits_size; // @[ClockDomain.scala:14:9]
wire [9:0] auto_xbar_anon_in_a_bits_source_0 = auto_xbar_anon_in_a_bits_source; // @[ClockDomain.scala:14:9]
wire [20:0] auto_xbar_anon_in_a_bits_address_0 = auto_xbar_anon_in_a_bits_address; // @[ClockDomain.scala:14:9]
wire [7:0] auto_xbar_anon_in_a_bits_mask_0 = auto_xbar_anon_in_a_bits_mask; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_a_bits_data_0 = auto_xbar_anon_in_a_bits_data; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_bits_corrupt_0 = auto_xbar_anon_in_a_bits_corrupt; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_ready_0 = auto_xbar_anon_in_d_ready; // @[ClockDomain.scala:14:9]
wire auto_clock_in_clock_0 = auto_clock_in_clock; // @[ClockDomain.scala:14:9]
wire auto_clock_in_reset_0 = auto_clock_in_reset; // @[ClockDomain.scala:14:9]
wire [1:0] auto_xbar_anon_in_d_bits_param = 2'h0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_sink = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_denied = 1'h0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_bits_corrupt = 1'h0; // @[ClockDomain.scala:14:9]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire clockNodeIn_clock = auto_clock_in_clock_0; // @[ClockDomain.scala:14:9]
wire clockNodeIn_reset = auto_clock_in_reset_0; // @[ClockDomain.scala:14:9]
wire auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9]
wire auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
wire [2:0] auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
wire [9:0] auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
wire [63:0] auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
wire auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
wire childClock; // @[LazyModuleImp.scala:155:31]
wire childReset; // @[LazyModuleImp.scala:158:31]
assign childClock = clockNodeIn_clock; // @[MixedNode.scala:551:17]
assign childReset = clockNodeIn_reset; // @[MixedNode.scala:551:17]
TLXbar_prcibus_i1_o2_a21d64s10k1z3u xbar ( // @[Xbar.scala:346:26]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (auto_xbar_anon_in_a_ready_0),
.auto_anon_in_a_valid (auto_xbar_anon_in_a_valid_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_opcode (auto_xbar_anon_in_a_bits_opcode_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_param (auto_xbar_anon_in_a_bits_param_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_size (auto_xbar_anon_in_a_bits_size_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_source (auto_xbar_anon_in_a_bits_source_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_address (auto_xbar_anon_in_a_bits_address_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_mask (auto_xbar_anon_in_a_bits_mask_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_data (auto_xbar_anon_in_a_bits_data_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_a_bits_corrupt (auto_xbar_anon_in_a_bits_corrupt_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_d_ready (auto_xbar_anon_in_d_ready_0), // @[ClockDomain.scala:14:9]
.auto_anon_in_d_valid (auto_xbar_anon_in_d_valid_0),
.auto_anon_in_d_bits_opcode (auto_xbar_anon_in_d_bits_opcode_0),
.auto_anon_in_d_bits_size (auto_xbar_anon_in_d_bits_size_0),
.auto_anon_in_d_bits_source (auto_xbar_anon_in_d_bits_source_0),
.auto_anon_in_d_bits_data (auto_xbar_anon_in_d_bits_data_0),
.auto_anon_out_1_a_ready (_fragmenter_1_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34]
.auto_anon_out_1_a_valid (_xbar_auto_anon_out_1_a_valid),
.auto_anon_out_1_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode),
.auto_anon_out_1_a_bits_param (_xbar_auto_anon_out_1_a_bits_param),
.auto_anon_out_1_a_bits_size (_xbar_auto_anon_out_1_a_bits_size),
.auto_anon_out_1_a_bits_source (_xbar_auto_anon_out_1_a_bits_source),
.auto_anon_out_1_a_bits_address (_xbar_auto_anon_out_1_a_bits_address),
.auto_anon_out_1_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask),
.auto_anon_out_1_a_bits_data (_xbar_auto_anon_out_1_a_bits_data),
.auto_anon_out_1_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt),
.auto_anon_out_1_d_ready (_xbar_auto_anon_out_1_d_ready),
.auto_anon_out_1_d_valid (_fragmenter_1_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34]
.auto_anon_out_1_d_bits_opcode (_fragmenter_1_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_anon_out_1_d_bits_size (_fragmenter_1_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34]
.auto_anon_out_1_d_bits_source (_fragmenter_1_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_a_ready (_fragmenter_auto_anon_in_a_ready), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_a_valid (_xbar_auto_anon_out_0_a_valid),
.auto_anon_out_0_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode),
.auto_anon_out_0_a_bits_param (_xbar_auto_anon_out_0_a_bits_param),
.auto_anon_out_0_a_bits_size (_xbar_auto_anon_out_0_a_bits_size),
.auto_anon_out_0_a_bits_source (_xbar_auto_anon_out_0_a_bits_source),
.auto_anon_out_0_a_bits_address (_xbar_auto_anon_out_0_a_bits_address),
.auto_anon_out_0_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask),
.auto_anon_out_0_a_bits_data (_xbar_auto_anon_out_0_a_bits_data),
.auto_anon_out_0_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt),
.auto_anon_out_0_d_ready (_xbar_auto_anon_out_0_d_ready),
.auto_anon_out_0_d_valid (_fragmenter_auto_anon_in_d_valid), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_d_bits_size (_fragmenter_auto_anon_in_d_bits_size), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_d_bits_source (_fragmenter_auto_anon_in_d_bits_source), // @[Fragmenter.scala:345:34]
.auto_anon_out_0_d_bits_data (_fragmenter_auto_anon_in_d_bits_data) // @[Fragmenter.scala:345:34]
); // @[Xbar.scala:346:26]
ClockGroupResetSynchronizer resetSynchronizer ( // @[ResetSynchronizer.scala:46:69]
.auto_in_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:73:33]
.auto_in_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:73:33]
.auto_out_member_allClocks_uncore_clock (auto_resetSynchronizer_out_member_allClocks_uncore_clock_0),
.auto_out_member_allClocks_uncore_reset (auto_resetSynchronizer_out_member_allClocks_uncore_reset_0)
); // @[ResetSynchronizer.scala:46:69]
TileClockGater clock_gater ( // @[HasChipyardPRCI.scala:73:33]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_clock_gater_in_1_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready),
.auto_clock_gater_in_1_a_valid (_fragmenter_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_param (_fragmenter_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_size (_fragmenter_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_source (_fragmenter_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_address (_fragmenter_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_data (_fragmenter_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_d_ready (_fragmenter_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34]
.auto_clock_gater_in_1_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid),
.auto_clock_gater_in_1_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode),
.auto_clock_gater_in_1_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size),
.auto_clock_gater_in_1_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source),
.auto_clock_gater_in_1_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data),
.auto_clock_gater_in_0_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock), // @[HasChipyardPRCI.scala:78:34]
.auto_clock_gater_in_0_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset), // @[HasChipyardPRCI.scala:78:34]
.auto_clock_gater_out_member_allClocks_uncore_clock (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_clock),
.auto_clock_gater_out_member_allClocks_uncore_reset (_clock_gater_auto_clock_gater_out_member_allClocks_uncore_reset)
); // @[HasChipyardPRCI.scala:73:33]
TLFragmenter_TileClockGater fragmenter ( // @[Fragmenter.scala:345:34]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (_fragmenter_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_xbar_auto_anon_out_0_a_valid), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_0_a_bits_opcode), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_param (_xbar_auto_anon_out_0_a_bits_param), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_size (_xbar_auto_anon_out_0_a_bits_size), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_source (_xbar_auto_anon_out_0_a_bits_source), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_address (_xbar_auto_anon_out_0_a_bits_address), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_mask (_xbar_auto_anon_out_0_a_bits_mask), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_data (_xbar_auto_anon_out_0_a_bits_data), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_0_a_bits_corrupt), // @[Xbar.scala:346:26]
.auto_anon_in_d_ready (_xbar_auto_anon_out_0_d_ready), // @[Xbar.scala:346:26]
.auto_anon_in_d_valid (_fragmenter_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fragmenter_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_size (_fragmenter_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_fragmenter_auto_anon_in_d_bits_source),
.auto_anon_in_d_bits_data (_fragmenter_auto_anon_in_d_bits_data),
.auto_anon_out_a_ready (_clock_gater_auto_clock_gater_in_1_a_ready), // @[HasChipyardPRCI.scala:73:33]
.auto_anon_out_a_valid (_fragmenter_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fragmenter_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_fragmenter_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_fragmenter_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_fragmenter_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_fragmenter_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_fragmenter_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fragmenter_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_fragmenter_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_fragmenter_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_clock_gater_auto_clock_gater_in_1_d_valid), // @[HasChipyardPRCI.scala:73:33]
.auto_anon_out_d_bits_opcode (_clock_gater_auto_clock_gater_in_1_d_bits_opcode), // @[HasChipyardPRCI.scala:73:33]
.auto_anon_out_d_bits_size (_clock_gater_auto_clock_gater_in_1_d_bits_size), // @[HasChipyardPRCI.scala:73:33]
.auto_anon_out_d_bits_source (_clock_gater_auto_clock_gater_in_1_d_bits_source), // @[HasChipyardPRCI.scala:73:33]
.auto_anon_out_d_bits_data (_clock_gater_auto_clock_gater_in_1_d_bits_data) // @[HasChipyardPRCI.scala:73:33]
); // @[Fragmenter.scala:345:34]
TileResetSetter reset_setter ( // @[HasChipyardPRCI.scala:78:34]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_clock_in_member_allClocks_uncore_clock (auto_reset_setter_clock_in_member_allClocks_uncore_clock_0), // @[ClockDomain.scala:14:9]
.auto_clock_in_member_allClocks_uncore_reset (auto_reset_setter_clock_in_member_allClocks_uncore_reset_0), // @[ClockDomain.scala:14:9]
.auto_clock_out_member_allClocks_uncore_clock (_reset_setter_auto_clock_out_member_allClocks_uncore_clock),
.auto_clock_out_member_allClocks_uncore_reset (_reset_setter_auto_clock_out_member_allClocks_uncore_reset),
.auto_tl_in_a_ready (_reset_setter_auto_tl_in_a_ready),
.auto_tl_in_a_valid (_fragmenter_1_auto_anon_out_a_valid), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data), // @[Fragmenter.scala:345:34]
.auto_tl_in_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt), // @[Fragmenter.scala:345:34]
.auto_tl_in_d_ready (_fragmenter_1_auto_anon_out_d_ready), // @[Fragmenter.scala:345:34]
.auto_tl_in_d_valid (_reset_setter_auto_tl_in_d_valid),
.auto_tl_in_d_bits_opcode (_reset_setter_auto_tl_in_d_bits_opcode),
.auto_tl_in_d_bits_size (_reset_setter_auto_tl_in_d_bits_size),
.auto_tl_in_d_bits_source (_reset_setter_auto_tl_in_d_bits_source)
); // @[HasChipyardPRCI.scala:78:34]
TLFragmenter_TileResetSetter fragmenter_1 ( // @[Fragmenter.scala:345:34]
.clock (childClock), // @[LazyModuleImp.scala:155:31]
.reset (childReset), // @[LazyModuleImp.scala:158:31]
.auto_anon_in_a_ready (_fragmenter_1_auto_anon_in_a_ready),
.auto_anon_in_a_valid (_xbar_auto_anon_out_1_a_valid), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_opcode (_xbar_auto_anon_out_1_a_bits_opcode), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_param (_xbar_auto_anon_out_1_a_bits_param), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_size (_xbar_auto_anon_out_1_a_bits_size), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_source (_xbar_auto_anon_out_1_a_bits_source), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_address (_xbar_auto_anon_out_1_a_bits_address), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_mask (_xbar_auto_anon_out_1_a_bits_mask), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_data (_xbar_auto_anon_out_1_a_bits_data), // @[Xbar.scala:346:26]
.auto_anon_in_a_bits_corrupt (_xbar_auto_anon_out_1_a_bits_corrupt), // @[Xbar.scala:346:26]
.auto_anon_in_d_ready (_xbar_auto_anon_out_1_d_ready), // @[Xbar.scala:346:26]
.auto_anon_in_d_valid (_fragmenter_1_auto_anon_in_d_valid),
.auto_anon_in_d_bits_opcode (_fragmenter_1_auto_anon_in_d_bits_opcode),
.auto_anon_in_d_bits_size (_fragmenter_1_auto_anon_in_d_bits_size),
.auto_anon_in_d_bits_source (_fragmenter_1_auto_anon_in_d_bits_source),
.auto_anon_out_a_ready (_reset_setter_auto_tl_in_a_ready), // @[HasChipyardPRCI.scala:78:34]
.auto_anon_out_a_valid (_fragmenter_1_auto_anon_out_a_valid),
.auto_anon_out_a_bits_opcode (_fragmenter_1_auto_anon_out_a_bits_opcode),
.auto_anon_out_a_bits_param (_fragmenter_1_auto_anon_out_a_bits_param),
.auto_anon_out_a_bits_size (_fragmenter_1_auto_anon_out_a_bits_size),
.auto_anon_out_a_bits_source (_fragmenter_1_auto_anon_out_a_bits_source),
.auto_anon_out_a_bits_address (_fragmenter_1_auto_anon_out_a_bits_address),
.auto_anon_out_a_bits_mask (_fragmenter_1_auto_anon_out_a_bits_mask),
.auto_anon_out_a_bits_data (_fragmenter_1_auto_anon_out_a_bits_data),
.auto_anon_out_a_bits_corrupt (_fragmenter_1_auto_anon_out_a_bits_corrupt),
.auto_anon_out_d_ready (_fragmenter_1_auto_anon_out_d_ready),
.auto_anon_out_d_valid (_reset_setter_auto_tl_in_d_valid), // @[HasChipyardPRCI.scala:78:34]
.auto_anon_out_d_bits_opcode (_reset_setter_auto_tl_in_d_bits_opcode), // @[HasChipyardPRCI.scala:78:34]
.auto_anon_out_d_bits_size (_reset_setter_auto_tl_in_d_bits_size), // @[HasChipyardPRCI.scala:78:34]
.auto_anon_out_d_bits_source (_reset_setter_auto_tl_in_d_bits_source) // @[HasChipyardPRCI.scala:78:34]
); // @[Fragmenter.scala:345:34]
assign auto_resetSynchronizer_out_member_allClocks_uncore_clock = auto_resetSynchronizer_out_member_allClocks_uncore_clock_0; // @[ClockDomain.scala:14:9]
assign auto_resetSynchronizer_out_member_allClocks_uncore_reset = auto_resetSynchronizer_out_member_allClocks_uncore_reset_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_a_ready = auto_xbar_anon_in_a_ready_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_valid = auto_xbar_anon_in_d_valid_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_opcode = auto_xbar_anon_in_d_bits_opcode_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_size = auto_xbar_anon_in_d_bits_size_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_source = auto_xbar_anon_in_d_bits_source_0; // @[ClockDomain.scala:14:9]
assign auto_xbar_anon_in_d_bits_data = auto_xbar_anon_in_d_bits_data_0; // @[ClockDomain.scala:14:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_361( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File PE.scala:
// See README.md for license details.
package gemmini
import chisel3._
import chisel3.util._
class PEControl[T <: Data : Arithmetic](accType: T) extends Bundle {
val dataflow = UInt(1.W) // TODO make this an Enum
val propagate = UInt(1.W) // Which register should be propagated (and which should be accumulated)?
val shift = UInt(log2Up(accType.getWidth).W) // TODO this isn't correct for Floats
}
class MacUnit[T <: Data](inputType: T, cType: T, dType: T) (implicit ev: Arithmetic[T]) extends Module {
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(inputType)
val in_c = Input(cType)
val out_d = Output(dType)
})
io.out_d := io.in_c.mac(io.in_a, io.in_b)
}
// TODO update documentation
/**
* A PE implementing a MAC operation. Configured as fully combinational when integrated into a Mesh.
* @param width Data width of operands
*/
class PE[T <: Data](inputType: T, outputType: T, accType: T, df: Dataflow.Value, max_simultaneous_matmuls: Int)
(implicit ev: Arithmetic[T]) extends Module { // Debugging variables
import ev._
val io = IO(new Bundle {
val in_a = Input(inputType)
val in_b = Input(outputType)
val in_d = Input(outputType)
val out_a = Output(inputType)
val out_b = Output(outputType)
val out_c = Output(outputType)
val in_control = Input(new PEControl(accType))
val out_control = Output(new PEControl(accType))
val in_id = Input(UInt(log2Up(max_simultaneous_matmuls).W))
val out_id = Output(UInt(log2Up(max_simultaneous_matmuls).W))
val in_last = Input(Bool())
val out_last = Output(Bool())
val in_valid = Input(Bool())
val out_valid = Output(Bool())
val bad_dataflow = Output(Bool())
})
val cType = if (df == Dataflow.WS) inputType else accType
// When creating PEs that support multiple dataflows, the
// elaboration/synthesis tools often fail to consolidate and de-duplicate
// MAC units. To force mac circuitry to be re-used, we create a "mac_unit"
// module here which just performs a single MAC operation
val mac_unit = Module(new MacUnit(inputType,
if (df == Dataflow.WS) outputType else accType, outputType))
val a = io.in_a
val b = io.in_b
val d = io.in_d
val c1 = Reg(cType)
val c2 = Reg(cType)
val dataflow = io.in_control.dataflow
val prop = io.in_control.propagate
val shift = io.in_control.shift
val id = io.in_id
val last = io.in_last
val valid = io.in_valid
io.out_a := a
io.out_control.dataflow := dataflow
io.out_control.propagate := prop
io.out_control.shift := shift
io.out_id := id
io.out_last := last
io.out_valid := valid
mac_unit.io.in_a := a
val last_s = RegEnable(prop, valid)
val flip = last_s =/= prop
val shift_offset = Mux(flip, shift, 0.U)
// Which dataflow are we using?
val OUTPUT_STATIONARY = Dataflow.OS.id.U(1.W)
val WEIGHT_STATIONARY = Dataflow.WS.id.U(1.W)
// Is c1 being computed on, or propagated forward (in the output-stationary dataflow)?
val COMPUTE = 0.U(1.W)
val PROPAGATE = 1.U(1.W)
io.bad_dataflow := false.B
when ((df == Dataflow.OS).B || ((df == Dataflow.BOTH).B && dataflow === OUTPUT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := (c1 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
c2 := mac_unit.io.out_d
c1 := d.withWidthOf(cType)
}.otherwise {
io.out_c := (c2 >> shift_offset).clippedToWidthOf(outputType)
io.out_b := b
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c1
c1 := mac_unit.io.out_d
c2 := d.withWidthOf(cType)
}
}.elsewhen ((df == Dataflow.WS).B || ((df == Dataflow.BOTH).B && dataflow === WEIGHT_STATIONARY)) {
when(prop === PROPAGATE) {
io.out_c := c1
mac_unit.io.in_b := c2.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c1 := d
}.otherwise {
io.out_c := c2
mac_unit.io.in_b := c1.asTypeOf(inputType)
mac_unit.io.in_c := b
io.out_b := mac_unit.io.out_d
c2 := d
}
}.otherwise {
io.bad_dataflow := true.B
//assert(false.B, "unknown dataflow")
io.out_c := DontCare
io.out_b := DontCare
mac_unit.io.in_b := b.asTypeOf(inputType)
mac_unit.io.in_c := c2
}
when (!valid) {
c1 := c1
c2 := c2
mac_unit.io.in_b := DontCare
mac_unit.io.in_c := DontCare
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
|
module PE_438( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_182 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File TLChannelCompactor.scala:
package testchipip.serdes
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
trait TLFieldHelper {
def getBodyFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleB => Seq(b.mask, b.data, b.corrupt)
case b: TLBundleC => Seq( b.data, b.corrupt)
case b: TLBundleD => Seq( b.data, b.corrupt)
case b: TLBundleE => Seq()
}
def getConstFields(b: TLChannel): Seq[Data] = b match {
case b: TLBundleA => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleB => Seq(b.opcode, b.param, b.size, b.source, b.address )
case b: TLBundleC => Seq(b.opcode, b.param, b.size, b.source, b.address, b.user, b.echo )
case b: TLBundleD => Seq(b.opcode, b.param, b.size, b.source, b.user, b.echo, b.sink, b.denied)
case b: TLBundleE => Seq( b.sink )
}
def minTLPayloadWidth(b: TLChannel): Int = Seq(getBodyFields(b), getConstFields(b)).map(_.map(_.getWidth).sum).max
def minTLPayloadWidth(bs: Seq[TLChannel]): Int = bs.map(b => minTLPayloadWidth(b)).max
def minTLPayloadWidth(b: TLBundle): Int = minTLPayloadWidth(Seq(b.a, b.b, b.c, b.d, b.e).map(_.bits))
}
class TLBeat(val beatWidth: Int) extends Bundle {
val payload = UInt(beatWidth.W)
val head = Bool()
val tail = Bool()
}
abstract class TLChannelToBeat[T <: TLChannel](gen: => T, edge: TLEdge, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Flipped(Decoupled(gen))
val beat = Decoupled(new TLBeat(beatWidth))
})
def unique(x: Vector[Boolean]): Bool = (x.filter(x=>x).size <= 1).B
// convert decoupled to irrevocable
val q = Module(new Queue(gen, 1, pipe=true, flow=true))
q.io.enq <> io.protocol
val protocol = q.io.deq
val has_body = Wire(Bool())
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val head = edge.first(protocol.bits, protocol.fire)
val tail = edge.last(protocol.bits, protocol.fire)
val body = Cat( body_fields.filter(_.getWidth > 0).map(_.asUInt))
val const = Cat(const_fields.filter(_.getWidth > 0).map(_.asUInt))
val is_body = RegInit(false.B)
io.beat.valid := protocol.valid
protocol.ready := io.beat.ready && (is_body || !has_body)
io.beat.bits.head := head && !is_body
io.beat.bits.tail := tail && (is_body || !has_body)
io.beat.bits.payload := Mux(is_body, body, const)
when (io.beat.fire && io.beat.bits.head) { is_body := true.B }
when (io.beat.fire && io.beat.bits.tail) { is_body := false.B }
}
abstract class TLChannelFromBeat[T <: TLChannel](gen: => T, nameSuffix: Option[String])(implicit val p: Parameters) extends Module with TLFieldHelper {
override def desiredName = (Seq(this.getClass.getSimpleName) ++ nameSuffix ++ Seq(gen.params.shortName)).mkString("_")
val beatWidth = minTLPayloadWidth(gen)
val io = IO(new Bundle {
val protocol = Decoupled(gen)
val beat = Flipped(Decoupled(new TLBeat(beatWidth)))
})
// Handle size = 1 gracefully (Chisel3 empty range is broken)
def trim(id: UInt, size: Int): UInt = if (size <= 1) 0.U else id(log2Ceil(size)-1, 0)
val protocol = Wire(Decoupled(gen))
io.protocol <> protocol
val body_fields = getBodyFields(protocol.bits)
val const_fields = getConstFields(protocol.bits)
val is_const = RegInit(true.B)
val const_reg = Reg(UInt(const_fields.map(_.getWidth).sum.W))
val const = Mux(io.beat.bits.head, io.beat.bits.payload, const_reg)
io.beat.ready := (is_const && !io.beat.bits.tail) || protocol.ready
protocol.valid := (!is_const || io.beat.bits.tail) && io.beat.valid
def assign(i: UInt, sigs: Seq[Data]) = {
var t = i
for (s <- sigs.reverse) {
s := t.asTypeOf(s.cloneType)
t = t >> s.getWidth
}
}
assign(const, const_fields)
assign(io.beat.bits.payload, body_fields)
when (io.beat.fire && io.beat.bits.head) { is_const := false.B; const_reg := io.beat.bits.payload }
when (io.beat.fire && io.beat.bits.tail) { is_const := true.B }
}
class TLAToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleA(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLAFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleA(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLBToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleB(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits) || (~protocol.bits.mask =/= 0.U)
}
class TLBFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleB(bundle), nameSuffix)(p) {
when (io.beat.bits.head) { io.protocol.bits.mask := ~(0.U(io.protocol.bits.mask.getWidth.W)) }
}
class TLCToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleC(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLCFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleC(bundle), nameSuffix)(p)
class TLDToBeat(edgeOut: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleD(bundle), edgeOut, nameSuffix)(p) {
has_body := edgeOut.hasData(protocol.bits)
}
class TLDFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleD(bundle), nameSuffix)(p)
class TLEToBeat(edgeIn: TLEdge, bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelToBeat(new TLBundleE(bundle), edgeIn, nameSuffix)(p) {
has_body := edgeIn.hasData(protocol.bits)
}
class TLEFromBeat(bundle: TLBundleParameters, nameSuffix: Option[String])(implicit p: Parameters) extends TLChannelFromBeat(new TLBundleE(bundle), nameSuffix)(p)
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLBToBeat_serial_tl_0_a64d64s8k8z8c( // @[TLChannelCompactor.scala:116:7]
input clock, // @[TLChannelCompactor.scala:116:7]
input reset, // @[TLChannelCompactor.scala:116:7]
input io_beat_ready, // @[TLChannelCompactor.scala:40:14]
output io_beat_bits_head, // @[TLChannelCompactor.scala:40:14]
output io_beat_bits_tail // @[TLChannelCompactor.scala:40:14]
);
wire io_beat_ready_0 = io_beat_ready; // @[TLChannelCompactor.scala:116:7]
wire [63:0] io_protocol_bits_address = 64'h0; // @[TLChannelCompactor.scala:40:14, :47:17, :116:7]
wire [63:0] io_protocol_bits_data = 64'h0; // @[TLChannelCompactor.scala:40:14, :47:17, :116:7]
wire [7:0] io_protocol_bits_size = 8'h0; // @[TLChannelCompactor.scala:40:14, :47:17, :116:7]
wire [7:0] io_protocol_bits_source = 8'h0; // @[TLChannelCompactor.scala:40:14, :47:17, :116:7]
wire [7:0] io_protocol_bits_mask = 8'h0; // @[TLChannelCompactor.scala:40:14, :47:17, :116:7]
wire [1:0] io_protocol_bits_param = 2'h0; // @[TLChannelCompactor.scala:40:14, :47:17, :116:7]
wire [2:0] io_protocol_bits_opcode = 3'h0; // @[TLChannelCompactor.scala:40:14, :47:17, :116:7]
wire [266:0] _head_beats1_decode_T = 267'hFFF; // @[package.scala:243:71]
wire [266:0] _tail_beats1_decode_T = 267'hFFF; // @[package.scala:243:71]
wire [11:0] _head_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _tail_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _head_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _tail_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [8:0] head_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] head_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] head_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] tail_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] tail_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] tail_count = 9'h0; // @[Edges.scala:234:25]
wire [72:0] body = 73'h0; // @[TLChannelCompactor.scala:57:18]
wire [71:0] body_hi = 72'h0; // @[TLChannelCompactor.scala:57:18, :58:18]
wire [71:0] const_lo = 72'h0; // @[TLChannelCompactor.scala:57:18, :58:18]
wire [4:0] const_hi_hi = 5'h0; // @[TLChannelCompactor.scala:58:18]
wire [12:0] const_hi = 13'h0; // @[TLChannelCompactor.scala:58:18]
wire [7:0] _has_body_T = 8'hFF; // @[TLChannelCompactor.scala:117:50]
wire [84:0] io_beat_bits_payload = 85'h0; // @[TLChannelCompactor.scala:40:14, :58:18, :66:33, :116:7]
wire [84:0] const_0 = 85'h0; // @[TLChannelCompactor.scala:40:14, :58:18, :66:33, :116:7]
wire [84:0] _io_beat_bits_payload_T = 85'h0; // @[TLChannelCompactor.scala:40:14, :58:18, :66:33, :116:7]
wire io_protocol_valid = 1'h0; // @[TLChannelCompactor.scala:116:7]
wire io_protocol_bits_corrupt = 1'h0; // @[TLChannelCompactor.scala:116:7]
wire io_beat_valid = 1'h0; // @[TLChannelCompactor.scala:116:7]
wire _head_T = 1'h0; // @[Decoupled.scala:51:35]
wire _head_beats1_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire head_done = 1'h0; // @[Edges.scala:233:22]
wire _tail_T = 1'h0; // @[Decoupled.scala:51:35]
wire _tail_beats1_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire tail_done = 1'h0; // @[Edges.scala:233:22]
wire _q_io_deq_ready_T = 1'h0; // @[TLChannelCompactor.scala:62:50]
wire _io_beat_bits_tail_T = 1'h0; // @[TLChannelCompactor.scala:65:50]
wire _has_body_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire io_protocol_ready = 1'h1; // @[TLChannelCompactor.scala:116:7]
wire has_body = 1'h1; // @[TLChannelCompactor.scala:51:22]
wire head_beats1_opdata = 1'h1; // @[Edges.scala:97:28]
wire _head_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire head_last = 1'h1; // @[Edges.scala:232:33]
wire tail_beats1_opdata = 1'h1; // @[Edges.scala:97:28]
wire _tail_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire tail = 1'h1; // @[Edges.scala:232:33]
wire has_body_opdata = 1'h1; // @[Edges.scala:97:28]
wire _has_body_T_1 = 1'h1; // @[TLChannelCompactor.scala:117:70]
wire _has_body_T_2 = 1'h1; // @[TLChannelCompactor.scala:117:46]
wire _io_beat_bits_head_T_1; // @[TLChannelCompactor.scala:64:35]
wire _io_beat_bits_tail_T_2; // @[TLChannelCompactor.scala:65:35]
wire io_beat_bits_head_0; // @[TLChannelCompactor.scala:116:7]
wire io_beat_bits_tail_0; // @[TLChannelCompactor.scala:116:7]
reg [8:0] head_counter; // @[Edges.scala:229:27]
wire [9:0] _head_counter1_T = {1'h0, head_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] head_counter1 = _head_counter1_T[8:0]; // @[Edges.scala:230:28]
wire head = head_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _head_last_T = head_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _head_count_T = ~head_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _head_counter_T = head ? 9'h0 : head_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [8:0] tail_counter; // @[Edges.scala:229:27]
wire [9:0] _tail_counter1_T = {1'h0, tail_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] tail_counter1 = _tail_counter1_T[8:0]; // @[Edges.scala:230:28]
wire tail_first = tail_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _tail_last_T = tail_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire [8:0] _tail_count_T = ~tail_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] _tail_counter_T = tail_first ? 9'h0 : tail_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg is_body; // @[TLChannelCompactor.scala:60:24]
wire _q_io_deq_ready_T_1 = is_body; // @[TLChannelCompactor.scala:60:24, :62:47]
wire _io_beat_bits_tail_T_1 = is_body; // @[TLChannelCompactor.scala:60:24, :65:47]
wire _q_io_deq_ready_T_2 = io_beat_ready_0 & _q_io_deq_ready_T_1; // @[TLChannelCompactor.scala:62:{35,47}, :116:7]
wire _io_beat_bits_head_T = ~is_body; // @[TLChannelCompactor.scala:60:24, :64:38]
assign _io_beat_bits_head_T_1 = head & _io_beat_bits_head_T; // @[TLChannelCompactor.scala:64:{35,38}]
assign io_beat_bits_head_0 = _io_beat_bits_head_T_1; // @[TLChannelCompactor.scala:64:35, :116:7]
assign _io_beat_bits_tail_T_2 = _io_beat_bits_tail_T_1; // @[TLChannelCompactor.scala:65:{35,47}]
assign io_beat_bits_tail_0 = _io_beat_bits_tail_T_2; // @[TLChannelCompactor.scala:65:35, :116:7]
always @(posedge clock) begin // @[TLChannelCompactor.scala:116:7]
if (reset) begin // @[TLChannelCompactor.scala:116:7]
head_counter <= 9'h0; // @[Edges.scala:229:27]
tail_counter <= 9'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TLChannelCompactor.scala:60:24]
end
always @(posedge)
Queue1_TLBundleB_a64d64s8k8z8c q ( // @[TLChannelCompactor.scala:47:17]
.clock (clock),
.reset (reset),
.io_deq_ready (_q_io_deq_ready_T_2) // @[TLChannelCompactor.scala:62:35]
); // @[TLChannelCompactor.scala:47:17]
assign io_beat_bits_head = io_beat_bits_head_0; // @[TLChannelCompactor.scala:116:7]
assign io_beat_bits_tail = io_beat_bits_tail_0; // @[TLChannelCompactor.scala:116:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_66( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_83 io_out_sink_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_77( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] c_sizes_set = 32'h0; // @[Monitor.scala:741:34]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_source = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_source = 2'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_set = 4'h0; // @[Monitor.scala:738:34]
wire [3:0] c_set_wo_ready = 4'h0; // @[Monitor.scala:739:34]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [35:0] _c_sizes_set_T_1 = 36'h0; // @[Monitor.scala:768:52]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_T = 5'h0; // @[Monitor.scala:767:79]
wire [4:0] _c_sizes_set_T = 5'h0; // @[Monitor.scala:768:77]
wire [34:0] _c_opcodes_set_T_1 = 35'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_set_wo_ready_T = 4'h1; // @[OneHot.scala:58:35]
wire [3:0] _c_set_T = 4'h1; // @[OneHot.scala:58:35]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [15:0] c_opcodes_set = 16'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [1:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [1:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [1:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [3:0] inflight; // @[Monitor.scala:614:27]
reg [15:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [31:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] a_set; // @[Monitor.scala:626:34]
wire [3:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [15:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [31:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [4:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [4:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [4:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [4:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [4:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [15:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [15:0] _a_opcode_lookup_T_6 = _a_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [4:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [4:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [4:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [4:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [31:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [31:0] _a_size_lookup_T_6 = {24'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [31:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[31:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [3:0] _GEN_3 = {2'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [3:0] _GEN_4 = 4'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [3:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [3:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 4'h0; // @[OneHot.scala:58:35]
wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1183 ? _a_set_T : 4'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [4:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [34:0] _a_opcodes_set_T_1 = {31'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[15:0] : 16'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [4:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [35:0] _a_sizes_set_T_1 = {31'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[31:0] : 32'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [3:0] d_clr; // @[Monitor.scala:664:34]
wire [3:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [15:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [31:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [3:0] _GEN_6 = {2'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [3:0] _GEN_7 = 4'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [3:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 4'h0; // @[OneHot.scala:58:35]
wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1198 ? _d_clr_T : 4'h0; // @[OneHot.scala:58:35]
wire [46:0] _d_opcodes_clr_T_5 = 47'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[15:0] : 16'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [46:0] _d_sizes_clr_T_5 = 47'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[31:0] : 32'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [3:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [3:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [3:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [15:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [15:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [15:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [31:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [31:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [31:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [3:0] inflight_1; // @[Monitor.scala:726:35]
wire [3:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [15:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [15:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [31:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [31:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [15:0] _c_opcode_lookup_T_6 = _c_opcode_lookup_T_1 & 16'hF; // @[Monitor.scala:749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [31:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [31:0] _c_size_lookup_T_6 = {24'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [31:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[31:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [3:0] d_clr_1; // @[Monitor.scala:774:34]
wire [3:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [15:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [31:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 4'h0; // @[OneHot.scala:58:35]
wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 4'h0; // @[OneHot.scala:58:35]
wire [46:0] _d_opcodes_clr_T_11 = 47'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[15:0] : 16'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [46:0] _d_sizes_clr_T_11 = 47'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[31:0] : 32'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 2'h0; // @[Monitor.scala:36:7, :795:113]
wire [3:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [3:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [15:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [15:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [31:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [31:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File Mem.scala:
package saturn.mem
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import saturn.common._
class LSIQEntry(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val op = new VectorMemMacroOp
def bound_all = op.mop =/= mopUnit
val bound_offset = UInt(pgIdxBits.W)
val ld_dep_mask = Vec(vParams.vliqEntries, Bool())
val st_dep_mask = Vec(vParams.vsiqEntries, Bool())
def containsBlock(addr: UInt) = {
val cl = addr(pgIdxBits-1,lgCacheBlockBytes)
val base_cl = op.base_offset >> lgCacheBlockBytes
val bound_cl = bound_offset >> lgCacheBlockBytes
(((addr >> pgIdxBits) === op.page) && (base_cl <= cl && bound_cl >= cl)) || bound_all
}
def overlaps(other: LSIQEntry) = {
(op.page === other.op.page) && (bound_all || other.bound_all || (
(op.base_offset <= other.bound_offset && bound_offset >= other.op.base_offset)
))
}
}
class IFQEntry(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val head = UInt(log2Ceil(dLenB).W)
val tail = UInt(log2Ceil(dLenB).W)
val masked = Bool()
val last = Bool()
val lsiq_id = UInt(lsiqIdBits.W)
val page_offset = UInt(pgIdxBits.W)
}
class MemRequest(bytes: Int, tagBits: Int)(implicit p: Parameters) extends CoreBundle()(p) {
val addr = UInt(coreMaxAddrBits.W)
val data = UInt((bytes*8).W)
val mask = UInt(bytes.W)
val tag = UInt(tagBits.W)
val store = Bool()
}
class MemResponse(bytes: Int, tagBits: Int)(implicit p: Parameters) extends CoreBundle()(p) {
val data = UInt((bytes*8).W)
val tag = UInt(tagBits.W)
}
class ScalarMemOrderCheckIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val addr = Input(UInt(coreMaxAddrBits.W))
val size = Input(UInt(2.W))
val store = Input(Bool())
val conflict = Output(Bool())
}
class VectorMemIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val load_req = Decoupled(new MemRequest(dLenB, dmemTagBits))
val load_resp = Input(Valid(new MemResponse(dLenB, dmemTagBits)))
val store_req = Decoupled(new MemRequest(dLenB, dmemTagBits))
val store_ack = Input(Valid(new MemResponse(dLenB, dmemTagBits)))
}
class VectorSGMemIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val req = Vec(vParams.vsgPorts, Decoupled(new MemRequest(1, sgmemTagBits)))
val resp = Vec(vParams.vsgPorts, Input(Valid(new MemResponse(1, sgmemTagBits))))
}
class VectorMemDatapathIO(implicit p: Parameters) extends CoreBundle()(p) with HasVectorParams {
val lresp = Decoupled(new Bundle {
val data = UInt(dLen.W)
val debug_id = UInt(debugIdSz.W)
})
val sdata = Flipped(Decoupled(new StoreDataMicroOp))
val mask_pop = Decoupled(new CompactorReq(dLenB))
val mask_data = Input(Vec(dLenB, Bool()))
val index_pop = Decoupled(new CompactorReq(dLenB))
val index_data = Input(Vec(dLenB, UInt(8.W)))
}
class VectorMemUnit(sgSize: Option[BigInt] = None)(implicit p: Parameters) extends CoreModule()(p) with HasVectorParams {
val io = IO(new Bundle {
val enq = Flipped(Decoupled(new VectorMemMacroOp))
val dmem = new VectorMemIO
val sgmem = sgSize.map(_ => new VectorSGMemIO)
val scalar_check = new ScalarMemOrderCheckIO
val vu = new VectorMemDatapathIO
val busy = Output(Bool())
})
def ptrIncr(u: UInt, sz: Int): Unit = {
val n = u +& 1.U
u := Mux(n === sz.U, 0.U, n)
}
val sgas = sgSize.map { size => Module(new ScatterGatherAddrGen(size)) }
val las = Module(new AddrGen)
val lifq = Module(new LoadOrderBuffer(vParams.vlifqEntries, vParams.vlrobEntries))
val lcu = Module(new Compactor(dLenB, dLenB, UInt(8.W), true))
val lss = Module(new LoadSegmenter)
val scu = Module(new Compactor(dLenB, dLenB, new MaskedByte, false))
val sss = Module(new StoreSegmenter)
val sas = Module(new AddrGen)
val sifq = Module(new DCEQueue(new IFQEntry, vParams.vsifqEntries))
val liq = Reg(Vec(vParams.vliqEntries, new LSIQEntry))
val liq_valids = RegInit(VecInit.fill(vParams.vliqEntries)(false.B))
val liq_las = RegInit(VecInit.fill(vParams.vliqEntries)(false.B))
val liq_enq_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W))
val liq_las_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W))
val liq_lss_ptr = RegInit(0.U(log2Ceil(vParams.vliqEntries).W))
val liq_enq_fire = Wire(Bool())
val liq_las_fire = Wire(Bool())
val liq_lss_fire = Wire(Bool())
val liq_enq_ready = !liq_valids(liq_enq_ptr)
val liq_las_valid = !liq_las(liq_las_ptr) && liq_valids(liq_las_ptr)
val liq_lss_valid = liq_valids(liq_lss_ptr)
val siq = Reg(Vec(vParams.vsiqEntries, new LSIQEntry))
val siq_valids = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B))
val siq_sss = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B))
val siq_sas = RegInit(VecInit.fill(vParams.vsiqEntries)(false.B))
val siq_enq_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W))
val siq_sss_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W))
val siq_sas_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W))
val siq_deq_ptr = RegInit(0.U(log2Ceil(vParams.vsiqEntries).W))
val siq_enq_fire = Wire(Bool())
val siq_sss_fire = Wire(Bool())
val siq_sas_fire = Wire(Bool())
val siq_deq_fire = Wire(Bool())
val siq_enq_ready = !siq_valids(siq_enq_ptr)
val siq_sss_valid = !siq_sss(siq_sss_ptr) && siq_valids(siq_sss_ptr)
val siq_sas_valid = !siq_sas(siq_sas_ptr) && siq_valids(siq_sas_ptr)
val enq_bound_max = (((io.enq.bits.nf +& 1.U) * io.enq.bits.vl) << io.enq.bits.elem_size) + io.enq.bits.base_offset - 1.U
val enq_bound = Mux((enq_bound_max >> pgIdxBits) =/= 0.U, ~(0.U(pgIdxBits.W)), enq_bound_max)
when (liq_enq_fire) {
liq(liq_enq_ptr).op := io.enq.bits
liq(liq_enq_ptr).bound_offset := enq_bound
liq(liq_enq_ptr).st_dep_mask := siq_valids
liq_las(liq_enq_ptr) := false.B
ptrIncr(liq_enq_ptr, vParams.vliqEntries)
liq_valids(liq_enq_ptr) := true.B
}
when (liq_las_fire) {
ptrIncr(liq_las_ptr, vParams.vliqEntries)
liq_las(liq_las_ptr) := true.B
}
when (liq_lss_fire) {
ptrIncr(liq_lss_ptr, vParams.vliqEntries)
liq_valids(liq_lss_ptr) := false.B
assert(liq_las(liq_lss_ptr) || (liq_lss_ptr === liq_las_ptr && liq_las_fire))
}
when (siq_enq_fire) {
siq(siq_enq_ptr).op := io.enq.bits
siq(siq_enq_ptr).bound_offset := enq_bound
siq(siq_enq_ptr).ld_dep_mask := liq_valids
siq_sss(siq_enq_ptr) := false.B
siq_sas(siq_enq_ptr) := false.B
ptrIncr(siq_enq_ptr, vParams.vsiqEntries)
siq_valids(siq_enq_ptr) := true.B
}
when (siq_sss_fire) {
ptrIncr(siq_sss_ptr, vParams.vsiqEntries)
siq_sss(siq_sss_ptr) := true.B
}
when (siq_sas_fire) {
ptrIncr(siq_sas_ptr, vParams.vsiqEntries)
siq_sas(siq_sas_ptr) := true.B
assert(siq_sss(siq_sas_ptr) || (siq_sss_fire && siq_sss_ptr === siq_sas_ptr))
}
when (siq_deq_fire) {
ptrIncr(siq_deq_ptr, vParams.vsiqEntries)
siq_valids(siq_deq_ptr) := false.B
assert(siq_sas(siq_deq_ptr) || (siq_sas_fire && siq_sas_ptr === siq_deq_ptr))
}
io.enq.ready := Mux(io.enq.bits.store, siq_enq_ready, liq_enq_ready)
liq_enq_fire := io.enq.valid && liq_enq_ready && !io.enq.bits.store
siq_enq_fire := io.enq.valid && siq_enq_ready && io.enq.bits.store
when (liq_lss_fire) { siq.foreach(_.ld_dep_mask(liq_lss_ptr) := false.B) }
when (siq_deq_fire) { liq.foreach(_.st_dep_mask(siq_deq_ptr) := false.B) }
val scalar_store_conflict = (0 until vParams.vsiqEntries).map { i =>
siq_valids(i) && (siq(i).containsBlock(io.scalar_check.addr) || !vParams.enableScalarVectorAddrDisambiguation.B)
}.orR
val scalar_load_conflict = (0 until vParams.vliqEntries).map { i =>
liq_valids(i) && (liq(i).containsBlock(io.scalar_check.addr) || !vParams.enableScalarVectorAddrDisambiguation.B)
}.orR
io.scalar_check.conflict := scalar_store_conflict || (scalar_load_conflict && io.scalar_check.store)
// Send indices/masks to las/sas
val las_older_than_sas = (liq_las_valid && !liq(liq_las_ptr).st_dep_mask(siq_sas_ptr)) || !siq_sas_valid
val maskindex_load = liq_las_valid && las_older_than_sas && !liq(liq_las_ptr).op.fast_sg
val maskindex_store = siq_sas_valid && !las_older_than_sas && !siq(siq_sas_ptr).op.fast_sg
val maskindex_gather = liq_las_valid && las_older_than_sas && liq(liq_las_ptr).op.fast_sg
val maskindex_scatter = siq_sas_valid && !las_older_than_sas && siq(siq_sas_ptr).op.fast_sg
las.io.maskindex.index := io.vu.index_data.asUInt
sas.io.maskindex.index := io.vu.index_data.asUInt
las.io.maskindex.mask := io.vu.mask_data(0)
sas.io.maskindex.mask := io.vu.mask_data(0)
io.vu.mask_pop.valid := false.B
io.vu.mask_pop.bits.head := 0.U
io.vu.mask_pop.bits.tail := 1.U
io.vu.index_pop.valid := false.B
io.vu.index_pop.bits.head := 0.U
io.vu.index_pop.bits.tail := 1.U
when (maskindex_load) {
io.vu.mask_pop.valid := las.io.maskindex.needs_mask && las.io.maskindex.ready
io.vu.index_pop.valid := las.io.maskindex.needs_index && las.io.maskindex.ready
io.vu.index_pop.bits.tail := 1.U << las.io.maskindex.eew
}
when (maskindex_store) {
io.vu.mask_pop.valid := sas.io.maskindex.needs_mask && sas.io.maskindex.ready
io.vu.index_pop.valid := sas.io.maskindex.needs_index && sas.io.maskindex.ready
io.vu.index_pop.bits.tail := 1.U << sas.io.maskindex.eew
}
// scatter/gather paths
sgas.foreach { sgas =>
sgas.io.index_pop.ready := false.B
sgas.io.mask_pop.ready := false.B
when (maskindex_gather || maskindex_scatter) {
io.vu.mask_pop <> sgas.io.mask_pop
io.vu.index_pop <> sgas.io.index_pop
}
sgas.io.index_data := io.vu.index_data
sgas.io.mask_data := io.vu.mask_data
sgas.io.valid := maskindex_gather || maskindex_scatter
sgas.io.lsiq_id := Mux(maskindex_gather, liq_las_ptr, siq_sas_ptr)
sgas.io.op := Mux(maskindex_gather, liq(liq_las_ptr).op, siq(siq_sas_ptr).op)
sgas.io.req <> io.sgmem.get.req
sgas.io.resp <> io.sgmem.get.resp
}
las.io.maskindex.valid := maskindex_load && (io.vu.mask_pop.ready || !las.io.maskindex.needs_mask) && (io.vu.index_pop.ready || !las.io.maskindex.needs_index)
sas.io.maskindex.valid := !maskindex_load && (io.vu.mask_pop.ready || !sas.io.maskindex.needs_mask) && (io.vu.index_pop.ready || !sas.io.maskindex.needs_index)
// Load Addr Sequencing
val las_order_block = (0 until vParams.vsiqEntries).map { i =>
val addr_conflict = siq(i).overlaps(liq(liq_las_ptr))
siq_valids(i) && addr_conflict && liq(liq_las_ptr).st_dep_mask(i)
}.orR
val dae_block = !vParams.enableDAE.B && (!io.vu.lresp.ready ||
io.vu.lresp.bits.debug_id =/= liq(liq_las_ptr).op.debug_id)
las.io.valid := liq_las_valid && !las_order_block && !liq(liq_las_ptr).op.fast_sg && !dae_block
las.io.lsiq_id := liq_las_ptr
las.io.op := liq(liq_las_ptr).op
liq_las_fire := Mux(liq(liq_las_ptr).op.fast_sg,
sgas.map(_.io.done && maskindex_gather).getOrElse(false.B), las.io.done)
las.io.tag <> lifq.io.reserve
las.io.out.ready := lifq.io.reserve.valid
lifq.io.entry := las.io.out.bits
lifq.io.push.valid := io.dmem.load_resp.valid
lifq.io.push.bits.data := io.dmem.load_resp.bits.data
lifq.io.push.bits.tag := io.dmem.load_resp.bits.tag
val load_arb = Module(new Arbiter(new MemRequest(dLenB, dmemTagBits), 2))
load_arb.io.in(1) <> las.io.req
load_arb.io.in(1).bits.store := false.B
load_arb.io.in(0) <> lifq.io.replay
load_arb.io.in(0).bits.addr := Cat(liq(lifq.io.replay_liq_id).op.page, lifq.io.replay.bits.addr(pgIdxBits-1,0))
when (io.dmem.store_req.valid) {
load_arb.io.in(0).valid := false.B
lifq.io.replay.ready := false.B
}
// Load compacting
lcu.io.push.valid := lifq.io.deq.valid
lcu.io.push.bits.head := lifq.io.deq.bits.head
lcu.io.push.bits.tail := lifq.io.deq.bits.tail
lcu.io.push_data := lifq.io.deq_data.asTypeOf(Vec(dLenB, UInt(8.W)))
lifq.io.deq.ready := lcu.io.push.ready
sgas.foreach { sgas =>
sgas.io.load_resp.ready := false.B
when (maskindex_gather && !lifq.io.busy) {
sgas.io.load_resp.ready := lcu.io.push.ready
lcu.io.push.valid := sgas.io.load_resp.valid
lcu.io.push.bits := sgas.io.load_resp.bits
lcu.io.push_data := sgas.io.load_data
}
}
// Load segment sequencing
lss.io.valid := liq_lss_valid
lss.io.op := liq(liq_lss_ptr).op
lcu.io.pop <> lss.io.compactor
lss.io.compactor_data := lcu.io.pop_data.asUInt
io.vu.lresp <> lss.io.resp
liq_lss_fire := lss.io.done
// Store segment sequencing
sss.io.valid := siq_sss_valid
sss.io.op := siq(siq_sss_ptr).op
scu.io.push <> sss.io.compactor
scu.io.push_data := sss.io.compactor_data
sss.io.stdata <> io.vu.sdata
siq_sss_fire := sss.io.done
// Store address sequencing
val sas_order_block = (0 until vParams.vliqEntries).map { i =>
val addr_conflict = liq(i).overlaps(siq(siq_sas_ptr))
liq_valids(i) && addr_conflict && siq(siq_sas_ptr).ld_dep_mask(i)
}.orR
sas.io.valid := siq_sas_valid && !sas_order_block && !siq(siq_sas_ptr).op.fast_sg
sas.io.lsiq_id := siq_sas_ptr
sas.io.op := siq(siq_sas_ptr).op
siq_sas_fire := Mux(siq(siq_sas_ptr).op.fast_sg, sgas.map(_.io.done && maskindex_scatter).getOrElse(false.B), sas.io.done)
val store_req_q = Module(new DCEQueue(new MemRequest(dLenB, dmemTagBits), 2))
store_req_q.io.enq <> sas.io.req
store_req_q.io.enq.bits.store := true.B
store_req_q.io.enq.bits.data := VecInit(scu.io.pop_data.map(_.data)).asUInt
store_req_q.io.enq.bits.mask := VecInit(scu.io.pop_data.map(_.mask)).asUInt & sas.io.req.bits.mask
val store_rob = Module(new ReorderBuffer(Bool(), vParams.vsifqEntries))
sas.io.tag <> store_rob.io.reserve
store_rob.io.reserve.ready := sas.io.tag.ready && sas.io.req.valid
sas.io.out.ready := sifq.io.enq.ready && scu.io.pop.ready
sifq.io.enq.valid := sas.io.out.valid && scu.io.pop.ready
sifq.io.enq.bits := sas.io.out.bits
scu.io.pop.valid := sas.io.out.valid && sifq.io.enq.ready
when (scu.io.pop.fire) {
for (i <- 0 until dLenB) {
assert(scu.io.pop_data(i).debug_id === sas.io.op.debug_id ||
i.U < scu.io.pop.bits.head ||
(i.U >= scu.io.pop.bits.tail && scu.io.pop.bits.tail =/= 0.U))
}
}
scu.io.pop.bits.head := sas.io.out.bits.head
scu.io.pop.bits.tail := sas.io.out.bits.tail
sgas.foreach { sgas =>
sgas.io.store_pop.ready := false.B
sgas.io.store_data := scu.io.pop_data.map(_.data)
when (maskindex_scatter && !store_rob.io.busy) {
sgas.io.store_pop.ready := scu.io.pop.ready
scu.io.pop.valid := sgas.io.store_pop.valid
scu.io.pop.bits := sgas.io.store_pop.bits
}
}
store_rob.io.push.valid := io.dmem.store_ack.valid
store_rob.io.push.bits.tag := io.dmem.store_ack.bits.tag
store_rob.io.push.bits.data := DontCare
sifq.io.deq.ready := sifq.io.deq.bits.masked || store_rob.io.deq.valid
store_rob.io.deq.ready := !sifq.io.deq.bits.masked && sifq.io.deq.valid
when (store_rob.io.deq.valid) { assert(sifq.io.deq.valid) }
siq_deq_fire := sifq.io.deq.fire && sifq.io.deq.bits.last
sgas.foreach { sgas =>
when (maskindex_scatter && sgas.io.valid && sgas.io.done) { siq_deq_fire := true.B }
}
if (vParams.latencyInject) {
val latency = Wire(UInt(32.W))
latency := PlusArg("saturn_mem_latency")
val delay_timer = RegInit(0.U(64.W))
delay_timer := delay_timer + 1.U
val load_delay = Module(new DelayQueue(new MemRequest(dLenB, dmemTagBits), 1024, 64))
val store_delay = Module(new DelayQueue(new MemRequest(dLenB, dmemTagBits), 1024, 64))
load_delay.io.timer := delay_timer
store_delay.io.timer := delay_timer
load_delay.io.delay := latency
store_delay.io.delay := latency
load_delay.io.enq <> load_arb.io.out
store_delay.io.enq <> store_req_q.io.deq
io.dmem.load_req <> load_delay.io.deq
io.dmem.store_req <> store_delay.io.deq
} else {
io.dmem.load_req <> load_arb.io.out
io.dmem.store_req <> store_req_q.io.deq
}
io.dmem.load_req.bits.mask := ~(0.U(dLenB.W))
io.busy := liq_valids.orR || siq_valids.orR
}
|
module VectorMemUnit( // @[Mem.scala:86:7]
input clock, // @[Mem.scala:86:7]
input reset, // @[Mem.scala:86:7]
output io_enq_ready, // @[Mem.scala:87:14]
input io_enq_valid, // @[Mem.scala:87:14]
input [15:0] io_enq_bits_debug_id, // @[Mem.scala:87:14]
input [11:0] io_enq_bits_base_offset, // @[Mem.scala:87:14]
input [19:0] io_enq_bits_page, // @[Mem.scala:87:14]
input [11:0] io_enq_bits_stride, // @[Mem.scala:87:14]
input [2:0] io_enq_bits_segstart, // @[Mem.scala:87:14]
input [2:0] io_enq_bits_segend, // @[Mem.scala:87:14]
input [6:0] io_enq_bits_vstart, // @[Mem.scala:87:14]
input [7:0] io_enq_bits_vl, // @[Mem.scala:87:14]
input [1:0] io_enq_bits_mop, // @[Mem.scala:87:14]
input io_enq_bits_vm, // @[Mem.scala:87:14]
input [2:0] io_enq_bits_nf, // @[Mem.scala:87:14]
input [1:0] io_enq_bits_idx_size, // @[Mem.scala:87:14]
input [1:0] io_enq_bits_elem_size, // @[Mem.scala:87:14]
input io_enq_bits_whole_reg, // @[Mem.scala:87:14]
input io_enq_bits_store, // @[Mem.scala:87:14]
input io_dmem_load_req_ready, // @[Mem.scala:87:14]
output io_dmem_load_req_valid, // @[Mem.scala:87:14]
output [39:0] io_dmem_load_req_bits_addr, // @[Mem.scala:87:14]
output [3:0] io_dmem_load_req_bits_tag, // @[Mem.scala:87:14]
input io_dmem_load_resp_valid, // @[Mem.scala:87:14]
input [63:0] io_dmem_load_resp_bits_data, // @[Mem.scala:87:14]
input [3:0] io_dmem_load_resp_bits_tag, // @[Mem.scala:87:14]
input io_dmem_store_req_ready, // @[Mem.scala:87:14]
output io_dmem_store_req_valid, // @[Mem.scala:87:14]
output [39:0] io_dmem_store_req_bits_addr, // @[Mem.scala:87:14]
output [63:0] io_dmem_store_req_bits_data, // @[Mem.scala:87:14]
output [7:0] io_dmem_store_req_bits_mask, // @[Mem.scala:87:14]
output [3:0] io_dmem_store_req_bits_tag, // @[Mem.scala:87:14]
input io_dmem_store_ack_valid, // @[Mem.scala:87:14]
input [3:0] io_dmem_store_ack_bits_tag, // @[Mem.scala:87:14]
input [39:0] io_scalar_check_addr, // @[Mem.scala:87:14]
input io_scalar_check_store, // @[Mem.scala:87:14]
output io_scalar_check_conflict, // @[Mem.scala:87:14]
input io_vu_lresp_ready, // @[Mem.scala:87:14]
output io_vu_lresp_valid, // @[Mem.scala:87:14]
output [63:0] io_vu_lresp_bits_data, // @[Mem.scala:87:14]
output [15:0] io_vu_lresp_bits_debug_id, // @[Mem.scala:87:14]
output io_vu_sdata_ready, // @[Mem.scala:87:14]
input io_vu_sdata_valid, // @[Mem.scala:87:14]
input [63:0] io_vu_sdata_bits_stdata, // @[Mem.scala:87:14]
input [7:0] io_vu_sdata_bits_stmask, // @[Mem.scala:87:14]
input [15:0] io_vu_sdata_bits_debug_id, // @[Mem.scala:87:14]
input io_vu_mask_pop_ready, // @[Mem.scala:87:14]
output io_vu_mask_pop_valid, // @[Mem.scala:87:14]
input io_vu_mask_data_0, // @[Mem.scala:87:14]
input io_vu_index_pop_ready, // @[Mem.scala:87:14]
output io_vu_index_pop_valid, // @[Mem.scala:87:14]
output [2:0] io_vu_index_pop_bits_tail, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_0, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_1, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_2, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_3, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_4, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_5, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_6, // @[Mem.scala:87:14]
input [7:0] io_vu_index_data_7, // @[Mem.scala:87:14]
output io_busy // @[Mem.scala:87:14]
);
wire siq_deq_fire; // @[Decoupled.scala:51:35]
wire _store_rob_io_reserve_valid; // @[Mem.scala:338:25]
wire [3:0] _store_rob_io_reserve_bits; // @[Mem.scala:338:25]
wire _store_rob_io_deq_valid; // @[Mem.scala:338:25]
wire _store_req_q_io_enq_ready; // @[Mem.scala:332:27]
wire _store_req_q_io_deq_valid; // @[Mem.scala:332:27]
wire _load_arb_io_in_0_ready; // @[Mem.scala:279:24]
wire _load_arb_io_in_1_ready; // @[Mem.scala:279:24]
wire _sifq_io_enq_ready; // @[Mem.scala:114:20]
wire _sifq_io_deq_valid; // @[Mem.scala:114:20]
wire _sifq_io_deq_bits_masked; // @[Mem.scala:114:20]
wire _sifq_io_deq_bits_last; // @[Mem.scala:114:20]
wire _sas_io_done; // @[Mem.scala:113:19]
wire _sas_io_tag_ready; // @[Mem.scala:113:19]
wire [1:0] _sas_io_maskindex_eew; // @[Mem.scala:113:19]
wire _sas_io_maskindex_needs_mask; // @[Mem.scala:113:19]
wire _sas_io_maskindex_needs_index; // @[Mem.scala:113:19]
wire _sas_io_maskindex_ready; // @[Mem.scala:113:19]
wire _sas_io_req_valid; // @[Mem.scala:113:19]
wire [39:0] _sas_io_req_bits_addr; // @[Mem.scala:113:19]
wire [7:0] _sas_io_req_bits_mask; // @[Mem.scala:113:19]
wire [3:0] _sas_io_req_bits_tag; // @[Mem.scala:113:19]
wire _sas_io_out_valid; // @[Mem.scala:113:19]
wire [2:0] _sas_io_out_bits_head; // @[Mem.scala:113:19]
wire [2:0] _sas_io_out_bits_tail; // @[Mem.scala:113:19]
wire _sas_io_out_bits_masked; // @[Mem.scala:113:19]
wire _sas_io_out_bits_last; // @[Mem.scala:113:19]
wire _sss_io_done; // @[Mem.scala:112:19]
wire _sss_io_compactor_valid; // @[Mem.scala:112:19]
wire [2:0] _sss_io_compactor_bits_head; // @[Mem.scala:112:19]
wire [2:0] _sss_io_compactor_bits_tail; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_0_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_0_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_0_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_1_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_1_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_1_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_2_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_2_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_2_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_3_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_3_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_3_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_4_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_4_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_4_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_5_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_5_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_5_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_6_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_6_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_6_mask; // @[Mem.scala:112:19]
wire [15:0] _sss_io_compactor_data_7_debug_id; // @[Mem.scala:112:19]
wire [7:0] _sss_io_compactor_data_7_data; // @[Mem.scala:112:19]
wire _sss_io_compactor_data_7_mask; // @[Mem.scala:112:19]
wire _scu_io_push_ready; // @[Mem.scala:111:19]
wire _scu_io_pop_ready; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_0_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_0_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_0_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_1_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_1_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_1_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_2_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_2_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_2_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_3_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_3_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_3_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_4_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_4_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_4_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_5_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_5_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_5_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_6_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_6_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_6_mask; // @[Mem.scala:111:19]
wire [15:0] _scu_io_pop_data_7_debug_id; // @[Mem.scala:111:19]
wire [7:0] _scu_io_pop_data_7_data; // @[Mem.scala:111:19]
wire _scu_io_pop_data_7_mask; // @[Mem.scala:111:19]
wire _lss_io_done; // @[Mem.scala:109:19]
wire _lss_io_compactor_valid; // @[Mem.scala:109:19]
wire [2:0] _lss_io_compactor_bits_head; // @[Mem.scala:109:19]
wire [2:0] _lss_io_compactor_bits_tail; // @[Mem.scala:109:19]
wire _lcu_io_push_ready; // @[Mem.scala:108:19]
wire _lcu_io_pop_ready; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_0; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_1; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_2; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_3; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_4; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_5; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_6; // @[Mem.scala:108:19]
wire [7:0] _lcu_io_pop_data_7; // @[Mem.scala:108:19]
wire _lifq_io_reserve_valid; // @[Mem.scala:107:20]
wire [2:0] _lifq_io_reserve_bits; // @[Mem.scala:107:20]
wire [1:0] _lifq_io_replay_liq_id; // @[Mem.scala:107:20]
wire _lifq_io_replay_valid; // @[Mem.scala:107:20]
wire [39:0] _lifq_io_replay_bits_addr; // @[Mem.scala:107:20]
wire [3:0] _lifq_io_replay_bits_tag; // @[Mem.scala:107:20]
wire _lifq_io_deq_valid; // @[Mem.scala:107:20]
wire [2:0] _lifq_io_deq_bits_head; // @[Mem.scala:107:20]
wire [2:0] _lifq_io_deq_bits_tail; // @[Mem.scala:107:20]
wire [63:0] _lifq_io_deq_data; // @[Mem.scala:107:20]
wire _las_io_done; // @[Mem.scala:106:19]
wire _las_io_tag_ready; // @[Mem.scala:106:19]
wire [1:0] _las_io_maskindex_eew; // @[Mem.scala:106:19]
wire _las_io_maskindex_needs_mask; // @[Mem.scala:106:19]
wire _las_io_maskindex_needs_index; // @[Mem.scala:106:19]
wire _las_io_maskindex_ready; // @[Mem.scala:106:19]
wire _las_io_req_valid; // @[Mem.scala:106:19]
wire [39:0] _las_io_req_bits_addr; // @[Mem.scala:106:19]
wire [3:0] _las_io_req_bits_tag; // @[Mem.scala:106:19]
wire [2:0] _las_io_out_bits_head; // @[Mem.scala:106:19]
wire [2:0] _las_io_out_bits_tail; // @[Mem.scala:106:19]
wire _las_io_out_bits_masked; // @[Mem.scala:106:19]
wire [1:0] _las_io_out_bits_lsiq_id; // @[Mem.scala:106:19]
wire [11:0] _las_io_out_bits_page_offset; // @[Mem.scala:106:19]
reg [15:0] liq_0_op_debug_id; // @[Mem.scala:116:16]
reg [11:0] liq_0_op_base_offset; // @[Mem.scala:116:16]
reg [19:0] liq_0_op_page; // @[Mem.scala:116:16]
reg [11:0] liq_0_op_stride; // @[Mem.scala:116:16]
reg [2:0] liq_0_op_segstart; // @[Mem.scala:116:16]
reg [2:0] liq_0_op_segend; // @[Mem.scala:116:16]
reg [6:0] liq_0_op_vstart; // @[Mem.scala:116:16]
reg [7:0] liq_0_op_vl; // @[Mem.scala:116:16]
reg [1:0] liq_0_op_mop; // @[Mem.scala:116:16]
reg liq_0_op_vm; // @[Mem.scala:116:16]
reg [2:0] liq_0_op_nf; // @[Mem.scala:116:16]
reg [1:0] liq_0_op_idx_size; // @[Mem.scala:116:16]
reg [1:0] liq_0_op_elem_size; // @[Mem.scala:116:16]
reg liq_0_op_whole_reg; // @[Mem.scala:116:16]
reg liq_0_op_fast_sg; // @[Mem.scala:116:16]
reg [11:0] liq_0_bound_offset; // @[Mem.scala:116:16]
reg liq_0_st_dep_mask_0; // @[Mem.scala:116:16]
reg liq_0_st_dep_mask_1; // @[Mem.scala:116:16]
reg liq_0_st_dep_mask_2; // @[Mem.scala:116:16]
reg liq_0_st_dep_mask_3; // @[Mem.scala:116:16]
reg [15:0] liq_1_op_debug_id; // @[Mem.scala:116:16]
reg [11:0] liq_1_op_base_offset; // @[Mem.scala:116:16]
reg [19:0] liq_1_op_page; // @[Mem.scala:116:16]
reg [11:0] liq_1_op_stride; // @[Mem.scala:116:16]
reg [2:0] liq_1_op_segstart; // @[Mem.scala:116:16]
reg [2:0] liq_1_op_segend; // @[Mem.scala:116:16]
reg [6:0] liq_1_op_vstart; // @[Mem.scala:116:16]
reg [7:0] liq_1_op_vl; // @[Mem.scala:116:16]
reg [1:0] liq_1_op_mop; // @[Mem.scala:116:16]
reg liq_1_op_vm; // @[Mem.scala:116:16]
reg [2:0] liq_1_op_nf; // @[Mem.scala:116:16]
reg [1:0] liq_1_op_idx_size; // @[Mem.scala:116:16]
reg [1:0] liq_1_op_elem_size; // @[Mem.scala:116:16]
reg liq_1_op_whole_reg; // @[Mem.scala:116:16]
reg liq_1_op_fast_sg; // @[Mem.scala:116:16]
reg [11:0] liq_1_bound_offset; // @[Mem.scala:116:16]
reg liq_1_st_dep_mask_0; // @[Mem.scala:116:16]
reg liq_1_st_dep_mask_1; // @[Mem.scala:116:16]
reg liq_1_st_dep_mask_2; // @[Mem.scala:116:16]
reg liq_1_st_dep_mask_3; // @[Mem.scala:116:16]
reg [15:0] liq_2_op_debug_id; // @[Mem.scala:116:16]
reg [11:0] liq_2_op_base_offset; // @[Mem.scala:116:16]
reg [19:0] liq_2_op_page; // @[Mem.scala:116:16]
reg [11:0] liq_2_op_stride; // @[Mem.scala:116:16]
reg [2:0] liq_2_op_segstart; // @[Mem.scala:116:16]
reg [2:0] liq_2_op_segend; // @[Mem.scala:116:16]
reg [6:0] liq_2_op_vstart; // @[Mem.scala:116:16]
reg [7:0] liq_2_op_vl; // @[Mem.scala:116:16]
reg [1:0] liq_2_op_mop; // @[Mem.scala:116:16]
reg liq_2_op_vm; // @[Mem.scala:116:16]
reg [2:0] liq_2_op_nf; // @[Mem.scala:116:16]
reg [1:0] liq_2_op_idx_size; // @[Mem.scala:116:16]
reg [1:0] liq_2_op_elem_size; // @[Mem.scala:116:16]
reg liq_2_op_whole_reg; // @[Mem.scala:116:16]
reg liq_2_op_fast_sg; // @[Mem.scala:116:16]
reg [11:0] liq_2_bound_offset; // @[Mem.scala:116:16]
reg liq_2_st_dep_mask_0; // @[Mem.scala:116:16]
reg liq_2_st_dep_mask_1; // @[Mem.scala:116:16]
reg liq_2_st_dep_mask_2; // @[Mem.scala:116:16]
reg liq_2_st_dep_mask_3; // @[Mem.scala:116:16]
reg [15:0] liq_3_op_debug_id; // @[Mem.scala:116:16]
reg [11:0] liq_3_op_base_offset; // @[Mem.scala:116:16]
reg [19:0] liq_3_op_page; // @[Mem.scala:116:16]
reg [11:0] liq_3_op_stride; // @[Mem.scala:116:16]
reg [2:0] liq_3_op_segstart; // @[Mem.scala:116:16]
reg [2:0] liq_3_op_segend; // @[Mem.scala:116:16]
reg [6:0] liq_3_op_vstart; // @[Mem.scala:116:16]
reg [7:0] liq_3_op_vl; // @[Mem.scala:116:16]
reg [1:0] liq_3_op_mop; // @[Mem.scala:116:16]
reg liq_3_op_vm; // @[Mem.scala:116:16]
reg [2:0] liq_3_op_nf; // @[Mem.scala:116:16]
reg [1:0] liq_3_op_idx_size; // @[Mem.scala:116:16]
reg [1:0] liq_3_op_elem_size; // @[Mem.scala:116:16]
reg liq_3_op_whole_reg; // @[Mem.scala:116:16]
reg liq_3_op_fast_sg; // @[Mem.scala:116:16]
reg [11:0] liq_3_bound_offset; // @[Mem.scala:116:16]
reg liq_3_st_dep_mask_0; // @[Mem.scala:116:16]
reg liq_3_st_dep_mask_1; // @[Mem.scala:116:16]
reg liq_3_st_dep_mask_2; // @[Mem.scala:116:16]
reg liq_3_st_dep_mask_3; // @[Mem.scala:116:16]
reg liq_valids_0; // @[Mem.scala:117:30]
reg liq_valids_1; // @[Mem.scala:117:30]
reg liq_valids_2; // @[Mem.scala:117:30]
reg liq_valids_3; // @[Mem.scala:117:30]
reg liq_las_0; // @[Mem.scala:118:30]
reg liq_las_1; // @[Mem.scala:118:30]
reg liq_las_2; // @[Mem.scala:118:30]
reg liq_las_3; // @[Mem.scala:118:30]
reg [1:0] liq_enq_ptr; // @[Mem.scala:119:30]
reg [1:0] liq_las_ptr; // @[Mem.scala:120:30]
reg [1:0] liq_lss_ptr; // @[Mem.scala:121:30]
wire [3:0] _GEN = {{liq_valids_3}, {liq_valids_2}, {liq_valids_1}, {liq_valids_0}}; // @[Mem.scala:117:30, :127:23]
wire _GEN_0 = _GEN[liq_enq_ptr]; // @[Mem.scala:119:30, :127:23]
wire [3:0] _GEN_1 = {{liq_las_3}, {liq_las_2}, {liq_las_1}, {liq_las_0}}; // @[Mem.scala:118:30, :128:23]
wire liq_las_valid = ~_GEN_1[liq_las_ptr] & _GEN[liq_las_ptr]; // @[Mem.scala:120:30, :127:23, :128:{23,45}]
reg [15:0] siq_0_op_debug_id; // @[Mem.scala:131:16]
reg [11:0] siq_0_op_base_offset; // @[Mem.scala:131:16]
reg [19:0] siq_0_op_page; // @[Mem.scala:131:16]
reg [11:0] siq_0_op_stride; // @[Mem.scala:131:16]
reg [2:0] siq_0_op_segstart; // @[Mem.scala:131:16]
reg [2:0] siq_0_op_segend; // @[Mem.scala:131:16]
reg [6:0] siq_0_op_vstart; // @[Mem.scala:131:16]
reg [7:0] siq_0_op_vl; // @[Mem.scala:131:16]
reg [1:0] siq_0_op_mop; // @[Mem.scala:131:16]
reg siq_0_op_vm; // @[Mem.scala:131:16]
reg [2:0] siq_0_op_nf; // @[Mem.scala:131:16]
reg [1:0] siq_0_op_idx_size; // @[Mem.scala:131:16]
reg [1:0] siq_0_op_elem_size; // @[Mem.scala:131:16]
reg siq_0_op_whole_reg; // @[Mem.scala:131:16]
reg siq_0_op_fast_sg; // @[Mem.scala:131:16]
reg [11:0] siq_0_bound_offset; // @[Mem.scala:131:16]
reg siq_0_ld_dep_mask_0; // @[Mem.scala:131:16]
reg siq_0_ld_dep_mask_1; // @[Mem.scala:131:16]
reg siq_0_ld_dep_mask_2; // @[Mem.scala:131:16]
reg siq_0_ld_dep_mask_3; // @[Mem.scala:131:16]
reg [15:0] siq_1_op_debug_id; // @[Mem.scala:131:16]
reg [11:0] siq_1_op_base_offset; // @[Mem.scala:131:16]
reg [19:0] siq_1_op_page; // @[Mem.scala:131:16]
reg [11:0] siq_1_op_stride; // @[Mem.scala:131:16]
reg [2:0] siq_1_op_segstart; // @[Mem.scala:131:16]
reg [2:0] siq_1_op_segend; // @[Mem.scala:131:16]
reg [6:0] siq_1_op_vstart; // @[Mem.scala:131:16]
reg [7:0] siq_1_op_vl; // @[Mem.scala:131:16]
reg [1:0] siq_1_op_mop; // @[Mem.scala:131:16]
reg siq_1_op_vm; // @[Mem.scala:131:16]
reg [2:0] siq_1_op_nf; // @[Mem.scala:131:16]
reg [1:0] siq_1_op_idx_size; // @[Mem.scala:131:16]
reg [1:0] siq_1_op_elem_size; // @[Mem.scala:131:16]
reg siq_1_op_whole_reg; // @[Mem.scala:131:16]
reg siq_1_op_fast_sg; // @[Mem.scala:131:16]
reg [11:0] siq_1_bound_offset; // @[Mem.scala:131:16]
reg siq_1_ld_dep_mask_0; // @[Mem.scala:131:16]
reg siq_1_ld_dep_mask_1; // @[Mem.scala:131:16]
reg siq_1_ld_dep_mask_2; // @[Mem.scala:131:16]
reg siq_1_ld_dep_mask_3; // @[Mem.scala:131:16]
reg [15:0] siq_2_op_debug_id; // @[Mem.scala:131:16]
reg [11:0] siq_2_op_base_offset; // @[Mem.scala:131:16]
reg [19:0] siq_2_op_page; // @[Mem.scala:131:16]
reg [11:0] siq_2_op_stride; // @[Mem.scala:131:16]
reg [2:0] siq_2_op_segstart; // @[Mem.scala:131:16]
reg [2:0] siq_2_op_segend; // @[Mem.scala:131:16]
reg [6:0] siq_2_op_vstart; // @[Mem.scala:131:16]
reg [7:0] siq_2_op_vl; // @[Mem.scala:131:16]
reg [1:0] siq_2_op_mop; // @[Mem.scala:131:16]
reg siq_2_op_vm; // @[Mem.scala:131:16]
reg [2:0] siq_2_op_nf; // @[Mem.scala:131:16]
reg [1:0] siq_2_op_idx_size; // @[Mem.scala:131:16]
reg [1:0] siq_2_op_elem_size; // @[Mem.scala:131:16]
reg siq_2_op_whole_reg; // @[Mem.scala:131:16]
reg siq_2_op_fast_sg; // @[Mem.scala:131:16]
reg [11:0] siq_2_bound_offset; // @[Mem.scala:131:16]
reg siq_2_ld_dep_mask_0; // @[Mem.scala:131:16]
reg siq_2_ld_dep_mask_1; // @[Mem.scala:131:16]
reg siq_2_ld_dep_mask_2; // @[Mem.scala:131:16]
reg siq_2_ld_dep_mask_3; // @[Mem.scala:131:16]
reg [15:0] siq_3_op_debug_id; // @[Mem.scala:131:16]
reg [11:0] siq_3_op_base_offset; // @[Mem.scala:131:16]
reg [19:0] siq_3_op_page; // @[Mem.scala:131:16]
reg [11:0] siq_3_op_stride; // @[Mem.scala:131:16]
reg [2:0] siq_3_op_segstart; // @[Mem.scala:131:16]
reg [2:0] siq_3_op_segend; // @[Mem.scala:131:16]
reg [6:0] siq_3_op_vstart; // @[Mem.scala:131:16]
reg [7:0] siq_3_op_vl; // @[Mem.scala:131:16]
reg [1:0] siq_3_op_mop; // @[Mem.scala:131:16]
reg siq_3_op_vm; // @[Mem.scala:131:16]
reg [2:0] siq_3_op_nf; // @[Mem.scala:131:16]
reg [1:0] siq_3_op_idx_size; // @[Mem.scala:131:16]
reg [1:0] siq_3_op_elem_size; // @[Mem.scala:131:16]
reg siq_3_op_whole_reg; // @[Mem.scala:131:16]
reg siq_3_op_fast_sg; // @[Mem.scala:131:16]
reg [11:0] siq_3_bound_offset; // @[Mem.scala:131:16]
reg siq_3_ld_dep_mask_0; // @[Mem.scala:131:16]
reg siq_3_ld_dep_mask_1; // @[Mem.scala:131:16]
reg siq_3_ld_dep_mask_2; // @[Mem.scala:131:16]
reg siq_3_ld_dep_mask_3; // @[Mem.scala:131:16]
reg siq_valids_0; // @[Mem.scala:132:30]
reg siq_valids_1; // @[Mem.scala:132:30]
reg siq_valids_2; // @[Mem.scala:132:30]
reg siq_valids_3; // @[Mem.scala:132:30]
reg siq_sss_0; // @[Mem.scala:133:30]
reg siq_sss_1; // @[Mem.scala:133:30]
reg siq_sss_2; // @[Mem.scala:133:30]
reg siq_sss_3; // @[Mem.scala:133:30]
reg siq_sas_0; // @[Mem.scala:134:30]
reg siq_sas_1; // @[Mem.scala:134:30]
reg siq_sas_2; // @[Mem.scala:134:30]
reg siq_sas_3; // @[Mem.scala:134:30]
reg [1:0] siq_enq_ptr; // @[Mem.scala:135:30]
reg [1:0] siq_sss_ptr; // @[Mem.scala:136:30]
reg [1:0] siq_sas_ptr; // @[Mem.scala:137:30]
reg [1:0] siq_deq_ptr; // @[Mem.scala:138:30]
wire [3:0] _GEN_2 = {{siq_valids_3}, {siq_valids_2}, {siq_valids_1}, {siq_valids_0}}; // @[Mem.scala:132:30, :145:23]
wire _GEN_3 = _GEN_2[siq_enq_ptr]; // @[Mem.scala:135:30, :145:23]
wire [3:0] _GEN_4 = {{siq_sss_3}, {siq_sss_2}, {siq_sss_1}, {siq_sss_0}}; // @[Mem.scala:133:30, :146:23]
wire [3:0] _GEN_5 = {{siq_sas_3}, {siq_sas_2}, {siq_sas_1}, {siq_sas_0}}; // @[Mem.scala:134:30, :147:23]
wire siq_sas_valid = ~_GEN_5[siq_sas_ptr] & _GEN_2[siq_sas_ptr]; // @[Mem.scala:137:30, :145:23, :147:{23,45}]
wire liq_enq_fire = io_enq_valid & ~_GEN_0 & ~io_enq_bits_store; // @[Mem.scala:127:23, :195:{32,49,52}]
wire siq_enq_fire = io_enq_valid & ~_GEN_3 & io_enq_bits_store; // @[Mem.scala:145:23, :196:{32,49}]
wire [3:0][11:0] _GEN_6 = {{liq_3_op_base_offset}, {liq_2_op_base_offset}, {liq_1_op_base_offset}, {liq_0_op_base_offset}}; // @[Mem.scala:116:16, :211:46]
wire [11:0] las_io_op_base_offset = _GEN_6[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0][19:0] _GEN_7 = {{liq_3_op_page}, {liq_2_op_page}, {liq_1_op_page}, {liq_0_op_page}}; // @[Mem.scala:116:16, :211:46]
wire [19:0] las_io_op_page = _GEN_7[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0][11:0] _GEN_8 = {{liq_3_op_stride}, {liq_2_op_stride}, {liq_1_op_stride}, {liq_0_op_stride}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][2:0] _GEN_9 = {{liq_3_op_segstart}, {liq_2_op_segstart}, {liq_1_op_segstart}, {liq_0_op_segstart}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][2:0] _GEN_10 = {{liq_3_op_segend}, {liq_2_op_segend}, {liq_1_op_segend}, {liq_0_op_segend}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][6:0] _GEN_11 = {{liq_3_op_vstart}, {liq_2_op_vstart}, {liq_1_op_vstart}, {liq_0_op_vstart}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][7:0] _GEN_12 = {{liq_3_op_vl}, {liq_2_op_vl}, {liq_1_op_vl}, {liq_0_op_vl}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][1:0] _GEN_13 = {{liq_3_op_mop}, {liq_2_op_mop}, {liq_1_op_mop}, {liq_0_op_mop}}; // @[Mem.scala:116:16, :211:46]
wire [1:0] las_io_op_mop = _GEN_13[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_14 = {{liq_3_op_vm}, {liq_2_op_vm}, {liq_1_op_vm}, {liq_0_op_vm}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][2:0] _GEN_15 = {{liq_3_op_nf}, {liq_2_op_nf}, {liq_1_op_nf}, {liq_0_op_nf}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][1:0] _GEN_16 = {{liq_3_op_idx_size}, {liq_2_op_idx_size}, {liq_1_op_idx_size}, {liq_0_op_idx_size}}; // @[Mem.scala:116:16, :211:46]
wire [3:0][1:0] _GEN_17 = {{liq_3_op_elem_size}, {liq_2_op_elem_size}, {liq_1_op_elem_size}, {liq_0_op_elem_size}}; // @[Mem.scala:116:16, :211:46]
wire [3:0] _GEN_18 = {{liq_3_op_whole_reg}, {liq_2_op_whole_reg}, {liq_1_op_whole_reg}, {liq_0_op_whole_reg}}; // @[Mem.scala:116:16, :211:46]
wire [3:0] _GEN_19 = {{liq_3_op_fast_sg}, {liq_2_op_fast_sg}, {liq_1_op_fast_sg}, {liq_0_op_fast_sg}}; // @[Mem.scala:116:16, :211:46]
wire _GEN_20 = _GEN_19[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0][11:0] _GEN_21 = {{liq_3_bound_offset}, {liq_2_bound_offset}, {liq_1_bound_offset}, {liq_0_bound_offset}}; // @[Mem.scala:116:16, :211:46]
wire [11:0] _GEN_22 = _GEN_21[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_23 = {{liq_3_st_dep_mask_0}, {liq_2_st_dep_mask_0}, {liq_1_st_dep_mask_0}, {liq_0_st_dep_mask_0}}; // @[Mem.scala:116:16, :211:46]
wire _GEN_24 = _GEN_23[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_25 = {{liq_3_st_dep_mask_1}, {liq_2_st_dep_mask_1}, {liq_1_st_dep_mask_1}, {liq_0_st_dep_mask_1}}; // @[Mem.scala:116:16, :211:46]
wire _GEN_26 = _GEN_25[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_27 = {{liq_3_st_dep_mask_2}, {liq_2_st_dep_mask_2}, {liq_1_st_dep_mask_2}, {liq_0_st_dep_mask_2}}; // @[Mem.scala:116:16, :211:46]
wire _GEN_28 = _GEN_27[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_29 = {{liq_3_st_dep_mask_3}, {liq_2_st_dep_mask_3}, {liq_1_st_dep_mask_3}, {liq_0_st_dep_mask_3}}; // @[Mem.scala:116:16, :211:46]
wire _GEN_30 = _GEN_29[liq_las_ptr]; // @[Mem.scala:120:30, :211:46]
wire [3:0] _GEN_31 = {{_GEN_30}, {_GEN_28}, {_GEN_26}, {_GEN_24}}; // @[Mem.scala:211:46]
wire las_older_than_sas = liq_las_valid & ~_GEN_31[siq_sas_ptr] | ~siq_sas_valid; // @[Mem.scala:128:45, :137:30, :147:45, :211:{43,46,90,93}]
wire maskindex_load = liq_las_valid & las_older_than_sas & ~_GEN_20; // @[Mem.scala:128:45, :211:{46,90}, :212:{41,64,67}]
wire [3:0][15:0] _GEN_32 = {{siq_3_op_debug_id}, {siq_2_op_debug_id}, {siq_1_op_debug_id}, {siq_0_op_debug_id}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][11:0] _GEN_33 = {{siq_3_op_base_offset}, {siq_2_op_base_offset}, {siq_1_op_base_offset}, {siq_0_op_base_offset}}; // @[Mem.scala:131:16, :213:67]
wire [11:0] sas_io_op_base_offset = _GEN_33[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67]
wire [3:0][19:0] _GEN_34 = {{siq_3_op_page}, {siq_2_op_page}, {siq_1_op_page}, {siq_0_op_page}}; // @[Mem.scala:131:16, :213:67]
wire [19:0] sas_io_op_page = _GEN_34[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67]
wire [3:0][11:0] _GEN_35 = {{siq_3_op_stride}, {siq_2_op_stride}, {siq_1_op_stride}, {siq_0_op_stride}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][2:0] _GEN_36 = {{siq_3_op_segstart}, {siq_2_op_segstart}, {siq_1_op_segstart}, {siq_0_op_segstart}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][2:0] _GEN_37 = {{siq_3_op_segend}, {siq_2_op_segend}, {siq_1_op_segend}, {siq_0_op_segend}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][6:0] _GEN_38 = {{siq_3_op_vstart}, {siq_2_op_vstart}, {siq_1_op_vstart}, {siq_0_op_vstart}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][7:0] _GEN_39 = {{siq_3_op_vl}, {siq_2_op_vl}, {siq_1_op_vl}, {siq_0_op_vl}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][1:0] _GEN_40 = {{siq_3_op_mop}, {siq_2_op_mop}, {siq_1_op_mop}, {siq_0_op_mop}}; // @[Mem.scala:131:16, :213:67]
wire [1:0] sas_io_op_mop = _GEN_40[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67]
wire [3:0] _GEN_41 = {{siq_3_op_vm}, {siq_2_op_vm}, {siq_1_op_vm}, {siq_0_op_vm}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][2:0] _GEN_42 = {{siq_3_op_nf}, {siq_2_op_nf}, {siq_1_op_nf}, {siq_0_op_nf}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][1:0] _GEN_43 = {{siq_3_op_idx_size}, {siq_2_op_idx_size}, {siq_1_op_idx_size}, {siq_0_op_idx_size}}; // @[Mem.scala:131:16, :213:67]
wire [3:0][1:0] _GEN_44 = {{siq_3_op_elem_size}, {siq_2_op_elem_size}, {siq_1_op_elem_size}, {siq_0_op_elem_size}}; // @[Mem.scala:131:16, :213:67]
wire [3:0] _GEN_45 = {{siq_3_op_whole_reg}, {siq_2_op_whole_reg}, {siq_1_op_whole_reg}, {siq_0_op_whole_reg}}; // @[Mem.scala:131:16, :213:67]
wire [3:0] _GEN_46 = {{siq_3_op_fast_sg}, {siq_2_op_fast_sg}, {siq_1_op_fast_sg}, {siq_0_op_fast_sg}}; // @[Mem.scala:131:16, :213:67]
wire _GEN_47 = _GEN_46[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67]
wire [3:0][11:0] _GEN_48 = {{siq_3_bound_offset}, {siq_2_bound_offset}, {siq_1_bound_offset}, {siq_0_bound_offset}}; // @[Mem.scala:131:16, :213:67]
wire [11:0] _GEN_49 = _GEN_48[siq_sas_ptr]; // @[Mem.scala:137:30, :213:67]
wire [3:0] _GEN_50 = {{siq_3_ld_dep_mask_0}, {siq_2_ld_dep_mask_0}, {siq_1_ld_dep_mask_0}, {siq_0_ld_dep_mask_0}}; // @[Mem.scala:131:16, :213:67]
wire [3:0] _GEN_51 = {{siq_3_ld_dep_mask_1}, {siq_2_ld_dep_mask_1}, {siq_1_ld_dep_mask_1}, {siq_0_ld_dep_mask_1}}; // @[Mem.scala:131:16, :213:67]
wire [3:0] _GEN_52 = {{siq_3_ld_dep_mask_2}, {siq_2_ld_dep_mask_2}, {siq_1_ld_dep_mask_2}, {siq_0_ld_dep_mask_2}}; // @[Mem.scala:131:16, :213:67]
wire [3:0] _GEN_53 = {{siq_3_ld_dep_mask_3}, {siq_2_ld_dep_mask_3}, {siq_1_ld_dep_mask_3}, {siq_0_ld_dep_mask_3}}; // @[Mem.scala:131:16, :213:67]
wire maskindex_store = siq_sas_valid & ~las_older_than_sas & ~_GEN_47; // @[Mem.scala:147:45, :211:90, :213:{41,44,64,67}]
wire [3:0] _io_vu_index_pop_bits_tail_T = 4'h1 << _las_io_maskindex_eew; // @[Mem.scala:106:19, :230:38]
wire [3:0] _io_vu_index_pop_bits_tail_T_1 = 4'h1 << _sas_io_maskindex_eew; // @[Mem.scala:113:19, :235:38]
wire liq_las_fire = ~_GEN_20 & _las_io_done; // @[Mem.scala:106:19, :211:46, :268:22]
wire [3:0][15:0] _GEN_54 = {{liq_3_op_debug_id}, {liq_2_op_debug_id}, {liq_1_op_debug_id}, {liq_0_op_debug_id}}; // @[Mem.scala:116:16, :308:13]
wire siq_sas_fire = ~_GEN_47 & _sas_io_done; // @[Mem.scala:113:19, :213:67, :330:22]
wire scu_io_pop_valid = _sas_io_out_valid & _sifq_io_enq_ready; // @[Mem.scala:113:19, :114:20, :345:40]
wire sifq_io_deq_ready = _sifq_io_deq_bits_masked | _store_rob_io_deq_valid; // @[Mem.scala:114:20, :338:25, :371:48]
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_41( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_179( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_200 io_out_sink_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.diplomacy
import chisel3._
import chisel3.util.{DecoupledIO, Queue, ReadyValidIO, isPow2, log2Ceil, log2Floor}
import freechips.rocketchip.util.ShiftQueue
/** Options for describing the attributes of memory regions */
object RegionType {
// Define the 'more relaxed than' ordering
val cases = Seq(CACHED, TRACKED, UNCACHED, IDEMPOTENT, VOLATILE, PUT_EFFECTS, GET_EFFECTS)
sealed trait T extends Ordered[T] {
def compare(that: T): Int = cases.indexOf(that) compare cases.indexOf(this)
}
case object CACHED extends T // an intermediate agent may have cached a copy of the region for you
case object TRACKED extends T // the region may have been cached by another master, but coherence is being provided
case object UNCACHED extends T // the region has not been cached yet, but should be cached when possible
case object IDEMPOTENT extends T // gets return most recently put content, but content should not be cached
case object VOLATILE extends T // content may change without a put, but puts and gets have no side effects
case object PUT_EFFECTS extends T // puts produce side effects and so must not be combined/delayed
case object GET_EFFECTS extends T // gets produce side effects and so must not be issued speculatively
}
// A non-empty half-open range; [start, end)
case class IdRange(start: Int, end: Int) extends Ordered[IdRange]
{
require (start >= 0, s"Ids cannot be negative, but got: $start.")
require (start <= end, "Id ranges cannot be negative.")
def compare(x: IdRange) = {
val primary = (this.start - x.start).signum
val secondary = (x.end - this.end).signum
if (primary != 0) primary else secondary
}
def overlaps(x: IdRange) = start < x.end && x.start < end
def contains(x: IdRange) = start <= x.start && x.end <= end
def contains(x: Int) = start <= x && x < end
def contains(x: UInt) =
if (size == 0) {
false.B
} else if (size == 1) { // simple comparison
x === start.U
} else {
// find index of largest different bit
val largestDeltaBit = log2Floor(start ^ (end-1))
val smallestCommonBit = largestDeltaBit + 1 // may not exist in x
val uncommonMask = (1 << smallestCommonBit) - 1
val uncommonBits = (x | 0.U(smallestCommonBit.W))(largestDeltaBit, 0)
// the prefix must match exactly (note: may shift ALL bits away)
(x >> smallestCommonBit) === (start >> smallestCommonBit).U &&
// firrtl constant prop range analysis can eliminate these two:
(start & uncommonMask).U <= uncommonBits &&
uncommonBits <= ((end-1) & uncommonMask).U
}
def shift(x: Int) = IdRange(start+x, end+x)
def size = end - start
def isEmpty = end == start
def range = start until end
}
object IdRange
{
def overlaps(s: Seq[IdRange]) = if (s.isEmpty) None else {
val ranges = s.sorted
(ranges.tail zip ranges.init) find { case (a, b) => a overlaps b }
}
}
// An potentially empty inclusive range of 2-powers [min, max] (in bytes)
case class TransferSizes(min: Int, max: Int)
{
def this(x: Int) = this(x, x)
require (min <= max, s"Min transfer $min > max transfer $max")
require (min >= 0 && max >= 0, s"TransferSizes must be positive, got: ($min, $max)")
require (max == 0 || isPow2(max), s"TransferSizes must be a power of 2, got: $max")
require (min == 0 || isPow2(min), s"TransferSizes must be a power of 2, got: $min")
require (max == 0 || min != 0, s"TransferSize 0 is forbidden unless (0,0), got: ($min, $max)")
def none = min == 0
def contains(x: Int) = isPow2(x) && min <= x && x <= max
def containsLg(x: Int) = contains(1 << x)
def containsLg(x: UInt) =
if (none) false.B
else if (min == max) { log2Ceil(min).U === x }
else { log2Ceil(min).U <= x && x <= log2Ceil(max).U }
def contains(x: TransferSizes) = x.none || (min <= x.min && x.max <= max)
def intersect(x: TransferSizes) =
if (x.max < min || max < x.min) TransferSizes.none
else TransferSizes(scala.math.max(min, x.min), scala.math.min(max, x.max))
// Not a union, because the result may contain sizes contained by neither term
// NOT TO BE CONFUSED WITH COVERPOINTS
def mincover(x: TransferSizes) = {
if (none) {
x
} else if (x.none) {
this
} else {
TransferSizes(scala.math.min(min, x.min), scala.math.max(max, x.max))
}
}
override def toString() = "TransferSizes[%d, %d]".format(min, max)
}
object TransferSizes {
def apply(x: Int) = new TransferSizes(x)
val none = new TransferSizes(0)
def mincover(seq: Seq[TransferSizes]) = seq.foldLeft(none)(_ mincover _)
def intersect(seq: Seq[TransferSizes]) = seq.reduce(_ intersect _)
implicit def asBool(x: TransferSizes) = !x.none
}
// AddressSets specify the address space managed by the manager
// Base is the base address, and mask are the bits consumed by the manager
// e.g: base=0x200, mask=0xff describes a device managing 0x200-0x2ff
// e.g: base=0x1000, mask=0xf0f decribes a device managing 0x1000-0x100f, 0x1100-0x110f, ...
case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
{
// Forbid misaligned base address (and empty sets)
require ((base & mask) == 0, s"Mis-aligned AddressSets are forbidden, got: ${this.toString}")
require (base >= 0, s"AddressSet negative base is ambiguous: $base") // TL2 address widths are not fixed => negative is ambiguous
// We do allow negative mask (=> ignore all high bits)
def contains(x: BigInt) = ((x ^ base) & ~mask) == 0
def contains(x: UInt) = ((x ^ base.U).zext & (~mask).S) === 0.S
// turn x into an address contained in this set
def legalize(x: UInt): UInt = base.U | (mask.U & x)
// overlap iff bitwise: both care (~mask0 & ~mask1) => both equal (base0=base1)
def overlaps(x: AddressSet) = (~(mask | x.mask) & (base ^ x.base)) == 0
// contains iff bitwise: x.mask => mask && contains(x.base)
def contains(x: AddressSet) = ((x.mask | (base ^ x.base)) & ~mask) == 0
// The number of bytes to which the manager must be aligned
def alignment = ((mask + 1) & ~mask)
// Is this a contiguous memory range
def contiguous = alignment == mask+1
def finite = mask >= 0
def max = { require (finite, "Max cannot be calculated on infinite mask"); base | mask }
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// Return an AddressSet that only contains the addresses both sets contain
def intersect(x: AddressSet): Option[AddressSet] = {
if (!overlaps(x)) {
None
} else {
val r_mask = mask & x.mask
val r_base = base | x.base
Some(AddressSet(r_base, r_mask))
}
}
def subtract(x: AddressSet): Seq[AddressSet] = {
intersect(x) match {
case None => Seq(this)
case Some(remove) => AddressSet.enumerateBits(mask & ~remove.mask).map { bit =>
val nmask = (mask & (bit-1)) | remove.mask
val nbase = (remove.base ^ bit) & ~nmask
AddressSet(nbase, nmask)
}
}
}
// AddressSets have one natural Ordering (the containment order, if contiguous)
def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first
val secondary = (x.mask - this.mask).signum // largest mask first
if (primary != 0) primary else secondary
}
// We always want to see things in hex
override def toString() = {
if (mask >= 0) {
"AddressSet(0x%x, 0x%x)".format(base, mask)
} else {
"AddressSet(0x%x, ~0x%x)".format(base, ~mask)
}
}
def toRanges = {
require (finite, "Ranges cannot be calculated on infinite mask")
val size = alignment
val fragments = mask & ~(size-1)
val bits = bitIndexes(fragments)
(BigInt(0) until (BigInt(1) << bits.size)).map { i =>
val off = bitIndexes(i).foldLeft(base) { case (a, b) => a.setBit(bits(b)) }
AddressRange(off, size)
}
}
}
object AddressSet
{
val everything = AddressSet(0, -1)
def misaligned(base: BigInt, size: BigInt, tail: Seq[AddressSet] = Seq()): Seq[AddressSet] = {
if (size == 0) tail.reverse else {
val maxBaseAlignment = base & (-base) // 0 for infinite (LSB)
val maxSizeAlignment = BigInt(1) << log2Floor(size) // MSB of size
val step =
if (maxBaseAlignment == 0 || maxBaseAlignment > maxSizeAlignment)
maxSizeAlignment else maxBaseAlignment
misaligned(base+step, size-step, AddressSet(base, step-1) +: tail)
}
}
def unify(seq: Seq[AddressSet], bit: BigInt): Seq[AddressSet] = {
// Pair terms up by ignoring 'bit'
seq.distinct.groupBy(x => x.copy(base = x.base & ~bit)).map { case (key, seq) =>
if (seq.size == 1) {
seq.head // singleton -> unaffected
} else {
key.copy(mask = key.mask | bit) // pair - widen mask by bit
}
}.toList
}
def unify(seq: Seq[AddressSet]): Seq[AddressSet] = {
val bits = seq.map(_.base).foldLeft(BigInt(0))(_ | _)
AddressSet.enumerateBits(bits).foldLeft(seq) { case (acc, bit) => unify(acc, bit) }.sorted
}
def enumerateMask(mask: BigInt): Seq[BigInt] = {
def helper(id: BigInt, tail: Seq[BigInt]): Seq[BigInt] =
if (id == mask) (id +: tail).reverse else helper(((~mask | id) + 1) & mask, id +: tail)
helper(0, Nil)
}
def enumerateBits(mask: BigInt): Seq[BigInt] = {
def helper(x: BigInt): Seq[BigInt] = {
if (x == 0) {
Nil
} else {
val bit = x & (-x)
bit +: helper(x & ~bit)
}
}
helper(mask)
}
}
case class BufferParams(depth: Int, flow: Boolean, pipe: Boolean)
{
require (depth >= 0, "Buffer depth must be >= 0")
def isDefined = depth > 0
def latency = if (isDefined && !flow) 1 else 0
def apply[T <: Data](x: DecoupledIO[T]) =
if (isDefined) Queue(x, depth, flow=flow, pipe=pipe)
else x
def irrevocable[T <: Data](x: ReadyValidIO[T]) =
if (isDefined) Queue.irrevocable(x, depth, flow=flow, pipe=pipe)
else x
def sq[T <: Data](x: DecoupledIO[T]) =
if (!isDefined) x else {
val sq = Module(new ShiftQueue(x.bits, depth, flow=flow, pipe=pipe))
sq.io.enq <> x
sq.io.deq
}
override def toString() = "BufferParams:%d%s%s".format(depth, if (flow) "F" else "", if (pipe) "P" else "")
}
object BufferParams
{
implicit def apply(depth: Int): BufferParams = BufferParams(depth, false, false)
val default = BufferParams(2)
val none = BufferParams(0)
val flow = BufferParams(1, true, false)
val pipe = BufferParams(1, false, true)
}
case class TriStateValue(value: Boolean, set: Boolean)
{
def update(orig: Boolean) = if (set) value else orig
}
object TriStateValue
{
implicit def apply(value: Boolean): TriStateValue = TriStateValue(value, true)
def unset = TriStateValue(false, false)
}
trait DirectedBuffers[T] {
def copyIn(x: BufferParams): T
def copyOut(x: BufferParams): T
def copyInOut(x: BufferParams): T
}
trait IdMapEntry {
def name: String
def from: IdRange
def to: IdRange
def isCache: Boolean
def requestFifo: Boolean
def maxTransactionsInFlight: Option[Int]
def pretty(fmt: String) =
if (from ne to) { // if the subclass uses the same reference for both from and to, assume its format string has an arity of 5
fmt.format(to.start, to.end, from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
} else {
fmt.format(from.start, from.end, s""""$name"""", if (isCache) " [CACHE]" else "", if (requestFifo) " [FIFO]" else "")
}
}
abstract class IdMap[T <: IdMapEntry] {
protected val fmt: String
val mapping: Seq[T]
def pretty: String = mapping.map(_.pretty(fmt)).mkString(",\n")
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_107( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File MultiHeadedQueue.scala:
package gemmini
import chisel3._
import chisel3.util._
import Util._
class MultiHeadedQueue[T <: Data](gen: T, entries: Int, heads: Int, maxpop: Int = 2) extends Module {
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = new Bundle {
val valid = Output(Vec(heads, Bool()))
val bits = Output(Vec(heads, gen))
val pop = Input(UInt(log2Ceil((entries min maxpop) + 1).W))
}
val len = Output(UInt(log2Ceil(entries+1).W))
})
assert(heads >= 1)
val regs = Reg(Vec(entries, gen))
val raddr = RegInit(0.U((log2Ceil(entries) max 1).W))
val waddr = RegInit(0.U((log2Ceil(entries) max 1).W))
val len = RegInit(0.U(log2Ceil(entries+1).W))
io.enq.ready := len < entries.U
io.len := len
for (i <- 0 until heads) {
io.deq.valid(i) := len > i.U
io.deq.bits(i) := regs(wrappingAdd(raddr, i.U, entries))
}
// Pushing
when (io.enq.fire) {
regs(waddr) := io.enq.bits
waddr := wrappingAdd(waddr, 1.U, entries)
len := len + 1.U
}
// Popping
when(io.deq.pop > 0.U) {
raddr := wrappingAdd(raddr, io.deq.pop, entries)
len := len - io.deq.pop + io.enq.fire
}
assert(io.deq.pop <= len && io.deq.pop <= heads.U && io.deq.pop <= maxpop.U)
}
object MultiHeadedQueue {
def apply[T <: Data](src: ReadyValidIO[T], entries: Int, heads: Int, maxpop: Int=2) = {
val q = Module(new MultiHeadedQueue(src.bits.cloneType, entries, heads, maxpop=maxpop))
q.io.enq <> src
(q.io.deq, q.io.len)
}
}
File LocalAddr.scala:
package gemmini
import chisel3._
import chisel3.util._
class LocalAddr(sp_banks: Int, sp_bank_entries: Int, acc_banks: Int, acc_bank_entries: Int) extends Bundle {
private val localAddrBits = 32 // TODO magic number
private val spAddrBits = log2Ceil(sp_banks * sp_bank_entries)
private val accAddrBits = log2Ceil(acc_banks * acc_bank_entries)
private val maxAddrBits = spAddrBits max accAddrBits
private val spBankBits = log2Up(sp_banks)
private val spBankRowBits = log2Up(sp_bank_entries)
private val accBankBits = log2Up(acc_banks)
val accBankRowBits = log2Up(acc_bank_entries)
val spRows = sp_banks * sp_bank_entries
val is_acc_addr = Bool()
val accumulate = Bool()
val read_full_acc_row = Bool()
val norm_cmd = NormCmd()
private val metadata_w = is_acc_addr.getWidth + accumulate.getWidth + read_full_acc_row.getWidth + norm_cmd.getWidth
assert(maxAddrBits + metadata_w < 32)
val garbage = UInt(((localAddrBits - maxAddrBits - metadata_w - 1) max 0).W)
val garbage_bit = if (localAddrBits - maxAddrBits >= metadata_w + 1) UInt(1.W) else UInt(0.W)
val data = UInt(maxAddrBits.W)
def sp_bank(dummy: Int = 0) = if (spAddrBits == spBankRowBits) 0.U else data(spAddrBits - 1, spBankRowBits)
def sp_row(dummy: Int = 0) = data(spBankRowBits - 1, 0)
def acc_bank(dummy: Int = 0) = if (accAddrBits == accBankRowBits) 0.U else data(accAddrBits - 1, accBankRowBits)
def acc_row(dummy: Int = 0) = data(accBankRowBits - 1, 0)
def full_sp_addr(dummy: Int = 0) = data(spAddrBits - 1, 0)
def full_acc_addr(dummy: Int = 0) = data(accAddrBits - 1, 0)
def is_same_address(other: LocalAddr): Bool = is_acc_addr === other.is_acc_addr && data === other.data
def is_same_address(other: UInt): Bool = is_same_address(other.asTypeOf(this))
def is_garbage(dummy: Int = 0) = is_acc_addr && accumulate && read_full_acc_row && data.andR &&
(if (garbage_bit.getWidth > 0) garbage_bit.asBool else true.B)
def +(other: UInt) = {
require(isPow2(sp_bank_entries)) // TODO remove this requirement
require(isPow2(acc_bank_entries)) // TODO remove this requirement
val result = WireInit(this)
result.data := data + other
result
}
def <=(other: LocalAddr) =
is_acc_addr === other.is_acc_addr &&
Mux(is_acc_addr, full_acc_addr() <= other.full_acc_addr(), full_sp_addr() <= other.full_sp_addr())
def <(other: LocalAddr) =
is_acc_addr === other.is_acc_addr &&
Mux(is_acc_addr, full_acc_addr() < other.full_acc_addr(), full_sp_addr() < other.full_sp_addr())
def >(other: LocalAddr) =
is_acc_addr === other.is_acc_addr &&
Mux(is_acc_addr, full_acc_addr() > other.full_acc_addr(), full_sp_addr() > other.full_sp_addr())
def add_with_overflow(other: UInt): Tuple2[LocalAddr, Bool] = {
require(isPow2(sp_bank_entries)) // TODO remove this requirement
require(isPow2(acc_bank_entries)) // TODO remove this requirement
val sum = data +& other
val overflow = Mux(is_acc_addr, sum(accAddrBits), sum(spAddrBits))
val result = WireInit(this)
result.data := sum(maxAddrBits - 1, 0)
(result, overflow)
}
// This function can only be used with non-accumulator addresses. Returns both new address and underflow
def floorSub(other: UInt, floor: UInt): (LocalAddr, Bool) = {
require(isPow2(sp_bank_entries)) // TODO remove this requirement
require(isPow2(acc_bank_entries)) // TODO remove this requirement
val underflow = data < (floor +& other)
val result = WireInit(this)
result.data := Mux(underflow, floor, data - other)
(result, underflow)
}
def make_this_garbage(dummy: Int = 0): Unit = {
is_acc_addr := true.B
accumulate := true.B
read_full_acc_row := true.B
garbage_bit := 1.U
data := ~(0.U(maxAddrBits.W))
}
}
object LocalAddr {
def cast_to_local_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = {
// This convenience function is basically the same as calling "asTypeOf(local_addr_t)". However, this convenience
// function will also cast unnecessary garbage bits to 0, which may help reduce multiplier/adder bitwidths
val result = WireInit(t.asTypeOf(local_addr_t))
if (result.garbage_bit.getWidth > 0) result.garbage := 0.U
result
}
def cast_to_sp_addr[T <: Data](local_addr_t: LocalAddr, t: T): LocalAddr = {
// This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage
// address
val result = WireInit(cast_to_local_addr(local_addr_t, t))
result.is_acc_addr := false.B
result.accumulate := false.B
result.read_full_acc_row := false.B
// assert(!result.garbage_bit, "cast_to_sp_addr doesn't work on garbage addresses")
result
}
def cast_to_acc_addr[T <: Data](local_addr_t: LocalAddr, t: T, accumulate: Bool, read_full: Bool): LocalAddr = {
// This function is a wrapper around cast_to_local_addr, but it assumes that the input will not be the garbage
// address
val result = WireInit(cast_to_local_addr(local_addr_t, t))
result.is_acc_addr := true.B
result.accumulate := accumulate
result.read_full_acc_row := read_full
// assert(!result.garbage_bit, "cast_to_acc_addr doesn't work on garbage addresses")
result
}
def garbage_addr(local_addr_t: LocalAddr): LocalAddr = {
val result = Wire(chiselTypeOf(local_addr_t))
result := DontCare
result.make_this_garbage()
result
}
}
File Arithmetic.scala:
// A simple type class for Chisel datatypes that can add and multiply. To add your own type, simply create your own:
// implicit MyTypeArithmetic extends Arithmetic[MyType] { ... }
package gemmini
import chisel3._
import chisel3.util._
import hardfloat._
// Bundles that represent the raw bits of custom datatypes
case class Float(expWidth: Int, sigWidth: Int) extends Bundle {
val bits = UInt((expWidth + sigWidth).W)
val bias: Int = (1 << (expWidth-1)) - 1
}
case class DummySInt(w: Int) extends Bundle {
val bits = UInt(w.W)
def dontCare: DummySInt = {
val o = Wire(new DummySInt(w))
o.bits := 0.U
o
}
}
// The Arithmetic typeclass which implements various arithmetic operations on custom datatypes
abstract class Arithmetic[T <: Data] {
implicit def cast(t: T): ArithmeticOps[T]
}
abstract class ArithmeticOps[T <: Data](self: T) {
def *(t: T): T
def mac(m1: T, m2: T): T // Returns (m1 * m2 + self)
def +(t: T): T
def -(t: T): T
def >>(u: UInt): T // This is a rounding shift! Rounds away from 0
def >(t: T): Bool
def identity: T
def withWidthOf(t: T): T
def clippedToWidthOf(t: T): T // Like "withWidthOf", except that it saturates
def relu: T
def zero: T
def minimum: T
// Optional parameters, which only need to be defined if you want to enable various optimizations for transformers
def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[T])] = None
def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = None
def mult_with_reciprocal[U <: Data](reciprocal: U) = self
}
object Arithmetic {
implicit object UIntArithmetic extends Arithmetic[UInt] {
override implicit def cast(self: UInt) = new ArithmeticOps(self) {
override def *(t: UInt) = self * t
override def mac(m1: UInt, m2: UInt) = m1 * m2 + self
override def +(t: UInt) = self + t
override def -(t: UInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = point_five & (zeros | ones_digit)
(self >> u).asUInt + r
}
override def >(t: UInt): Bool = self > t
override def withWidthOf(t: UInt) = self.asTypeOf(t)
override def clippedToWidthOf(t: UInt) = {
val sat = ((1 << (t.getWidth-1))-1).U
Mux(self > sat, sat, self)(t.getWidth-1, 0)
}
override def relu: UInt = self
override def zero: UInt = 0.U
override def identity: UInt = 1.U
override def minimum: UInt = 0.U
}
}
implicit object SIntArithmetic extends Arithmetic[SInt] {
override implicit def cast(self: SInt) = new ArithmeticOps(self) {
override def *(t: SInt) = self * t
override def mac(m1: SInt, m2: SInt) = m1 * m2 + self
override def +(t: SInt) = self + t
override def -(t: SInt) = self - t
override def >>(u: UInt) = {
// The equation we use can be found here: https://riscv.github.io/documents/riscv-v-spec/#_vector_fixed_point_rounding_mode_register_vxrm
// TODO Do we need to explicitly handle the cases where "u" is a small number (like 0)? What is the default behavior here?
val point_five = Mux(u === 0.U, 0.U, self(u - 1.U))
val zeros = Mux(u <= 1.U, 0.U, self.asUInt & ((1.U << (u - 1.U)).asUInt - 1.U)) =/= 0.U
val ones_digit = self(u)
val r = (point_five & (zeros | ones_digit)).asBool
(self >> u).asSInt + Mux(r, 1.S, 0.S)
}
override def >(t: SInt): Bool = self > t
override def withWidthOf(t: SInt) = {
if (self.getWidth >= t.getWidth)
self(t.getWidth-1, 0).asSInt
else {
val sign_bits = t.getWidth - self.getWidth
val sign = self(self.getWidth-1)
Cat(Cat(Seq.fill(sign_bits)(sign)), self).asTypeOf(t)
}
}
override def clippedToWidthOf(t: SInt): SInt = {
val maxsat = ((1 << (t.getWidth-1))-1).S
val minsat = (-(1 << (t.getWidth-1))).S
MuxCase(self, Seq((self > maxsat) -> maxsat, (self < minsat) -> minsat))(t.getWidth-1, 0).asSInt
}
override def relu: SInt = Mux(self >= 0.S, self, 0.S)
override def zero: SInt = 0.S
override def identity: SInt = 1.S
override def minimum: SInt = (-(1 << (self.getWidth-1))).S
override def divider(denom_t: UInt, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(denom_t.cloneType))
val output = Wire(Decoupled(self.cloneType))
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def sin_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def uin_to_float(x: UInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := x
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = sin_to_float(self)
val denom_rec = uin_to_float(input.bits)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := self_rec
divider.io.b := denom_rec
divider.io.roundingMode := consts.round_minMag
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := float_to_in(divider.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def sqrt: Option[(DecoupledIO[UInt], DecoupledIO[SInt])] = {
// TODO this uses a floating point divider, but we should use an integer divider instead
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(self.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
val expWidth = log2Up(self.getWidth) + 1
val sigWidth = self.getWidth
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag // consts.round_near_maxMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
// Instantiate the hardloat sqrt
val sqrter = Module(new DivSqrtRecFN_small(expWidth, sigWidth, 0))
input.ready := sqrter.io.inReady
sqrter.io.inValid := input.valid
sqrter.io.sqrtOp := true.B
sqrter.io.a := self_rec
sqrter.io.b := DontCare
sqrter.io.roundingMode := consts.round_minMag
sqrter.io.detectTininess := consts.tininess_afterRounding
output.valid := sqrter.io.outValid_sqrt
output.bits := float_to_in(sqrter.io.out)
assert(!output.valid || output.ready)
Some((input, output))
}
override def reciprocal[U <: Data](u: U, options: Int = 0): Option[(DecoupledIO[UInt], DecoupledIO[U])] = u match {
case Float(expWidth, sigWidth) =>
val input = Wire(Decoupled(UInt(0.W)))
val output = Wire(Decoupled(u.cloneType))
input.bits := DontCare
// We translate our integer to floating-point form so that we can use the hardfloat divider
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
val self_rec = in_to_float(self)
val one_rec = in_to_float(1.S)
// Instantiate the hardloat divider
val divider = Module(new DivSqrtRecFN_small(expWidth, sigWidth, options))
input.ready := divider.io.inReady
divider.io.inValid := input.valid
divider.io.sqrtOp := false.B
divider.io.a := one_rec
divider.io.b := self_rec
divider.io.roundingMode := consts.round_near_even
divider.io.detectTininess := consts.tininess_afterRounding
output.valid := divider.io.outValid_div
output.bits := fNFromRecFN(expWidth, sigWidth, divider.io.out).asTypeOf(u)
assert(!output.valid || output.ready)
Some((input, output))
case _ => None
}
override def mult_with_reciprocal[U <: Data](reciprocal: U): SInt = reciprocal match {
case recip @ Float(expWidth, sigWidth) =>
def in_to_float(x: SInt) = {
val in_to_rec_fn = Module(new INToRecFN(intWidth = self.getWidth, expWidth, sigWidth))
in_to_rec_fn.io.signedIn := true.B
in_to_rec_fn.io.in := x.asUInt
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
in_to_rec_fn.io.out
}
def float_to_in(x: UInt) = {
val rec_fn_to_in = Module(new RecFNToIN(expWidth = expWidth, sigWidth, self.getWidth))
rec_fn_to_in.io.signedOut := true.B
rec_fn_to_in.io.in := x
rec_fn_to_in.io.roundingMode := consts.round_minMag
rec_fn_to_in.io.out.asSInt
}
val self_rec = in_to_float(self)
val reciprocal_rec = recFNFromFN(expWidth, sigWidth, recip.bits)
// Instantiate the hardloat divider
val muladder = Module(new MulRecFN(expWidth, sigWidth))
muladder.io.roundingMode := consts.round_near_even
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := reciprocal_rec
float_to_in(muladder.io.out)
case _ => self
}
}
}
implicit object FloatArithmetic extends Arithmetic[Float] {
// TODO Floating point arithmetic currently switches between recoded and standard formats for every operation. However, it should stay in the recoded format as it travels through the systolic array
override implicit def cast(self: Float): ArithmeticOps[Float] = new ArithmeticOps(self) {
override def *(t: Float): Float = {
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := t_rec_resized
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def mac(m1: Float, m2: Float): Float = {
// Recode all operands
val m1_rec = recFNFromFN(m1.expWidth, m1.sigWidth, m1.bits)
val m2_rec = recFNFromFN(m2.expWidth, m2.sigWidth, m2.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize m1 to self's width
val m1_resizer = Module(new RecFNToRecFN(m1.expWidth, m1.sigWidth, self.expWidth, self.sigWidth))
m1_resizer.io.in := m1_rec
m1_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m1_resizer.io.detectTininess := consts.tininess_afterRounding
val m1_rec_resized = m1_resizer.io.out
// Resize m2 to self's width
val m2_resizer = Module(new RecFNToRecFN(m2.expWidth, m2.sigWidth, self.expWidth, self.sigWidth))
m2_resizer.io.in := m2_rec
m2_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
m2_resizer.io.detectTininess := consts.tininess_afterRounding
val m2_rec_resized = m2_resizer.io.out
// Perform multiply-add
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := m1_rec_resized
muladder.io.b := m2_rec_resized
muladder.io.c := self_rec
// Convert result to standard format // TODO remove these intermediate recodings
val out = Wire(Float(self.expWidth, self.sigWidth))
out.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
out
}
override def +(t: Float): Float = {
require(self.getWidth >= t.getWidth) // This just makes it easier to write the resizing code
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Generate 1 as a float
val in_to_rec_fn = Module(new INToRecFN(1, self.expWidth, self.sigWidth))
in_to_rec_fn.io.signedIn := false.B
in_to_rec_fn.io.in := 1.U
in_to_rec_fn.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
in_to_rec_fn.io.detectTininess := consts.tininess_afterRounding
val one_rec = in_to_rec_fn.io.out
// Resize t
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
// Perform addition
val muladder = Module(new MulAddRecFN(self.expWidth, self.sigWidth))
muladder.io.op := 0.U
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := t_rec_resized
muladder.io.b := one_rec
muladder.io.c := self_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def -(t: Float): Float = {
val t_sgn = t.bits(t.getWidth-1)
val neg_t = Cat(~t_sgn, t.bits(t.getWidth-2,0)).asTypeOf(t)
self + neg_t
}
override def >>(u: UInt): Float = {
// Recode self
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Get 2^(-u) as a recoded float
val shift_exp = Wire(UInt(self.expWidth.W))
shift_exp := self.bias.U - u
val shift_fn = Cat(0.U(1.W), shift_exp, 0.U((self.sigWidth-1).W))
val shift_rec = recFNFromFN(self.expWidth, self.sigWidth, shift_fn)
assert(shift_exp =/= 0.U, "scaling by denormalized numbers is not currently supported")
// Multiply self and 2^(-u)
val muladder = Module(new MulRecFN(self.expWidth, self.sigWidth))
muladder.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
muladder.io.detectTininess := consts.tininess_afterRounding
muladder.io.a := self_rec
muladder.io.b := shift_rec
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := fNFromRecFN(self.expWidth, self.sigWidth, muladder.io.out)
result
}
override def >(t: Float): Bool = {
// Recode all operands
val t_rec = recFNFromFN(t.expWidth, t.sigWidth, t.bits)
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
// Resize t to self's width
val t_resizer = Module(new RecFNToRecFN(t.expWidth, t.sigWidth, self.expWidth, self.sigWidth))
t_resizer.io.in := t_rec
t_resizer.io.roundingMode := consts.round_near_even
t_resizer.io.detectTininess := consts.tininess_afterRounding
val t_rec_resized = t_resizer.io.out
val comparator = Module(new CompareRecFN(self.expWidth, self.sigWidth))
comparator.io.a := self_rec
comparator.io.b := t_rec_resized
comparator.io.signaling := false.B
comparator.io.gt
}
override def withWidthOf(t: Float): Float = {
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def clippedToWidthOf(t: Float): Float = {
// TODO check for overflow. Right now, we just assume that overflow doesn't happen
val self_rec = recFNFromFN(self.expWidth, self.sigWidth, self.bits)
val resizer = Module(new RecFNToRecFN(self.expWidth, self.sigWidth, t.expWidth, t.sigWidth))
resizer.io.in := self_rec
resizer.io.roundingMode := consts.round_near_even // consts.round_near_maxMag
resizer.io.detectTininess := consts.tininess_afterRounding
val result = Wire(Float(t.expWidth, t.sigWidth))
result.bits := fNFromRecFN(t.expWidth, t.sigWidth, resizer.io.out)
result
}
override def relu: Float = {
val raw = rawFloatFromFN(self.expWidth, self.sigWidth, self.bits)
val result = Wire(Float(self.expWidth, self.sigWidth))
result.bits := Mux(!raw.isZero && raw.sign, 0.U, self.bits)
result
}
override def zero: Float = 0.U.asTypeOf(self)
override def identity: Float = Cat(0.U(2.W), ~(0.U((self.expWidth-1).W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
override def minimum: Float = Cat(1.U, ~(0.U(self.expWidth.W)), 0.U((self.sigWidth-1).W)).asTypeOf(self)
}
}
implicit object DummySIntArithmetic extends Arithmetic[DummySInt] {
override implicit def cast(self: DummySInt) = new ArithmeticOps(self) {
override def *(t: DummySInt) = self.dontCare
override def mac(m1: DummySInt, m2: DummySInt) = self.dontCare
override def +(t: DummySInt) = self.dontCare
override def -(t: DummySInt) = self.dontCare
override def >>(t: UInt) = self.dontCare
override def >(t: DummySInt): Bool = false.B
override def identity = self.dontCare
override def withWidthOf(t: DummySInt) = self.dontCare
override def clippedToWidthOf(t: DummySInt) = self.dontCare
override def relu = self.dontCare
override def zero = self.dontCare
override def minimum: DummySInt = self.dontCare
}
}
}
File Util.scala:
package gemmini
import chisel3._
import chisel3.util._
object Util {
def wrappingAdd(u: UInt, n: UInt, max_plus_one: Int): UInt = {
val max = max_plus_one - 1
if (max == 0) {
0.U
} else {
assert(n <= max.U, "cannot wrapAdd when n is larger than max")
Mux(u >= max.U - n + 1.U && n =/= 0.U, n - (max.U - u) - 1.U, u + n)
}
}
def wrappingAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = {
val max = max_plus_one - 1.U
assert(n <= max || max === 0.U, "cannot wrapAdd when n is larger than max, unless max is 0")
/*
Mux(!en, u,
Mux (max === 0.U, 0.U,
Mux(u >= max - n + 1.U && n =/= 0.U, n - (max - u) - 1.U, u + n)))
*/
MuxCase(u + n, Seq(
(!en) -> u,
(max === 0.U) -> 0.U,
(u >= max - n + 1.U && n =/= 0.U) -> (n - (max - u) - 1.U)
))
}
def satAdd(u: UInt, v: UInt, max: UInt): UInt = {
Mux(u +& v > max, max, u + v)
}
def floorAdd(u: UInt, n: UInt, max_plus_one: UInt, en: Bool = true.B): UInt = {
val max = max_plus_one - 1.U
MuxCase(u + n, Seq(
(!en) -> u,
((u +& n) > max) -> 0.U
))
}
def sFloorAdd(s: SInt, n: UInt, max_plus_one: SInt, min: SInt, en: Bool = true.B): SInt = {
val max = max_plus_one - 1.S
MuxCase(s + n.zext, Seq(
(!en) -> s,
((s +& n.zext) > max) -> min
))
}
def wrappingSub(u: UInt, n: UInt, max_plus_one: Int): UInt = {
val max = max_plus_one - 1
assert(n <= max.U, "cannot wrapSub when n is larger than max")
Mux(u < n, max.U - (n-u) + 1.U, u - n)
}
def ceilingDivide(numer: Int, denom: Int): Int = {
if (numer % denom == 0) { numer / denom }
else { numer / denom + 1}
}
def closestLowerPowerOf2(u: UInt): UInt = {
// TODO figure out a more efficient way of doing this. Is this many muxes really necessary?
val exp = u.asBools.zipWithIndex.map { case (b, i) =>
Mux(b, i.U, 0.U)
}.reduce((acc, u) => Mux(acc > u, acc, u))
(1.U << exp).asUInt
}
def closestAlignedLowerPowerOf2(u: UInt, addr: UInt, stride: UInt, rowBytes: Int): UInt = {
val lgRowBytes = log2Ceil(rowBytes)
// TODO figure out a more efficient way of doing this. Is this many muxes really necessary?
val exp = u.asBools.zipWithIndex.map { case (b, i) =>
Mux(b && addr(i + lgRowBytes - 1, 0) === 0.U && stride(i + lgRowBytes - 1, 0) === 0.U, i.U, 0.U)
}.reduce((acc, u) => Mux(acc > u, acc, u))
(1.U << exp).asUInt
}
// This function will return "next" with a 0-cycle delay when the "enable" signal is high. It's like a queue with
// the "pipe" and "flow" parameters set to "true"
def RegEnableThru[T <: Data](next: T, enable: Bool): T = {
val buf = RegEnable(next, enable)
Mux(enable, next, buf)
}
def RegEnableThru[T <: Data](next: T, init: T, enable: Bool): T = {
val buf = RegEnable(next, init, enable)
Mux(enable, next, buf)
}
def maxOf(u1: UInt, u2: UInt): UInt = {
Mux(u1 > u2, u1, u2)
}
def maxOf[T <: Data](x: T, y: T)(implicit ev: Arithmetic[T]): T = {
import ev._
Mux(x > y, x, y)
}
def minOf(u1: UInt, u2: UInt): UInt = {
Mux(u1 < u2, u1, u2)
}
def accumulateTree[T <: Data](xs: Seq[T])(implicit ev: Arithmetic[T]): T = {
import ev._
assert(xs.nonEmpty, "can't accumulate 0 elements")
if (xs.length == 1) {
xs.head
} else {
val upperRowLen = 1 << log2Ceil(xs.length)
val upperRow = xs.padTo(upperRowLen, xs.head.zero)
val pairs = upperRow.grouped(2)
val lowerRow = pairs.map { case Seq(a, b) => a + b }
accumulateTree(lowerRow.toSeq)
}
}
// An undirectioned Valid bundle
class UDValid[T <: Data](t: T) extends Bundle {
val valid = Bool()
val bits = t.cloneType
def push(b: T): Unit = {
valid := true.B
bits := b
}
def pop(dummy: Int = 0): T = {
valid := false.B
bits
}
}
object UDValid {
def apply[T <: Data](t: T): UDValid[T] = new UDValid(t)
}
// creates a Reg and the next-state Wire, and returns both
def regwire(bits: Int) = {
val wire = Wire(UInt(bits.W))
val reg = RegNext(wire)
wire := reg // default wire to read from reg
(reg, wire)
}
}
File ExecuteController.scala:
package gemmini
import chisel3._
import chisel3.util._
import GemminiISA._
import Util._
import org.chipsalliance.cde.config.Parameters
import midas.targetutils.PerfCounter
// TODO do we still need to flush when the dataflow is weight stationary? Won't the result just keep travelling through on its own?
class ExecuteController[T <: Data, U <: Data, V <: Data](xLen: Int, tagWidth: Int, config: GemminiArrayConfig[T, U, V])
(implicit p: Parameters, ev: Arithmetic[T]) extends Module {
import config._
import ev._
val io = IO(new Bundle {
val cmd = Flipped(Decoupled(new GemminiCmd(reservation_station_entries)))
val im2col = new Bundle {
val req = Decoupled(new Im2ColReadReq(config))
val resp = Flipped(Decoupled(new Im2ColReadResp(config)))
}
val srams = new Bundle {
val read = Vec(sp_banks, new ScratchpadReadIO(sp_bank_entries, sp_width))
val write = Vec(sp_banks, new ScratchpadWriteIO(sp_bank_entries, sp_width, (sp_width / (aligned_to * 8)) max 1))
}
val acc = new Bundle {
val read_req = Vec(acc_banks, Decoupled(new AccumulatorReadReq(
acc_bank_entries, accType, acc_scale_t
)))
val read_resp = Flipped(Vec(acc_banks, Decoupled(new AccumulatorScaleResp(
Vec(meshColumns, Vec(tileColumns, inputType)),
Vec(meshColumns, Vec(tileColumns, accType))
))))
// val write = Vec(acc_banks, new AccumulatorWriteIO(acc_bank_entries, Vec(meshColumns, Vec(tileColumns, accType))))
val write = Vec(acc_banks, Decoupled(new AccumulatorWriteReq(acc_bank_entries, Vec(meshColumns, Vec(tileColumns, accType)))))
}
val completed = Valid(UInt(log2Up(reservation_station_entries).W))
val busy = Output(Bool())
val counter = new CounterEventIO()
})
val block_size = meshRows*tileRows
val mesh_tag = new Bundle with TagQueueTag {
val rob_id = UDValid(UInt(log2Up(reservation_station_entries).W))
val addr = local_addr_t.cloneType
val rows = UInt(log2Up(block_size + 1).W)
val cols = UInt(log2Up(block_size + 1).W)
override def make_this_garbage(dummy: Int = 0): Unit = {
rob_id.valid := false.B
addr.make_this_garbage()
}
}
val unrolled_cmd = TransposePreloadUnroller(io.cmd, config, io.counter)
val cmd_q_heads = 3
assert(ex_queue_length >= cmd_q_heads)
// val (cmd, _) = MultiHeadedQueue(io.cmd, ex_queue_length, cmd_q_heads)
val (cmd, _) = MultiHeadedQueue(unrolled_cmd, ex_queue_length, cmd_q_heads)
cmd.pop := 0.U
// STATE defines
val waiting_for_cmd :: compute :: flush :: flushing :: Nil = Enum(4)
val control_state = RegInit(waiting_for_cmd)
// Instruction-related variables
val current_dataflow = if (dataflow == Dataflow.BOTH) Reg(UInt(1.W)) else dataflow.id.U
val functs = cmd.bits.map(_.cmd.inst.funct)
val rs1s = VecInit(cmd.bits.map(_.cmd.rs1))
val rs2s = VecInit(cmd.bits.map(_.cmd.rs2))
val DoConfig = functs(0) === CONFIG_CMD
val DoComputes = functs.map(f => f === COMPUTE_AND_FLIP_CMD || f === COMPUTE_AND_STAY_CMD)
val DoPreloads = functs.map(_ === PRELOAD_CMD)
val preload_cmd_place = Mux(DoPreloads(0), 0.U, 1.U)
// val a_address_place = Mux(current_dataflow === Dataflow.WS.id.U, 0.U, Mux(preload_cmd_place === 0.U, 1.U, 2.U))
val in_prop = functs(0) === COMPUTE_AND_FLIP_CMD
val in_prop_flush = Reg(Bool())
when (current_dataflow === Dataflow.WS.id.U) {
in_prop_flush := false.B
}
val ocol = RegInit(0.U(8.W))
val orow = RegInit(0.U(8.W))
val krow = RegInit(0.U(4.W))
val weight_stride = RegInit(0.U(3.W))
val channel = RegInit(0.U(9.W))
val row_turn = RegInit(0.U(11.W))
val row_left = RegInit(0.U(4.W))
val kdim2 = RegInit(0.U(8.W))
val weight_double_bank = RegInit(false.B)
val weight_triple_bank = RegInit(false.B)
val icol = WireInit(0.U(9.W))
val irow = WireInit(0.U(9.W))
icol := ((ocol - 1.U) * weight_stride + krow)//.asSInt
irow := ((orow - 1.U) * weight_stride + krow)//.asSInt
val im2col_turn = WireInit(0.U(9.W))
val in_shift = Reg(UInt(log2Up(accType.getWidth).W))
val acc_scale = Reg(acc_scale_t)
val activation = if (has_nonlinear_activations) Reg(UInt(Activation.bitwidth.W)) else Activation.NONE // TODO magic number
val a_transpose = Reg(Bool())
val bd_transpose = Reg(Bool())
val config_initialized = RegInit(false.B)
val a_should_be_fed_into_transposer = Mux(current_dataflow === Dataflow.OS.id.U, !a_transpose, a_transpose)
val a_address_place = Mux(preload_cmd_place === 0.U, 1.U, Mux(a_should_be_fed_into_transposer, 2.U, 0.U))
val b_should_be_fed_into_transposer = current_dataflow === Dataflow.OS.id.U && bd_transpose
val b_address_place = Mux(preload_cmd_place === 0.U, 1.U, Mux(b_should_be_fed_into_transposer, 2.U, 0.U))
val d_should_be_fed_into_transposer = current_dataflow === Dataflow.WS.id.U && bd_transpose
assert(!(config_initialized &&
(a_should_be_fed_into_transposer +& b_should_be_fed_into_transposer +& d_should_be_fed_into_transposer) > 1.U),
"Too many inputs are being fed into the single transposer we have")
//fix by input
val im2col_en = config.hasIm2Col.B && weight_stride =/= 0.U
// SRAM addresses of matmul operands
val a_address_rs1 = rs1s(a_address_place).asTypeOf(local_addr_t)
val b_address_rs2 = rs2s(b_address_place).asTypeOf(local_addr_t)
val d_address_rs1 = rs1s(preload_cmd_place).asTypeOf(local_addr_t)
val c_address_rs2 = rs2s(preload_cmd_place).asTypeOf(local_addr_t)
if (dataflow == Dataflow.OS && hardcode_d_to_garbage_addr) {
d_address_rs1.make_this_garbage()
} else if (dataflow == Dataflow.WS && hardcode_d_to_garbage_addr) {
b_address_rs2.make_this_garbage()
}
val multiply_garbage = a_address_rs1.is_garbage()
val accumulate_zeros = b_address_rs2.is_garbage()
val preload_zeros = d_address_rs1.is_garbage()
val a_cols_default = rs1s(a_address_place)(32 + log2Up(block_size + 1) - 1, 32) // TODO magic numbers
val a_rows_default = rs1s(a_address_place)(48 + log2Up(block_size + 1) - 1, 48) // TODO magic numbers
val b_cols_default = rs2s(b_address_place)(32 + log2Up(block_size + 1) - 1, 32) // TODO magic numbers
val b_rows_default = rs2s(b_address_place)(48 + log2Up(block_size + 1) - 1, 48) // TODO magic numbers
val d_cols_default = rs1s(preload_cmd_place)(32 + log2Up(block_size + 1) - 1, 32) // TODO magic numbers
val d_rows_default = rs1s(preload_cmd_place)(48 + log2Up(block_size + 1) - 1, 48) // TODO magic numbers
val a_cols = Mux(a_transpose, a_rows_default, a_cols_default)
val a_rows = Mux(a_transpose, a_cols_default, a_rows_default)
val b_cols = Mux(current_dataflow === Dataflow.OS.id.U && bd_transpose, b_rows_default, b_cols_default)
val b_rows = Mux(current_dataflow === Dataflow.OS.id.U && bd_transpose, b_cols_default, b_rows_default)
val d_cols = Mux(current_dataflow === Dataflow.WS.id.U && bd_transpose, d_rows_default, d_cols_default)
val d_rows = Mux(current_dataflow === Dataflow.WS.id.U && bd_transpose, d_cols_default, d_rows_default)
val c_cols = rs2s(preload_cmd_place)(32 + log2Up(block_size + 1) - 1, 32) // TODO magic numbers
val c_rows = rs2s(preload_cmd_place)(48 + log2Up(block_size + 1) - 1, 48) // TODO magic numbers
// Dependency stuff
io.completed.valid := false.B
io.completed.bits := DontCare
// val pending_completed_rob_id = Reg(UDValid(UInt(log2Up(rob_entries).W)))
val pending_completed_rob_ids = Reg(Vec(2, UDValid(UInt(log2Up(reservation_station_entries).W))))
// Instantiate a queue which queues up signals which must be fed into the mesh
val mesh_cntl_signals_q = Module(new Queue(new ComputeCntlSignals, spad_read_delay+1,
pipe=true))
val cntl_ready = mesh_cntl_signals_q.io.enq.ready
val cntl_valid = mesh_cntl_signals_q.io.deq.valid
val cntl = mesh_cntl_signals_q.io.deq.bits
// Instantiate the actual mesh
val mesh = Module(new MeshWithDelays(inputType, spatialArrayOutputType, accType, mesh_tag, dataflow, tree_reduction, tile_latency, mesh_output_delay,
tileRows, tileColumns, meshRows, meshColumns, shifter_banks, shifter_banks))
mesh.io.a.valid := false.B
mesh.io.b.valid := false.B
mesh.io.d.valid := false.B
mesh.io.req.valid := control_state === flush
mesh.io.a.bits := DontCare
mesh.io.b.bits := DontCare
mesh.io.d.bits := DontCare
mesh.io.req.bits.tag := DontCare
mesh.io.req.bits.tag.cols := cntl.c_cols
mesh.io.req.bits.tag.rows := cntl.c_rows
mesh.io.req.bits.total_rows := block_size.U
mesh.io.req.bits.pe_control.propagate := Mux(control_state === flush, in_prop_flush, cntl.prop)
mesh.io.req.bits.pe_control.dataflow := cntl.dataflow
mesh.io.req.bits.pe_control.shift := cntl.shift
mesh.io.req.bits.a_transpose := cntl.a_transpose
mesh.io.req.bits.bd_transpose := cntl.bd_transpose
mesh.io.req.bits.tag.rob_id := cntl.rob_id
mesh.io.req.bits.flush := Mux(control_state === flush && !cntl_valid, 1.U, 0.U) // We want to make sure that the mesh has absorbed all inputs before flushing
// Hazards
val raw_hazards_are_impossible = !ex_read_from_acc && !ex_write_to_spad // Special case where RAW hazards are impossible
val raw_hazard_pre = mesh.io.tags_in_progress.map { t =>
val is_garbage = t.addr.is_garbage()
val pre_raw_haz = t.addr.is_same_address(rs1s(0))
val mul_raw_haz = t.addr.is_same_address(rs1s(1)) || t.addr.is_same_address(rs2s(1))
!is_garbage && (pre_raw_haz || mul_raw_haz) && !raw_hazards_are_impossible.B
}.reduce(_ || _)
val raw_hazard_mulpre = mesh.io.tags_in_progress.map { t =>
val is_garbage = t.addr.is_garbage()
val pre_raw_haz = t.addr.is_same_address(rs1s(1))
val mul_raw_haz = t.addr.is_same_address(rs1s(2)) || t.addr.is_same_address(rs2s(2))
!is_garbage && (mul_raw_haz || pre_raw_haz) && !raw_hazards_are_impossible.B
}.reduce(_ || _)
val third_instruction_needed = a_address_place > 1.U || b_address_place > 1.U || preload_cmd_place > 1.U || !raw_hazards_are_impossible.B
val matmul_in_progress = mesh.io.tags_in_progress.map(_.rob_id.valid).reduce(_ || _)
io.busy := cmd.valid(0) || matmul_in_progress
// SRAM scratchpad
// Fire counters which resolve same-bank accesses
val a_fire_counter = Reg(UInt(log2Up(block_size).W))
val b_fire_counter = Reg(UInt(log2Up(block_size).W))
val d_fire_counter = Reg(UInt(log2Up(block_size).W))
val a_fire_started = RegInit(false.B)
val d_fire_started = RegInit(false.B)
val b_fire_started = RegInit(false.B)
// "A" stride variables
val a_addr_offset = Reg(UInt((16 + log2Up(block_size)).W))
val a_addr_stride = Reg(UInt(16.W)) // TODO magic numbers
// "C" stride variables
val c_addr_stride = Reg(UInt(16.W)) // TODO magic numbers
val a_address = a_address_rs1 + a_addr_offset
val b_address = b_address_rs2 + b_fire_counter
val d_address = d_address_rs1 + (block_size.U - 1.U - d_fire_counter)
val dataAbank = a_address.sp_bank()
val dataBbank = b_address.sp_bank()
val dataDbank = d_address.sp_bank()
val dataABankAcc = a_address.acc_bank()
val dataBBankAcc = b_address.acc_bank()
val dataDBankAcc = d_address.acc_bank()
val a_read_from_acc = ex_read_from_acc.B && a_address_rs1.is_acc_addr
val b_read_from_acc = ex_read_from_acc.B && b_address_rs2.is_acc_addr
val d_read_from_acc = ex_read_from_acc.B && d_address_rs1.is_acc_addr
val start_inputting_a = WireInit(false.B)
val start_inputting_b = WireInit(false.B)
val start_inputting_d = WireInit(false.B)
val start_array_outputting = WireInit(false.B)
val a_garbage = a_address_rs1.is_garbage() || !start_inputting_a
val b_garbage = b_address_rs2.is_garbage() || !start_inputting_b
val d_garbage = d_address_rs1.is_garbage() || !start_inputting_d
// TODO merge these into one enum
val perform_single_preload = RegInit(false.B)
val perform_single_mul = RegInit(false.B)
val perform_mul_pre = RegInit(false.B)
val performing_single_preload = WireInit(perform_single_preload && control_state === compute)
val performing_single_mul = WireInit(perform_single_mul && control_state === compute)
val performing_mul_pre = WireInit(perform_mul_pre && control_state === compute)
val total_rows = WireInit(block_size.U) // The total number of rows of A, B, and D to feed into the mesh
// TODO Also reduce the number of rows when "perform_single_preload === true.B"
when (current_dataflow === Dataflow.WS.id.U && d_garbage &&
!a_should_be_fed_into_transposer && !b_should_be_fed_into_transposer && !d_should_be_fed_into_transposer) {
val rows_a = Mux(a_garbage, 1.U, a_rows)
val rows_b = Mux(b_garbage, 1.U, b_rows)
/* We can only retire one ROB instruction per cycle (max), but if total_rows == 1, then we would be trying to retire
2 ROB instructions per cycle (one for the preload, and one for the compute). Therefore, to prevent ROB
instructions from being lost, we set a minimum floor for total_rows of 2.
Furthermore, two writes to the same accumulator address must occur at least 4 cycles apart to allow the write to
fully propagate through. Therefore, we raise the minimum floor for total_rows to 4.
TODO: add a WAW check to the ROB so that we can lower the floor back to 2
*/
total_rows := maxOf(maxOf(rows_a, rows_b), 4.U)
}
//added for mul_pre sync
val mul_pre_counter_sub = RegInit(0.U(3.W))
val mul_pre_counter_count = RegInit(0.U(3.W))
val mul_pre_counter_lock = RegInit(false.B)
// These variables determine whether or not the row that is currently being read should be completely padded with 0
val a_row_is_not_all_zeros = a_fire_counter < a_rows
val b_row_is_not_all_zeros = b_fire_counter < b_rows
val d_row_is_not_all_zeros = block_size.U - 1.U - d_fire_counter < d_rows //Todo: d_fire_counter_mulpre?
val im2col_wire = io.im2col.req.ready
def same_bank(addr1: LocalAddr, addr2: LocalAddr, is_garbage1: Bool, is_garbage2: Bool, start_inputting1: Bool, start_inputting2: Bool, can_be_im2colled: Boolean): Bool = {
val addr1_read_from_acc = addr1.is_acc_addr
val addr2_read_from_acc = addr2.is_acc_addr
val is_garbage = is_garbage1 || is_garbage2 ||
!start_inputting1 || !start_inputting2
val is_being_im2colled = can_be_im2colled.B && im2col_wire && im2col_en//im2col_wire
!is_garbage && !is_being_im2colled && ((addr1_read_from_acc && addr2_read_from_acc) ||
(!addr1_read_from_acc && !addr2_read_from_acc && addr1.sp_bank() === addr2.sp_bank()))
}
val a_ready = WireInit(true.B)
val b_ready = WireInit(true.B)
val d_ready = WireInit(true.B)
case class Operand(addr: LocalAddr, is_garbage: Bool, start_inputting: Bool, counter: UInt, started: Bool, can_be_im2colled: Boolean, priority: Int) {
val done = counter === 0.U && started
}
val a_operand = Operand(a_address, a_address_rs1.is_garbage(), start_inputting_a, a_fire_counter, a_fire_started, true, 0)
val b_operand = Operand(b_address, b_address_rs2.is_garbage(), start_inputting_b, b_fire_counter, b_fire_started, false, 1)
val d_operand = Operand(d_address, d_address_rs1.is_garbage(), start_inputting_d, d_fire_counter, d_fire_started, false, 2)
val operands = Seq(a_operand, b_operand, d_operand)
val Seq(a_valid, b_valid, d_valid) = operands.map { case Operand(addr, is_garbage, start_inputting, counter, started, can_be_im2colled, priority) =>
val others = operands.filter(_.priority != priority)
val same_banks = others.map(o => same_bank(addr, o.addr, is_garbage, o.is_garbage, start_inputting, o.start_inputting, can_be_im2colled || o.can_be_im2colled))
val same_counter = others.map(o => started === o.started && counter === o.counter)
val one_ahead = others.map(o => started && counter === wrappingAdd(o.counter, 1.U, total_rows))
val higher_priorities = others.map(o => (o.priority < priority).B)
val must_wait_for = ((same_banks zip same_counter) zip (one_ahead zip higher_priorities)).map {
case ((sb, sc), (oa, hp)) =>
(sb && hp && sc) || oa
}
!must_wait_for.reduce(_ || _)
}
val a_fire = a_valid && a_ready
val b_fire = b_valid && b_ready
val d_fire = d_valid && d_ready
val firing = start_inputting_a || start_inputting_b || start_inputting_d
when (!firing) {
a_fire_counter := 0.U
a_addr_offset := 0.U
}.elsewhen (firing && a_fire && cntl_ready) {
a_fire_counter := wrappingAdd(a_fire_counter, 1.U, total_rows)
a_addr_offset := Mux(a_fire_counter === (total_rows-1.U), 0.U, a_addr_offset + a_addr_stride)
a_fire_started := true.B
}
when (!firing) {
b_fire_counter := 0.U
}.elsewhen (firing && b_fire && cntl_ready) {
b_fire_counter := wrappingAdd(b_fire_counter, 1.U, total_rows)
b_fire_started := true.B
}
when (!firing) {
d_fire_counter := 0.U
}.elsewhen (firing && d_fire && cntl_ready) {
d_fire_counter := wrappingAdd(d_fire_counter, 1.U, total_rows)
d_fire_started := true.B
}
when(performing_mul_pre && !cntl_ready && !mul_pre_counter_lock){
mul_pre_counter_count := d_fire_counter //store 2
}.elsewhen(!performing_mul_pre){
mul_pre_counter_count := 0.U
mul_pre_counter_lock := false.B
}.elsewhen(!cntl_ready){
mul_pre_counter_lock := true.B
}
when(!io.im2col.resp.bits.im2col_delay && performing_mul_pre){
mul_pre_counter_sub := Mux(mul_pre_counter_sub > 0.U, mul_pre_counter_sub - 1.U, 0.U)
}.elsewhen(io.im2col.resp.bits.im2col_delay){
mul_pre_counter_sub := 2.U
}.otherwise{mul_pre_counter_sub := 0.U}
// The last line in this (long) Boolean is just to make sure that we don't think we're done as soon as we begin firing
// TODO change when square requirement lifted
val about_to_fire_all_rows = ((a_fire_counter === (total_rows-1.U) && a_fire) || a_fire_counter === 0.U) &&
((b_fire_counter === (total_rows-1.U) && b_fire) || b_fire_counter === 0.U) &&
((d_fire_counter === (total_rows-1.U) && d_fire) || d_fire_counter === 0.U) &&
(a_fire_started || b_fire_started || d_fire_started) &&
cntl_ready
when (about_to_fire_all_rows) {
a_fire_started := false.B
b_fire_started := false.B
d_fire_started := false.B
}
val d_fire_counter_mulpre = WireInit(b_fire_counter)
when(performing_mul_pre && !io.im2col.resp.bits.im2col_delay&&im2col_en){
d_fire_counter_mulpre := d_fire_counter - mul_pre_counter_sub
}.otherwise{d_fire_counter_mulpre := d_fire_counter}
// Scratchpad reads
for (i <- 0 until sp_banks) {
val read_a = a_valid && !a_read_from_acc && dataAbank === i.U && start_inputting_a && !multiply_garbage && a_row_is_not_all_zeros && !(im2col_wire&&im2col_en)
val read_b = b_valid && !b_read_from_acc && dataBbank === i.U && start_inputting_b && !accumulate_zeros && b_row_is_not_all_zeros //&& !im2col_wire
val read_d = d_valid && !d_read_from_acc && dataDbank === i.U && start_inputting_d && !preload_zeros && d_row_is_not_all_zeros //&& !im2col_wire
Seq((read_a, a_ready), (read_b, b_ready), (read_d, d_ready)).foreach { case (rd, r) =>
when (rd && !io.srams.read(i).req.ready) {
r := false.B
}
}
if (ex_read_from_spad) {
io.srams.read(i).req.valid := (read_a || read_b || read_d) && cntl_ready
io.srams.read(i).req.bits.fromDMA := false.B
io.srams.read(i).req.bits.addr := MuxCase(a_address_rs1.sp_row() + a_fire_counter,
Seq(read_b -> (b_address_rs2.sp_row() + b_fire_counter),
read_d -> (d_address_rs1.sp_row() + block_size.U - 1.U - d_fire_counter_mulpre)))
// TODO this just overrides the previous line. Should we erase the previous line?
when(im2col_en === false.B) {
io.srams.read(i).req.bits.addr := MuxCase(a_address.sp_row(),
Seq(read_b -> b_address.sp_row(),
read_d -> d_address.sp_row()))
}
} else {
io.srams.read(i).req.valid := false.B
io.srams.read(i).req.bits.fromDMA := false.B
io.srams.read(i).req.bits.addr := DontCare
}
io.srams.read(i).resp.ready := false.B
}
// Accumulator read
for (i <- 0 until acc_banks) {
val read_a_from_acc = a_valid && a_read_from_acc && dataABankAcc === i.U && start_inputting_a && !multiply_garbage && a_row_is_not_all_zeros && !(im2col_wire&&im2col_en)
val read_b_from_acc = b_valid && b_read_from_acc && dataBBankAcc === i.U && start_inputting_b && !accumulate_zeros && b_row_is_not_all_zeros //&& !im2col_wire
val read_d_from_acc = d_valid && d_read_from_acc && dataDBankAcc === i.U && start_inputting_d && !preload_zeros && d_row_is_not_all_zeros //&& !im2col_wire
Seq((read_a_from_acc, a_ready), (read_b_from_acc, b_ready), (read_d_from_acc, d_ready)).foreach { case (rd, r) =>
when(rd && !io.acc.read_req(i).ready) {
r := false.B
}
}
if (ex_read_from_acc) {
io.acc.read_req(i).valid := read_a_from_acc || read_b_from_acc || read_d_from_acc
io.acc.read_req(i).bits.scale := acc_scale
io.acc.read_req(i).bits.full := false.B
io.acc.read_req(i).bits.igelu_qb := DontCare
io.acc.read_req(i).bits.igelu_qc := DontCare
io.acc.read_req(i).bits.iexp_qln2 := DontCare
io.acc.read_req(i).bits.iexp_qln2_inv := DontCare
io.acc.read_req(i).bits.act := activation
io.acc.read_req(i).bits.fromDMA := false.B
io.acc.read_req(i).bits.addr := MuxCase(a_address_rs1.acc_row() + a_fire_counter,
Seq(read_b_from_acc -> (b_address_rs2.acc_row() + b_fire_counter),
read_d_from_acc -> (d_address_rs1.acc_row() + block_size.U - 1.U - d_fire_counter)))
// TODO this just overrides the previous line. Should we erase the previous line?
when(im2col_en === false.B){
io.acc.read_req(i).bits.addr := MuxCase(a_address.acc_row(),
Seq(read_b_from_acc -> b_address.acc_row(),
read_d_from_acc -> d_address.acc_row()))
}
} else {
io.acc.read_req(i).valid := false.B
io.acc.read_req(i).bits.scale := DontCare
io.acc.read_req(i).bits.full := false.B
io.acc.read_req(i).bits.igelu_qb := DontCare
io.acc.read_req(i).bits.igelu_qc := DontCare
io.acc.read_req(i).bits.iexp_qln2 := DontCare
io.acc.read_req(i).bits.iexp_qln2_inv := DontCare
io.acc.read_req(i).bits.act := DontCare
io.acc.read_req(i).bits.fromDMA := false.B
io.acc.read_req(i).bits.addr := DontCare
}
io.acc.read_resp(i).ready := false.B
}
// Im2Col reads
{
val read_a = a_valid && start_inputting_a && !multiply_garbage && im2col_wire&&im2col_en //or just im2col_wire
when (read_a && !io.im2col.req.ready) {
a_ready := false.B
}
io.im2col.req.valid := read_a
io.im2col.req.bits.addr := a_address_rs1
io.im2col.req.bits.icol := icol
io.im2col.req.bits.irow := irow
io.im2col.req.bits.ocol := ocol
io.im2col.req.bits.stride := weight_stride
io.im2col.req.bits.krow := krow
io.im2col.req.bits.kdim2 := kdim2
io.im2col.req.bits.row_turn := row_turn
io.im2col.req.bits.row_left := row_left
io.im2col.req.bits.channel := channel
io.im2col.req.bits.im2col_cmd := im2col_en
io.im2col.req.bits.start_inputting := start_inputting_a
io.im2col.req.bits.weight_double_bank := weight_double_bank
io.im2col.req.bits.weight_triple_bank := weight_triple_bank
io.im2col.resp.ready := mesh.io.a.ready
}
// FSM logic
switch (control_state) {
is(waiting_for_cmd) {
// Default state
perform_single_preload := false.B
perform_mul_pre := false.B
perform_single_mul := false.B
when(cmd.valid(0))
{
when(DoConfig && !matmul_in_progress && !pending_completed_rob_ids.map(_.valid).reduce(_ || _)) {
val config_ex_rs1 = rs1s(0).asTypeOf(new ConfigExRs1(acc_scale_t_bits))
val config_ex_rs2 = rs2s(0).asTypeOf(new ConfigExRs2)
val config_cmd_type = rs1s(0)(1,0) // TODO magic numbers
when (config_cmd_type === CONFIG_EX) {
val set_only_strides = config_ex_rs1.set_only_strides
when (!set_only_strides) {
if (has_nonlinear_activations) {
activation := config_ex_rs1.activation
}
in_shift := config_ex_rs2.in_shift
acc_scale := rs1s(0)(xLen - 1, 32).asTypeOf(acc_scale_t) // TODO magic number
a_transpose := config_ex_rs1.a_transpose
bd_transpose := config_ex_rs1.b_transpose
if (dataflow == Dataflow.BOTH) {
current_dataflow := config_ex_rs1.dataflow
}
}
a_addr_stride := config_ex_rs1.a_stride // TODO this needs to be kept in sync with ROB.scala
c_addr_stride := config_ex_rs2.c_stride // TODO this needs to be kept in sync with ROB.scala
config_initialized := true.B
}.otherwise { // config_cmd_type === CONFIG_IM2COL
ocol := cmd.bits(0).cmd.rs2(63, 56)
kdim2 := cmd.bits(0).cmd.rs2(55, 48) //increased bitwidth
krow := cmd.bits(0).cmd.rs2(47, 44) //increased bitwidth
channel := cmd.bits(0).cmd.rs2(31, 23)
weight_stride := cmd.bits(0).cmd.rs2(22, 20)
weight_double_bank := cmd.bits(0).cmd.rs1(58) //added
weight_triple_bank := cmd.bits(0).cmd.rs1(59)
row_left := cmd.bits(0).cmd.rs1(57, 54)
row_turn := cmd.bits(0).cmd.rs1(53, 42)
}
io.completed := cmd.bits(0).rob_id
cmd.pop := 1.U
}
// Preload
.elsewhen(DoPreloads(0) && cmd.valid(1) && (raw_hazards_are_impossible.B || !raw_hazard_pre)) {
perform_single_preload := true.B
performing_single_preload := true.B
//start_inputting_a := current_dataflow === Dataflow.OS.id.U
//start_inputting_d := true.B
start_inputting_a := a_should_be_fed_into_transposer
start_inputting_b := b_should_be_fed_into_transposer
start_inputting_d := true.B
control_state := compute
}
// Overlap compute and preload
.elsewhen(DoComputes(0) && cmd.valid(1) && DoPreloads(1) && (!third_instruction_needed || (cmd.valid(2) && !raw_hazard_mulpre)))
{
perform_mul_pre := true.B
performing_mul_pre := true.B
start_inputting_a := true.B
start_inputting_b := true.B
start_inputting_d := true.B
control_state := compute
}
// Single mul
.elsewhen(DoComputes(0)) {
perform_single_mul := true.B
performing_single_mul := true.B
start_inputting_a := !a_should_be_fed_into_transposer
start_inputting_b := !b_should_be_fed_into_transposer
control_state := compute
}
// Flush
.elsewhen(matmul_in_progress && (current_dataflow === Dataflow.OS.id.U || DoConfig)) {
control_state := flush
}
}.elsewhen(matmul_in_progress && current_dataflow === Dataflow.OS.id.U) {
// TODO code duplication
control_state := flush
}
}
is(compute) {
// Only preloading
when(perform_single_preload) {
start_inputting_a := a_should_be_fed_into_transposer
start_inputting_b := b_should_be_fed_into_transposer
start_inputting_d := true.B
when(about_to_fire_all_rows) {
cmd.pop := 1.U
control_state := waiting_for_cmd
pending_completed_rob_ids(0).valid := cmd.bits(0).rob_id.valid && c_address_rs2.is_garbage()
pending_completed_rob_ids(0).bits := cmd.bits(0).rob_id.bits
when(current_dataflow === Dataflow.OS.id.U) {
in_prop_flush := !rs2s(0).asTypeOf(local_addr_t).is_garbage()
}
}
}
// Overlapping
.elsewhen(perform_mul_pre) {
start_inputting_a := true.B
start_inputting_b := true.B
start_inputting_d := true.B
when(about_to_fire_all_rows) {
cmd.pop := 2.U
control_state := waiting_for_cmd
pending_completed_rob_ids(0) := cmd.bits(0).rob_id
pending_completed_rob_ids(1).valid := cmd.bits(1).rob_id.valid && c_address_rs2.is_garbage()
pending_completed_rob_ids(1).bits := cmd.bits(1).rob_id.bits
when(current_dataflow === Dataflow.OS.id.U) {
in_prop_flush := !rs2s(1).asTypeOf(local_addr_t).is_garbage()
}
}
}
// Only compute
.elsewhen(perform_single_mul) {
start_inputting_a := !a_should_be_fed_into_transposer
start_inputting_b := !b_should_be_fed_into_transposer
when(about_to_fire_all_rows) {
cmd.pop := 1.U
control_state := waiting_for_cmd
pending_completed_rob_ids(0) := cmd.bits(0).rob_id
}
}
}
is(flush) {
when(mesh.io.req.fire) {
control_state := flushing
}
}
is(flushing) {
when(mesh.io.req.ready) {
// TODO we waste a cycle here if it was better to continue with the flush
control_state := waiting_for_cmd
}
}
}
// Computing logic
val computing = performing_mul_pre || performing_single_mul || performing_single_preload
class ComputeCntlSignals extends Bundle {
val perform_mul_pre = Bool()
val perform_single_mul = Bool()
val perform_single_preload = Bool()
val a_bank = UInt(log2Up(sp_banks).W)
val b_bank = UInt(log2Up(sp_banks).W)
val d_bank = UInt(log2Up(sp_banks).W)
val a_bank_acc = UInt(log2Up(acc_banks).W)
val b_bank_acc = UInt(log2Up(acc_banks).W)
val d_bank_acc = UInt(log2Up(acc_banks).W)
val a_read_from_acc = Bool()
val b_read_from_acc = Bool()
val d_read_from_acc = Bool()
val a_garbage = Bool()
val b_garbage = Bool()
val d_garbage = Bool()
val accumulate_zeros = Bool()
val preload_zeros = Bool()
val a_fire = Bool()
val b_fire = Bool()
val d_fire = Bool()
val a_unpadded_cols = UInt(log2Up(block_size + 1).W)
val b_unpadded_cols = UInt(log2Up(block_size + 1).W)
val d_unpadded_cols = UInt(log2Up(block_size + 1).W)
val c_addr = local_addr_t.cloneType
val c_rows = UInt(log2Up(block_size + 1).W)
val c_cols = UInt(log2Up(block_size + 1).W)
val a_transpose = Bool()
val bd_transpose = Bool()
val total_rows = UInt(log2Up(block_size + 1).W)
val rob_id = UDValid(UInt(log2Up(reservation_station_entries).W))
val dataflow = UInt(1.W)
val prop = UInt(1.W)
val shift = UInt(log2Up(accType.getWidth).W)
val im2colling = Bool()
val first = Bool()
}
mesh_cntl_signals_q.io.enq.valid := computing
mesh_cntl_signals_q.io.enq.bits.perform_mul_pre := performing_mul_pre
mesh_cntl_signals_q.io.enq.bits.perform_single_mul := performing_single_mul
mesh_cntl_signals_q.io.enq.bits.perform_single_preload := performing_single_preload
mesh_cntl_signals_q.io.enq.bits.a_bank := dataAbank
mesh_cntl_signals_q.io.enq.bits.b_bank := dataBbank
mesh_cntl_signals_q.io.enq.bits.d_bank := dataDbank
mesh_cntl_signals_q.io.enq.bits.a_bank_acc := dataABankAcc
mesh_cntl_signals_q.io.enq.bits.b_bank_acc := dataBBankAcc
mesh_cntl_signals_q.io.enq.bits.d_bank_acc := dataDBankAcc
mesh_cntl_signals_q.io.enq.bits.a_garbage := a_garbage
mesh_cntl_signals_q.io.enq.bits.b_garbage := b_garbage
mesh_cntl_signals_q.io.enq.bits.d_garbage := d_garbage
mesh_cntl_signals_q.io.enq.bits.a_read_from_acc := a_read_from_acc
mesh_cntl_signals_q.io.enq.bits.b_read_from_acc := b_read_from_acc
mesh_cntl_signals_q.io.enq.bits.d_read_from_acc := d_read_from_acc
mesh_cntl_signals_q.io.enq.bits.accumulate_zeros := accumulate_zeros
mesh_cntl_signals_q.io.enq.bits.preload_zeros := preload_zeros //&& (in_shift(19) =/= 1.U)) //fixed for negative shift?
mesh_cntl_signals_q.io.enq.bits.a_unpadded_cols := Mux(a_row_is_not_all_zeros, a_cols, 0.U)
mesh_cntl_signals_q.io.enq.bits.b_unpadded_cols := Mux(b_row_is_not_all_zeros, b_cols, 0.U)
mesh_cntl_signals_q.io.enq.bits.d_unpadded_cols := Mux(d_row_is_not_all_zeros, d_cols, 0.U)
mesh_cntl_signals_q.io.enq.bits.total_rows := total_rows
mesh_cntl_signals_q.io.enq.bits.a_fire := a_fire
mesh_cntl_signals_q.io.enq.bits.b_fire := b_fire
mesh_cntl_signals_q.io.enq.bits.d_fire := d_fire
mesh_cntl_signals_q.io.enq.bits.c_addr := c_address_rs2
mesh_cntl_signals_q.io.enq.bits.c_rows := c_rows
mesh_cntl_signals_q.io.enq.bits.c_cols := c_cols
mesh_cntl_signals_q.io.enq.bits.a_transpose := a_transpose
mesh_cntl_signals_q.io.enq.bits.bd_transpose := bd_transpose
mesh_cntl_signals_q.io.enq.bits.rob_id.valid := !performing_single_mul && !c_address_rs2.is_garbage()
mesh_cntl_signals_q.io.enq.bits.rob_id.bits := cmd.bits(preload_cmd_place).rob_id.bits
mesh_cntl_signals_q.io.enq.bits.dataflow := current_dataflow
mesh_cntl_signals_q.io.enq.bits.prop := Mux(performing_single_preload, in_prop_flush, in_prop)//prop) //available propagate or not?
mesh_cntl_signals_q.io.enq.bits.shift := in_shift
mesh_cntl_signals_q.io.enq.bits.im2colling := im2col_wire && im2col_en //im2col_wire
mesh_cntl_signals_q.io.enq.bits.first := !a_fire_started && !b_fire_started && !d_fire_started
val readData = VecInit(io.srams.read.map(_.resp.bits.data))
val accReadData = if (ex_read_from_acc) VecInit(io.acc.read_resp.map(_.bits.data.asUInt)) else readData
val im2ColData = io.im2col.resp.bits.a_im2col.asUInt
val readValid = VecInit(io.srams.read.map(bank => ex_read_from_spad.B && bank.resp.valid && !bank.resp.bits.fromDMA))
val accReadValid = VecInit(io.acc.read_resp.map(bank => ex_read_from_acc.B && bank.valid && !bank.bits.fromDMA))
val im2ColValid = io.im2col.resp.valid
mesh_cntl_signals_q.io.deq.ready := (!cntl.a_fire || mesh.io.a.fire || !mesh.io.a.ready) &&
(!cntl.b_fire || mesh.io.b.fire || !mesh.io.b.ready) &&
(!cntl.d_fire || mesh.io.d.fire || !mesh.io.d.ready) &&
(!cntl.first || mesh.io.req.ready)
val dataA_valid = cntl.a_garbage || cntl.a_unpadded_cols === 0.U || Mux(cntl.im2colling, im2ColValid, Mux(cntl.a_read_from_acc, accReadValid(cntl.a_bank_acc), readValid(cntl.a_bank)))
val dataB_valid = cntl.b_garbage || cntl.b_unpadded_cols === 0.U || MuxCase(readValid(cntl.b_bank), Seq(
cntl.accumulate_zeros -> false.B,
cntl.b_read_from_acc -> accReadValid(cntl.b_bank_acc)
))
val dataD_valid = cntl.d_garbage || cntl.d_unpadded_cols === 0.U || MuxCase(readValid(cntl.d_bank), Seq(
cntl.preload_zeros -> false.B,
cntl.d_read_from_acc -> accReadValid(cntl.d_bank_acc)
))
//added for negative bitshift
val preload_zero_counter = RegInit(0.U(5.W))
//val neg_shift_sub = block_size.U - cntl.c_rows
preload_zero_counter := wrappingAdd(preload_zero_counter, 1.U, block_size.U, dataA_valid && dataD_valid && cntl.preload_zeros && (cntl.perform_single_preload || cntl.perform_mul_pre))
val dataA_unpadded = Mux(cntl.im2colling, im2ColData, Mux(cntl.a_read_from_acc, accReadData(cntl.a_bank_acc), readData(cntl.a_bank)))
val dataB_unpadded = MuxCase(readData(cntl.b_bank), Seq(cntl.accumulate_zeros -> 0.U, cntl.b_read_from_acc -> accReadData(cntl.b_bank_acc)))
val dataD_unpadded = MuxCase(readData(cntl.d_bank), Seq(cntl.preload_zeros -> 0.U, cntl.d_read_from_acc -> accReadData(cntl.d_bank_acc)))
val dataA = VecInit(dataA_unpadded.asTypeOf(Vec(block_size, inputType)).zipWithIndex.map { case (d, i) => Mux(i.U < cntl.a_unpadded_cols, d, inputType.zero)})
val dataB = VecInit(dataB_unpadded.asTypeOf(Vec(block_size, inputType)).zipWithIndex.map { case (d, i) => Mux(i.U < cntl.b_unpadded_cols, d, inputType.zero)})
val dataD = VecInit(dataD_unpadded.asTypeOf(Vec(block_size, inputType)).zipWithIndex.map { case (d, i) => Mux(i.U < cntl.d_unpadded_cols, d, inputType.zero)})
// Pop responses off the scratchpad io ports
when (mesh_cntl_signals_q.io.deq.fire) {
when (cntl.a_fire && mesh.io.a.fire && !cntl.a_garbage && cntl.a_unpadded_cols > 0.U && !cntl.im2colling) {
when (cntl.a_read_from_acc) {
io.acc.read_resp(cntl.a_bank_acc).ready := !io.acc.read_resp(cntl.a_bank_acc).bits.fromDMA
}.otherwise {
io.srams.read(cntl.a_bank).resp.ready := !io.srams.read(cntl.a_bank).resp.bits.fromDMA
}
}
when (cntl.b_fire && mesh.io.b.fire && !cntl.b_garbage && !cntl.accumulate_zeros && cntl.b_unpadded_cols > 0.U) {
when (cntl.b_read_from_acc) {
io.acc.read_resp(cntl.b_bank_acc).ready := !io.acc.read_resp(cntl.b_bank_acc).bits.fromDMA
}.otherwise {
io.srams.read(cntl.b_bank).resp.ready := !io.srams.read(cntl.b_bank).resp.bits.fromDMA
}
}
when (cntl.d_fire && mesh.io.d.fire && !cntl.d_garbage && !cntl.preload_zeros && cntl.d_unpadded_cols > 0.U) {
when (cntl.d_read_from_acc) {
io.acc.read_resp(cntl.d_bank_acc).ready := !io.acc.read_resp(cntl.d_bank_acc).bits.fromDMA
}.otherwise {
io.srams.read(cntl.d_bank).resp.ready := !io.srams.read(cntl.d_bank).resp.bits.fromDMA
}
}
}
if (!ex_read_from_acc) {
for (acc_r <- io.acc.read_resp) {
acc_r.ready := true.B
}
}
when (cntl_valid) {
// Default inputs
mesh.io.a.valid := cntl.a_fire && dataA_valid
mesh.io.b.valid := cntl.b_fire && dataB_valid
mesh.io.d.valid := cntl.d_fire && dataD_valid
mesh.io.a.bits := dataA.asTypeOf(Vec(meshRows, Vec(tileRows, inputType)))
mesh.io.b.bits := dataB.asTypeOf(Vec(meshColumns, Vec(tileColumns, inputType)))
mesh.io.d.bits := dataD.asTypeOf(Vec(meshColumns, Vec(tileColumns, inputType)))
mesh.io.req.valid := mesh_cntl_signals_q.io.deq.fire && (cntl.a_fire || cntl.b_fire || cntl.d_fire)
mesh.io.req.bits.tag.addr := cntl.c_addr
mesh.io.req.bits.total_rows := cntl.total_rows
}
when (cntl_valid && cntl.perform_single_preload) {
mesh.io.a.bits := Mux(a_should_be_fed_into_transposer, dataA.asUInt, 0.U).asTypeOf(Vec(meshRows, Vec(tileRows, inputType)))
mesh.io.b.bits := Mux(b_should_be_fed_into_transposer, dataB.asUInt, 0.U).asTypeOf(Vec(meshColumns, Vec(tileColumns, inputType)))
}
when (cntl_valid && cntl.perform_single_mul) {
mesh.io.a.bits := Mux(a_should_be_fed_into_transposer, 0.U, dataA.asUInt).asTypeOf(Vec(meshRows, Vec(tileRows, inputType)))
mesh.io.b.bits := Mux(b_should_be_fed_into_transposer, 0.U, dataB.asUInt).asTypeOf(Vec(meshColumns, Vec(tileColumns, inputType)))
mesh.io.req.bits.tag.addr.make_this_garbage()
}
// Scratchpad writes
// val output_counter = new Counter(block_size)
val output_counter = RegInit(0.U(log2Up(block_size).W))
val w_total_output_rows = mesh.io.resp.bits.total_rows
val w_address = Mux(current_dataflow === Dataflow.WS.id.U, mesh.io.resp.bits.tag.addr + output_counter * c_addr_stride,
mesh.io.resp.bits.tag.addr + (w_total_output_rows - 1.U - output_counter * c_addr_stride))
val write_to_acc = w_address.is_acc_addr
val w_bank = Mux(write_to_acc, w_address.acc_bank(), w_address.sp_bank())
val w_row = Mux(write_to_acc, w_address.acc_row(), w_address.sp_row())
val is_garbage_addr = mesh.io.resp.bits.tag.addr.is_garbage()
val w_matrix_rows = mesh.io.resp.bits.tag.rows
val w_matrix_cols = mesh.io.resp.bits.tag.cols
val write_this_row = Mux(current_dataflow === Dataflow.WS.id.U, output_counter < w_matrix_rows,
w_total_output_rows - 1.U - output_counter < w_matrix_rows)
val w_mask = (0 until block_size).map(_.U < w_matrix_cols) // This is an element-wise mask, rather than a byte-wise mask
// Write to normal scratchpad
for(i <- 0 until sp_banks) {
val activated_wdata = VecInit(mesh.io.resp.bits.data.map(v => VecInit(v.map { e =>
val e_clipped = e.clippedToWidthOf(inputType)
val e_act = MuxCase(e_clipped, Seq(
(activation === Activation.RELU) -> e_clipped.relu))
e_act
})))
if (ex_write_to_spad) {
io.srams.write(i).en := start_array_outputting && w_bank === i.U && !write_to_acc && !is_garbage_addr && write_this_row
io.srams.write(i).addr := w_row
io.srams.write(i).data := activated_wdata.asUInt
io.srams.write(i).mask := w_mask.flatMap(b => Seq.fill(inputType.getWidth / (aligned_to * 8))(b))
} else {
io.srams.write(i).en := false.B
io.srams.write(i).addr := DontCare
io.srams.write(i).data := DontCare
io.srams.write(i).mask := DontCare
}
}
// Write to accumulator
for (i <- 0 until acc_banks) {
if (ex_write_to_acc) {
io.acc.write(i).valid := start_array_outputting && w_bank === i.U && write_to_acc && !is_garbage_addr && write_this_row
io.acc.write(i).bits.addr := w_row
io.acc.write(i).bits.data := VecInit(mesh.io.resp.bits.data.map(v => VecInit(v.map(e => e.withWidthOf(accType)))))
io.acc.write(i).bits.acc := w_address.accumulate
io.acc.write(i).bits.mask := w_mask.flatMap(b => Seq.fill(accType.getWidth / (aligned_to * 8))(b))
} else {
io.acc.write(i).valid := false.B
io.acc.write(i).bits.addr := DontCare
io.acc.write(i).bits.data := DontCare
io.acc.write(i).bits.acc := DontCare
io.acc.write(i).bits.mask := DontCare
}
assert(!(io.acc.write(i).valid && !io.acc.write(i).ready), "Execute controller write to AccumulatorMem was skipped")
}
// Handle dependencies and turn off outputs for garbage addresses
val mesh_completed_rob_id_fire = WireInit(false.B)
//val complete_lock = RegInit(false.B)
//Seah: added for WS accumulator
when(mesh.io.resp.fire && mesh.io.resp.bits.tag.rob_id.valid) {
output_counter := wrappingAdd(output_counter, 1.U, w_total_output_rows)
val last = mesh.io.resp.bits.last
when(last) {
mesh_completed_rob_id_fire := true.B
io.completed.valid := true.B
io.completed.bits := mesh.io.resp.bits.tag.rob_id.bits
}
start_array_outputting := !is_garbage_addr
}
when (!mesh_completed_rob_id_fire) {
when(pending_completed_rob_ids(0).valid) {
io.completed.valid := true.B
io.completed.bits := pending_completed_rob_ids(0).pop()
}.elsewhen(pending_completed_rob_ids(1).valid) {
io.completed.valid := true.B
io.completed.bits := pending_completed_rob_ids(1).pop()
}
}
val complete_bits_count = RegInit(0.U(15.W))
when(io.completed.valid) {
complete_bits_count := complete_bits_count + 1.U
}
when (reset.asBool) {
// pending_completed_rob_id.valid := false.B
pending_completed_rob_ids.foreach(_.valid := false.B)
}
// Performance counter
CounterEventIO.init(io.counter)
io.counter.connectEventSignal(CounterEvent.EXE_ACTIVE_CYCLE, control_state === compute)
io.counter.connectEventSignal(CounterEvent.EXE_FLUSH_CYCLE,
control_state === flushing || control_state === flush)
io.counter.connectEventSignal(CounterEvent.EXE_CONTROL_Q_BLOCK_CYCLE,
!mesh_cntl_signals_q.io.enq.ready && mesh_cntl_signals_q.io.enq.valid)
io.counter.connectEventSignal(CounterEvent.EXE_PRELOAD_HAZ_CYCLE,
cmd.valid(0) && DoPreloads(0) && cmd.valid(1) && raw_hazard_pre)
io.counter.connectEventSignal(CounterEvent.EXE_OVERLAP_HAZ_CYCLE,
cmd.valid(0) && DoPreloads(1) && cmd.valid(1) && DoComputes(0) && cmd.valid(2) && raw_hazard_mulpre)
io.counter.connectEventSignal(CounterEvent.A_GARBAGE_CYCLES, cntl.a_garbage)
io.counter.connectEventSignal(CounterEvent.B_GARBAGE_CYCLES, cntl.b_garbage)
io.counter.connectEventSignal(CounterEvent.D_GARBAGE_CYCLES, cntl.d_garbage)
io.counter.connectEventSignal(CounterEvent.ACC_A_WAIT_CYCLE,
!(!cntl.a_fire || mesh.io.a.fire || !mesh.io.a.ready) && cntl.a_read_from_acc && !cntl.im2colling)
io.counter.connectEventSignal(CounterEvent.ACC_B_WAIT_CYCLE,
!(!cntl.b_fire || mesh.io.b.fire || !mesh.io.b.ready) && cntl.b_read_from_acc)
io.counter.connectEventSignal(CounterEvent.ACC_D_WAIT_CYCLE,
!(!cntl.d_fire || mesh.io.d.fire || !mesh.io.d.ready) && cntl.d_read_from_acc)
io.counter.connectEventSignal(CounterEvent.SCRATCHPAD_A_WAIT_CYCLE,
!(!cntl.a_fire || mesh.io.a.fire || !mesh.io.a.ready) && !cntl.a_read_from_acc && !cntl.im2colling)
io.counter.connectEventSignal(CounterEvent.SCRATCHPAD_B_WAIT_CYCLE,
!(!cntl.b_fire || mesh.io.b.fire || !mesh.io.b.ready) && !cntl.b_read_from_acc)
io.counter.connectEventSignal(CounterEvent.SCRATCHPAD_D_WAIT_CYCLE,
!(!cntl.d_fire || mesh.io.d.fire || !mesh.io.d.ready) && !cntl.d_read_from_acc)
if (use_firesim_simulation_counters) {
val ex_flush_cycle = control_state === flushing || control_state === flush
val ex_preload_haz_cycle = cmd.valid(0) && DoPreloads(0) && cmd.valid(1) && raw_hazard_pre
val ex_mulpre_haz_cycle = cmd.valid(0) && DoPreloads(1) && cmd.valid(1) && DoComputes(0) && cmd.valid(2) && raw_hazard_mulpre
PerfCounter(ex_flush_cycle, "ex_flush_cycle", "cycles during which the ex controller is flushing the spatial array")
PerfCounter(ex_preload_haz_cycle, "ex_preload_haz_cycle", "cycles during which the execute controller is stalling preloads due to hazards")
PerfCounter(ex_mulpre_haz_cycle, "ex_mulpre_haz_cycle", "cycles during which the execute controller is stalling matmuls due to hazards")
}
}
File TransposePreloadUnroller.scala:
package gemmini
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import Util._
import midas.targetutils.PerfCounter
class TransposePreloadUnroller[T <: Data, U <: Data, V <: Data](config: GemminiArrayConfig[T, U, V])
(implicit p: Parameters) extends Module {
import config._
import GemminiISA._
val io = IO(new Bundle {
val in = Flipped(Decoupled(new GemminiCmd(reservation_station_entries)))
val out = Decoupled(new GemminiCmd(reservation_station_entries))
val counter = new CounterEventIO()
})
object State extends ChiselEnum {
val idle = Value
val first_compute, second_preload = Value
}
import State._
val state = RegInit(idle)
val garbage_addr = ~0.U(32.W)
val (q, len) = MultiHeadedQueue(io.in, entries=2, heads=2, maxpop = 1)
val cmds = q.bits
val valids = q.valid
val functs = cmds.map(_.cmd.inst.funct)
val first_preload = valids(0) && functs(0) === PRELOAD_CMD && state === idle
val b_transposed_and_ws = Reg(Bool())
val unroll_preload = b_transposed_and_ws && valids(1) && functs(1) === COMPUTE_AND_FLIP_CMD
val first_preload_cmd = WireInit(cmds(0))
first_preload_cmd.cmd.rs2 := Cat(cmds(0).cmd.rs2(63, 32), garbage_addr)
first_preload_cmd.rob_id.valid := false.B
val first_compute_cmd = WireInit(cmds(1))
first_compute_cmd.cmd.inst.rs1 := Cat(cmds(1).cmd.rs1(63, 32), garbage_addr)
first_compute_cmd.cmd.inst.rs2 := Cat(cmds(1).cmd.rs2(63, 32), garbage_addr)
first_compute_cmd.cmd.inst.funct := COMPUTE_AND_STAY_CMD
first_compute_cmd.rob_id.valid := false.B
val second_preload_cmd = WireInit(cmds(0))
second_preload_cmd.cmd.rs1 := Cat(cmds(0).cmd.rs1(63, 32), garbage_addr)
val config_cmd_type = cmds(0).cmd.rs1(1,0) // TODO magic numbers
val is_config = functs(0) === CONFIG_CMD && config_cmd_type === CONFIG_EX
io.out.valid := MuxCase(valids(0), Seq(
first_preload -> (!b_transposed_and_ws || valids(1)),
(state > first_compute) -> true.B
))
io.out.bits := MuxCase(cmds(0), Seq(
(first_preload && unroll_preload) -> first_preload_cmd,
(state === first_compute) -> first_compute_cmd,
(state === second_preload) -> second_preload_cmd,
))
q.pop := Mux(io.out.fire && !(first_preload && unroll_preload) && state =/= first_compute, 1.U, 0.U)
when (io.out.fire) {
when (is_config) {
val set_only_strides = cmds(0).cmd.rs1(7)
when (!set_only_strides) {
b_transposed_and_ws := ((dataflow == Dataflow.WS).B || cmds(0).cmd.rs1(2) === Dataflow.WS.id.U) && cmds(0).cmd.rs1(9)
}
}.elsewhen (first_preload && unroll_preload) {
state := first_compute
}.elsewhen (state >= first_compute) {
state := state.next
}
}
CounterEventIO.init(io.counter)
io.counter.connectEventSignal(CounterEvent.TRANSPOSE_PRELOAD_UNROLLER_ACTIVE_CYCLES, state =/= idle)
}
object TransposePreloadUnroller {
def apply[T <: Data, U <: Data, V <: Data](in: ReadyValidIO[GemminiCmd], config: GemminiArrayConfig[T, U, V], counter: CounterEventIO)(implicit p: Parameters): DecoupledIO[GemminiCmd] = {
val mod = Module(new TransposePreloadUnroller(config))
mod.io.in <> in
counter.collect(mod.io.counter)
mod.io.out
}
}
|
module ExecuteController( // @[ExecuteController.scala:12:7]
input clock, // @[ExecuteController.scala:12:7]
input reset, // @[ExecuteController.scala:12:7]
output io_cmd_ready, // @[ExecuteController.scala:17:14]
input io_cmd_valid, // @[ExecuteController.scala:17:14]
input [6:0] io_cmd_bits_cmd_inst_funct, // @[ExecuteController.scala:17:14]
input [4:0] io_cmd_bits_cmd_inst_rs2, // @[ExecuteController.scala:17:14]
input [4:0] io_cmd_bits_cmd_inst_rs1, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_inst_xd, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_inst_xs1, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_inst_xs2, // @[ExecuteController.scala:17:14]
input [4:0] io_cmd_bits_cmd_inst_rd, // @[ExecuteController.scala:17:14]
input [6:0] io_cmd_bits_cmd_inst_opcode, // @[ExecuteController.scala:17:14]
input [63:0] io_cmd_bits_cmd_rs1, // @[ExecuteController.scala:17:14]
input [63:0] io_cmd_bits_cmd_rs2, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_debug, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_cease, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_wfi, // @[ExecuteController.scala:17:14]
input [31:0] io_cmd_bits_cmd_status_isa, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_dprv, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_dv, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_prv, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_v, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_sd, // @[ExecuteController.scala:17:14]
input [22:0] io_cmd_bits_cmd_status_zero2, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mpv, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_gva, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mbe, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_sbe, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_sxl, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_uxl, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_sd_rv32, // @[ExecuteController.scala:17:14]
input [7:0] io_cmd_bits_cmd_status_zero1, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_tsr, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_tw, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_tvm, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mxr, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_sum, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mprv, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_xs, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_fs, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_mpp, // @[ExecuteController.scala:17:14]
input [1:0] io_cmd_bits_cmd_status_vs, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_spp, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mpie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_ube, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_spie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_upie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_mie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_hie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_sie, // @[ExecuteController.scala:17:14]
input io_cmd_bits_cmd_status_uie, // @[ExecuteController.scala:17:14]
input [5:0] io_cmd_bits_rob_id_bits, // @[ExecuteController.scala:17:14]
input io_cmd_bits_from_matmul_fsm, // @[ExecuteController.scala:17:14]
input io_cmd_bits_from_conv_fsm, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_addr_is_acc_addr, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_addr_accumulate, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_addr_read_full_acc_row, // @[ExecuteController.scala:17:14]
output [2:0] io_im2col_req_bits_addr_norm_cmd, // @[ExecuteController.scala:17:14]
output [10:0] io_im2col_req_bits_addr_garbage, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_addr_garbage_bit, // @[ExecuteController.scala:17:14]
output [13:0] io_im2col_req_bits_addr_data, // @[ExecuteController.scala:17:14]
output [7:0] io_im2col_req_bits_ocol, // @[ExecuteController.scala:17:14]
output [3:0] io_im2col_req_bits_krow, // @[ExecuteController.scala:17:14]
output [8:0] io_im2col_req_bits_icol, // @[ExecuteController.scala:17:14]
output [8:0] io_im2col_req_bits_irow, // @[ExecuteController.scala:17:14]
output [2:0] io_im2col_req_bits_stride, // @[ExecuteController.scala:17:14]
output [8:0] io_im2col_req_bits_channel, // @[ExecuteController.scala:17:14]
output [10:0] io_im2col_req_bits_row_turn, // @[ExecuteController.scala:17:14]
output [7:0] io_im2col_req_bits_kdim2, // @[ExecuteController.scala:17:14]
output [3:0] io_im2col_req_bits_row_left, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_weight_double_bank, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_weight_triple_bank, // @[ExecuteController.scala:17:14]
output io_im2col_req_bits_start_inputting, // @[ExecuteController.scala:17:14]
output io_im2col_resp_ready, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_0, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_1, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_2, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_3, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_4, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_5, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_6, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_7, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_8, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_9, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_10, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_11, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_12, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_13, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_14, // @[ExecuteController.scala:17:14]
input [7:0] io_im2col_resp_bits_a_im2col_15, // @[ExecuteController.scala:17:14]
input io_im2col_resp_bits_im2col_end, // @[ExecuteController.scala:17:14]
input [8:0] io_im2col_resp_bits_im2col_turn, // @[ExecuteController.scala:17:14]
input [6:0] io_im2col_resp_bits_row_turn, // @[ExecuteController.scala:17:14]
input io_srams_read_0_req_ready, // @[ExecuteController.scala:17:14]
output io_srams_read_0_req_valid, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_read_0_req_bits_addr, // @[ExecuteController.scala:17:14]
output io_srams_read_0_resp_ready, // @[ExecuteController.scala:17:14]
input io_srams_read_0_resp_valid, // @[ExecuteController.scala:17:14]
input [127:0] io_srams_read_0_resp_bits_data, // @[ExecuteController.scala:17:14]
input io_srams_read_0_resp_bits_fromDMA, // @[ExecuteController.scala:17:14]
input io_srams_read_1_req_ready, // @[ExecuteController.scala:17:14]
output io_srams_read_1_req_valid, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_read_1_req_bits_addr, // @[ExecuteController.scala:17:14]
output io_srams_read_1_resp_ready, // @[ExecuteController.scala:17:14]
input io_srams_read_1_resp_valid, // @[ExecuteController.scala:17:14]
input [127:0] io_srams_read_1_resp_bits_data, // @[ExecuteController.scala:17:14]
input io_srams_read_1_resp_bits_fromDMA, // @[ExecuteController.scala:17:14]
input io_srams_read_2_req_ready, // @[ExecuteController.scala:17:14]
output io_srams_read_2_req_valid, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_read_2_req_bits_addr, // @[ExecuteController.scala:17:14]
output io_srams_read_2_resp_ready, // @[ExecuteController.scala:17:14]
input io_srams_read_2_resp_valid, // @[ExecuteController.scala:17:14]
input [127:0] io_srams_read_2_resp_bits_data, // @[ExecuteController.scala:17:14]
input io_srams_read_2_resp_bits_fromDMA, // @[ExecuteController.scala:17:14]
input io_srams_read_3_req_ready, // @[ExecuteController.scala:17:14]
output io_srams_read_3_req_valid, // @[ExecuteController.scala:17:14]
output [11:0] io_srams_read_3_req_bits_addr, // @[ExecuteController.scala:17:14]
output io_srams_read_3_resp_ready, // @[ExecuteController.scala:17:14]
input io_srams_read_3_resp_valid, // @[ExecuteController.scala:17:14]
input [127:0] io_srams_read_3_resp_bits_data, // @[ExecuteController.scala:17:14]
input io_srams_read_3_resp_bits_fromDMA, // @[ExecuteController.scala:17:14]
input io_acc_read_req_0_ready, // @[ExecuteController.scala:17:14]
input io_acc_read_req_1_ready, // @[ExecuteController.scala:17:14]
input io_acc_read_resp_0_valid, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_0_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_1_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_2_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_3_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_4_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_5_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_6_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_7_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_8_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_9_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_10_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_11_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_12_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_13_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_14_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_0_bits_data_15_0, // @[ExecuteController.scala:17:14]
input [1:0] io_acc_read_resp_0_bits_acc_bank_id, // @[ExecuteController.scala:17:14]
input io_acc_read_resp_0_bits_fromDMA, // @[ExecuteController.scala:17:14]
input io_acc_read_resp_1_valid, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_0_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_1_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_2_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_3_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_4_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_5_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_6_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_7_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_8_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_9_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_10_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_11_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_12_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_13_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_14_0, // @[ExecuteController.scala:17:14]
input [31:0] io_acc_read_resp_1_bits_data_15_0, // @[ExecuteController.scala:17:14]
input [1:0] io_acc_read_resp_1_bits_acc_bank_id, // @[ExecuteController.scala:17:14]
input io_acc_read_resp_1_bits_fromDMA, // @[ExecuteController.scala:17:14]
output io_acc_write_0_valid, // @[ExecuteController.scala:17:14]
output [8:0] io_acc_write_0_bits_addr, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_0_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_1_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_2_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_3_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_4_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_5_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_6_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_7_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_8_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_9_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_10_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_11_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_12_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_13_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_14_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_0_bits_data_15_0, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_acc, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_0, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_1, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_2, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_3, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_4, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_5, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_6, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_7, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_8, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_9, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_10, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_11, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_12, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_13, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_14, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_15, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_16, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_17, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_18, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_19, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_20, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_21, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_22, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_23, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_24, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_25, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_26, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_27, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_28, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_29, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_30, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_31, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_32, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_33, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_34, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_35, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_36, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_37, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_38, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_39, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_40, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_41, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_42, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_43, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_44, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_45, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_46, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_47, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_48, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_49, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_50, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_51, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_52, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_53, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_54, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_55, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_56, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_57, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_58, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_59, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_60, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_61, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_62, // @[ExecuteController.scala:17:14]
output io_acc_write_0_bits_mask_63, // @[ExecuteController.scala:17:14]
output io_acc_write_1_valid, // @[ExecuteController.scala:17:14]
output [8:0] io_acc_write_1_bits_addr, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_0_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_1_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_2_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_3_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_4_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_5_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_6_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_7_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_8_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_9_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_10_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_11_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_12_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_13_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_14_0, // @[ExecuteController.scala:17:14]
output [31:0] io_acc_write_1_bits_data_15_0, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_acc, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_0, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_1, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_2, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_3, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_4, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_5, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_6, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_7, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_8, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_9, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_10, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_11, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_12, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_13, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_14, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_15, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_16, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_17, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_18, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_19, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_20, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_21, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_22, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_23, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_24, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_25, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_26, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_27, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_28, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_29, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_30, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_31, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_32, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_33, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_34, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_35, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_36, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_37, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_38, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_39, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_40, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_41, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_42, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_43, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_44, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_45, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_46, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_47, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_48, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_49, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_50, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_51, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_52, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_53, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_54, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_55, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_56, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_57, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_58, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_59, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_60, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_61, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_62, // @[ExecuteController.scala:17:14]
output io_acc_write_1_bits_mask_63, // @[ExecuteController.scala:17:14]
output io_completed_valid, // @[ExecuteController.scala:17:14]
output [5:0] io_completed_bits, // @[ExecuteController.scala:17:14]
output io_busy, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_24, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_25, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_26, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_29, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_30, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_31, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_32, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_33, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_34, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_35, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_36, // @[ExecuteController.scala:17:14]
output io_counter_event_signal_37, // @[ExecuteController.scala:17:14]
input io_counter_external_reset // @[ExecuteController.scala:17:14]
);
wire w_address_result_garbage_bit; // @[LocalAddr.scala:50:26]
wire [10:0] w_address_result_garbage; // @[LocalAddr.scala:50:26]
wire [2:0] w_address_result_norm_cmd; // @[LocalAddr.scala:50:26]
wire w_address_result_read_full_acc_row; // @[LocalAddr.scala:50:26]
wire w_address_result_accumulate; // @[LocalAddr.scala:50:26]
wire w_address_result_is_acc_addr; // @[LocalAddr.scala:50:26]
wire mesh_io_d_valid; // @[ExecuteController.scala:191:19, :873:21, :877:21]
wire mesh_io_b_valid; // @[ExecuteController.scala:190:19, :873:21, :876:21]
wire mesh_io_a_valid; // @[ExecuteController.scala:189:19, :873:21, :875:21]
wire in_prop_flush_qual2_garbage_bit; // @[ExecuteController.scala:666:47]
wire in_prop_flush_qual1_garbage_bit; // @[ExecuteController.scala:647:47]
wire c_address_rs2_garbage_bit; // @[ExecuteController.scala:142:55]
wire d_address_rs1_garbage_bit; // @[ExecuteController.scala:141:55]
wire [10:0] d_address_rs1_garbage; // @[ExecuteController.scala:141:55]
wire [2:0] d_address_rs1_norm_cmd; // @[ExecuteController.scala:141:55]
wire d_address_rs1_read_full_acc_row; // @[ExecuteController.scala:141:55]
wire d_address_rs1_accumulate; // @[ExecuteController.scala:141:55]
wire d_address_rs1_is_acc_addr; // @[ExecuteController.scala:141:55]
wire [10:0] b_address_rs2_garbage; // @[ExecuteController.scala:140:53]
wire [2:0] b_address_rs2_norm_cmd; // @[ExecuteController.scala:140:53]
wire [63:0] rs2s_0; // @[ExecuteController.scala:81:21]
wire [63:0] rs1s_0; // @[ExecuteController.scala:80:21]
wire _mesh_io_a_ready; // @[ExecuteController.scala:186:20]
wire _mesh_io_b_ready; // @[ExecuteController.scala:186:20]
wire _mesh_io_d_ready; // @[ExecuteController.scala:186:20]
wire _mesh_io_req_ready; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_tag_rob_id_valid; // @[ExecuteController.scala:186:20]
wire [5:0] _mesh_io_resp_bits_tag_rob_id_bits; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_tag_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_tag_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_tag_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire [2:0] _mesh_io_resp_bits_tag_addr_norm_cmd; // @[ExecuteController.scala:186:20]
wire [10:0] _mesh_io_resp_bits_tag_addr_garbage; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_tag_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_resp_bits_tag_addr_data; // @[ExecuteController.scala:186:20]
wire [4:0] _mesh_io_resp_bits_tag_rows; // @[ExecuteController.scala:186:20]
wire [4:0] _mesh_io_resp_bits_tag_cols; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_0_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_1_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_2_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_3_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_4_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_5_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_6_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_7_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_8_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_9_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_10_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_11_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_12_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_13_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_14_0; // @[ExecuteController.scala:186:20]
wire [19:0] _mesh_io_resp_bits_data_15_0; // @[ExecuteController.scala:186:20]
wire [4:0] _mesh_io_resp_bits_total_rows; // @[ExecuteController.scala:186:20]
wire _mesh_io_resp_bits_last; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_0_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_0_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_0_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_0_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_0_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_0_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_1_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_1_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_1_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_1_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_1_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_1_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_2_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_2_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_2_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_2_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_2_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_2_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_3_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_3_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_3_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_3_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_3_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_3_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_4_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_4_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_4_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_4_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_4_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_4_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_5_rob_id_valid; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_5_addr_is_acc_addr; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_5_addr_accumulate; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_5_addr_read_full_acc_row; // @[ExecuteController.scala:186:20]
wire _mesh_io_tags_in_progress_5_addr_garbage_bit; // @[ExecuteController.scala:186:20]
wire [13:0] _mesh_io_tags_in_progress_5_addr_data; // @[ExecuteController.scala:186:20]
wire _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_valid; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_perform_mul_pre; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_perform_single_mul; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_perform_single_preload; // @[ExecuteController.scala:178:35]
wire [1:0] _mesh_cntl_signals_q_io_deq_bits_a_bank; // @[ExecuteController.scala:178:35]
wire [1:0] _mesh_cntl_signals_q_io_deq_bits_b_bank; // @[ExecuteController.scala:178:35]
wire [1:0] _mesh_cntl_signals_q_io_deq_bits_d_bank; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_a_bank_acc; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_b_bank_acc; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_d_bank_acc; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_a_read_from_acc; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_a_garbage; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_b_garbage; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_d_garbage; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_accumulate_zeros; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_preload_zeros; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_a_fire; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_b_fire; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_d_fire; // @[ExecuteController.scala:178:35]
wire [4:0] _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols; // @[ExecuteController.scala:178:35]
wire [4:0] _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols; // @[ExecuteController.scala:178:35]
wire [4:0] _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_c_addr_is_acc_addr; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_c_addr_accumulate; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_c_addr_read_full_acc_row; // @[ExecuteController.scala:178:35]
wire [2:0] _mesh_cntl_signals_q_io_deq_bits_c_addr_norm_cmd; // @[ExecuteController.scala:178:35]
wire [10:0] _mesh_cntl_signals_q_io_deq_bits_c_addr_garbage; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_c_addr_garbage_bit; // @[ExecuteController.scala:178:35]
wire [13:0] _mesh_cntl_signals_q_io_deq_bits_c_addr_data; // @[ExecuteController.scala:178:35]
wire [4:0] _mesh_cntl_signals_q_io_deq_bits_c_rows; // @[ExecuteController.scala:178:35]
wire [4:0] _mesh_cntl_signals_q_io_deq_bits_c_cols; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_a_transpose; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_bd_transpose; // @[ExecuteController.scala:178:35]
wire [4:0] _mesh_cntl_signals_q_io_deq_bits_total_rows; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_rob_id_valid; // @[ExecuteController.scala:178:35]
wire [5:0] _mesh_cntl_signals_q_io_deq_bits_rob_id_bits; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_dataflow; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_prop; // @[ExecuteController.scala:178:35]
wire [4:0] _mesh_cntl_signals_q_io_deq_bits_shift; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_im2colling; // @[ExecuteController.scala:178:35]
wire _mesh_cntl_signals_q_io_deq_bits_first; // @[ExecuteController.scala:178:35]
wire _cmd_q_io_enq_ready; // @[MultiHeadedQueue.scala:53:19]
wire _cmd_q_io_deq_valid_0; // @[MultiHeadedQueue.scala:53:19]
wire _cmd_q_io_deq_valid_1; // @[MultiHeadedQueue.scala:53:19]
wire _cmd_q_io_deq_valid_2; // @[MultiHeadedQueue.scala:53:19]
wire [6:0] _cmd_q_io_deq_bits_0_cmd_inst_funct; // @[MultiHeadedQueue.scala:53:19]
wire [63:0] _cmd_q_io_deq_bits_0_cmd_rs1; // @[MultiHeadedQueue.scala:53:19]
wire [63:0] _cmd_q_io_deq_bits_0_cmd_rs2; // @[MultiHeadedQueue.scala:53:19]
wire _cmd_q_io_deq_bits_0_rob_id_valid; // @[MultiHeadedQueue.scala:53:19]
wire [5:0] _cmd_q_io_deq_bits_0_rob_id_bits; // @[MultiHeadedQueue.scala:53:19]
wire [6:0] _cmd_q_io_deq_bits_1_cmd_inst_funct; // @[MultiHeadedQueue.scala:53:19]
wire _cmd_q_io_deq_bits_1_rob_id_valid; // @[MultiHeadedQueue.scala:53:19]
wire [5:0] _cmd_q_io_deq_bits_1_rob_id_bits; // @[MultiHeadedQueue.scala:53:19]
wire [6:0] _cmd_q_io_deq_bits_2_cmd_inst_funct; // @[MultiHeadedQueue.scala:53:19]
wire [5:0] _cmd_q_io_deq_bits_2_rob_id_bits; // @[MultiHeadedQueue.scala:53:19]
wire _unrolled_cmd_mod_io_out_valid; // @[TransposePreloadUnroller.scala:88:21]
wire [6:0] _unrolled_cmd_mod_io_out_bits_cmd_inst_funct; // @[TransposePreloadUnroller.scala:88:21]
wire [4:0] _unrolled_cmd_mod_io_out_bits_cmd_inst_rs2; // @[TransposePreloadUnroller.scala:88:21]
wire [4:0] _unrolled_cmd_mod_io_out_bits_cmd_inst_rs1; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_inst_xd; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_inst_xs1; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_inst_xs2; // @[TransposePreloadUnroller.scala:88:21]
wire [4:0] _unrolled_cmd_mod_io_out_bits_cmd_inst_rd; // @[TransposePreloadUnroller.scala:88:21]
wire [6:0] _unrolled_cmd_mod_io_out_bits_cmd_inst_opcode; // @[TransposePreloadUnroller.scala:88:21]
wire [63:0] _unrolled_cmd_mod_io_out_bits_cmd_rs1; // @[TransposePreloadUnroller.scala:88:21]
wire [63:0] _unrolled_cmd_mod_io_out_bits_cmd_rs2; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_debug; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_cease; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_wfi; // @[TransposePreloadUnroller.scala:88:21]
wire [31:0] _unrolled_cmd_mod_io_out_bits_cmd_status_isa; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_dprv; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_dv; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_prv; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_v; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_sd; // @[TransposePreloadUnroller.scala:88:21]
wire [22:0] _unrolled_cmd_mod_io_out_bits_cmd_status_zero2; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mpv; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_gva; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mbe; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_sbe; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_sxl; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_uxl; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_sd_rv32; // @[TransposePreloadUnroller.scala:88:21]
wire [7:0] _unrolled_cmd_mod_io_out_bits_cmd_status_zero1; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_tsr; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_tw; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_tvm; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mxr; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_sum; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mprv; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_xs; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_fs; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_mpp; // @[TransposePreloadUnroller.scala:88:21]
wire [1:0] _unrolled_cmd_mod_io_out_bits_cmd_status_vs; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_spp; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mpie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_ube; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_spie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_upie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_mie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_hie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_sie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_cmd_status_uie; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_rob_id_valid; // @[TransposePreloadUnroller.scala:88:21]
wire [5:0] _unrolled_cmd_mod_io_out_bits_rob_id_bits; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_from_matmul_fsm; // @[TransposePreloadUnroller.scala:88:21]
wire _unrolled_cmd_mod_io_out_bits_from_conv_fsm; // @[TransposePreloadUnroller.scala:88:21]
wire io_cmd_valid_0 = io_cmd_valid; // @[ExecuteController.scala:12:7]
wire [6:0] io_cmd_bits_cmd_inst_funct_0 = io_cmd_bits_cmd_inst_funct; // @[ExecuteController.scala:12:7]
wire [4:0] io_cmd_bits_cmd_inst_rs2_0 = io_cmd_bits_cmd_inst_rs2; // @[ExecuteController.scala:12:7]
wire [4:0] io_cmd_bits_cmd_inst_rs1_0 = io_cmd_bits_cmd_inst_rs1; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_inst_xd_0 = io_cmd_bits_cmd_inst_xd; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_inst_xs1_0 = io_cmd_bits_cmd_inst_xs1; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_inst_xs2_0 = io_cmd_bits_cmd_inst_xs2; // @[ExecuteController.scala:12:7]
wire [4:0] io_cmd_bits_cmd_inst_rd_0 = io_cmd_bits_cmd_inst_rd; // @[ExecuteController.scala:12:7]
wire [6:0] io_cmd_bits_cmd_inst_opcode_0 = io_cmd_bits_cmd_inst_opcode; // @[ExecuteController.scala:12:7]
wire [63:0] io_cmd_bits_cmd_rs1_0 = io_cmd_bits_cmd_rs1; // @[ExecuteController.scala:12:7]
wire [63:0] io_cmd_bits_cmd_rs2_0 = io_cmd_bits_cmd_rs2; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_debug_0 = io_cmd_bits_cmd_status_debug; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_cease_0 = io_cmd_bits_cmd_status_cease; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_wfi_0 = io_cmd_bits_cmd_status_wfi; // @[ExecuteController.scala:12:7]
wire [31:0] io_cmd_bits_cmd_status_isa_0 = io_cmd_bits_cmd_status_isa; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_dprv_0 = io_cmd_bits_cmd_status_dprv; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_dv_0 = io_cmd_bits_cmd_status_dv; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_prv_0 = io_cmd_bits_cmd_status_prv; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_v_0 = io_cmd_bits_cmd_status_v; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_sd_0 = io_cmd_bits_cmd_status_sd; // @[ExecuteController.scala:12:7]
wire [22:0] io_cmd_bits_cmd_status_zero2_0 = io_cmd_bits_cmd_status_zero2; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mpv_0 = io_cmd_bits_cmd_status_mpv; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_gva_0 = io_cmd_bits_cmd_status_gva; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mbe_0 = io_cmd_bits_cmd_status_mbe; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_sbe_0 = io_cmd_bits_cmd_status_sbe; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_sxl_0 = io_cmd_bits_cmd_status_sxl; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_uxl_0 = io_cmd_bits_cmd_status_uxl; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_sd_rv32_0 = io_cmd_bits_cmd_status_sd_rv32; // @[ExecuteController.scala:12:7]
wire [7:0] io_cmd_bits_cmd_status_zero1_0 = io_cmd_bits_cmd_status_zero1; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_tsr_0 = io_cmd_bits_cmd_status_tsr; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_tw_0 = io_cmd_bits_cmd_status_tw; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_tvm_0 = io_cmd_bits_cmd_status_tvm; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mxr_0 = io_cmd_bits_cmd_status_mxr; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_sum_0 = io_cmd_bits_cmd_status_sum; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mprv_0 = io_cmd_bits_cmd_status_mprv; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_xs_0 = io_cmd_bits_cmd_status_xs; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_fs_0 = io_cmd_bits_cmd_status_fs; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_mpp_0 = io_cmd_bits_cmd_status_mpp; // @[ExecuteController.scala:12:7]
wire [1:0] io_cmd_bits_cmd_status_vs_0 = io_cmd_bits_cmd_status_vs; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_spp_0 = io_cmd_bits_cmd_status_spp; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mpie_0 = io_cmd_bits_cmd_status_mpie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_ube_0 = io_cmd_bits_cmd_status_ube; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_spie_0 = io_cmd_bits_cmd_status_spie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_upie_0 = io_cmd_bits_cmd_status_upie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_mie_0 = io_cmd_bits_cmd_status_mie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_hie_0 = io_cmd_bits_cmd_status_hie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_sie_0 = io_cmd_bits_cmd_status_sie; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_cmd_status_uie_0 = io_cmd_bits_cmd_status_uie; // @[ExecuteController.scala:12:7]
wire [5:0] io_cmd_bits_rob_id_bits_0 = io_cmd_bits_rob_id_bits; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_from_matmul_fsm_0 = io_cmd_bits_from_matmul_fsm; // @[ExecuteController.scala:12:7]
wire io_cmd_bits_from_conv_fsm_0 = io_cmd_bits_from_conv_fsm; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_0_0 = io_im2col_resp_bits_a_im2col_0; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_1_0 = io_im2col_resp_bits_a_im2col_1; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_2_0 = io_im2col_resp_bits_a_im2col_2; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_3_0 = io_im2col_resp_bits_a_im2col_3; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_4_0 = io_im2col_resp_bits_a_im2col_4; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_5_0 = io_im2col_resp_bits_a_im2col_5; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_6_0 = io_im2col_resp_bits_a_im2col_6; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_7_0 = io_im2col_resp_bits_a_im2col_7; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_8_0 = io_im2col_resp_bits_a_im2col_8; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_9_0 = io_im2col_resp_bits_a_im2col_9; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_10_0 = io_im2col_resp_bits_a_im2col_10; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_11_0 = io_im2col_resp_bits_a_im2col_11; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_12_0 = io_im2col_resp_bits_a_im2col_12; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_13_0 = io_im2col_resp_bits_a_im2col_13; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_14_0 = io_im2col_resp_bits_a_im2col_14; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_resp_bits_a_im2col_15_0 = io_im2col_resp_bits_a_im2col_15; // @[ExecuteController.scala:12:7]
wire io_im2col_resp_bits_im2col_end_0 = io_im2col_resp_bits_im2col_end; // @[ExecuteController.scala:12:7]
wire [8:0] io_im2col_resp_bits_im2col_turn_0 = io_im2col_resp_bits_im2col_turn; // @[ExecuteController.scala:12:7]
wire [6:0] io_im2col_resp_bits_row_turn_0 = io_im2col_resp_bits_row_turn; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_req_ready_0 = io_srams_read_0_req_ready; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_resp_valid_0 = io_srams_read_0_resp_valid; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_read_0_resp_bits_data_0 = io_srams_read_0_resp_bits_data; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_resp_bits_fromDMA_0 = io_srams_read_0_resp_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_req_ready_0 = io_srams_read_1_req_ready; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_resp_valid_0 = io_srams_read_1_resp_valid; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_read_1_resp_bits_data_0 = io_srams_read_1_resp_bits_data; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_resp_bits_fromDMA_0 = io_srams_read_1_resp_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_req_ready_0 = io_srams_read_2_req_ready; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_resp_valid_0 = io_srams_read_2_resp_valid; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_read_2_resp_bits_data_0 = io_srams_read_2_resp_bits_data; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_resp_bits_fromDMA_0 = io_srams_read_2_resp_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_req_ready_0 = io_srams_read_3_req_ready; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_resp_valid_0 = io_srams_read_3_resp_valid; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_read_3_resp_bits_data_0 = io_srams_read_3_resp_bits_data; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_resp_bits_fromDMA_0 = io_srams_read_3_resp_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_0_ready_0 = io_acc_read_req_0_ready; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_1_ready_0 = io_acc_read_req_1_ready; // @[ExecuteController.scala:12:7]
wire io_acc_read_resp_0_valid_0 = io_acc_read_resp_0_valid; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_0_0_0 = io_acc_read_resp_0_bits_data_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_1_0_0 = io_acc_read_resp_0_bits_data_1_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_2_0_0 = io_acc_read_resp_0_bits_data_2_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_3_0_0 = io_acc_read_resp_0_bits_data_3_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_4_0_0 = io_acc_read_resp_0_bits_data_4_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_5_0_0 = io_acc_read_resp_0_bits_data_5_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_6_0_0 = io_acc_read_resp_0_bits_data_6_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_7_0_0 = io_acc_read_resp_0_bits_data_7_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_8_0_0 = io_acc_read_resp_0_bits_data_8_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_9_0_0 = io_acc_read_resp_0_bits_data_9_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_10_0_0 = io_acc_read_resp_0_bits_data_10_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_11_0_0 = io_acc_read_resp_0_bits_data_11_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_12_0_0 = io_acc_read_resp_0_bits_data_12_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_13_0_0 = io_acc_read_resp_0_bits_data_13_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_14_0_0 = io_acc_read_resp_0_bits_data_14_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_0_bits_data_15_0_0 = io_acc_read_resp_0_bits_data_15_0; // @[ExecuteController.scala:12:7]
wire [1:0] io_acc_read_resp_0_bits_acc_bank_id_0 = io_acc_read_resp_0_bits_acc_bank_id; // @[ExecuteController.scala:12:7]
wire io_acc_read_resp_0_bits_fromDMA_0 = io_acc_read_resp_0_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_acc_read_resp_1_valid_0 = io_acc_read_resp_1_valid; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_0_0_0 = io_acc_read_resp_1_bits_data_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_1_0_0 = io_acc_read_resp_1_bits_data_1_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_2_0_0 = io_acc_read_resp_1_bits_data_2_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_3_0_0 = io_acc_read_resp_1_bits_data_3_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_4_0_0 = io_acc_read_resp_1_bits_data_4_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_5_0_0 = io_acc_read_resp_1_bits_data_5_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_6_0_0 = io_acc_read_resp_1_bits_data_6_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_7_0_0 = io_acc_read_resp_1_bits_data_7_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_8_0_0 = io_acc_read_resp_1_bits_data_8_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_9_0_0 = io_acc_read_resp_1_bits_data_9_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_10_0_0 = io_acc_read_resp_1_bits_data_10_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_11_0_0 = io_acc_read_resp_1_bits_data_11_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_12_0_0 = io_acc_read_resp_1_bits_data_12_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_13_0_0 = io_acc_read_resp_1_bits_data_13_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_14_0_0 = io_acc_read_resp_1_bits_data_14_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_resp_1_bits_data_15_0_0 = io_acc_read_resp_1_bits_data_15_0; // @[ExecuteController.scala:12:7]
wire [1:0] io_acc_read_resp_1_bits_acc_bank_id_0 = io_acc_read_resp_1_bits_acc_bank_id; // @[ExecuteController.scala:12:7]
wire io_acc_read_resp_1_bits_fromDMA_0 = io_acc_read_resp_1_bits_fromDMA; // @[ExecuteController.scala:12:7]
wire io_counter_external_reset_0 = io_counter_external_reset; // @[ExecuteController.scala:12:7]
wire _one_ahead_T_3 = reset; // @[Util.scala:19:11]
wire _one_ahead_T_30 = reset; // @[Util.scala:19:11]
wire _one_ahead_T_57 = reset; // @[Util.scala:19:11]
wire _one_ahead_T_84 = reset; // @[Util.scala:19:11]
wire _one_ahead_T_111 = reset; // @[Util.scala:19:11]
wire _one_ahead_T_138 = reset; // @[Util.scala:19:11]
wire _a_fire_counter_T_3 = reset; // @[Util.scala:19:11]
wire _b_fire_counter_T_3 = reset; // @[Util.scala:19:11]
wire _d_fire_counter_T_3 = reset; // @[Util.scala:19:11]
wire _preload_zero_counter_T_7 = reset; // @[Util.scala:19:11]
wire _output_counter_T_3 = reset; // @[Util.scala:19:11]
wire [7:0] _irow_T_1 = 8'hFF; // @[ExecuteController.scala:112:18]
wire [8:0] _irow_T = 9'h1FF; // @[ExecuteController.scala:112:18]
wire io_im2col_req_valid = 1'h0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_im2col_cmd = 1'h0; // @[ExecuteController.scala:12:7]
wire io_im2col_resp_valid = 1'h0; // @[ExecuteController.scala:12:7]
wire io_im2col_resp_bits_im2col_delay = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_req_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_req_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_req_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_req_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_en = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_0 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_1 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_2 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_3 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_4 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_5 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_6 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_7 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_8 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_9 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_10 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_11 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_12 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_13 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_14 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_0_mask_15 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_en = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_0 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_1 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_2 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_3 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_4 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_5 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_6 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_7 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_8 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_9 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_10 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_11 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_12 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_13 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_14 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_1_mask_15 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_en = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_0 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_1 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_2 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_3 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_4 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_5 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_6 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_7 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_8 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_9 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_10 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_11 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_12 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_13 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_14 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_2_mask_15 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_en = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_0 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_1 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_2 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_3 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_4 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_5 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_6 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_7 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_8 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_9 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_10 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_11 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_12 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_13 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_14 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_srams_write_3_mask_15 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_0_valid = 1'h0; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_0_bits_full = 1'h0; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_0_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_1_valid = 1'h0; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_1_bits_full = 1'h0; // @[ExecuteController.scala:12:7]
wire io_acc_read_req_1_bits_fromDMA = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_0 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_1 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_2 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_3 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_4 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_5 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_6 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_7 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_8 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_9 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_10 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_11 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_12 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_13 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_14 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_15 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_16 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_17 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_18 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_19 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_20 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_21 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_22 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_23 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_27 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_28 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_38 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_39 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_40 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_41 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_42 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_43 = 1'h0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_44 = 1'h0; // @[ExecuteController.scala:12:7]
wire _a_should_be_fed_into_transposer_T = 1'h0; // @[ExecuteController.scala:123:62]
wire _b_should_be_fed_into_transposer_T = 1'h0; // @[ExecuteController.scala:126:58]
wire b_should_be_fed_into_transposer = 1'h0; // @[ExecuteController.scala:126:79]
wire im2col_en = 1'h0; // @[ExecuteController.scala:136:38]
wire _b_cols_T = 1'h0; // @[ExecuteController.scala:163:37]
wire _b_cols_T_1 = 1'h0; // @[ExecuteController.scala:163:58]
wire _b_rows_T = 1'h0; // @[ExecuteController.scala:164:37]
wire _b_rows_T_1 = 1'h0; // @[ExecuteController.scala:164:58]
wire _raw_hazard_pre_T_3 = 1'h0; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_4 = 1'h0; // @[ExecuteController.scala:217:49]
wire _raw_hazard_pre_T_8 = 1'h0; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_9 = 1'h0; // @[ExecuteController.scala:217:49]
wire _raw_hazard_pre_T_13 = 1'h0; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_14 = 1'h0; // @[ExecuteController.scala:217:49]
wire _raw_hazard_pre_T_18 = 1'h0; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_19 = 1'h0; // @[ExecuteController.scala:217:49]
wire _raw_hazard_pre_T_23 = 1'h0; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_24 = 1'h0; // @[ExecuteController.scala:217:49]
wire _raw_hazard_pre_T_28 = 1'h0; // @[ExecuteController.scala:217:52]
wire _raw_hazard_pre_T_29 = 1'h0; // @[ExecuteController.scala:217:49]
wire _raw_hazard_pre_T_30 = 1'h0; // @[ExecuteController.scala:218:14]
wire _raw_hazard_pre_T_31 = 1'h0; // @[ExecuteController.scala:218:14]
wire _raw_hazard_pre_T_32 = 1'h0; // @[ExecuteController.scala:218:14]
wire _raw_hazard_pre_T_33 = 1'h0; // @[ExecuteController.scala:218:14]
wire raw_hazard_pre = 1'h0; // @[ExecuteController.scala:218:14]
wire _raw_hazard_mulpre_T_3 = 1'h0; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_4 = 1'h0; // @[ExecuteController.scala:225:49]
wire _raw_hazard_mulpre_T_8 = 1'h0; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_9 = 1'h0; // @[ExecuteController.scala:225:49]
wire _raw_hazard_mulpre_T_13 = 1'h0; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_14 = 1'h0; // @[ExecuteController.scala:225:49]
wire _raw_hazard_mulpre_T_18 = 1'h0; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_19 = 1'h0; // @[ExecuteController.scala:225:49]
wire _raw_hazard_mulpre_T_23 = 1'h0; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_24 = 1'h0; // @[ExecuteController.scala:225:49]
wire _raw_hazard_mulpre_T_28 = 1'h0; // @[ExecuteController.scala:225:52]
wire _raw_hazard_mulpre_T_29 = 1'h0; // @[ExecuteController.scala:225:49]
wire _raw_hazard_mulpre_T_30 = 1'h0; // @[ExecuteController.scala:226:14]
wire _raw_hazard_mulpre_T_31 = 1'h0; // @[ExecuteController.scala:226:14]
wire _raw_hazard_mulpre_T_32 = 1'h0; // @[ExecuteController.scala:226:14]
wire _raw_hazard_mulpre_T_33 = 1'h0; // @[ExecuteController.scala:226:14]
wire raw_hazard_mulpre = 1'h0; // @[ExecuteController.scala:226:14]
wire _third_instruction_needed_T_3 = 1'h0; // @[ExecuteController.scala:228:102]
wire _third_instruction_needed_T_5 = 1'h0; // @[ExecuteController.scala:228:111]
wire a_read_from_acc = 1'h0; // @[ExecuteController.scala:263:44]
wire b_read_from_acc = 1'h0; // @[ExecuteController.scala:264:44]
wire d_read_from_acc = 1'h0; // @[ExecuteController.scala:265:44]
wire same_banks_is_being_im2colled = 1'h0; // @[ExecuteController.scala:323:64]
wire _same_banks_T = 1'h0; // @[ExecuteController.scala:325:5]
wire _same_banks_T_2 = 1'h0; // @[ExecuteController.scala:325:17]
wire _same_banks_T_5 = 1'h0; // @[ExecuteController.scala:326:32]
wire _same_banks_T_6 = 1'h0; // @[ExecuteController.scala:326:29]
wire _same_banks_T_10 = 1'h0; // @[ExecuteController.scala:326:53]
wire same_banks_0 = 1'h0; // @[ExecuteController.scala:325:40]
wire same_banks_is_being_im2colled_1 = 1'h0; // @[ExecuteController.scala:323:64]
wire _one_ahead_T_8 = 1'h0; // @[Util.scala:28:8]
wire _one_ahead_T_35 = 1'h0; // @[Util.scala:28:8]
wire _must_wait_for_T = 1'h0; // @[ExecuteController.scala:353:13]
wire _must_wait_for_T_1 = 1'h0; // @[ExecuteController.scala:353:19]
wire _must_wait_for_T_2 = 1'h0; // @[ExecuteController.scala:353:13]
wire _must_wait_for_T_3 = 1'h0; // @[ExecuteController.scala:353:19]
wire same_banks_is_being_im2colled_2 = 1'h0; // @[ExecuteController.scala:323:64]
wire _same_banks_T_24 = 1'h0; // @[ExecuteController.scala:325:5]
wire _same_banks_T_26 = 1'h0; // @[ExecuteController.scala:325:17]
wire _same_banks_T_28 = 1'h0; // @[ExecuteController.scala:326:8]
wire _same_banks_T_30 = 1'h0; // @[ExecuteController.scala:326:29]
wire _same_banks_T_34 = 1'h0; // @[ExecuteController.scala:326:53]
wire same_banks_0_1 = 1'h0; // @[ExecuteController.scala:325:40]
wire _same_banks_is_being_im2colled_T_3 = 1'h0; // @[ExecuteController.scala:323:49]
wire same_banks_is_being_im2colled_3 = 1'h0; // @[ExecuteController.scala:323:64]
wire _same_banks_T_36 = 1'h0; // @[ExecuteController.scala:325:5]
wire _same_banks_T_38 = 1'h0; // @[ExecuteController.scala:325:17]
wire _same_banks_T_40 = 1'h0; // @[ExecuteController.scala:326:8]
wire _same_banks_T_42 = 1'h0; // @[ExecuteController.scala:326:29]
wire _same_banks_T_46 = 1'h0; // @[ExecuteController.scala:326:53]
wire same_banks_1_1 = 1'h0; // @[ExecuteController.scala:325:40]
wire _one_ahead_T_62 = 1'h0; // @[Util.scala:28:8]
wire _one_ahead_T_89 = 1'h0; // @[Util.scala:28:8]
wire _must_wait_for_T_4 = 1'h0; // @[ExecuteController.scala:353:13]
wire _must_wait_for_T_5 = 1'h0; // @[ExecuteController.scala:353:19]
wire _must_wait_for_T_6 = 1'h0; // @[ExecuteController.scala:353:13]
wire _must_wait_for_T_7 = 1'h0; // @[ExecuteController.scala:353:19]
wire same_banks_is_being_im2colled_4 = 1'h0; // @[ExecuteController.scala:323:64]
wire _same_banks_is_being_im2colled_T_5 = 1'h0; // @[ExecuteController.scala:323:49]
wire same_banks_is_being_im2colled_5 = 1'h0; // @[ExecuteController.scala:323:64]
wire _same_banks_T_60 = 1'h0; // @[ExecuteController.scala:325:5]
wire _same_banks_T_62 = 1'h0; // @[ExecuteController.scala:325:17]
wire _same_banks_T_65 = 1'h0; // @[ExecuteController.scala:326:32]
wire _same_banks_T_66 = 1'h0; // @[ExecuteController.scala:326:29]
wire _same_banks_T_70 = 1'h0; // @[ExecuteController.scala:326:53]
wire same_banks_1_2 = 1'h0; // @[ExecuteController.scala:325:40]
wire _one_ahead_T_116 = 1'h0; // @[Util.scala:28:8]
wire _one_ahead_T_143 = 1'h0; // @[Util.scala:28:8]
wire _must_wait_for_T_10 = 1'h0; // @[ExecuteController.scala:353:13]
wire _must_wait_for_T_11 = 1'h0; // @[ExecuteController.scala:353:19]
wire _a_fire_counter_T_8 = 1'h0; // @[Util.scala:28:8]
wire _b_fire_counter_T_8 = 1'h0; // @[Util.scala:28:8]
wire _d_fire_counter_T_8 = 1'h0; // @[Util.scala:28:8]
wire _read_a_T_8 = 1'h0; // @[ExecuteController.scala:424:151]
wire _read_b_T_5 = 1'h0; // @[ExecuteController.scala:425:91]
wire _read_b_T_6 = 1'h0; // @[ExecuteController.scala:425:88]
wire read_b = 1'h0; // @[ExecuteController.scala:425:109]
wire _read_a_T_18 = 1'h0; // @[ExecuteController.scala:424:151]
wire _read_b_T_12 = 1'h0; // @[ExecuteController.scala:425:91]
wire _read_b_T_13 = 1'h0; // @[ExecuteController.scala:425:88]
wire read_b_1 = 1'h0; // @[ExecuteController.scala:425:109]
wire _read_a_T_28 = 1'h0; // @[ExecuteController.scala:424:151]
wire _read_b_T_19 = 1'h0; // @[ExecuteController.scala:425:91]
wire _read_b_T_20 = 1'h0; // @[ExecuteController.scala:425:88]
wire read_b_2 = 1'h0; // @[ExecuteController.scala:425:109]
wire _read_a_T_38 = 1'h0; // @[ExecuteController.scala:424:151]
wire _read_b_T_26 = 1'h0; // @[ExecuteController.scala:425:91]
wire _read_b_T_27 = 1'h0; // @[ExecuteController.scala:425:88]
wire read_b_3 = 1'h0; // @[ExecuteController.scala:425:109]
wire _read_a_from_acc_T = 1'h0; // @[ExecuteController.scala:458:35]
wire _read_a_from_acc_T_2 = 1'h0; // @[ExecuteController.scala:458:54]
wire _read_a_from_acc_T_3 = 1'h0; // @[ExecuteController.scala:458:78]
wire _read_a_from_acc_T_5 = 1'h0; // @[ExecuteController.scala:458:99]
wire _read_a_from_acc_T_6 = 1'h0; // @[ExecuteController.scala:458:120]
wire _read_a_from_acc_T_7 = 1'h0; // @[ExecuteController.scala:458:162]
wire read_a_from_acc = 1'h0; // @[ExecuteController.scala:458:146]
wire _read_b_from_acc_T = 1'h0; // @[ExecuteController.scala:459:35]
wire _read_b_from_acc_T_2 = 1'h0; // @[ExecuteController.scala:459:54]
wire _read_b_from_acc_T_3 = 1'h0; // @[ExecuteController.scala:459:78]
wire _read_b_from_acc_T_4 = 1'h0; // @[ExecuteController.scala:459:102]
wire _read_b_from_acc_T_5 = 1'h0; // @[ExecuteController.scala:459:99]
wire read_b_from_acc = 1'h0; // @[ExecuteController.scala:459:120]
wire _read_d_from_acc_T = 1'h0; // @[ExecuteController.scala:460:35]
wire _read_d_from_acc_T_2 = 1'h0; // @[ExecuteController.scala:460:54]
wire _read_d_from_acc_T_3 = 1'h0; // @[ExecuteController.scala:460:78]
wire _read_d_from_acc_T_5 = 1'h0; // @[ExecuteController.scala:460:99]
wire read_d_from_acc = 1'h0; // @[ExecuteController.scala:460:117]
wire _read_a_from_acc_T_9 = 1'h0; // @[ExecuteController.scala:458:35]
wire _read_a_from_acc_T_11 = 1'h0; // @[ExecuteController.scala:458:54]
wire _read_a_from_acc_T_12 = 1'h0; // @[ExecuteController.scala:458:78]
wire _read_a_from_acc_T_14 = 1'h0; // @[ExecuteController.scala:458:99]
wire _read_a_from_acc_T_15 = 1'h0; // @[ExecuteController.scala:458:120]
wire _read_a_from_acc_T_16 = 1'h0; // @[ExecuteController.scala:458:162]
wire read_a_from_acc_1 = 1'h0; // @[ExecuteController.scala:458:146]
wire _read_b_from_acc_T_6 = 1'h0; // @[ExecuteController.scala:459:35]
wire _read_b_from_acc_T_8 = 1'h0; // @[ExecuteController.scala:459:54]
wire _read_b_from_acc_T_9 = 1'h0; // @[ExecuteController.scala:459:78]
wire _read_b_from_acc_T_10 = 1'h0; // @[ExecuteController.scala:459:102]
wire _read_b_from_acc_T_11 = 1'h0; // @[ExecuteController.scala:459:99]
wire read_b_from_acc_1 = 1'h0; // @[ExecuteController.scala:459:120]
wire _read_d_from_acc_T_6 = 1'h0; // @[ExecuteController.scala:460:35]
wire _read_d_from_acc_T_8 = 1'h0; // @[ExecuteController.scala:460:54]
wire _read_d_from_acc_T_9 = 1'h0; // @[ExecuteController.scala:460:78]
wire _read_d_from_acc_T_11 = 1'h0; // @[ExecuteController.scala:460:99]
wire read_d_from_acc_1 = 1'h0; // @[ExecuteController.scala:460:117]
wire read_a_4 = 1'h0; // @[ExecuteController.scala:506:82]
wire _mesh_cntl_signals_q_io_enq_bits_im2colling_T = 1'h0; // @[ExecuteController.scala:799:61]
wire _accReadValid_T = 1'h0; // @[ExecuteController.scala:808:78]
wire _accReadValid_T_2 = 1'h0; // @[ExecuteController.scala:808:92]
wire _accReadValid_T_3 = 1'h0; // @[ExecuteController.scala:808:78]
wire _accReadValid_T_5 = 1'h0; // @[ExecuteController.scala:808:92]
wire accReadValid_0 = 1'h0; // @[ExecuteController.scala:808:29]
wire accReadValid_1 = 1'h0; // @[ExecuteController.scala:808:29]
wire _preload_zero_counter_T_5 = 1'h0; // @[Util.scala:19:28]
wire _preload_zero_counter_T_9 = 1'h0; // @[Util.scala:19:11]
wire _preload_zero_counter_T_13 = 1'h0; // @[Util.scala:29:12]
wire _output_counter_T_8 = 1'h0; // @[Util.scala:28:8]
wire io_cmd_bits_rob_id_valid = 1'h1; // @[ExecuteController.scala:12:7]
wire io_im2col_req_ready = 1'h1; // @[ExecuteController.scala:12:7]
wire io_acc_read_resp_0_ready = 1'h1; // @[ExecuteController.scala:12:7]
wire io_acc_read_resp_1_ready = 1'h1; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_ready = 1'h1; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_ready = 1'h1; // @[ExecuteController.scala:12:7]
wire _d_should_be_fed_into_transposer_T = 1'h1; // @[ExecuteController.scala:129:58]
wire b_address_rs2_is_acc_addr = 1'h1; // @[ExecuteController.scala:140:53]
wire b_address_rs2_accumulate = 1'h1; // @[ExecuteController.scala:140:53]
wire b_address_rs2_read_full_acc_row = 1'h1; // @[ExecuteController.scala:140:53]
wire b_address_rs2_garbage_bit = 1'h1; // @[ExecuteController.scala:140:53]
wire _accumulate_zeros_T = 1'h1; // @[LocalAddr.scala:43:48]
wire _accumulate_zeros_T_1 = 1'h1; // @[LocalAddr.scala:43:62]
wire _accumulate_zeros_T_2 = 1'h1; // @[LocalAddr.scala:43:91]
wire _accumulate_zeros_T_3 = 1'h1; // @[LocalAddr.scala:43:83]
wire _accumulate_zeros_T_4 = 1'h1; // @[LocalAddr.scala:44:48]
wire accumulate_zeros = 1'h1; // @[LocalAddr.scala:43:96]
wire _d_cols_T = 1'h1; // @[ExecuteController.scala:165:37]
wire _d_rows_T = 1'h1; // @[ExecuteController.scala:166:37]
wire b_address_is_acc_addr = 1'h1; // @[LocalAddr.scala:50:26]
wire b_address_accumulate = 1'h1; // @[LocalAddr.scala:50:26]
wire b_address_read_full_acc_row = 1'h1; // @[LocalAddr.scala:50:26]
wire b_address_garbage_bit = 1'h1; // @[LocalAddr.scala:50:26]
wire _b_garbage_T = 1'h1; // @[LocalAddr.scala:43:48]
wire _b_garbage_T_1 = 1'h1; // @[LocalAddr.scala:43:62]
wire _b_garbage_T_2 = 1'h1; // @[LocalAddr.scala:43:91]
wire _b_garbage_T_3 = 1'h1; // @[LocalAddr.scala:43:83]
wire _b_garbage_T_4 = 1'h1; // @[LocalAddr.scala:44:48]
wire _b_garbage_T_5 = 1'h1; // @[LocalAddr.scala:43:96]
wire b_garbage = 1'h1; // @[ExecuteController.scala:273:46]
wire b_ready = 1'h1; // @[ExecuteController.scala:330:25]
wire _same_banks_is_garbage_T = 1'h1; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_2 = 1'h1; // @[ExecuteController.scala:320:49]
wire same_banks_is_garbage = 1'h1; // @[ExecuteController.scala:321:25]
wire _same_banks_is_being_im2colled_T = 1'h1; // @[ExecuteController.scala:323:49]
wire _same_banks_T_1 = 1'h1; // @[ExecuteController.scala:325:20]
wire _same_banks_is_being_im2colled_T_1 = 1'h1; // @[ExecuteController.scala:323:49]
wire _same_banks_T_13 = 1'h1; // @[ExecuteController.scala:325:20]
wire _one_ahead_T_15 = 1'h1; // @[Util.scala:30:32]
wire _one_ahead_T_42 = 1'h1; // @[Util.scala:30:32]
wire _same_banks_is_garbage_T_8 = 1'h1; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_10 = 1'h1; // @[ExecuteController.scala:320:49]
wire same_banks_is_garbage_2 = 1'h1; // @[ExecuteController.scala:321:25]
wire _same_banks_is_being_im2colled_T_2 = 1'h1; // @[ExecuteController.scala:323:49]
wire _same_banks_T_25 = 1'h1; // @[ExecuteController.scala:325:20]
wire _same_banks_is_garbage_T_12 = 1'h1; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_14 = 1'h1; // @[ExecuteController.scala:320:49]
wire same_banks_is_garbage_3 = 1'h1; // @[ExecuteController.scala:321:25]
wire _same_banks_T_37 = 1'h1; // @[ExecuteController.scala:325:20]
wire _one_ahead_T_69 = 1'h1; // @[Util.scala:30:32]
wire _one_ahead_T_96 = 1'h1; // @[Util.scala:30:32]
wire _same_banks_is_being_im2colled_T_4 = 1'h1; // @[ExecuteController.scala:323:49]
wire _same_banks_T_49 = 1'h1; // @[ExecuteController.scala:325:20]
wire _same_banks_is_garbage_T_20 = 1'h1; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_22 = 1'h1; // @[ExecuteController.scala:320:49]
wire same_banks_is_garbage_5 = 1'h1; // @[ExecuteController.scala:321:25]
wire _same_banks_T_61 = 1'h1; // @[ExecuteController.scala:325:20]
wire _one_ahead_T_123 = 1'h1; // @[Util.scala:30:32]
wire _one_ahead_T_150 = 1'h1; // @[Util.scala:30:32]
wire _a_fire_counter_T_15 = 1'h1; // @[Util.scala:30:32]
wire _b_fire_counter_T_15 = 1'h1; // @[Util.scala:30:32]
wire _d_fire_counter_T_15 = 1'h1; // @[Util.scala:30:32]
wire _read_a_T = 1'h1; // @[ExecuteController.scala:424:29]
wire _read_a_T_9 = 1'h1; // @[ExecuteController.scala:424:138]
wire _read_b_T = 1'h1; // @[ExecuteController.scala:425:29]
wire _read_d_T = 1'h1; // @[ExecuteController.scala:426:29]
wire _read_a_T_10 = 1'h1; // @[ExecuteController.scala:424:29]
wire _read_a_T_19 = 1'h1; // @[ExecuteController.scala:424:138]
wire _read_b_T_7 = 1'h1; // @[ExecuteController.scala:425:29]
wire _read_d_T_7 = 1'h1; // @[ExecuteController.scala:426:29]
wire _read_a_T_20 = 1'h1; // @[ExecuteController.scala:424:29]
wire _read_a_T_29 = 1'h1; // @[ExecuteController.scala:424:138]
wire _read_b_T_14 = 1'h1; // @[ExecuteController.scala:425:29]
wire _read_d_T_14 = 1'h1; // @[ExecuteController.scala:426:29]
wire _read_a_T_30 = 1'h1; // @[ExecuteController.scala:424:29]
wire _read_a_T_39 = 1'h1; // @[ExecuteController.scala:424:138]
wire _read_b_T_21 = 1'h1; // @[ExecuteController.scala:425:29]
wire _read_d_T_21 = 1'h1; // @[ExecuteController.scala:426:29]
wire _read_a_from_acc_T_8 = 1'h1; // @[ExecuteController.scala:458:149]
wire _read_a_from_acc_T_17 = 1'h1; // @[ExecuteController.scala:458:149]
wire _start_inputting_b_T = 1'h1; // @[ExecuteController.scala:618:32]
wire _start_inputting_b_T_1 = 1'h1; // @[ExecuteController.scala:673:30]
wire _preload_zero_counter_T_4 = 1'h1; // @[Util.scala:19:14]
wire _preload_zero_counter_T_6 = 1'h1; // @[Util.scala:19:21]
wire _preload_zero_counter_T_19 = 1'h1; // @[Util.scala:30:32]
wire _w_address_T = 1'h1; // @[ExecuteController.scala:907:40]
wire _write_this_row_T = 1'h1; // @[ExecuteController.scala:919:45]
wire _output_counter_T_15 = 1'h1; // @[Util.scala:30:32]
wire [11:0] io_srams_write_0_addr = 12'h0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_write_1_addr = 12'h0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_write_2_addr = 12'h0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_write_3_addr = 12'h0; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_write_0_data = 128'h0; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_write_1_data = 128'h0; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_write_2_data = 128'h0; // @[ExecuteController.scala:12:7]
wire [127:0] io_srams_write_3_data = 128'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_0_bits_scale_bits = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_0_bits_igelu_qb = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_0_bits_igelu_qc = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_0_bits_iexp_qln2 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_0_bits_iexp_qln2_inv = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_1_bits_scale_bits = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_1_bits_igelu_qb = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_1_bits_igelu_qc = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_1_bits_iexp_qln2 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_read_req_1_bits_iexp_qln2_inv = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_0 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_1 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_2 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_3 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_4 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_5 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_6 = 32'h0; // @[ExecuteController.scala:12:7]
wire [31:0] io_counter_external_values_7 = 32'h0; // @[ExecuteController.scala:12:7]
wire [8:0] io_acc_read_req_0_bits_addr = 9'h0; // @[ExecuteController.scala:12:7]
wire [8:0] io_acc_read_req_1_bits_addr = 9'h0; // @[ExecuteController.scala:12:7]
wire [8:0] im2col_turn = 9'h0; // @[ExecuteController.scala:114:29]
wire [2:0] io_acc_read_req_0_bits_act = 3'h0; // @[ExecuteController.scala:12:7]
wire [2:0] io_acc_read_req_1_bits_act = 3'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_0_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_1_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_2_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_3_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_4_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_5_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_6_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_7_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_8_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_9_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_10_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_11_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_12_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_13_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_14_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_0_bits_full_data_15_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_0_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_1_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_2_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_3_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_4_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_5_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_6_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_7_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_8_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_9_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_10_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_11_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_12_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_13_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_14_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [7:0] io_acc_read_resp_1_bits_full_data_15_0 = 8'h0; // @[ExecuteController.scala:12:7]
wire [13:0] b_address_rs2_data = 14'h3FFF; // @[ExecuteController.scala:140:53]
wire [13:0] _view__data_T = 14'h3FFF; // @[LocalAddr.scala:99:13]
wire [13:0] _mesh_io_req_bits_tag_addr_data_T = 14'h3FFF; // @[LocalAddr.scala:99:13]
wire [4:0] _d_address_T_1 = 5'hF; // @[ExecuteController.scala:253:49]
wire [4:0] _d_row_is_not_all_zeros_T_1 = 5'hF; // @[ExecuteController.scala:312:45]
wire [4:0] preload_zero_counter_max = 5'hF; // @[Util.scala:18:28]
wire [4:0] _preload_zero_counter_T_17 = 5'hF; // @[Util.scala:30:21]
wire [5:0] _d_address_T = 6'hF; // @[ExecuteController.scala:253:49]
wire [5:0] _d_row_is_not_all_zeros_T = 6'hF; // @[ExecuteController.scala:312:45]
wire [5:0] _preload_zero_counter_max_T = 6'hF; // @[Util.scala:18:28]
wire [5:0] _preload_zero_counter_T_16 = 6'hF; // @[Util.scala:30:21]
wire [4:0] _preload_zero_counter_T_15 = 5'hE; // @[Util.scala:30:17]
wire [5:0] _preload_zero_counter_T_14 = 6'hE; // @[Util.scala:30:17]
wire [11:0] _io_srams_read_0_req_bits_addr_T_3 = 12'hFFF; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T_3 = 12'hFFF; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T_3 = 12'hFFF; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T_3 = 12'hFFF; // @[LocalAddr.scala:34:36]
wire [4:0] rows_b = 5'h1; // @[ExecuteController.scala:291:21]
wire [1:0] _b_address_place_T_1 = 2'h0; // @[ExecuteController.scala:127:64]
wire a_address_rs1_is_acc_addr; // @[ExecuteController.scala:139:53]
wire a_address_rs1_accumulate; // @[ExecuteController.scala:139:53]
wire a_address_rs1_read_full_acc_row; // @[ExecuteController.scala:139:53]
wire [2:0] a_address_rs1_norm_cmd; // @[ExecuteController.scala:139:53]
wire [10:0] a_address_rs1_garbage; // @[ExecuteController.scala:139:53]
wire a_address_rs1_garbage_bit; // @[ExecuteController.scala:139:53]
wire [13:0] a_address_rs1_data; // @[ExecuteController.scala:139:53]
wire [8:0] icol; // @[ExecuteController.scala:108:22]
wire [8:0] irow; // @[ExecuteController.scala:109:22]
wire start_inputting_a; // @[ExecuteController.scala:267:35]
wire [7:0] _im2ColData_T = io_im2col_resp_bits_a_im2col_0_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_1 = io_im2col_resp_bits_a_im2col_1_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_2 = io_im2col_resp_bits_a_im2col_2_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_3 = io_im2col_resp_bits_a_im2col_3_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_4 = io_im2col_resp_bits_a_im2col_4_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_5 = io_im2col_resp_bits_a_im2col_5_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_6 = io_im2col_resp_bits_a_im2col_6_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_7 = io_im2col_resp_bits_a_im2col_7_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_8 = io_im2col_resp_bits_a_im2col_8_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_9 = io_im2col_resp_bits_a_im2col_9_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_10 = io_im2col_resp_bits_a_im2col_10_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_11 = io_im2col_resp_bits_a_im2col_11_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_12 = io_im2col_resp_bits_a_im2col_12_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_13 = io_im2col_resp_bits_a_im2col_13_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_14 = io_im2col_resp_bits_a_im2col_14_0; // @[ExecuteController.scala:12:7, :805:49]
wire [7:0] _im2ColData_T_15 = io_im2col_resp_bits_a_im2col_15_0; // @[ExecuteController.scala:12:7, :805:49]
wire _io_srams_read_0_req_valid_T_2; // @[ExecuteController.scala:435:66]
wire [11:0] _io_srams_read_0_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _readValid_T = io_srams_read_0_resp_valid_0; // @[ExecuteController.scala:12:7, :807:73]
wire [127:0] readData_0 = io_srams_read_0_resp_bits_data_0; // @[ExecuteController.scala:12:7, :803:25]
wire _io_srams_read_1_req_valid_T_2; // @[ExecuteController.scala:435:66]
wire [11:0] _io_srams_read_1_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _readValid_T_3 = io_srams_read_1_resp_valid_0; // @[ExecuteController.scala:12:7, :807:73]
wire [127:0] readData_1 = io_srams_read_1_resp_bits_data_0; // @[ExecuteController.scala:12:7, :803:25]
wire _io_srams_read_2_req_valid_T_2; // @[ExecuteController.scala:435:66]
wire [11:0] _io_srams_read_2_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _readValid_T_6 = io_srams_read_2_resp_valid_0; // @[ExecuteController.scala:12:7, :807:73]
wire [127:0] readData_2 = io_srams_read_2_resp_bits_data_0; // @[ExecuteController.scala:12:7, :803:25]
wire _io_srams_read_3_req_valid_T_2; // @[ExecuteController.scala:435:66]
wire [11:0] _io_srams_read_3_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _readValid_T_9 = io_srams_read_3_resp_valid_0; // @[ExecuteController.scala:12:7, :807:73]
wire [127:0] readData_3 = io_srams_read_3_resp_bits_data_0; // @[ExecuteController.scala:12:7, :803:25]
wire _io_acc_write_0_valid_T_5; // @[ExecuteController.scala:949:109]
wire w_address_accumulate; // @[ExecuteController.scala:907:22]
wire w_mask_0; // @[ExecuteController.scala:921:45]
wire w_mask_1; // @[ExecuteController.scala:921:45]
wire w_mask_2; // @[ExecuteController.scala:921:45]
wire w_mask_3; // @[ExecuteController.scala:921:45]
wire w_mask_4; // @[ExecuteController.scala:921:45]
wire w_mask_5; // @[ExecuteController.scala:921:45]
wire w_mask_6; // @[ExecuteController.scala:921:45]
wire w_mask_7; // @[ExecuteController.scala:921:45]
wire w_mask_8; // @[ExecuteController.scala:921:45]
wire w_mask_9; // @[ExecuteController.scala:921:45]
wire w_mask_10; // @[ExecuteController.scala:921:45]
wire w_mask_11; // @[ExecuteController.scala:921:45]
wire w_mask_12; // @[ExecuteController.scala:921:45]
wire w_mask_13; // @[ExecuteController.scala:921:45]
wire w_mask_14; // @[ExecuteController.scala:921:45]
wire w_mask_15; // @[ExecuteController.scala:921:45]
wire _io_acc_write_1_valid_T_5; // @[ExecuteController.scala:949:109]
wire _io_busy_T; // @[ExecuteController.scala:232:27]
wire io_cmd_ready_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_addr_is_acc_addr_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_addr_accumulate_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_addr_read_full_acc_row_0; // @[ExecuteController.scala:12:7]
wire [2:0] io_im2col_req_bits_addr_norm_cmd_0; // @[ExecuteController.scala:12:7]
wire [10:0] io_im2col_req_bits_addr_garbage_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_addr_garbage_bit_0; // @[ExecuteController.scala:12:7]
wire [13:0] io_im2col_req_bits_addr_data_0; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_req_bits_ocol_0; // @[ExecuteController.scala:12:7]
wire [3:0] io_im2col_req_bits_krow_0; // @[ExecuteController.scala:12:7]
wire [8:0] io_im2col_req_bits_icol_0; // @[ExecuteController.scala:12:7]
wire [8:0] io_im2col_req_bits_irow_0; // @[ExecuteController.scala:12:7]
wire [2:0] io_im2col_req_bits_stride_0; // @[ExecuteController.scala:12:7]
wire [8:0] io_im2col_req_bits_channel_0; // @[ExecuteController.scala:12:7]
wire [10:0] io_im2col_req_bits_row_turn_0; // @[ExecuteController.scala:12:7]
wire [7:0] io_im2col_req_bits_kdim2_0; // @[ExecuteController.scala:12:7]
wire [3:0] io_im2col_req_bits_row_left_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_weight_double_bank_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_weight_triple_bank_0; // @[ExecuteController.scala:12:7]
wire io_im2col_req_bits_start_inputting_0; // @[ExecuteController.scala:12:7]
wire io_im2col_resp_ready_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_read_0_req_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_req_valid_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_0_resp_ready_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_read_1_req_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_req_valid_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_1_resp_ready_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_read_2_req_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_req_valid_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_2_resp_ready_0; // @[ExecuteController.scala:12:7]
wire [11:0] io_srams_read_3_req_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_req_valid_0; // @[ExecuteController.scala:12:7]
wire io_srams_read_3_resp_ready_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_0_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_1_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_2_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_3_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_4_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_5_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_6_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_7_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_8_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_9_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_10_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_11_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_12_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_13_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_14_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_0_bits_data_15_0_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_0_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_1_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_2_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_3_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_4_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_5_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_6_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_7_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_8_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_9_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_10_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_11_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_12_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_13_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_14_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_15_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_16_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_17_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_18_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_19_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_20_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_21_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_22_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_23_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_24_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_25_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_26_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_27_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_28_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_29_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_30_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_31_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_32_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_33_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_34_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_35_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_36_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_37_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_38_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_39_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_40_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_41_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_42_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_43_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_44_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_45_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_46_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_47_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_48_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_49_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_50_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_51_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_52_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_53_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_54_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_55_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_56_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_57_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_58_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_59_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_60_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_61_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_62_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_mask_63_0; // @[ExecuteController.scala:12:7]
wire [8:0] io_acc_write_0_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_bits_acc_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_0_valid_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_0_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_1_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_2_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_3_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_4_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_5_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_6_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_7_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_8_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_9_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_10_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_11_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_12_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_13_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_14_0_0; // @[ExecuteController.scala:12:7]
wire [31:0] io_acc_write_1_bits_data_15_0_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_0_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_1_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_2_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_3_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_4_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_5_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_6_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_7_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_8_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_9_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_10_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_11_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_12_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_13_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_14_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_15_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_16_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_17_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_18_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_19_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_20_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_21_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_22_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_23_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_24_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_25_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_26_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_27_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_28_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_29_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_30_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_31_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_32_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_33_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_34_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_35_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_36_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_37_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_38_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_39_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_40_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_41_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_42_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_43_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_44_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_45_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_46_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_47_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_48_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_49_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_50_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_51_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_52_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_53_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_54_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_55_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_56_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_57_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_58_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_59_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_60_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_61_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_62_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_mask_63_0; // @[ExecuteController.scala:12:7]
wire [8:0] io_acc_write_1_bits_addr_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_bits_acc_0; // @[ExecuteController.scala:12:7]
wire io_acc_write_1_valid_0; // @[ExecuteController.scala:12:7]
wire io_completed_valid_0; // @[ExecuteController.scala:12:7]
wire [5:0] io_completed_bits_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_24_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_25_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_26_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_29_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_30_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_31_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_32_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_33_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_34_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_35_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_36_0; // @[ExecuteController.scala:12:7]
wire io_counter_event_signal_37_0; // @[ExecuteController.scala:12:7]
wire io_busy_0; // @[ExecuteController.scala:12:7]
reg [1:0] control_state; // @[ExecuteController.scala:74:30]
wire [63:0] _config_ex_rs1_WIRE = rs1s_0; // @[ExecuteController.scala:80:21, :542:47]
wire [63:0] rs1s_1; // @[ExecuteController.scala:80:21]
wire [63:0] rs1s_2; // @[ExecuteController.scala:80:21]
wire [63:0] _config_ex_rs2_WIRE = rs2s_0; // @[ExecuteController.scala:81:21, :543:47]
wire [63:0] rs2s_1; // @[ExecuteController.scala:81:21]
wire [63:0] rs2s_2; // @[ExecuteController.scala:81:21]
wire DoConfig = _cmd_q_io_deq_bits_0_cmd_inst_funct == 7'h0; // @[MultiHeadedQueue.scala:53:19]
wire _GEN = _cmd_q_io_deq_bits_0_cmd_inst_funct == 7'h4; // @[MultiHeadedQueue.scala:53:19]
wire _DoComputes_T; // @[ExecuteController.scala:84:38]
assign _DoComputes_T = _GEN; // @[ExecuteController.scala:84:38]
wire in_prop; // @[ExecuteController.scala:90:27]
assign in_prop = _GEN; // @[ExecuteController.scala:84:38, :90:27]
wire _DoComputes_T_1 = _cmd_q_io_deq_bits_0_cmd_inst_funct == 7'h5; // @[MultiHeadedQueue.scala:53:19]
wire DoComputes_0 = _DoComputes_T | _DoComputes_T_1; // @[ExecuteController.scala:84:{38,63,68}]
wire _DoComputes_T_2 = _cmd_q_io_deq_bits_1_cmd_inst_funct == 7'h4; // @[MultiHeadedQueue.scala:53:19]
wire _DoComputes_T_3 = _cmd_q_io_deq_bits_1_cmd_inst_funct == 7'h5; // @[MultiHeadedQueue.scala:53:19]
wire DoComputes_1 = _DoComputes_T_2 | _DoComputes_T_3; // @[ExecuteController.scala:84:{38,63,68}]
wire _DoComputes_T_4 = _cmd_q_io_deq_bits_2_cmd_inst_funct == 7'h4; // @[MultiHeadedQueue.scala:53:19]
wire _DoComputes_T_5 = _cmd_q_io_deq_bits_2_cmd_inst_funct == 7'h5; // @[MultiHeadedQueue.scala:53:19]
wire DoComputes_2 = _DoComputes_T_4 | _DoComputes_T_5; // @[ExecuteController.scala:84:{38,63,68}]
wire DoPreloads_0 = _cmd_q_io_deq_bits_0_cmd_inst_funct == 7'h6; // @[MultiHeadedQueue.scala:53:19]
wire DoPreloads_1 = _cmd_q_io_deq_bits_1_cmd_inst_funct == 7'h6; // @[MultiHeadedQueue.scala:53:19]
wire DoPreloads_2 = _cmd_q_io_deq_bits_2_cmd_inst_funct == 7'h6; // @[MultiHeadedQueue.scala:53:19]
wire preload_cmd_place = ~DoPreloads_0; // @[ExecuteController.scala:85:33, :87:30]
reg [7:0] ocol; // @[ExecuteController.scala:97:21]
assign io_im2col_req_bits_ocol_0 = ocol; // @[ExecuteController.scala:12:7, :97:21]
reg [3:0] krow; // @[ExecuteController.scala:99:21]
assign io_im2col_req_bits_krow_0 = krow; // @[ExecuteController.scala:12:7, :99:21]
reg [2:0] weight_stride; // @[ExecuteController.scala:100:30]
assign io_im2col_req_bits_stride_0 = weight_stride; // @[ExecuteController.scala:12:7, :100:30]
reg [8:0] channel; // @[ExecuteController.scala:101:24]
assign io_im2col_req_bits_channel_0 = channel; // @[ExecuteController.scala:12:7, :101:24]
reg [10:0] row_turn; // @[ExecuteController.scala:102:25]
assign io_im2col_req_bits_row_turn_0 = row_turn; // @[ExecuteController.scala:12:7, :102:25]
reg [3:0] row_left; // @[ExecuteController.scala:103:25]
assign io_im2col_req_bits_row_left_0 = row_left; // @[ExecuteController.scala:12:7, :103:25]
reg [7:0] kdim2; // @[ExecuteController.scala:104:22]
assign io_im2col_req_bits_kdim2_0 = kdim2; // @[ExecuteController.scala:12:7, :104:22]
reg weight_double_bank; // @[ExecuteController.scala:105:35]
assign io_im2col_req_bits_weight_double_bank_0 = weight_double_bank; // @[ExecuteController.scala:12:7, :105:35]
reg weight_triple_bank; // @[ExecuteController.scala:106:35]
assign io_im2col_req_bits_weight_triple_bank_0 = weight_triple_bank; // @[ExecuteController.scala:12:7, :106:35]
assign io_im2col_req_bits_icol_0 = icol; // @[ExecuteController.scala:12:7, :108:22]
assign io_im2col_req_bits_irow_0 = irow; // @[ExecuteController.scala:12:7, :109:22]
wire [8:0] _icol_T = {1'h0, ocol} - 9'h1; // @[ExecuteController.scala:97:21, :111:18]
wire [7:0] _icol_T_1 = _icol_T[7:0]; // @[ExecuteController.scala:111:18]
wire [10:0] _GEN_0 = {8'h0, weight_stride}; // @[ExecuteController.scala:100:30, :111:25]
wire [10:0] _icol_T_2 = {3'h0, _icol_T_1} * _GEN_0; // @[ExecuteController.scala:111:{18,25}]
wire [11:0] _GEN_1 = {8'h0, krow}; // @[ExecuteController.scala:99:21, :111:41]
wire [11:0] _icol_T_3 = {1'h0, _icol_T_2} + _GEN_1; // @[ExecuteController.scala:111:{25,41}]
wire [10:0] _icol_T_4 = _icol_T_3[10:0]; // @[ExecuteController.scala:111:41]
assign icol = _icol_T_4[8:0]; // @[ExecuteController.scala:108:22, :111:{8,41}]
wire [10:0] _irow_T_2 = _GEN_0 * 11'hFF; // @[ExecuteController.scala:111:25, :112:25]
wire [11:0] _irow_T_3 = {1'h0, _irow_T_2} + _GEN_1; // @[ExecuteController.scala:111:41, :112:{25,41}]
wire [10:0] _irow_T_4 = _irow_T_3[10:0]; // @[ExecuteController.scala:112:41]
assign irow = _irow_T_4[8:0]; // @[ExecuteController.scala:109:22, :112:{8,41}]
reg [4:0] in_shift; // @[ExecuteController.scala:116:21]
reg [31:0] acc_scale_bits; // @[ExecuteController.scala:117:22]
reg [2:0] activation; // @[ExecuteController.scala:118:54]
reg a_transpose; // @[ExecuteController.scala:119:24]
wire a_should_be_fed_into_transposer = a_transpose; // @[ExecuteController.scala:119:24, :123:44]
reg bd_transpose; // @[ExecuteController.scala:120:25]
wire d_should_be_fed_into_transposer = bd_transpose; // @[ExecuteController.scala:120:25, :129:79]
wire _d_cols_T_1 = bd_transpose; // @[ExecuteController.scala:120:25, :165:58]
wire _d_rows_T_1 = bd_transpose; // @[ExecuteController.scala:120:25, :166:58]
reg config_initialized; // @[ExecuteController.scala:121:35]
wire _a_should_be_fed_into_transposer_T_1 = ~a_transpose; // @[ExecuteController.scala:119:24, :123:84]
wire _a_address_place_T = ~preload_cmd_place; // @[ExecuteController.scala:87:30, :124:47]
wire [1:0] _a_address_place_T_1 = {a_should_be_fed_into_transposer, 1'h0}; // @[ExecuteController.scala:123:44, :124:64]
wire [1:0] a_address_place = _a_address_place_T ? 2'h1 : _a_address_place_T_1; // @[ExecuteController.scala:124:{28,47,64}]
wire _b_address_place_T = ~preload_cmd_place; // @[ExecuteController.scala:87:30, :124:47, :127:47]
wire [1:0] b_address_place = {1'h0, _b_address_place_T}; // @[ExecuteController.scala:127:{28,47}]
wire _im2col_en_T = |weight_stride; // @[ExecuteController.scala:100:30, :136:55]
wire _a_address_rs1_T_6; // @[ExecuteController.scala:139:53]
assign io_im2col_req_bits_addr_is_acc_addr_0 = a_address_rs1_is_acc_addr; // @[ExecuteController.scala:12:7, :139:53]
wire _a_address_rs1_T_5; // @[ExecuteController.scala:139:53]
wire a_address_is_acc_addr = a_address_rs1_is_acc_addr; // @[LocalAddr.scala:50:26]
assign io_im2col_req_bits_addr_accumulate_0 = a_address_rs1_accumulate; // @[ExecuteController.scala:12:7, :139:53]
wire _a_address_rs1_T_4; // @[ExecuteController.scala:139:53]
wire a_address_accumulate = a_address_rs1_accumulate; // @[LocalAddr.scala:50:26]
assign io_im2col_req_bits_addr_read_full_acc_row_0 = a_address_rs1_read_full_acc_row; // @[ExecuteController.scala:12:7, :139:53]
wire [2:0] _a_address_rs1_WIRE_2; // @[ExecuteController.scala:139:53]
wire a_address_read_full_acc_row = a_address_rs1_read_full_acc_row; // @[LocalAddr.scala:50:26]
assign io_im2col_req_bits_addr_norm_cmd_0 = a_address_rs1_norm_cmd; // @[ExecuteController.scala:12:7, :139:53]
wire [10:0] _a_address_rs1_T_2; // @[ExecuteController.scala:139:53]
wire [2:0] a_address_norm_cmd = a_address_rs1_norm_cmd; // @[LocalAddr.scala:50:26]
assign io_im2col_req_bits_addr_garbage_0 = a_address_rs1_garbage; // @[ExecuteController.scala:12:7, :139:53]
wire _a_address_rs1_T_1; // @[ExecuteController.scala:139:53]
wire [10:0] a_address_garbage = a_address_rs1_garbage; // @[LocalAddr.scala:50:26]
assign io_im2col_req_bits_addr_garbage_bit_0 = a_address_rs1_garbage_bit; // @[ExecuteController.scala:12:7, :139:53]
wire [13:0] _a_address_rs1_T; // @[ExecuteController.scala:139:53]
wire _multiply_garbage_T_4 = a_address_rs1_garbage_bit; // @[LocalAddr.scala:44:48]
wire a_address_garbage_bit = a_address_rs1_garbage_bit; // @[LocalAddr.scala:50:26]
wire _a_garbage_T_4 = a_address_rs1_garbage_bit; // @[LocalAddr.scala:44:48]
assign io_im2col_req_bits_addr_data_0 = a_address_rs1_data; // @[ExecuteController.scala:12:7, :139:53]
wire [3:0][63:0] _GEN_2 = {{rs1s_0}, {rs1s_2}, {rs1s_1}, {rs1s_0}}; // @[ExecuteController.scala:80:21, :139:53]
wire [31:0] _a_address_rs1_WIRE = _GEN_2[a_address_place][31:0]; // @[ExecuteController.scala:124:28, :139:53]
assign _a_address_rs1_T = _a_address_rs1_WIRE[13:0]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_data = _a_address_rs1_T; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_T_1 = _a_address_rs1_WIRE[14]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_garbage_bit = _a_address_rs1_T_1; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_T_2 = _a_address_rs1_WIRE[25:15]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_garbage = _a_address_rs1_T_2; // @[ExecuteController.scala:139:53]
wire [2:0] _a_address_rs1_T_3 = _a_address_rs1_WIRE[28:26]; // @[ExecuteController.scala:139:53]
wire [2:0] _a_address_rs1_WIRE_1 = _a_address_rs1_T_3; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_WIRE_2 = _a_address_rs1_WIRE_1; // @[ExecuteController.scala:139:53]
assign a_address_rs1_norm_cmd = _a_address_rs1_WIRE_2; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_T_4 = _a_address_rs1_WIRE[29]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_read_full_acc_row = _a_address_rs1_T_4; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_T_5 = _a_address_rs1_WIRE[30]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_accumulate = _a_address_rs1_T_5; // @[ExecuteController.scala:139:53]
assign _a_address_rs1_T_6 = _a_address_rs1_WIRE[31]; // @[ExecuteController.scala:139:53]
assign a_address_rs1_is_acc_addr = _a_address_rs1_T_6; // @[ExecuteController.scala:139:53]
wire [2:0] _b_address_rs2_WIRE_2; // @[ExecuteController.scala:140:53]
wire [10:0] _b_address_rs2_T_2; // @[ExecuteController.scala:140:53]
wire [2:0] b_address_norm_cmd = b_address_rs2_norm_cmd; // @[LocalAddr.scala:50:26]
wire [10:0] b_address_garbage = b_address_rs2_garbage; // @[LocalAddr.scala:50:26]
wire [3:0][63:0] _GEN_3 = {{rs2s_0}, {rs2s_2}, {rs2s_1}, {rs2s_0}}; // @[ExecuteController.scala:81:21, :140:53]
wire [31:0] _b_address_rs2_WIRE = _GEN_3[b_address_place][31:0]; // @[ExecuteController.scala:127:28, :140:53]
wire [13:0] _b_address_rs2_T = _b_address_rs2_WIRE[13:0]; // @[ExecuteController.scala:140:53]
wire _b_address_rs2_T_1 = _b_address_rs2_WIRE[14]; // @[ExecuteController.scala:140:53]
assign _b_address_rs2_T_2 = _b_address_rs2_WIRE[25:15]; // @[ExecuteController.scala:140:53]
assign b_address_rs2_garbage = _b_address_rs2_T_2; // @[ExecuteController.scala:140:53]
wire [2:0] _b_address_rs2_T_3 = _b_address_rs2_WIRE[28:26]; // @[ExecuteController.scala:140:53]
wire [2:0] _b_address_rs2_WIRE_1 = _b_address_rs2_T_3; // @[ExecuteController.scala:140:53]
assign _b_address_rs2_WIRE_2 = _b_address_rs2_WIRE_1; // @[ExecuteController.scala:140:53]
assign b_address_rs2_norm_cmd = _b_address_rs2_WIRE_2; // @[ExecuteController.scala:140:53]
wire _b_address_rs2_T_4 = _b_address_rs2_WIRE[29]; // @[ExecuteController.scala:140:53]
wire _b_address_rs2_T_5 = _b_address_rs2_WIRE[30]; // @[ExecuteController.scala:140:53]
wire _b_address_rs2_T_6 = _b_address_rs2_WIRE[31]; // @[ExecuteController.scala:140:53]
wire _d_address_rs1_T_6; // @[ExecuteController.scala:141:55]
wire _d_address_rs1_T_5; // @[ExecuteController.scala:141:55]
wire d_address_is_acc_addr = d_address_rs1_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _d_address_rs1_T_4; // @[ExecuteController.scala:141:55]
wire d_address_accumulate = d_address_rs1_accumulate; // @[LocalAddr.scala:50:26]
wire [2:0] _d_address_rs1_WIRE_2; // @[ExecuteController.scala:141:55]
wire d_address_read_full_acc_row = d_address_rs1_read_full_acc_row; // @[LocalAddr.scala:50:26]
wire [10:0] _d_address_rs1_T_2; // @[ExecuteController.scala:141:55]
wire [2:0] d_address_norm_cmd = d_address_rs1_norm_cmd; // @[LocalAddr.scala:50:26]
wire _d_address_rs1_T_1; // @[ExecuteController.scala:141:55]
wire [10:0] d_address_garbage = d_address_rs1_garbage; // @[LocalAddr.scala:50:26]
wire [13:0] _d_address_rs1_T; // @[ExecuteController.scala:141:55]
wire _preload_zeros_T_4 = d_address_rs1_garbage_bit; // @[LocalAddr.scala:44:48]
wire d_address_garbage_bit = d_address_rs1_garbage_bit; // @[LocalAddr.scala:50:26]
wire _d_garbage_T_4 = d_address_rs1_garbage_bit; // @[LocalAddr.scala:44:48]
wire [13:0] d_address_rs1_data; // @[ExecuteController.scala:141:55]
wire [1:0] _GEN_4 = {1'h0, preload_cmd_place}; // @[ExecuteController.scala:87:30, :141:55]
wire [31:0] _d_address_rs1_WIRE = _GEN_2[_GEN_4][31:0]; // @[ExecuteController.scala:139:53, :141:55]
assign _d_address_rs1_T = _d_address_rs1_WIRE[13:0]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_data = _d_address_rs1_T; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_T_1 = _d_address_rs1_WIRE[14]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_garbage_bit = _d_address_rs1_T_1; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_T_2 = _d_address_rs1_WIRE[25:15]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_garbage = _d_address_rs1_T_2; // @[ExecuteController.scala:141:55]
wire [2:0] _d_address_rs1_T_3 = _d_address_rs1_WIRE[28:26]; // @[ExecuteController.scala:141:55]
wire [2:0] _d_address_rs1_WIRE_1 = _d_address_rs1_T_3; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_WIRE_2 = _d_address_rs1_WIRE_1; // @[ExecuteController.scala:141:55]
assign d_address_rs1_norm_cmd = _d_address_rs1_WIRE_2; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_T_4 = _d_address_rs1_WIRE[29]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_read_full_acc_row = _d_address_rs1_T_4; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_T_5 = _d_address_rs1_WIRE[30]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_accumulate = _d_address_rs1_T_5; // @[ExecuteController.scala:141:55]
assign _d_address_rs1_T_6 = _d_address_rs1_WIRE[31]; // @[ExecuteController.scala:141:55]
assign d_address_rs1_is_acc_addr = _d_address_rs1_T_6; // @[ExecuteController.scala:141:55]
wire _c_address_rs2_T_6; // @[ExecuteController.scala:142:55]
wire _c_address_rs2_T_5; // @[ExecuteController.scala:142:55]
wire _c_address_rs2_T_4; // @[ExecuteController.scala:142:55]
wire [2:0] _c_address_rs2_WIRE_2; // @[ExecuteController.scala:142:55]
wire [10:0] _c_address_rs2_T_2; // @[ExecuteController.scala:142:55]
wire _c_address_rs2_T_1; // @[ExecuteController.scala:142:55]
wire [13:0] _c_address_rs2_T; // @[ExecuteController.scala:142:55]
wire _pending_completed_rob_ids_0_valid_T_4 = c_address_rs2_garbage_bit; // @[LocalAddr.scala:44:48]
wire _pending_completed_rob_ids_1_valid_T_4 = c_address_rs2_garbage_bit; // @[LocalAddr.scala:44:48]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_5 = c_address_rs2_garbage_bit; // @[LocalAddr.scala:44:48]
wire c_address_rs2_is_acc_addr; // @[ExecuteController.scala:142:55]
wire c_address_rs2_accumulate; // @[ExecuteController.scala:142:55]
wire c_address_rs2_read_full_acc_row; // @[ExecuteController.scala:142:55]
wire [2:0] c_address_rs2_norm_cmd; // @[ExecuteController.scala:142:55]
wire [10:0] c_address_rs2_garbage; // @[ExecuteController.scala:142:55]
wire [13:0] c_address_rs2_data; // @[ExecuteController.scala:142:55]
wire [31:0] _c_address_rs2_WIRE = _GEN_3[_GEN_4][31:0]; // @[ExecuteController.scala:140:53, :141:55, :142:55]
assign _c_address_rs2_T = _c_address_rs2_WIRE[13:0]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_data = _c_address_rs2_T; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_T_1 = _c_address_rs2_WIRE[14]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_garbage_bit = _c_address_rs2_T_1; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_T_2 = _c_address_rs2_WIRE[25:15]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_garbage = _c_address_rs2_T_2; // @[ExecuteController.scala:142:55]
wire [2:0] _c_address_rs2_T_3 = _c_address_rs2_WIRE[28:26]; // @[ExecuteController.scala:142:55]
wire [2:0] _c_address_rs2_WIRE_1 = _c_address_rs2_T_3; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_WIRE_2 = _c_address_rs2_WIRE_1; // @[ExecuteController.scala:142:55]
assign c_address_rs2_norm_cmd = _c_address_rs2_WIRE_2; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_T_4 = _c_address_rs2_WIRE[29]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_read_full_acc_row = _c_address_rs2_T_4; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_T_5 = _c_address_rs2_WIRE[30]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_accumulate = _c_address_rs2_T_5; // @[ExecuteController.scala:142:55]
assign _c_address_rs2_T_6 = _c_address_rs2_WIRE[31]; // @[ExecuteController.scala:142:55]
assign c_address_rs2_is_acc_addr = _c_address_rs2_T_6; // @[ExecuteController.scala:142:55]
wire _T_17 = a_address_rs1_is_acc_addr & a_address_rs1_accumulate; // @[LocalAddr.scala:43:48]
wire _multiply_garbage_T; // @[LocalAddr.scala:43:48]
assign _multiply_garbage_T = _T_17; // @[LocalAddr.scala:43:48]
wire _a_garbage_T; // @[LocalAddr.scala:43:48]
assign _a_garbage_T = _T_17; // @[LocalAddr.scala:43:48]
wire _multiply_garbage_T_1 = _multiply_garbage_T & a_address_rs1_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _multiply_garbage_T_2 = &a_address_rs1_data; // @[LocalAddr.scala:43:91]
wire _multiply_garbage_T_3 = _multiply_garbage_T_1 & _multiply_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire multiply_garbage = _multiply_garbage_T_3 & _multiply_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _T_29 = d_address_rs1_is_acc_addr & d_address_rs1_accumulate; // @[LocalAddr.scala:43:48]
wire _preload_zeros_T; // @[LocalAddr.scala:43:48]
assign _preload_zeros_T = _T_29; // @[LocalAddr.scala:43:48]
wire _d_garbage_T; // @[LocalAddr.scala:43:48]
assign _d_garbage_T = _T_29; // @[LocalAddr.scala:43:48]
wire _preload_zeros_T_1 = _preload_zeros_T & d_address_rs1_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _preload_zeros_T_2 = &d_address_rs1_data; // @[LocalAddr.scala:43:91]
wire _preload_zeros_T_3 = _preload_zeros_T_1 & _preload_zeros_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire preload_zeros = _preload_zeros_T_3 & _preload_zeros_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire [4:0] a_cols_default = _GEN_2[a_address_place][36:32]; // @[ExecuteController.scala:124:28, :139:53, :154:45]
wire [4:0] a_rows_default = _GEN_2[a_address_place][52:48]; // @[ExecuteController.scala:124:28, :139:53, :155:45]
wire [4:0] b_cols_default = _GEN_3[b_address_place][36:32]; // @[ExecuteController.scala:127:28, :140:53, :156:45]
wire [4:0] b_cols = b_cols_default; // @[ExecuteController.scala:156:45, :163:19]
wire [4:0] b_rows_default = _GEN_3[b_address_place][52:48]; // @[ExecuteController.scala:127:28, :140:53, :157:45]
wire [4:0] b_rows = b_rows_default; // @[ExecuteController.scala:157:45, :164:19]
wire [4:0] d_cols_default = _GEN_2[_GEN_4][36:32]; // @[ExecuteController.scala:139:53, :141:55, :158:47]
wire [4:0] d_rows_default = _GEN_2[_GEN_4][52:48]; // @[ExecuteController.scala:139:53, :141:55, :159:47]
wire [4:0] a_cols = a_transpose ? a_rows_default : a_cols_default; // @[ExecuteController.scala:119:24, :154:45, :155:45, :161:19]
wire [4:0] a_rows = a_transpose ? a_cols_default : a_rows_default; // @[ExecuteController.scala:119:24, :154:45, :155:45, :162:19]
wire [4:0] d_cols = _d_cols_T_1 ? d_rows_default : d_cols_default; // @[ExecuteController.scala:158:47, :159:47, :165:{19,58}]
wire [4:0] d_rows = _d_rows_T_1 ? d_cols_default : d_rows_default; // @[ExecuteController.scala:158:47, :159:47, :166:{19,58}]
wire [4:0] c_cols = _GEN_3[_GEN_4][36:32]; // @[ExecuteController.scala:140:53, :141:55, :142:55, :167:39]
wire [4:0] c_rows = _GEN_3[_GEN_4][52:48]; // @[ExecuteController.scala:140:53, :141:55, :142:55, :168:39]
reg pending_completed_rob_ids_0_valid; // @[ExecuteController.scala:175:38]
reg [5:0] pending_completed_rob_ids_0_bits; // @[ExecuteController.scala:175:38]
reg pending_completed_rob_ids_1_valid; // @[ExecuteController.scala:175:38]
reg [5:0] pending_completed_rob_ids_1_bits; // @[ExecuteController.scala:175:38]
wire _T_617 = control_state == 2'h2; // @[ExecuteController.scala:74:30, :192:38]
wire _mesh_io_req_valid_T; // @[ExecuteController.scala:192:38]
assign _mesh_io_req_valid_T = _T_617; // @[ExecuteController.scala:192:38]
wire _mesh_io_req_bits_pe_control_propagate_T; // @[ExecuteController.scala:201:62]
assign _mesh_io_req_bits_pe_control_propagate_T = _T_617; // @[ExecuteController.scala:192:38, :201:62]
wire _mesh_io_req_bits_flush_T; // @[ExecuteController.scala:207:47]
assign _mesh_io_req_bits_flush_T = _T_617; // @[ExecuteController.scala:192:38, :207:47]
wire _mesh_io_req_bits_pe_control_propagate_T_1 = ~_mesh_io_req_bits_pe_control_propagate_T & _mesh_cntl_signals_q_io_deq_bits_prop; // @[ExecuteController.scala:178:35, :201:{47,62}]
wire _mesh_io_req_bits_flush_T_1 = ~_mesh_cntl_signals_q_io_deq_valid; // @[ExecuteController.scala:178:35, :207:60]
wire _mesh_io_req_bits_flush_T_2 = _mesh_io_req_bits_flush_T & _mesh_io_req_bits_flush_T_1; // @[ExecuteController.scala:207:{47,57,60}]
wire _mesh_io_req_bits_flush_T_3 = _mesh_io_req_bits_flush_T_2; // @[ExecuteController.scala:207:{32,57}]
wire _GEN_5 = _mesh_io_tags_in_progress_0_addr_is_acc_addr & _mesh_io_tags_in_progress_0_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T = _GEN_5; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T = _GEN_5; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_1 = _raw_hazard_pre_is_garbage_T & _mesh_io_tags_in_progress_0_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_2 = &_mesh_io_tags_in_progress_0_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_3 = _raw_hazard_pre_is_garbage_T_1 & _raw_hazard_pre_is_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_4; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage = _raw_hazard_pre_is_garbage_T_3 & _raw_hazard_pre_is_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_5; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_4; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_1; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_1 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_5 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_9 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_13 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_17 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_pre_raw_haz_WIRE_21 = rs1s_0[31:0]; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T = _raw_hazard_pre_pre_raw_haz_WIRE_1[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_data = _raw_hazard_pre_pre_raw_haz_T; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_1 = _raw_hazard_pre_pre_raw_haz_WIRE_1[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_1; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_2 = _raw_hazard_pre_pre_raw_haz_WIRE_1[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_garbage = _raw_hazard_pre_pre_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_3 = _raw_hazard_pre_pre_raw_haz_WIRE_1[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_2 = _raw_hazard_pre_pre_raw_haz_T_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_3 = _raw_hazard_pre_pre_raw_haz_WIRE_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_4 = _raw_hazard_pre_pre_raw_haz_WIRE_1[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_4; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_5 = _raw_hazard_pre_pre_raw_haz_WIRE_1[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_accumulate = _raw_hazard_pre_pre_raw_haz_T_5; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_6 = _raw_hazard_pre_pre_raw_haz_WIRE_1[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_7 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_8 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz = _raw_hazard_pre_pre_raw_haz_T_7 & _raw_hazard_pre_pre_raw_haz_T_8; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_5; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_4; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_1; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_1 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_9 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_17 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_25 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_33 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_41 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_1 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_5 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_9 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_13 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_17 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_21 = rs1s_1[31:0]; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T = _raw_hazard_pre_mul_raw_haz_WIRE_1[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_data = _raw_hazard_pre_mul_raw_haz_T; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_1 = _raw_hazard_pre_mul_raw_haz_WIRE_1[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_1; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_2 = _raw_hazard_pre_mul_raw_haz_WIRE_1[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_garbage = _raw_hazard_pre_mul_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_3 = _raw_hazard_pre_mul_raw_haz_WIRE_1[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_2 = _raw_hazard_pre_mul_raw_haz_T_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_3 = _raw_hazard_pre_mul_raw_haz_WIRE_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_4 = _raw_hazard_pre_mul_raw_haz_WIRE_1[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_4; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_5 = _raw_hazard_pre_mul_raw_haz_WIRE_1[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_accumulate = _raw_hazard_pre_mul_raw_haz_T_5; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_6 = _raw_hazard_pre_mul_raw_haz_WIRE_1[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_7 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_8 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_9 = _raw_hazard_pre_mul_raw_haz_T_7 & _raw_hazard_pre_mul_raw_haz_T_8; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_16; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_12; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_10; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_5 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_13 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_21 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_29 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_37 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_pre_mul_raw_haz_WIRE_45 = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _in_prop_flush_qual2_WIRE = rs2s_1[31:0]; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_10 = _raw_hazard_pre_mul_raw_haz_WIRE_5[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_4_data = _raw_hazard_pre_mul_raw_haz_T_10; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_11 = _raw_hazard_pre_mul_raw_haz_WIRE_5[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_4_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_12 = _raw_hazard_pre_mul_raw_haz_WIRE_5[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_4_garbage = _raw_hazard_pre_mul_raw_haz_T_12; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_13 = _raw_hazard_pre_mul_raw_haz_WIRE_5[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_6 = _raw_hazard_pre_mul_raw_haz_T_13; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_7 = _raw_hazard_pre_mul_raw_haz_WIRE_6; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_4_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_14 = _raw_hazard_pre_mul_raw_haz_WIRE_5[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_4_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_14; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_15 = _raw_hazard_pre_mul_raw_haz_WIRE_5[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_4_accumulate = _raw_hazard_pre_mul_raw_haz_T_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_16 = _raw_hazard_pre_mul_raw_haz_WIRE_5[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_4_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_16; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_17 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_4_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_18 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_4_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_19 = _raw_hazard_pre_mul_raw_haz_T_17 & _raw_hazard_pre_mul_raw_haz_T_18; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz = _raw_hazard_pre_mul_raw_haz_T_9 | _raw_hazard_pre_mul_raw_haz_T_19; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T = ~raw_hazard_pre_is_garbage; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_1 = raw_hazard_pre_pre_raw_haz | raw_hazard_pre_mul_raw_haz; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_2 = _raw_hazard_pre_T & _raw_hazard_pre_T_1; // @[ExecuteController.scala:217:{5,17,33}]
wire _GEN_6 = _mesh_io_tags_in_progress_1_addr_is_acc_addr & _mesh_io_tags_in_progress_1_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_5; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_5 = _GEN_6; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_5; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_5 = _GEN_6; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_6 = _raw_hazard_pre_is_garbage_T_5 & _mesh_io_tags_in_progress_1_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_7 = &_mesh_io_tags_in_progress_1_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_8 = _raw_hazard_pre_is_garbage_T_6 & _raw_hazard_pre_is_garbage_T_7; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_9; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_1 = _raw_hazard_pre_is_garbage_T_8 & _raw_hazard_pre_is_garbage_T_9; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_14; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_13; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_10; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_9; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_9 = _raw_hazard_pre_pre_raw_haz_WIRE_5[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_4_data = _raw_hazard_pre_pre_raw_haz_T_9; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_10 = _raw_hazard_pre_pre_raw_haz_WIRE_5[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_4_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_10; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_11 = _raw_hazard_pre_pre_raw_haz_WIRE_5[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_4_garbage = _raw_hazard_pre_pre_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_12 = _raw_hazard_pre_pre_raw_haz_WIRE_5[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_6 = _raw_hazard_pre_pre_raw_haz_T_12; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_7 = _raw_hazard_pre_pre_raw_haz_WIRE_6; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_4_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_13 = _raw_hazard_pre_pre_raw_haz_WIRE_5[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_4_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_13; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_14 = _raw_hazard_pre_pre_raw_haz_WIRE_5[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_4_accumulate = _raw_hazard_pre_pre_raw_haz_T_14; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_15 = _raw_hazard_pre_pre_raw_haz_WIRE_5[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_4_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_16 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_4_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_17 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_4_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_1 = _raw_hazard_pre_pre_raw_haz_T_16 & _raw_hazard_pre_pre_raw_haz_T_17; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_26; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_25; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_21; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_20; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_20 = _raw_hazard_pre_mul_raw_haz_WIRE_9[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_8_data = _raw_hazard_pre_mul_raw_haz_T_20; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_21 = _raw_hazard_pre_mul_raw_haz_WIRE_9[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_8_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_21; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_22 = _raw_hazard_pre_mul_raw_haz_WIRE_9[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_8_garbage = _raw_hazard_pre_mul_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_23 = _raw_hazard_pre_mul_raw_haz_WIRE_9[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_10 = _raw_hazard_pre_mul_raw_haz_T_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_11 = _raw_hazard_pre_mul_raw_haz_WIRE_10; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_8_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_24 = _raw_hazard_pre_mul_raw_haz_WIRE_9[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_8_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_24; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_25 = _raw_hazard_pre_mul_raw_haz_WIRE_9[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_8_accumulate = _raw_hazard_pre_mul_raw_haz_T_25; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_26 = _raw_hazard_pre_mul_raw_haz_WIRE_9[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_8_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_26; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_27 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_8_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_28 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_8_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_29 = _raw_hazard_pre_mul_raw_haz_T_27 & _raw_hazard_pre_mul_raw_haz_T_28; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_36; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_35; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_34; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_31; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_30 = _raw_hazard_pre_mul_raw_haz_WIRE_13[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_12_data = _raw_hazard_pre_mul_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_31 = _raw_hazard_pre_mul_raw_haz_WIRE_13[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_12_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_32 = _raw_hazard_pre_mul_raw_haz_WIRE_13[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_12_garbage = _raw_hazard_pre_mul_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_33 = _raw_hazard_pre_mul_raw_haz_WIRE_13[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_14 = _raw_hazard_pre_mul_raw_haz_T_33; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_15 = _raw_hazard_pre_mul_raw_haz_WIRE_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_12_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_34 = _raw_hazard_pre_mul_raw_haz_WIRE_13[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_12_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_34; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_35 = _raw_hazard_pre_mul_raw_haz_WIRE_13[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_12_accumulate = _raw_hazard_pre_mul_raw_haz_T_35; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_36 = _raw_hazard_pre_mul_raw_haz_WIRE_13[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_12_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_36; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_37 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_12_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_38 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_12_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_39 = _raw_hazard_pre_mul_raw_haz_T_37 & _raw_hazard_pre_mul_raw_haz_T_38; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_1 = _raw_hazard_pre_mul_raw_haz_T_29 | _raw_hazard_pre_mul_raw_haz_T_39; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_5 = ~raw_hazard_pre_is_garbage_1; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_6 = raw_hazard_pre_pre_raw_haz_1 | raw_hazard_pre_mul_raw_haz_1; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_7 = _raw_hazard_pre_T_5 & _raw_hazard_pre_T_6; // @[ExecuteController.scala:217:{5,17,33}]
wire _GEN_7 = _mesh_io_tags_in_progress_2_addr_is_acc_addr & _mesh_io_tags_in_progress_2_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_10; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_10 = _GEN_7; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_10; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_10 = _GEN_7; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_11 = _raw_hazard_pre_is_garbage_T_10 & _mesh_io_tags_in_progress_2_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_12 = &_mesh_io_tags_in_progress_2_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_13 = _raw_hazard_pre_is_garbage_T_11 & _raw_hazard_pre_is_garbage_T_12; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_14; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_2 = _raw_hazard_pre_is_garbage_T_13 & _raw_hazard_pre_is_garbage_T_14; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_23; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_20; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_19; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_18; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_18 = _raw_hazard_pre_pre_raw_haz_WIRE_9[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_8_data = _raw_hazard_pre_pre_raw_haz_T_18; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_19 = _raw_hazard_pre_pre_raw_haz_WIRE_9[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_8_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_20 = _raw_hazard_pre_pre_raw_haz_WIRE_9[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_8_garbage = _raw_hazard_pre_pre_raw_haz_T_20; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_21 = _raw_hazard_pre_pre_raw_haz_WIRE_9[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_10 = _raw_hazard_pre_pre_raw_haz_T_21; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_11 = _raw_hazard_pre_pre_raw_haz_WIRE_10; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_8_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_22 = _raw_hazard_pre_pre_raw_haz_WIRE_9[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_8_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_22; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_23 = _raw_hazard_pre_pre_raw_haz_WIRE_9[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_8_accumulate = _raw_hazard_pre_pre_raw_haz_T_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_24 = _raw_hazard_pre_pre_raw_haz_WIRE_9[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_8_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_25 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_8_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_26 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_8_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_2 = _raw_hazard_pre_pre_raw_haz_T_25 & _raw_hazard_pre_pre_raw_haz_T_26; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_45; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_44; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_41; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_40 = _raw_hazard_pre_mul_raw_haz_WIRE_17[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_16_data = _raw_hazard_pre_mul_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_41 = _raw_hazard_pre_mul_raw_haz_WIRE_17[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_16_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_41; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_42 = _raw_hazard_pre_mul_raw_haz_WIRE_17[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_16_garbage = _raw_hazard_pre_mul_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_43 = _raw_hazard_pre_mul_raw_haz_WIRE_17[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_18 = _raw_hazard_pre_mul_raw_haz_T_43; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_19 = _raw_hazard_pre_mul_raw_haz_WIRE_18; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_16_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_44 = _raw_hazard_pre_mul_raw_haz_WIRE_17[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_16_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_44; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_45 = _raw_hazard_pre_mul_raw_haz_WIRE_17[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_16_accumulate = _raw_hazard_pre_mul_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_46 = _raw_hazard_pre_mul_raw_haz_WIRE_17[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_16_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_47 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_16_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_48 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_16_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_49 = _raw_hazard_pre_mul_raw_haz_T_47 & _raw_hazard_pre_mul_raw_haz_T_48; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_55; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_54; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_52; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_50 = _raw_hazard_pre_mul_raw_haz_WIRE_21[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_20_data = _raw_hazard_pre_mul_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_51 = _raw_hazard_pre_mul_raw_haz_WIRE_21[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_20_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_51; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_52 = _raw_hazard_pre_mul_raw_haz_WIRE_21[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_20_garbage = _raw_hazard_pre_mul_raw_haz_T_52; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_53 = _raw_hazard_pre_mul_raw_haz_WIRE_21[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_22 = _raw_hazard_pre_mul_raw_haz_T_53; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_23 = _raw_hazard_pre_mul_raw_haz_WIRE_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_20_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_54 = _raw_hazard_pre_mul_raw_haz_WIRE_21[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_20_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_54; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_55 = _raw_hazard_pre_mul_raw_haz_WIRE_21[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_20_accumulate = _raw_hazard_pre_mul_raw_haz_T_55; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_56 = _raw_hazard_pre_mul_raw_haz_WIRE_21[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_20_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_57 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_20_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_58 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_20_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_59 = _raw_hazard_pre_mul_raw_haz_T_57 & _raw_hazard_pre_mul_raw_haz_T_58; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_2 = _raw_hazard_pre_mul_raw_haz_T_49 | _raw_hazard_pre_mul_raw_haz_T_59; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_10 = ~raw_hazard_pre_is_garbage_2; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_11 = raw_hazard_pre_pre_raw_haz_2 | raw_hazard_pre_mul_raw_haz_2; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_12 = _raw_hazard_pre_T_10 & _raw_hazard_pre_T_11; // @[ExecuteController.scala:217:{5,17,33}]
wire _GEN_8 = _mesh_io_tags_in_progress_3_addr_is_acc_addr & _mesh_io_tags_in_progress_3_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_15; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_15 = _GEN_8; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_15; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_15 = _GEN_8; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_16 = _raw_hazard_pre_is_garbage_T_15 & _mesh_io_tags_in_progress_3_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_17 = &_mesh_io_tags_in_progress_3_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_18 = _raw_hazard_pre_is_garbage_T_16 & _raw_hazard_pre_is_garbage_T_17; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_19; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_3 = _raw_hazard_pre_is_garbage_T_18 & _raw_hazard_pre_is_garbage_T_19; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_33; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_31; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_29; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_28; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_27 = _raw_hazard_pre_pre_raw_haz_WIRE_13[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_12_data = _raw_hazard_pre_pre_raw_haz_T_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_28 = _raw_hazard_pre_pre_raw_haz_WIRE_13[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_12_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_28; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_29 = _raw_hazard_pre_pre_raw_haz_WIRE_13[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_12_garbage = _raw_hazard_pre_pre_raw_haz_T_29; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_30 = _raw_hazard_pre_pre_raw_haz_WIRE_13[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_14 = _raw_hazard_pre_pre_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_15 = _raw_hazard_pre_pre_raw_haz_WIRE_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_12_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_31 = _raw_hazard_pre_pre_raw_haz_WIRE_13[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_12_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_32 = _raw_hazard_pre_pre_raw_haz_WIRE_13[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_12_accumulate = _raw_hazard_pre_pre_raw_haz_T_32; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_33 = _raw_hazard_pre_pre_raw_haz_WIRE_13[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_12_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_33; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_34 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_12_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_35 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_12_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_3 = _raw_hazard_pre_pre_raw_haz_T_34 & _raw_hazard_pre_pre_raw_haz_T_35; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_66; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_65; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_64; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_62; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_61; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_60; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_60 = _raw_hazard_pre_mul_raw_haz_WIRE_25[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_24_data = _raw_hazard_pre_mul_raw_haz_T_60; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_61 = _raw_hazard_pre_mul_raw_haz_WIRE_25[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_24_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_61; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_62 = _raw_hazard_pre_mul_raw_haz_WIRE_25[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_24_garbage = _raw_hazard_pre_mul_raw_haz_T_62; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_63 = _raw_hazard_pre_mul_raw_haz_WIRE_25[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_26 = _raw_hazard_pre_mul_raw_haz_T_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_27 = _raw_hazard_pre_mul_raw_haz_WIRE_26; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_24_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_64 = _raw_hazard_pre_mul_raw_haz_WIRE_25[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_24_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_64; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_65 = _raw_hazard_pre_mul_raw_haz_WIRE_25[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_24_accumulate = _raw_hazard_pre_mul_raw_haz_T_65; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_66 = _raw_hazard_pre_mul_raw_haz_WIRE_25[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_24_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_66; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_67 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_24_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_68 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_24_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_69 = _raw_hazard_pre_mul_raw_haz_T_67 & _raw_hazard_pre_mul_raw_haz_T_68; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_76; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_75; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_74; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_72; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_71; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_70; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_70 = _raw_hazard_pre_mul_raw_haz_WIRE_29[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_28_data = _raw_hazard_pre_mul_raw_haz_T_70; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_71 = _raw_hazard_pre_mul_raw_haz_WIRE_29[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_28_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_71; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_72 = _raw_hazard_pre_mul_raw_haz_WIRE_29[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_28_garbage = _raw_hazard_pre_mul_raw_haz_T_72; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_73 = _raw_hazard_pre_mul_raw_haz_WIRE_29[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_30 = _raw_hazard_pre_mul_raw_haz_T_73; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_31 = _raw_hazard_pre_mul_raw_haz_WIRE_30; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_28_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_74 = _raw_hazard_pre_mul_raw_haz_WIRE_29[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_28_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_74; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_75 = _raw_hazard_pre_mul_raw_haz_WIRE_29[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_28_accumulate = _raw_hazard_pre_mul_raw_haz_T_75; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_76 = _raw_hazard_pre_mul_raw_haz_WIRE_29[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_28_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_76; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_77 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_28_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_78 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_28_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_79 = _raw_hazard_pre_mul_raw_haz_T_77 & _raw_hazard_pre_mul_raw_haz_T_78; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_3 = _raw_hazard_pre_mul_raw_haz_T_69 | _raw_hazard_pre_mul_raw_haz_T_79; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_15 = ~raw_hazard_pre_is_garbage_3; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_16 = raw_hazard_pre_pre_raw_haz_3 | raw_hazard_pre_mul_raw_haz_3; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_17 = _raw_hazard_pre_T_15 & _raw_hazard_pre_T_16; // @[ExecuteController.scala:217:{5,17,33}]
wire _GEN_9 = _mesh_io_tags_in_progress_4_addr_is_acc_addr & _mesh_io_tags_in_progress_4_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_20; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_20 = _GEN_9; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_20; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_20 = _GEN_9; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_21 = _raw_hazard_pre_is_garbage_T_20 & _mesh_io_tags_in_progress_4_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_22 = &_mesh_io_tags_in_progress_4_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_23 = _raw_hazard_pre_is_garbage_T_21 & _raw_hazard_pre_is_garbage_T_22; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_24; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_4 = _raw_hazard_pre_is_garbage_T_23 & _raw_hazard_pre_is_garbage_T_24; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_41; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_40; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_38; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_37; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_36; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_36 = _raw_hazard_pre_pre_raw_haz_WIRE_17[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_16_data = _raw_hazard_pre_pre_raw_haz_T_36; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_37 = _raw_hazard_pre_pre_raw_haz_WIRE_17[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_16_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_37; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_38 = _raw_hazard_pre_pre_raw_haz_WIRE_17[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_16_garbage = _raw_hazard_pre_pre_raw_haz_T_38; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_39 = _raw_hazard_pre_pre_raw_haz_WIRE_17[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_18 = _raw_hazard_pre_pre_raw_haz_T_39; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_19 = _raw_hazard_pre_pre_raw_haz_WIRE_18; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_16_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_40 = _raw_hazard_pre_pre_raw_haz_WIRE_17[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_16_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_41 = _raw_hazard_pre_pre_raw_haz_WIRE_17[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_16_accumulate = _raw_hazard_pre_pre_raw_haz_T_41; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_42 = _raw_hazard_pre_pre_raw_haz_WIRE_17[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_16_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_43 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_16_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_44 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_16_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_4 = _raw_hazard_pre_pre_raw_haz_T_43 & _raw_hazard_pre_pre_raw_haz_T_44; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_86; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_85; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_84; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_82; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_81; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_80; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_80 = _raw_hazard_pre_mul_raw_haz_WIRE_33[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_32_data = _raw_hazard_pre_mul_raw_haz_T_80; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_81 = _raw_hazard_pre_mul_raw_haz_WIRE_33[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_32_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_81; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_82 = _raw_hazard_pre_mul_raw_haz_WIRE_33[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_32_garbage = _raw_hazard_pre_mul_raw_haz_T_82; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_83 = _raw_hazard_pre_mul_raw_haz_WIRE_33[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_34 = _raw_hazard_pre_mul_raw_haz_T_83; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_35 = _raw_hazard_pre_mul_raw_haz_WIRE_34; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_32_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_84 = _raw_hazard_pre_mul_raw_haz_WIRE_33[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_32_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_84; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_85 = _raw_hazard_pre_mul_raw_haz_WIRE_33[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_32_accumulate = _raw_hazard_pre_mul_raw_haz_T_85; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_86 = _raw_hazard_pre_mul_raw_haz_WIRE_33[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_32_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_86; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_87 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_32_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_88 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_32_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_89 = _raw_hazard_pre_mul_raw_haz_T_87 & _raw_hazard_pre_mul_raw_haz_T_88; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_95; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_94; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_91; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_90 = _raw_hazard_pre_mul_raw_haz_WIRE_37[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_36_data = _raw_hazard_pre_mul_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_91 = _raw_hazard_pre_mul_raw_haz_WIRE_37[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_36_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_91; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_92 = _raw_hazard_pre_mul_raw_haz_WIRE_37[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_36_garbage = _raw_hazard_pre_mul_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_93 = _raw_hazard_pre_mul_raw_haz_WIRE_37[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_38 = _raw_hazard_pre_mul_raw_haz_T_93; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_39 = _raw_hazard_pre_mul_raw_haz_WIRE_38; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_36_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_94 = _raw_hazard_pre_mul_raw_haz_WIRE_37[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_36_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_94; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_95 = _raw_hazard_pre_mul_raw_haz_WIRE_37[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_36_accumulate = _raw_hazard_pre_mul_raw_haz_T_95; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_96 = _raw_hazard_pre_mul_raw_haz_WIRE_37[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_36_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_97 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_36_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_98 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_36_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_99 = _raw_hazard_pre_mul_raw_haz_T_97 & _raw_hazard_pre_mul_raw_haz_T_98; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_4 = _raw_hazard_pre_mul_raw_haz_T_89 | _raw_hazard_pre_mul_raw_haz_T_99; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_20 = ~raw_hazard_pre_is_garbage_4; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_21 = raw_hazard_pre_pre_raw_haz_4 | raw_hazard_pre_mul_raw_haz_4; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_22 = _raw_hazard_pre_T_20 & _raw_hazard_pre_T_21; // @[ExecuteController.scala:217:{5,17,33}]
wire _GEN_10 = _mesh_io_tags_in_progress_5_addr_is_acc_addr & _mesh_io_tags_in_progress_5_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_25; // @[LocalAddr.scala:43:48]
assign _raw_hazard_pre_is_garbage_T_25 = _GEN_10; // @[LocalAddr.scala:43:48]
wire _raw_hazard_mulpre_is_garbage_T_25; // @[LocalAddr.scala:43:48]
assign _raw_hazard_mulpre_is_garbage_T_25 = _GEN_10; // @[LocalAddr.scala:43:48]
wire _raw_hazard_pre_is_garbage_T_26 = _raw_hazard_pre_is_garbage_T_25 & _mesh_io_tags_in_progress_5_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_pre_is_garbage_T_27 = &_mesh_io_tags_in_progress_5_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_pre_is_garbage_T_28 = _raw_hazard_pre_is_garbage_T_26 & _raw_hazard_pre_is_garbage_T_27; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_pre_is_garbage_T_29; // @[LocalAddr.scala:44:48]
wire raw_hazard_pre_is_garbage_5 = _raw_hazard_pre_is_garbage_T_28 & _raw_hazard_pre_is_garbage_T_29; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_pre_pre_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_50; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_49; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_T_47; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_45 = _raw_hazard_pre_pre_raw_haz_WIRE_21[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_pre_raw_haz_WIRE_20_data = _raw_hazard_pre_pre_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_46 = _raw_hazard_pre_pre_raw_haz_WIRE_21[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_20_garbage_bit = _raw_hazard_pre_pre_raw_haz_T_46; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_47 = _raw_hazard_pre_pre_raw_haz_WIRE_21[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_pre_raw_haz_WIRE_20_garbage = _raw_hazard_pre_pre_raw_haz_T_47; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_T_48 = _raw_hazard_pre_pre_raw_haz_WIRE_21[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_22 = _raw_hazard_pre_pre_raw_haz_T_48; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_WIRE_23 = _raw_hazard_pre_pre_raw_haz_WIRE_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_pre_raw_haz_WIRE_20_norm_cmd = _raw_hazard_pre_pre_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_49 = _raw_hazard_pre_pre_raw_haz_WIRE_21[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_20_read_full_acc_row = _raw_hazard_pre_pre_raw_haz_T_49; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_50 = _raw_hazard_pre_pre_raw_haz_WIRE_21[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_20_accumulate = _raw_hazard_pre_pre_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_pre_raw_haz_T_51 = _raw_hazard_pre_pre_raw_haz_WIRE_21[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_WIRE_20_is_acc_addr = _raw_hazard_pre_pre_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_pre_raw_haz_T_52 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_pre_pre_raw_haz_WIRE_20_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_pre_raw_haz_T_53 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_pre_pre_raw_haz_WIRE_20_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_pre_pre_raw_haz_5 = _raw_hazard_pre_pre_raw_haz_T_52 & _raw_hazard_pre_pre_raw_haz_T_53; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_106; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_105; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_104; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_102; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_101; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_100; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_100 = _raw_hazard_pre_mul_raw_haz_WIRE_41[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_40_data = _raw_hazard_pre_mul_raw_haz_T_100; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_101 = _raw_hazard_pre_mul_raw_haz_WIRE_41[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_40_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_101; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_102 = _raw_hazard_pre_mul_raw_haz_WIRE_41[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_40_garbage = _raw_hazard_pre_mul_raw_haz_T_102; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_103 = _raw_hazard_pre_mul_raw_haz_WIRE_41[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_42 = _raw_hazard_pre_mul_raw_haz_T_103; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_43 = _raw_hazard_pre_mul_raw_haz_WIRE_42; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_40_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_104 = _raw_hazard_pre_mul_raw_haz_WIRE_41[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_40_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_104; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_105 = _raw_hazard_pre_mul_raw_haz_WIRE_41[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_40_accumulate = _raw_hazard_pre_mul_raw_haz_T_105; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_106 = _raw_hazard_pre_mul_raw_haz_WIRE_41[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_40_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_106; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_107 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_40_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_108 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_40_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_109 = _raw_hazard_pre_mul_raw_haz_T_107 & _raw_hazard_pre_mul_raw_haz_T_108; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_pre_mul_raw_haz_T_116; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_115; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_114; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_T_112; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_111; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_T_110; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_110 = _raw_hazard_pre_mul_raw_haz_WIRE_45[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_pre_mul_raw_haz_WIRE_44_data = _raw_hazard_pre_mul_raw_haz_T_110; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_111 = _raw_hazard_pre_mul_raw_haz_WIRE_45[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_44_garbage_bit = _raw_hazard_pre_mul_raw_haz_T_111; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_112 = _raw_hazard_pre_mul_raw_haz_WIRE_45[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_pre_mul_raw_haz_WIRE_44_garbage = _raw_hazard_pre_mul_raw_haz_T_112; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_T_113 = _raw_hazard_pre_mul_raw_haz_WIRE_45[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_46 = _raw_hazard_pre_mul_raw_haz_T_113; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_WIRE_47 = _raw_hazard_pre_mul_raw_haz_WIRE_46; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_pre_mul_raw_haz_WIRE_44_norm_cmd = _raw_hazard_pre_mul_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_114 = _raw_hazard_pre_mul_raw_haz_WIRE_45[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_44_read_full_acc_row = _raw_hazard_pre_mul_raw_haz_T_114; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_115 = _raw_hazard_pre_mul_raw_haz_WIRE_45[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_44_accumulate = _raw_hazard_pre_mul_raw_haz_T_115; // @[LocalAddr.scala:42:74]
assign _raw_hazard_pre_mul_raw_haz_T_116 = _raw_hazard_pre_mul_raw_haz_WIRE_45[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_WIRE_44_is_acc_addr = _raw_hazard_pre_mul_raw_haz_T_116; // @[LocalAddr.scala:42:74]
wire _raw_hazard_pre_mul_raw_haz_T_117 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_pre_mul_raw_haz_WIRE_44_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_118 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_pre_mul_raw_haz_WIRE_44_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_pre_mul_raw_haz_T_119 = _raw_hazard_pre_mul_raw_haz_T_117 & _raw_hazard_pre_mul_raw_haz_T_118; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_pre_mul_raw_haz_5 = _raw_hazard_pre_mul_raw_haz_T_109 | _raw_hazard_pre_mul_raw_haz_T_119; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_25 = ~raw_hazard_pre_is_garbage_5; // @[LocalAddr.scala:43:96]
wire _raw_hazard_pre_T_26 = raw_hazard_pre_pre_raw_haz_5 | raw_hazard_pre_mul_raw_haz_5; // @[LocalAddr.scala:41:83]
wire _raw_hazard_pre_T_27 = _raw_hazard_pre_T_25 & _raw_hazard_pre_T_26; // @[ExecuteController.scala:217:{5,17,33}]
wire _raw_hazard_mulpre_is_garbage_T_1 = _raw_hazard_mulpre_is_garbage_T & _mesh_io_tags_in_progress_0_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_2 = &_mesh_io_tags_in_progress_0_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_3 = _raw_hazard_mulpre_is_garbage_T_1 & _raw_hazard_mulpre_is_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_4; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage = _raw_hazard_mulpre_is_garbage_T_3 & _raw_hazard_mulpre_is_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_5; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_4; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_1; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_data = _raw_hazard_mulpre_pre_raw_haz_T; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_1 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_1; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_2 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_garbage = _raw_hazard_mulpre_pre_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_3 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_2 = _raw_hazard_mulpre_pre_raw_haz_T_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_3 = _raw_hazard_mulpre_pre_raw_haz_WIRE_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_4 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_4; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_5 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_5; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_6 = _raw_hazard_mulpre_pre_raw_haz_WIRE_1[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_7 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_8 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz = _raw_hazard_mulpre_pre_raw_haz_T_7 & _raw_hazard_mulpre_pre_raw_haz_T_8; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_5; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_4; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_1; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_1 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_9 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_17 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_25 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_33 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_41 = rs1s_2[31:0]; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_data = _raw_hazard_mulpre_mul_raw_haz_T; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_1 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_1; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_2 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_garbage = _raw_hazard_mulpre_mul_raw_haz_T_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_3 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_2 = _raw_hazard_mulpre_mul_raw_haz_T_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_3 = _raw_hazard_mulpre_mul_raw_haz_WIRE_2; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_3; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_4 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_4; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_5 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_5; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_6 = _raw_hazard_mulpre_mul_raw_haz_WIRE_1[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_6; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_7 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_8 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_9 = _raw_hazard_mulpre_mul_raw_haz_T_7 & _raw_hazard_mulpre_mul_raw_haz_T_8; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_16; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_12; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_10; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_5 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_13 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_21 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_29 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_37 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
wire [31:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_45 = rs2s_2[31:0]; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_10 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_4_data = _raw_hazard_mulpre_mul_raw_haz_T_10; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_11 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_4_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_12 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_4_garbage = _raw_hazard_mulpre_mul_raw_haz_T_12; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_13 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_6 = _raw_hazard_mulpre_mul_raw_haz_T_13; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_7 = _raw_hazard_mulpre_mul_raw_haz_WIRE_6; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_4_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_14 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_4_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_14; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_15 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_4_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_16 = _raw_hazard_mulpre_mul_raw_haz_WIRE_5[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_4_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_16; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_17 = _mesh_io_tags_in_progress_0_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_4_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_18 = _mesh_io_tags_in_progress_0_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_4_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_19 = _raw_hazard_mulpre_mul_raw_haz_T_17 & _raw_hazard_mulpre_mul_raw_haz_T_18; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz = _raw_hazard_mulpre_mul_raw_haz_T_9 | _raw_hazard_mulpre_mul_raw_haz_T_19; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T = ~raw_hazard_mulpre_is_garbage; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_1 = raw_hazard_mulpre_mul_raw_haz | raw_hazard_mulpre_pre_raw_haz; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_2 = _raw_hazard_mulpre_T & _raw_hazard_mulpre_T_1; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_is_garbage_T_6 = _raw_hazard_mulpre_is_garbage_T_5 & _mesh_io_tags_in_progress_1_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_7 = &_mesh_io_tags_in_progress_1_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_8 = _raw_hazard_mulpre_is_garbage_T_6 & _raw_hazard_mulpre_is_garbage_T_7; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_9; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_1 = _raw_hazard_mulpre_is_garbage_T_8 & _raw_hazard_mulpre_is_garbage_T_9; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_14; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_13; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_10; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_9; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_9 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_4_data = _raw_hazard_mulpre_pre_raw_haz_T_9; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_10 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_4_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_10; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_11 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_4_garbage = _raw_hazard_mulpre_pre_raw_haz_T_11; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_12 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_6 = _raw_hazard_mulpre_pre_raw_haz_T_12; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_7 = _raw_hazard_mulpre_pre_raw_haz_WIRE_6; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_4_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_7; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_13 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_4_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_13; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_14 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_4_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_14; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_15 = _raw_hazard_mulpre_pre_raw_haz_WIRE_5[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_4_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_15; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_16 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_4_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_17 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_4_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_1 = _raw_hazard_mulpre_pre_raw_haz_T_16 & _raw_hazard_mulpre_pre_raw_haz_T_17; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_26; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_25; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_21; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_20; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_20 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_8_data = _raw_hazard_mulpre_mul_raw_haz_T_20; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_21 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_8_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_21; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_22 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_8_garbage = _raw_hazard_mulpre_mul_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_23 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_10 = _raw_hazard_mulpre_mul_raw_haz_T_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_11 = _raw_hazard_mulpre_mul_raw_haz_WIRE_10; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_8_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_24 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_8_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_24; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_25 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_8_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_25; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_26 = _raw_hazard_mulpre_mul_raw_haz_WIRE_9[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_8_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_26; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_27 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_8_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_28 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_8_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_29 = _raw_hazard_mulpre_mul_raw_haz_T_27 & _raw_hazard_mulpre_mul_raw_haz_T_28; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_36; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_35; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_34; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_31; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_30 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_12_data = _raw_hazard_mulpre_mul_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_31 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_12_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_32 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_12_garbage = _raw_hazard_mulpre_mul_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_33 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_14 = _raw_hazard_mulpre_mul_raw_haz_T_33; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_15 = _raw_hazard_mulpre_mul_raw_haz_WIRE_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_12_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_34 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_12_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_34; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_35 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_12_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_35; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_36 = _raw_hazard_mulpre_mul_raw_haz_WIRE_13[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_12_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_36; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_37 = _mesh_io_tags_in_progress_1_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_12_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_38 = _mesh_io_tags_in_progress_1_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_12_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_39 = _raw_hazard_mulpre_mul_raw_haz_T_37 & _raw_hazard_mulpre_mul_raw_haz_T_38; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_1 = _raw_hazard_mulpre_mul_raw_haz_T_29 | _raw_hazard_mulpre_mul_raw_haz_T_39; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_5 = ~raw_hazard_mulpre_is_garbage_1; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_6 = raw_hazard_mulpre_mul_raw_haz_1 | raw_hazard_mulpre_pre_raw_haz_1; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_7 = _raw_hazard_mulpre_T_5 & _raw_hazard_mulpre_T_6; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_is_garbage_T_11 = _raw_hazard_mulpre_is_garbage_T_10 & _mesh_io_tags_in_progress_2_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_12 = &_mesh_io_tags_in_progress_2_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_13 = _raw_hazard_mulpre_is_garbage_T_11 & _raw_hazard_mulpre_is_garbage_T_12; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_14; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_2 = _raw_hazard_mulpre_is_garbage_T_13 & _raw_hazard_mulpre_is_garbage_T_14; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_23; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_20; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_19; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_18; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_18 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_8_data = _raw_hazard_mulpre_pre_raw_haz_T_18; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_19 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_8_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_20 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_8_garbage = _raw_hazard_mulpre_pre_raw_haz_T_20; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_21 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_10 = _raw_hazard_mulpre_pre_raw_haz_T_21; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_11 = _raw_hazard_mulpre_pre_raw_haz_WIRE_10; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_8_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_11; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_22 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_8_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_22; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_23 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_8_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_24 = _raw_hazard_mulpre_pre_raw_haz_WIRE_9[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_8_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_24; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_25 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_8_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_26 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_8_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_2 = _raw_hazard_mulpre_pre_raw_haz_T_25 & _raw_hazard_mulpre_pre_raw_haz_T_26; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_45; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_44; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_41; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_40 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_16_data = _raw_hazard_mulpre_mul_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_41 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_16_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_41; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_42 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_16_garbage = _raw_hazard_mulpre_mul_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_43 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_18 = _raw_hazard_mulpre_mul_raw_haz_T_43; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_19 = _raw_hazard_mulpre_mul_raw_haz_WIRE_18; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_16_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_44 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_16_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_44; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_45 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_16_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_46 = _raw_hazard_mulpre_mul_raw_haz_WIRE_17[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_16_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_47 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_16_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_48 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_16_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_49 = _raw_hazard_mulpre_mul_raw_haz_T_47 & _raw_hazard_mulpre_mul_raw_haz_T_48; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_55; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_54; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_52; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_50 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_20_data = _raw_hazard_mulpre_mul_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_51 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_20_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_51; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_52 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_20_garbage = _raw_hazard_mulpre_mul_raw_haz_T_52; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_53 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_22 = _raw_hazard_mulpre_mul_raw_haz_T_53; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_23 = _raw_hazard_mulpre_mul_raw_haz_WIRE_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_20_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_54 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_20_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_54; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_55 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_20_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_55; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_56 = _raw_hazard_mulpre_mul_raw_haz_WIRE_21[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_20_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_56; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_57 = _mesh_io_tags_in_progress_2_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_20_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_58 = _mesh_io_tags_in_progress_2_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_20_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_59 = _raw_hazard_mulpre_mul_raw_haz_T_57 & _raw_hazard_mulpre_mul_raw_haz_T_58; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_2 = _raw_hazard_mulpre_mul_raw_haz_T_49 | _raw_hazard_mulpre_mul_raw_haz_T_59; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_10 = ~raw_hazard_mulpre_is_garbage_2; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_11 = raw_hazard_mulpre_mul_raw_haz_2 | raw_hazard_mulpre_pre_raw_haz_2; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_12 = _raw_hazard_mulpre_T_10 & _raw_hazard_mulpre_T_11; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_is_garbage_T_16 = _raw_hazard_mulpre_is_garbage_T_15 & _mesh_io_tags_in_progress_3_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_17 = &_mesh_io_tags_in_progress_3_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_18 = _raw_hazard_mulpre_is_garbage_T_16 & _raw_hazard_mulpre_is_garbage_T_17; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_19; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_3 = _raw_hazard_mulpre_is_garbage_T_18 & _raw_hazard_mulpre_is_garbage_T_19; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_33; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_32; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_31; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_29; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_28; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_27 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_12_data = _raw_hazard_mulpre_pre_raw_haz_T_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_28 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_12_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_28; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_29 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_12_garbage = _raw_hazard_mulpre_pre_raw_haz_T_29; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_30 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_14 = _raw_hazard_mulpre_pre_raw_haz_T_30; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_15 = _raw_hazard_mulpre_pre_raw_haz_WIRE_14; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_12_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_15; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_31 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_12_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_32 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_12_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_32; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_33 = _raw_hazard_mulpre_pre_raw_haz_WIRE_13[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_12_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_33; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_34 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_12_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_35 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_12_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_3 = _raw_hazard_mulpre_pre_raw_haz_T_34 & _raw_hazard_mulpre_pre_raw_haz_T_35; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_66; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_65; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_64; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_62; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_61; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_60; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_60 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_24_data = _raw_hazard_mulpre_mul_raw_haz_T_60; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_61 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_24_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_61; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_62 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_24_garbage = _raw_hazard_mulpre_mul_raw_haz_T_62; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_63 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_26 = _raw_hazard_mulpre_mul_raw_haz_T_63; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_27 = _raw_hazard_mulpre_mul_raw_haz_WIRE_26; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_24_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_27; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_64 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_24_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_64; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_65 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_24_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_65; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_66 = _raw_hazard_mulpre_mul_raw_haz_WIRE_25[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_24_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_66; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_67 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_24_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_68 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_24_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_69 = _raw_hazard_mulpre_mul_raw_haz_T_67 & _raw_hazard_mulpre_mul_raw_haz_T_68; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_76; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_75; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_74; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_72; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_71; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_70; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_70 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_28_data = _raw_hazard_mulpre_mul_raw_haz_T_70; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_71 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_28_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_71; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_72 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_28_garbage = _raw_hazard_mulpre_mul_raw_haz_T_72; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_73 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_30 = _raw_hazard_mulpre_mul_raw_haz_T_73; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_31 = _raw_hazard_mulpre_mul_raw_haz_WIRE_30; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_28_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_31; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_74 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_28_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_74; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_75 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_28_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_75; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_76 = _raw_hazard_mulpre_mul_raw_haz_WIRE_29[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_28_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_76; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_77 = _mesh_io_tags_in_progress_3_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_28_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_78 = _mesh_io_tags_in_progress_3_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_28_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_79 = _raw_hazard_mulpre_mul_raw_haz_T_77 & _raw_hazard_mulpre_mul_raw_haz_T_78; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_3 = _raw_hazard_mulpre_mul_raw_haz_T_69 | _raw_hazard_mulpre_mul_raw_haz_T_79; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_15 = ~raw_hazard_mulpre_is_garbage_3; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_16 = raw_hazard_mulpre_mul_raw_haz_3 | raw_hazard_mulpre_pre_raw_haz_3; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_17 = _raw_hazard_mulpre_T_15 & _raw_hazard_mulpre_T_16; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_is_garbage_T_21 = _raw_hazard_mulpre_is_garbage_T_20 & _mesh_io_tags_in_progress_4_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_22 = &_mesh_io_tags_in_progress_4_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_23 = _raw_hazard_mulpre_is_garbage_T_21 & _raw_hazard_mulpre_is_garbage_T_22; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_24; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_4 = _raw_hazard_mulpre_is_garbage_T_23 & _raw_hazard_mulpre_is_garbage_T_24; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_41; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_40; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_38; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_37; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_36; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_36 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_16_data = _raw_hazard_mulpre_pre_raw_haz_T_36; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_37 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_16_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_37; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_38 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_16_garbage = _raw_hazard_mulpre_pre_raw_haz_T_38; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_39 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_18 = _raw_hazard_mulpre_pre_raw_haz_T_39; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_19 = _raw_hazard_mulpre_pre_raw_haz_WIRE_18; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_16_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_19; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_40 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_16_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_40; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_41 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_16_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_41; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_42 = _raw_hazard_mulpre_pre_raw_haz_WIRE_17[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_16_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_42; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_43 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_16_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_44 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_16_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_4 = _raw_hazard_mulpre_pre_raw_haz_T_43 & _raw_hazard_mulpre_pre_raw_haz_T_44; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_86; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_85; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_84; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_82; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_81; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_80; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_80 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_32_data = _raw_hazard_mulpre_mul_raw_haz_T_80; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_81 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_32_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_81; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_82 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_32_garbage = _raw_hazard_mulpre_mul_raw_haz_T_82; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_83 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_34 = _raw_hazard_mulpre_mul_raw_haz_T_83; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_35 = _raw_hazard_mulpre_mul_raw_haz_WIRE_34; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_32_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_35; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_84 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_32_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_84; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_85 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_32_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_85; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_86 = _raw_hazard_mulpre_mul_raw_haz_WIRE_33[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_32_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_86; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_87 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_32_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_88 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_32_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_89 = _raw_hazard_mulpre_mul_raw_haz_T_87 & _raw_hazard_mulpre_mul_raw_haz_T_88; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_95; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_94; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_91; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_90 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_36_data = _raw_hazard_mulpre_mul_raw_haz_T_90; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_91 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_36_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_91; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_92 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_36_garbage = _raw_hazard_mulpre_mul_raw_haz_T_92; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_93 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_38 = _raw_hazard_mulpre_mul_raw_haz_T_93; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_39 = _raw_hazard_mulpre_mul_raw_haz_WIRE_38; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_36_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_39; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_94 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_36_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_94; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_95 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_36_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_95; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_96 = _raw_hazard_mulpre_mul_raw_haz_WIRE_37[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_36_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_96; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_97 = _mesh_io_tags_in_progress_4_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_36_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_98 = _mesh_io_tags_in_progress_4_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_36_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_99 = _raw_hazard_mulpre_mul_raw_haz_T_97 & _raw_hazard_mulpre_mul_raw_haz_T_98; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_4 = _raw_hazard_mulpre_mul_raw_haz_T_89 | _raw_hazard_mulpre_mul_raw_haz_T_99; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_20 = ~raw_hazard_mulpre_is_garbage_4; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_21 = raw_hazard_mulpre_mul_raw_haz_4 | raw_hazard_mulpre_pre_raw_haz_4; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_22 = _raw_hazard_mulpre_T_20 & _raw_hazard_mulpre_T_21; // @[ExecuteController.scala:225:{5,17,33}]
wire _raw_hazard_mulpre_is_garbage_T_26 = _raw_hazard_mulpre_is_garbage_T_25 & _mesh_io_tags_in_progress_5_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _raw_hazard_mulpre_is_garbage_T_27 = &_mesh_io_tags_in_progress_5_addr_data; // @[LocalAddr.scala:43:91]
wire _raw_hazard_mulpre_is_garbage_T_28 = _raw_hazard_mulpre_is_garbage_T_26 & _raw_hazard_mulpre_is_garbage_T_27; // @[LocalAddr.scala:43:{62,83,91}]
wire _raw_hazard_mulpre_is_garbage_T_29; // @[LocalAddr.scala:44:48]
wire raw_hazard_mulpre_is_garbage_5 = _raw_hazard_mulpre_is_garbage_T_28 & _raw_hazard_mulpre_is_garbage_T_29; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _raw_hazard_mulpre_pre_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_50; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_49; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_T_47; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_46; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_45 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_20_data = _raw_hazard_mulpre_pre_raw_haz_T_45; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_46 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_20_garbage_bit = _raw_hazard_mulpre_pre_raw_haz_T_46; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_47 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_20_garbage = _raw_hazard_mulpre_pre_raw_haz_T_47; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_T_48 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_22 = _raw_hazard_mulpre_pre_raw_haz_T_48; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_WIRE_23 = _raw_hazard_mulpre_pre_raw_haz_WIRE_22; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_pre_raw_haz_WIRE_20_norm_cmd = _raw_hazard_mulpre_pre_raw_haz_WIRE_23; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_49 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_20_read_full_acc_row = _raw_hazard_mulpre_pre_raw_haz_T_49; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_50 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_20_accumulate = _raw_hazard_mulpre_pre_raw_haz_T_50; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_pre_raw_haz_T_51 = _raw_hazard_mulpre_pre_raw_haz_WIRE_21[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_WIRE_20_is_acc_addr = _raw_hazard_mulpre_pre_raw_haz_T_51; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_52 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_mulpre_pre_raw_haz_WIRE_20_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_pre_raw_haz_T_53 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_mulpre_pre_raw_haz_WIRE_20_data; // @[LocalAddr.scala:41:91, :42:74]
wire raw_hazard_mulpre_pre_raw_haz_5 = _raw_hazard_mulpre_pre_raw_haz_T_52 & _raw_hazard_mulpre_pre_raw_haz_T_53; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_106; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_105; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_104; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_102; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_101; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_100; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_100 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_40_data = _raw_hazard_mulpre_mul_raw_haz_T_100; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_101 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_40_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_101; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_102 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_40_garbage = _raw_hazard_mulpre_mul_raw_haz_T_102; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_103 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_42 = _raw_hazard_mulpre_mul_raw_haz_T_103; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_43 = _raw_hazard_mulpre_mul_raw_haz_WIRE_42; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_40_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_43; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_104 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_40_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_104; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_105 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_40_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_105; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_106 = _raw_hazard_mulpre_mul_raw_haz_WIRE_41[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_40_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_106; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_107 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_40_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_108 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_40_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_109 = _raw_hazard_mulpre_mul_raw_haz_T_107 & _raw_hazard_mulpre_mul_raw_haz_T_108; // @[LocalAddr.scala:41:{61,83,91}]
wire _raw_hazard_mulpre_mul_raw_haz_T_116; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_115; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_114; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_T_112; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_111; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_T_110; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_110 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[13:0]; // @[LocalAddr.scala:42:74]
wire [13:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_44_data = _raw_hazard_mulpre_mul_raw_haz_T_110; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_111 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[14]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_44_garbage_bit = _raw_hazard_mulpre_mul_raw_haz_T_111; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_112 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[25:15]; // @[LocalAddr.scala:42:74]
wire [10:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_44_garbage = _raw_hazard_mulpre_mul_raw_haz_T_112; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_T_113 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[28:26]; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_46 = _raw_hazard_mulpre_mul_raw_haz_T_113; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_WIRE_47 = _raw_hazard_mulpre_mul_raw_haz_WIRE_46; // @[LocalAddr.scala:42:74]
wire [2:0] _raw_hazard_mulpre_mul_raw_haz_WIRE_44_norm_cmd = _raw_hazard_mulpre_mul_raw_haz_WIRE_47; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_114 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[29]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_44_read_full_acc_row = _raw_hazard_mulpre_mul_raw_haz_T_114; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_115 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[30]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_44_accumulate = _raw_hazard_mulpre_mul_raw_haz_T_115; // @[LocalAddr.scala:42:74]
assign _raw_hazard_mulpre_mul_raw_haz_T_116 = _raw_hazard_mulpre_mul_raw_haz_WIRE_45[31]; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_WIRE_44_is_acc_addr = _raw_hazard_mulpre_mul_raw_haz_T_116; // @[LocalAddr.scala:42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_117 = _mesh_io_tags_in_progress_5_addr_is_acc_addr == _raw_hazard_mulpre_mul_raw_haz_WIRE_44_is_acc_addr; // @[LocalAddr.scala:41:61, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_118 = _mesh_io_tags_in_progress_5_addr_data == _raw_hazard_mulpre_mul_raw_haz_WIRE_44_data; // @[LocalAddr.scala:41:91, :42:74]
wire _raw_hazard_mulpre_mul_raw_haz_T_119 = _raw_hazard_mulpre_mul_raw_haz_T_117 & _raw_hazard_mulpre_mul_raw_haz_T_118; // @[LocalAddr.scala:41:{61,83,91}]
wire raw_hazard_mulpre_mul_raw_haz_5 = _raw_hazard_mulpre_mul_raw_haz_T_109 | _raw_hazard_mulpre_mul_raw_haz_T_119; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_25 = ~raw_hazard_mulpre_is_garbage_5; // @[LocalAddr.scala:43:96]
wire _raw_hazard_mulpre_T_26 = raw_hazard_mulpre_mul_raw_haz_5 | raw_hazard_mulpre_pre_raw_haz_5; // @[LocalAddr.scala:41:83]
wire _raw_hazard_mulpre_T_27 = _raw_hazard_mulpre_T_25 & _raw_hazard_mulpre_T_26; // @[ExecuteController.scala:225:{5,17,33}]
wire _third_instruction_needed_T = a_address_place[1]; // @[ExecuteController.scala:124:28, :228:50]
wire _third_instruction_needed_T_1 = b_address_place[1]; // @[ExecuteController.scala:127:28, :228:75]
wire _third_instruction_needed_T_2 = _third_instruction_needed_T | _third_instruction_needed_T_1; // @[ExecuteController.scala:228:{50,56,75}]
wire _third_instruction_needed_T_4 = _third_instruction_needed_T_2; // @[ExecuteController.scala:228:{56,81}]
wire third_instruction_needed = _third_instruction_needed_T_4; // @[ExecuteController.scala:228:{81,108}]
wire _matmul_in_progress_T = _mesh_io_tags_in_progress_0_rob_id_valid | _mesh_io_tags_in_progress_1_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_1 = _matmul_in_progress_T | _mesh_io_tags_in_progress_2_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_2 = _matmul_in_progress_T_1 | _mesh_io_tags_in_progress_3_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire _matmul_in_progress_T_3 = _matmul_in_progress_T_2 | _mesh_io_tags_in_progress_4_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
wire matmul_in_progress = _matmul_in_progress_T_3 | _mesh_io_tags_in_progress_5_rob_id_valid; // @[ExecuteController.scala:186:20, :230:82]
assign _io_busy_T = _cmd_q_io_deq_valid_0 | matmul_in_progress; // @[MultiHeadedQueue.scala:53:19]
assign io_busy_0 = _io_busy_T; // @[ExecuteController.scala:12:7, :232:27]
reg [3:0] a_fire_counter; // @[ExecuteController.scala:236:27]
reg [3:0] b_fire_counter; // @[ExecuteController.scala:237:27]
reg [3:0] d_fire_counter; // @[ExecuteController.scala:238:27]
wire [3:0] d_fire_counter_mulpre = d_fire_counter; // @[ExecuteController.scala:238:27, :417:39]
reg a_fire_started; // @[ExecuteController.scala:240:31]
reg d_fire_started; // @[ExecuteController.scala:241:31]
reg b_fire_started; // @[ExecuteController.scala:242:31]
reg [19:0] a_addr_offset; // @[ExecuteController.scala:245:26]
reg [15:0] a_addr_stride; // @[ExecuteController.scala:246:26]
reg [15:0] c_addr_stride; // @[ExecuteController.scala:249:26]
wire _same_banks_T_3 = a_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_27 = a_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire [13:0] a_address_data; // @[LocalAddr.scala:50:26]
wire [20:0] _GEN_11 = {1'h0, a_addr_offset}; // @[LocalAddr.scala:51:25]
wire [20:0] _a_address_result_data_T = {7'h0, a_address_rs1_data} + _GEN_11; // @[LocalAddr.scala:51:25]
wire [19:0] _a_address_result_data_T_1 = _a_address_result_data_T[19:0]; // @[LocalAddr.scala:51:25]
assign a_address_data = _a_address_result_data_T_1[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}]
wire [13:0] _b_address_result_data_T_1; // @[LocalAddr.scala:51:25]
wire [13:0] b_address_data; // @[LocalAddr.scala:50:26]
wire [14:0] _b_address_result_data_T = {11'h0, b_fire_counter} + 15'h3FFF; // @[LocalAddr.scala:51:25]
assign _b_address_result_data_T_1 = _b_address_result_data_T[13:0]; // @[LocalAddr.scala:51:25]
assign b_address_data = _b_address_result_data_T_1; // @[LocalAddr.scala:50:26, :51:25]
wire [5:0] _GEN_12 = {2'h0, d_fire_counter}; // @[ExecuteController.scala:238:27, :253:55]
wire [5:0] _GEN_13 = 6'hF - _GEN_12; // @[ExecuteController.scala:253:55]
wire [5:0] _d_address_T_2; // @[ExecuteController.scala:253:55]
assign _d_address_T_2 = _GEN_13; // @[ExecuteController.scala:253:55]
wire [5:0] _d_row_is_not_all_zeros_T_2; // @[ExecuteController.scala:312:51]
assign _d_row_is_not_all_zeros_T_2 = _GEN_13; // @[ExecuteController.scala:253:55, :312:51]
wire [4:0] _d_address_T_3 = _d_address_T_2[4:0]; // @[ExecuteController.scala:253:55]
wire _same_banks_T_39 = d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_63 = d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire [13:0] _d_address_result_data_T_1; // @[LocalAddr.scala:51:25]
wire [13:0] d_address_data; // @[LocalAddr.scala:50:26]
wire [14:0] _d_address_result_data_T = {1'h0, d_address_rs1_data} + {10'h0, _d_address_T_3}; // @[LocalAddr.scala:51:25]
assign _d_address_result_data_T_1 = _d_address_result_data_T[13:0]; // @[LocalAddr.scala:51:25]
assign d_address_data = _d_address_result_data_T_1; // @[LocalAddr.scala:50:26, :51:25]
wire [1:0] dataAbank = a_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_7 = a_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_19 = a_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_32 = a_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_56 = a_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] dataBbank = b_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_8 = b_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_31 = b_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_43 = b_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_68 = b_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] dataDbank = d_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_20 = d_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_44 = d_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_55 = d_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire [1:0] _same_banks_T_67 = d_address_data[13:12]; // @[LocalAddr.scala:33:79, :50:26]
wire dataABankAcc = a_address_data[9]; // @[LocalAddr.scala:35:82, :50:26]
wire _read_a_from_acc_T_10 = dataABankAcc; // @[LocalAddr.scala:35:82]
wire dataBBankAcc = b_address_data[9]; // @[LocalAddr.scala:35:82, :50:26]
wire _read_b_from_acc_T_7 = dataBBankAcc; // @[LocalAddr.scala:35:82]
wire dataDBankAcc = d_address_data[9]; // @[LocalAddr.scala:35:82, :50:26]
wire _read_d_from_acc_T_7 = dataDBankAcc; // @[LocalAddr.scala:35:82]
assign io_im2col_req_bits_start_inputting_0 = start_inputting_a; // @[ExecuteController.scala:12:7, :267:35]
wire start_inputting_b; // @[ExecuteController.scala:268:35]
wire start_inputting_d; // @[ExecuteController.scala:269:35]
wire start_array_outputting; // @[ExecuteController.scala:270:40]
wire _a_garbage_T_1 = _a_garbage_T & a_address_rs1_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _a_garbage_T_2 = &a_address_rs1_data; // @[LocalAddr.scala:43:91]
wire _a_garbage_T_3 = _a_garbage_T_1 & _a_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _a_garbage_T_5 = _a_garbage_T_3 & _a_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _a_garbage_T_6 = ~start_inputting_a; // @[ExecuteController.scala:267:35, :272:49]
wire a_garbage = _a_garbage_T_5 | _a_garbage_T_6; // @[LocalAddr.scala:43:96]
wire _b_garbage_T_6 = ~start_inputting_b; // @[ExecuteController.scala:268:35, :273:49]
wire _d_garbage_T_1 = _d_garbage_T & d_address_rs1_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _d_garbage_T_2 = &d_address_rs1_data; // @[LocalAddr.scala:43:91]
wire _d_garbage_T_3 = _d_garbage_T_1 & _d_garbage_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _d_garbage_T_5 = _d_garbage_T_3 & _d_garbage_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _d_garbage_T_6 = ~start_inputting_d; // @[ExecuteController.scala:269:35, :274:49]
wire d_garbage = _d_garbage_T_5 | _d_garbage_T_6; // @[LocalAddr.scala:43:96]
reg perform_single_preload; // @[ExecuteController.scala:277:39]
reg perform_single_mul; // @[ExecuteController.scala:278:35]
reg perform_mul_pre; // @[ExecuteController.scala:279:32]
wire _T_615 = control_state == 2'h1; // @[ExecuteController.scala:74:30, :281:84]
assign io_counter_event_signal_24_0 = _T_615; // @[ExecuteController.scala:12:7, :281:84]
wire _performing_single_preload_T; // @[ExecuteController.scala:281:84]
assign _performing_single_preload_T = _T_615; // @[ExecuteController.scala:281:84]
wire _performing_single_mul_T; // @[ExecuteController.scala:282:76]
assign _performing_single_mul_T = _T_615; // @[ExecuteController.scala:281:84, :282:76]
wire _performing_mul_pre_T; // @[ExecuteController.scala:283:70]
assign _performing_mul_pre_T = _T_615; // @[ExecuteController.scala:281:84, :283:70]
wire _performing_single_preload_T_1 = perform_single_preload & _performing_single_preload_T; // @[ExecuteController.scala:277:39, :281:{67,84}]
wire performing_single_preload; // @[ExecuteController.scala:281:43]
wire _performing_single_mul_T_1 = perform_single_mul & _performing_single_mul_T; // @[ExecuteController.scala:278:35, :282:{59,76}]
wire performing_single_mul; // @[ExecuteController.scala:282:39]
wire _performing_mul_pre_T_1 = perform_mul_pre & _performing_mul_pre_T; // @[ExecuteController.scala:279:32, :283:{53,70}]
wire performing_mul_pre; // @[ExecuteController.scala:283:36]
wire [4:0] total_rows; // @[ExecuteController.scala:285:28]
wire [4:0] rows_a = a_garbage ? 5'h1 : a_rows; // @[ExecuteController.scala:162:19, :272:46, :290:21]
wire _total_rows_T = |(rows_a[4:1]); // @[Util.scala:100:12]
wire [4:0] _total_rows_T_1 = _total_rows_T ? rows_a : 5'h1; // @[Util.scala:100:{8,12}]
wire _total_rows_T_2 = _total_rows_T_1 > 5'h4; // @[Util.scala:100:{8,12}]
wire [4:0] _total_rows_T_3 = _total_rows_T_2 ? _total_rows_T_1 : 5'h4; // @[Util.scala:100:{8,12}]
assign total_rows = d_garbage & ~a_should_be_fed_into_transposer & ~d_should_be_fed_into_transposer ? _total_rows_T_3 : 5'h10; // @[Util.scala:100:8]
reg [2:0] mul_pre_counter_sub; // @[ExecuteController.scala:305:36]
reg [2:0] mul_pre_counter_count; // @[ExecuteController.scala:306:38]
reg mul_pre_counter_lock; // @[ExecuteController.scala:307:37]
wire [4:0] _GEN_14 = {1'h0, a_fire_counter}; // @[ExecuteController.scala:236:27, :310:47]
wire a_row_is_not_all_zeros = _GEN_14 < a_rows; // @[ExecuteController.scala:162:19, :310:47]
wire [4:0] _GEN_15 = {1'h0, b_fire_counter}; // @[ExecuteController.scala:237:27, :311:47]
wire b_row_is_not_all_zeros = _GEN_15 < b_rows; // @[ExecuteController.scala:164:19, :311:47]
wire [4:0] _d_row_is_not_all_zeros_T_3 = _d_row_is_not_all_zeros_T_2[4:0]; // @[ExecuteController.scala:312:51]
wire d_row_is_not_all_zeros = _d_row_is_not_all_zeros_T_3 < d_rows; // @[ExecuteController.scala:166:19, :312:{51,68}]
wire a_ready; // @[ExecuteController.scala:329:25]
wire d_ready; // @[ExecuteController.scala:331:25]
wire _GEN_16 = a_fire_counter == 4'h0; // @[ExecuteController.scala:236:27, :334:24]
wire _done_T; // @[ExecuteController.scala:334:24]
assign _done_T = _GEN_16; // @[ExecuteController.scala:334:24]
wire _about_to_fire_all_rows_T_4; // @[ExecuteController.scala:405:99]
assign _about_to_fire_all_rows_T_4 = _GEN_16; // @[ExecuteController.scala:334:24, :405:99]
wire done = _done_T & a_fire_started; // @[ExecuteController.scala:240:31, :334:{24,32}]
wire _GEN_17 = b_fire_counter == 4'h0; // @[ExecuteController.scala:237:27, :334:24]
wire _done_T_1; // @[ExecuteController.scala:334:24]
assign _done_T_1 = _GEN_17; // @[ExecuteController.scala:334:24]
wire _about_to_fire_all_rows_T_10; // @[ExecuteController.scala:406:72]
assign _about_to_fire_all_rows_T_10 = _GEN_17; // @[ExecuteController.scala:334:24, :406:72]
wire done_1 = _done_T_1 & b_fire_started; // @[ExecuteController.scala:242:31, :334:{24,32}]
wire _GEN_18 = d_fire_counter == 4'h0; // @[ExecuteController.scala:238:27, :334:24]
wire _done_T_2; // @[ExecuteController.scala:334:24]
assign _done_T_2 = _GEN_18; // @[ExecuteController.scala:334:24]
wire _about_to_fire_all_rows_T_17; // @[ExecuteController.scala:407:72]
assign _about_to_fire_all_rows_T_17 = _GEN_18; // @[ExecuteController.scala:334:24, :407:72]
wire done_2 = _done_T_2 & d_fire_started; // @[ExecuteController.scala:241:31, :334:{24,32}]
wire _same_banks_is_garbage_T_1 = ~start_inputting_a; // @[ExecuteController.scala:267:35, :272:49, :321:7]
wire _same_banks_is_garbage_T_3 = ~start_inputting_b; // @[ExecuteController.scala:268:35, :273:49, :321:28]
wire _same_banks_T_11 = _same_banks_T_3; // @[ExecuteController.scala:325:{65,89}]
wire _same_banks_T_4 = ~a_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_9 = _same_banks_T_7 == _same_banks_T_8; // @[LocalAddr.scala:33:79]
wire _GEN_19 = _T_17 & a_address_rs1_read_full_acc_row & (&a_address_rs1_data) & a_address_rs1_garbage_bit | _T_29 & d_address_rs1_read_full_acc_row & (&d_address_rs1_data) & d_address_rs1_garbage_bit; // @[LocalAddr.scala:43:{48,62,83,91,96}]
wire _same_banks_is_garbage_T_4; // @[ExecuteController.scala:320:34]
assign _same_banks_is_garbage_T_4 = _GEN_19; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_16; // @[ExecuteController.scala:320:34]
assign _same_banks_is_garbage_T_16 = _GEN_19; // @[ExecuteController.scala:320:34]
wire _same_banks_is_garbage_T_5 = ~start_inputting_a; // @[ExecuteController.scala:267:35, :272:49, :321:7]
wire _same_banks_is_garbage_T_6 = _same_banks_is_garbage_T_4 | _same_banks_is_garbage_T_5; // @[ExecuteController.scala:320:{34,49}, :321:7]
wire _same_banks_is_garbage_T_7 = ~start_inputting_d; // @[ExecuteController.scala:269:35, :274:49, :321:28]
wire same_banks_is_garbage_1 = _same_banks_is_garbage_T_6 | _same_banks_is_garbage_T_7; // @[ExecuteController.scala:320:49, :321:{25,28}]
wire _same_banks_T_12 = ~same_banks_is_garbage_1; // @[ExecuteController.scala:321:25, :325:5]
wire _same_banks_T_14 = _same_banks_T_12; // @[ExecuteController.scala:325:{5,17}]
wire _GEN_20 = a_address_is_acc_addr & d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_15; // @[ExecuteController.scala:325:65]
assign _same_banks_T_15 = _GEN_20; // @[ExecuteController.scala:325:65]
wire _same_banks_T_51; // @[ExecuteController.scala:325:65]
assign _same_banks_T_51 = _GEN_20; // @[ExecuteController.scala:325:65]
wire _same_banks_T_16 = ~a_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_17 = ~d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_18 = _same_banks_T_16 & _same_banks_T_17; // @[ExecuteController.scala:326:{8,29,32}]
wire _same_banks_T_21 = _same_banks_T_19 == _same_banks_T_20; // @[LocalAddr.scala:33:79]
wire _same_banks_T_22 = _same_banks_T_18 & _same_banks_T_21; // @[ExecuteController.scala:326:{29,53,72}]
wire _same_banks_T_23 = _same_banks_T_15 | _same_banks_T_22; // @[ExecuteController.scala:325:{65,89}, :326:53]
wire same_banks_1 = _same_banks_T_14 & _same_banks_T_23; // @[ExecuteController.scala:325:{17,40,89}]
wire _GEN_21 = a_fire_started == b_fire_started; // @[ExecuteController.scala:240:31, :242:31, :345:48]
wire _same_counter_T; // @[ExecuteController.scala:345:48]
assign _same_counter_T = _GEN_21; // @[ExecuteController.scala:345:48]
wire _same_counter_T_4; // @[ExecuteController.scala:345:48]
assign _same_counter_T_4 = _GEN_21; // @[ExecuteController.scala:345:48]
wire _GEN_22 = a_fire_counter == b_fire_counter; // @[ExecuteController.scala:236:27, :237:27, :345:73]
wire _same_counter_T_1; // @[ExecuteController.scala:345:73]
assign _same_counter_T_1 = _GEN_22; // @[ExecuteController.scala:345:73]
wire _same_counter_T_5; // @[ExecuteController.scala:345:73]
assign _same_counter_T_5 = _GEN_22; // @[ExecuteController.scala:345:73]
wire same_counter_0 = _same_counter_T & _same_counter_T_1; // @[ExecuteController.scala:345:{48,62,73}]
wire _GEN_23 = a_fire_started == d_fire_started; // @[ExecuteController.scala:240:31, :241:31, :345:48]
wire _same_counter_T_2; // @[ExecuteController.scala:345:48]
assign _same_counter_T_2 = _GEN_23; // @[ExecuteController.scala:345:48]
wire _same_counter_T_8; // @[ExecuteController.scala:345:48]
assign _same_counter_T_8 = _GEN_23; // @[ExecuteController.scala:345:48]
wire _GEN_24 = a_fire_counter == d_fire_counter; // @[ExecuteController.scala:236:27, :238:27, :345:73]
wire _same_counter_T_3; // @[ExecuteController.scala:345:73]
assign _same_counter_T_3 = _GEN_24; // @[ExecuteController.scala:345:73]
wire _same_counter_T_9; // @[ExecuteController.scala:345:73]
assign _same_counter_T_9 = _GEN_24; // @[ExecuteController.scala:345:73]
wire same_counter_1 = _same_counter_T_2 & _same_counter_T_3; // @[ExecuteController.scala:345:{48,62,73}]
wire [5:0] _GEN_25 = {1'h0, total_rows} - 6'h1; // @[Util.scala:18:28]
wire [5:0] _one_ahead_max_T; // @[Util.scala:18:28]
assign _one_ahead_max_T = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _one_ahead_max_T_1; // @[Util.scala:18:28]
assign _one_ahead_max_T_1 = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _one_ahead_max_T_2; // @[Util.scala:18:28]
assign _one_ahead_max_T_2 = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _one_ahead_max_T_3; // @[Util.scala:18:28]
assign _one_ahead_max_T_3 = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _one_ahead_max_T_4; // @[Util.scala:18:28]
assign _one_ahead_max_T_4 = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _one_ahead_max_T_5; // @[Util.scala:18:28]
assign _one_ahead_max_T_5 = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _a_fire_counter_max_T; // @[Util.scala:18:28]
assign _a_fire_counter_max_T = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _a_addr_offset_T; // @[ExecuteController.scala:370:56]
assign _a_addr_offset_T = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _b_fire_counter_max_T; // @[Util.scala:18:28]
assign _b_fire_counter_max_T = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _d_fire_counter_max_T; // @[Util.scala:18:28]
assign _d_fire_counter_max_T = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _about_to_fire_all_rows_T; // @[ExecuteController.scala:405:64]
assign _about_to_fire_all_rows_T = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _about_to_fire_all_rows_T_6; // @[ExecuteController.scala:406:37]
assign _about_to_fire_all_rows_T_6 = _GEN_25; // @[Util.scala:18:28]
wire [5:0] _about_to_fire_all_rows_T_13; // @[ExecuteController.scala:407:37]
assign _about_to_fire_all_rows_T_13 = _GEN_25; // @[Util.scala:18:28]
wire [4:0] one_ahead_max = _one_ahead_max_T[4:0]; // @[Util.scala:18:28]
wire _one_ahead_T = |one_ahead_max; // @[Util.scala:18:28, :19:14]
wire _GEN_26 = one_ahead_max == 5'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_1; // @[Util.scala:19:28]
assign _one_ahead_T_1 = _GEN_26; // @[Util.scala:19:28]
wire _one_ahead_T_9; // @[Util.scala:29:12]
assign _one_ahead_T_9 = _GEN_26; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_2 = _one_ahead_T | _one_ahead_T_1; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_4 = ~_one_ahead_T_3; // @[Util.scala:19:11]
wire _one_ahead_T_5 = ~_one_ahead_T_2; // @[Util.scala:19:{11,21}]
wire [4:0] _GEN_27 = _GEN_15 + 5'h1; // @[Util.scala:27:15]
wire [4:0] _one_ahead_T_6; // @[Util.scala:27:15]
assign _one_ahead_T_6 = _GEN_27; // @[Util.scala:27:15]
wire [4:0] _one_ahead_T_141; // @[Util.scala:27:15]
assign _one_ahead_T_141 = _GEN_27; // @[Util.scala:27:15]
wire [4:0] _b_fire_counter_T_6; // @[Util.scala:27:15]
assign _b_fire_counter_T_6 = _GEN_27; // @[Util.scala:27:15]
wire [3:0] _one_ahead_T_7 = _one_ahead_T_6[3:0]; // @[Util.scala:27:15]
wire [5:0] _GEN_28 = {1'h0, one_ahead_max}; // @[Util.scala:18:28, :30:17]
wire [5:0] _one_ahead_T_10 = _GEN_28 - 6'h1; // @[Util.scala:30:17]
wire [4:0] _one_ahead_T_11 = _one_ahead_T_10[4:0]; // @[Util.scala:30:17]
wire [5:0] _one_ahead_T_12 = {1'h0, _one_ahead_T_11} + 6'h1; // @[Util.scala:30:{17,21}]
wire [4:0] _one_ahead_T_13 = _one_ahead_T_12[4:0]; // @[Util.scala:30:21]
wire _one_ahead_T_14 = _GEN_15 >= _one_ahead_T_13; // @[Util.scala:30:{10,21}]
wire _one_ahead_T_16 = _one_ahead_T_14; // @[Util.scala:30:{10,27}]
wire [5:0] _GEN_29 = {2'h0, b_fire_counter}; // @[Util.scala:30:54]
wire [5:0] _one_ahead_T_17 = _GEN_28 - _GEN_29; // @[Util.scala:30:{17,54}]
wire [4:0] _one_ahead_T_18 = _one_ahead_T_17[4:0]; // @[Util.scala:30:54]
wire [5:0] _one_ahead_T_19 = 6'h1 - {1'h0, _one_ahead_T_18}; // @[Util.scala:30:{47,54}]
wire [4:0] _one_ahead_T_20 = _one_ahead_T_19[4:0]; // @[Util.scala:30:47]
wire [5:0] _one_ahead_T_21 = {1'h0, _one_ahead_T_20} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _one_ahead_T_22 = _one_ahead_T_21[4:0]; // @[Util.scala:30:59]
wire [4:0] _one_ahead_T_23 = _one_ahead_T_16 ? _one_ahead_T_22 : {1'h0, _one_ahead_T_7}; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_24 = _one_ahead_T_9 ? 5'h0 : _one_ahead_T_23; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_25 = _one_ahead_T_24; // @[Mux.scala:126:16]
wire _one_ahead_T_26 = _GEN_14 == _one_ahead_T_25; // @[Mux.scala:126:16]
wire one_ahead_0 = a_fire_started & _one_ahead_T_26; // @[ExecuteController.scala:240:31, :347:{45,56}]
wire must_wait_for_0 = one_ahead_0; // @[ExecuteController.scala:347:45, :353:26]
wire [4:0] one_ahead_max_1 = _one_ahead_max_T_1[4:0]; // @[Util.scala:18:28]
wire _one_ahead_T_27 = |one_ahead_max_1; // @[Util.scala:18:28, :19:14]
wire _GEN_30 = one_ahead_max_1 == 5'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_28; // @[Util.scala:19:28]
assign _one_ahead_T_28 = _GEN_30; // @[Util.scala:19:28]
wire _one_ahead_T_36; // @[Util.scala:29:12]
assign _one_ahead_T_36 = _GEN_30; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_29 = _one_ahead_T_27 | _one_ahead_T_28; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_31 = ~_one_ahead_T_30; // @[Util.scala:19:11]
wire _one_ahead_T_32 = ~_one_ahead_T_29; // @[Util.scala:19:{11,21}]
wire [4:0] _GEN_31 = {1'h0, d_fire_counter}; // @[Util.scala:27:15]
wire [4:0] _GEN_32 = _GEN_31 + 5'h1; // @[Util.scala:27:15]
wire [4:0] _one_ahead_T_33; // @[Util.scala:27:15]
assign _one_ahead_T_33 = _GEN_32; // @[Util.scala:27:15]
wire [4:0] _one_ahead_T_87; // @[Util.scala:27:15]
assign _one_ahead_T_87 = _GEN_32; // @[Util.scala:27:15]
wire [4:0] _d_fire_counter_T_6; // @[Util.scala:27:15]
assign _d_fire_counter_T_6 = _GEN_32; // @[Util.scala:27:15]
wire [3:0] _one_ahead_T_34 = _one_ahead_T_33[3:0]; // @[Util.scala:27:15]
wire [5:0] _GEN_33 = {1'h0, one_ahead_max_1}; // @[Util.scala:18:28, :30:17]
wire [5:0] _one_ahead_T_37 = _GEN_33 - 6'h1; // @[Util.scala:30:17]
wire [4:0] _one_ahead_T_38 = _one_ahead_T_37[4:0]; // @[Util.scala:30:17]
wire [5:0] _one_ahead_T_39 = {1'h0, _one_ahead_T_38} + 6'h1; // @[Util.scala:30:{17,21}]
wire [4:0] _one_ahead_T_40 = _one_ahead_T_39[4:0]; // @[Util.scala:30:21]
wire _one_ahead_T_41 = _GEN_31 >= _one_ahead_T_40; // @[Util.scala:27:15, :30:{10,21}]
wire _one_ahead_T_43 = _one_ahead_T_41; // @[Util.scala:30:{10,27}]
wire [5:0] _one_ahead_T_44 = _GEN_33 - _GEN_12; // @[Util.scala:30:{17,54}]
wire [4:0] _one_ahead_T_45 = _one_ahead_T_44[4:0]; // @[Util.scala:30:54]
wire [5:0] _one_ahead_T_46 = 6'h1 - {1'h0, _one_ahead_T_45}; // @[Util.scala:30:{47,54}]
wire [4:0] _one_ahead_T_47 = _one_ahead_T_46[4:0]; // @[Util.scala:30:47]
wire [5:0] _one_ahead_T_48 = {1'h0, _one_ahead_T_47} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _one_ahead_T_49 = _one_ahead_T_48[4:0]; // @[Util.scala:30:59]
wire [4:0] _one_ahead_T_50 = _one_ahead_T_43 ? _one_ahead_T_49 : {1'h0, _one_ahead_T_34}; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_51 = _one_ahead_T_36 ? 5'h0 : _one_ahead_T_50; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_52 = _one_ahead_T_51; // @[Mux.scala:126:16]
wire _one_ahead_T_53 = _GEN_14 == _one_ahead_T_52; // @[Mux.scala:126:16]
wire one_ahead_1 = a_fire_started & _one_ahead_T_53; // @[ExecuteController.scala:240:31, :347:{45,56}]
wire must_wait_for_1 = one_ahead_1; // @[ExecuteController.scala:347:45, :353:26]
wire a_valid = ~(must_wait_for_0 | must_wait_for_1); // @[ExecuteController.scala:353:26, :356:{5,29}]
wire _read_a_T_1 = a_valid; // @[ExecuteController.scala:356:5, :424:26]
wire _read_a_T_11 = a_valid; // @[ExecuteController.scala:356:5, :424:26]
wire _read_a_T_21 = a_valid; // @[ExecuteController.scala:356:5, :424:26]
wire _read_a_T_31 = a_valid; // @[ExecuteController.scala:356:5, :424:26]
wire _same_banks_is_garbage_T_9 = ~start_inputting_b; // @[ExecuteController.scala:268:35, :273:49, :321:7]
wire _same_banks_is_garbage_T_11 = ~start_inputting_a; // @[ExecuteController.scala:267:35, :272:49, :321:28]
wire _same_banks_T_35 = _same_banks_T_27; // @[ExecuteController.scala:325:{65,89}]
wire _same_banks_T_29 = ~a_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_33 = _same_banks_T_31 == _same_banks_T_32; // @[LocalAddr.scala:33:79]
wire _same_banks_is_garbage_T_13 = ~start_inputting_b; // @[ExecuteController.scala:268:35, :273:49, :321:7]
wire _same_banks_is_garbage_T_15 = ~start_inputting_d; // @[ExecuteController.scala:269:35, :274:49, :321:28]
wire _same_banks_T_47 = _same_banks_T_39; // @[ExecuteController.scala:325:{65,89}]
wire _same_banks_T_41 = ~d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_45 = _same_banks_T_43 == _same_banks_T_44; // @[LocalAddr.scala:33:79]
wire same_counter_0_1 = _same_counter_T_4 & _same_counter_T_5; // @[ExecuteController.scala:345:{48,62,73}]
wire _GEN_34 = b_fire_started == d_fire_started; // @[ExecuteController.scala:241:31, :242:31, :345:48]
wire _same_counter_T_6; // @[ExecuteController.scala:345:48]
assign _same_counter_T_6 = _GEN_34; // @[ExecuteController.scala:345:48]
wire _same_counter_T_10; // @[ExecuteController.scala:345:48]
assign _same_counter_T_10 = _GEN_34; // @[ExecuteController.scala:345:48]
wire _GEN_35 = b_fire_counter == d_fire_counter; // @[ExecuteController.scala:237:27, :238:27, :345:73]
wire _same_counter_T_7; // @[ExecuteController.scala:345:73]
assign _same_counter_T_7 = _GEN_35; // @[ExecuteController.scala:345:73]
wire _same_counter_T_11; // @[ExecuteController.scala:345:73]
assign _same_counter_T_11 = _GEN_35; // @[ExecuteController.scala:345:73]
wire same_counter_1_1 = _same_counter_T_6 & _same_counter_T_7; // @[ExecuteController.scala:345:{48,62,73}]
wire [4:0] one_ahead_max_2 = _one_ahead_max_T_2[4:0]; // @[Util.scala:18:28]
wire _one_ahead_T_54 = |one_ahead_max_2; // @[Util.scala:18:28, :19:14]
wire _GEN_36 = one_ahead_max_2 == 5'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_55; // @[Util.scala:19:28]
assign _one_ahead_T_55 = _GEN_36; // @[Util.scala:19:28]
wire _one_ahead_T_63; // @[Util.scala:29:12]
assign _one_ahead_T_63 = _GEN_36; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_56 = _one_ahead_T_54 | _one_ahead_T_55; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_58 = ~_one_ahead_T_57; // @[Util.scala:19:11]
wire _one_ahead_T_59 = ~_one_ahead_T_56; // @[Util.scala:19:{11,21}]
wire [4:0] _GEN_37 = _GEN_14 + 5'h1; // @[Util.scala:27:15]
wire [4:0] _one_ahead_T_60; // @[Util.scala:27:15]
assign _one_ahead_T_60 = _GEN_37; // @[Util.scala:27:15]
wire [4:0] _one_ahead_T_114; // @[Util.scala:27:15]
assign _one_ahead_T_114 = _GEN_37; // @[Util.scala:27:15]
wire [4:0] _a_fire_counter_T_6; // @[Util.scala:27:15]
assign _a_fire_counter_T_6 = _GEN_37; // @[Util.scala:27:15]
wire [3:0] _one_ahead_T_61 = _one_ahead_T_60[3:0]; // @[Util.scala:27:15]
wire [5:0] _GEN_38 = {1'h0, one_ahead_max_2}; // @[Util.scala:18:28, :30:17]
wire [5:0] _one_ahead_T_64 = _GEN_38 - 6'h1; // @[Util.scala:30:17]
wire [4:0] _one_ahead_T_65 = _one_ahead_T_64[4:0]; // @[Util.scala:30:17]
wire [5:0] _one_ahead_T_66 = {1'h0, _one_ahead_T_65} + 6'h1; // @[Util.scala:30:{17,21}]
wire [4:0] _one_ahead_T_67 = _one_ahead_T_66[4:0]; // @[Util.scala:30:21]
wire _one_ahead_T_68 = _GEN_14 >= _one_ahead_T_67; // @[Util.scala:30:{10,21}]
wire _one_ahead_T_70 = _one_ahead_T_68; // @[Util.scala:30:{10,27}]
wire [5:0] _GEN_39 = {2'h0, a_fire_counter}; // @[Util.scala:30:54]
wire [5:0] _one_ahead_T_71 = _GEN_38 - _GEN_39; // @[Util.scala:30:{17,54}]
wire [4:0] _one_ahead_T_72 = _one_ahead_T_71[4:0]; // @[Util.scala:30:54]
wire [5:0] _one_ahead_T_73 = 6'h1 - {1'h0, _one_ahead_T_72}; // @[Util.scala:30:{47,54}]
wire [4:0] _one_ahead_T_74 = _one_ahead_T_73[4:0]; // @[Util.scala:30:47]
wire [5:0] _one_ahead_T_75 = {1'h0, _one_ahead_T_74} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _one_ahead_T_76 = _one_ahead_T_75[4:0]; // @[Util.scala:30:59]
wire [4:0] _one_ahead_T_77 = _one_ahead_T_70 ? _one_ahead_T_76 : {1'h0, _one_ahead_T_61}; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_78 = _one_ahead_T_63 ? 5'h0 : _one_ahead_T_77; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_79 = _one_ahead_T_78; // @[Mux.scala:126:16]
wire _one_ahead_T_80 = _GEN_15 == _one_ahead_T_79; // @[Mux.scala:126:16]
wire one_ahead_0_1 = b_fire_started & _one_ahead_T_80; // @[ExecuteController.scala:242:31, :347:{45,56}]
wire must_wait_for_0_1 = one_ahead_0_1; // @[ExecuteController.scala:347:45, :353:26]
wire [4:0] one_ahead_max_3 = _one_ahead_max_T_3[4:0]; // @[Util.scala:18:28]
wire _one_ahead_T_81 = |one_ahead_max_3; // @[Util.scala:18:28, :19:14]
wire _GEN_40 = one_ahead_max_3 == 5'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_82; // @[Util.scala:19:28]
assign _one_ahead_T_82 = _GEN_40; // @[Util.scala:19:28]
wire _one_ahead_T_90; // @[Util.scala:29:12]
assign _one_ahead_T_90 = _GEN_40; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_83 = _one_ahead_T_81 | _one_ahead_T_82; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_85 = ~_one_ahead_T_84; // @[Util.scala:19:11]
wire _one_ahead_T_86 = ~_one_ahead_T_83; // @[Util.scala:19:{11,21}]
wire [3:0] _one_ahead_T_88 = _one_ahead_T_87[3:0]; // @[Util.scala:27:15]
wire [5:0] _GEN_41 = {1'h0, one_ahead_max_3}; // @[Util.scala:18:28, :30:17]
wire [5:0] _one_ahead_T_91 = _GEN_41 - 6'h1; // @[Util.scala:30:17]
wire [4:0] _one_ahead_T_92 = _one_ahead_T_91[4:0]; // @[Util.scala:30:17]
wire [5:0] _one_ahead_T_93 = {1'h0, _one_ahead_T_92} + 6'h1; // @[Util.scala:30:{17,21}]
wire [4:0] _one_ahead_T_94 = _one_ahead_T_93[4:0]; // @[Util.scala:30:21]
wire _one_ahead_T_95 = _GEN_31 >= _one_ahead_T_94; // @[Util.scala:27:15, :30:{10,21}]
wire _one_ahead_T_97 = _one_ahead_T_95; // @[Util.scala:30:{10,27}]
wire [5:0] _one_ahead_T_98 = _GEN_41 - _GEN_12; // @[Util.scala:30:{17,54}]
wire [4:0] _one_ahead_T_99 = _one_ahead_T_98[4:0]; // @[Util.scala:30:54]
wire [5:0] _one_ahead_T_100 = 6'h1 - {1'h0, _one_ahead_T_99}; // @[Util.scala:30:{47,54}]
wire [4:0] _one_ahead_T_101 = _one_ahead_T_100[4:0]; // @[Util.scala:30:47]
wire [5:0] _one_ahead_T_102 = {1'h0, _one_ahead_T_101} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _one_ahead_T_103 = _one_ahead_T_102[4:0]; // @[Util.scala:30:59]
wire [4:0] _one_ahead_T_104 = _one_ahead_T_97 ? _one_ahead_T_103 : {1'h0, _one_ahead_T_88}; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_105 = _one_ahead_T_90 ? 5'h0 : _one_ahead_T_104; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_106 = _one_ahead_T_105; // @[Mux.scala:126:16]
wire _one_ahead_T_107 = _GEN_15 == _one_ahead_T_106; // @[Mux.scala:126:16]
wire one_ahead_1_1 = b_fire_started & _one_ahead_T_107; // @[ExecuteController.scala:242:31, :347:{45,56}]
wire must_wait_for_1_1 = one_ahead_1_1; // @[ExecuteController.scala:347:45, :353:26]
wire b_valid = ~(must_wait_for_0_1 | must_wait_for_1_1); // @[ExecuteController.scala:353:26, :356:{5,29}]
wire b_fire = b_valid; // @[ExecuteController.scala:356:5, :360:24]
wire _read_b_T_1 = b_valid; // @[ExecuteController.scala:356:5, :425:26]
wire _read_b_T_8 = b_valid; // @[ExecuteController.scala:356:5, :425:26]
wire _read_b_T_15 = b_valid; // @[ExecuteController.scala:356:5, :425:26]
wire _read_b_T_22 = b_valid; // @[ExecuteController.scala:356:5, :425:26]
wire _same_banks_is_garbage_T_17 = ~start_inputting_d; // @[ExecuteController.scala:269:35, :274:49, :321:7]
wire _same_banks_is_garbage_T_18 = _same_banks_is_garbage_T_16 | _same_banks_is_garbage_T_17; // @[ExecuteController.scala:320:{34,49}, :321:7]
wire _same_banks_is_garbage_T_19 = ~start_inputting_a; // @[ExecuteController.scala:267:35, :272:49, :321:28]
wire same_banks_is_garbage_4 = _same_banks_is_garbage_T_18 | _same_banks_is_garbage_T_19; // @[ExecuteController.scala:320:49, :321:{25,28}]
wire _same_banks_T_48 = ~same_banks_is_garbage_4; // @[ExecuteController.scala:321:25, :325:5]
wire _same_banks_T_50 = _same_banks_T_48; // @[ExecuteController.scala:325:{5,17}]
wire _same_banks_T_52 = ~d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_53 = ~a_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_54 = _same_banks_T_52 & _same_banks_T_53; // @[ExecuteController.scala:326:{8,29,32}]
wire _same_banks_T_57 = _same_banks_T_55 == _same_banks_T_56; // @[LocalAddr.scala:33:79]
wire _same_banks_T_58 = _same_banks_T_54 & _same_banks_T_57; // @[ExecuteController.scala:326:{29,53,72}]
wire _same_banks_T_59 = _same_banks_T_51 | _same_banks_T_58; // @[ExecuteController.scala:325:{65,89}, :326:53]
wire same_banks_0_2 = _same_banks_T_50 & _same_banks_T_59; // @[ExecuteController.scala:325:{17,40,89}]
wire _must_wait_for_T_8 = same_banks_0_2; // @[ExecuteController.scala:325:40, :353:13]
wire _same_banks_is_garbage_T_21 = ~start_inputting_d; // @[ExecuteController.scala:269:35, :274:49, :321:7]
wire _same_banks_is_garbage_T_23 = ~start_inputting_b; // @[ExecuteController.scala:268:35, :273:49, :321:28]
wire _same_banks_T_71 = _same_banks_T_63; // @[ExecuteController.scala:325:{65,89}]
wire _same_banks_T_64 = ~d_address_is_acc_addr; // @[LocalAddr.scala:50:26]
wire _same_banks_T_69 = _same_banks_T_67 == _same_banks_T_68; // @[LocalAddr.scala:33:79]
wire same_counter_0_2 = _same_counter_T_8 & _same_counter_T_9; // @[ExecuteController.scala:345:{48,62,73}]
wire same_counter_1_2 = _same_counter_T_10 & _same_counter_T_11; // @[ExecuteController.scala:345:{48,62,73}]
wire [4:0] one_ahead_max_4 = _one_ahead_max_T_4[4:0]; // @[Util.scala:18:28]
wire _one_ahead_T_108 = |one_ahead_max_4; // @[Util.scala:18:28, :19:14]
wire _GEN_42 = one_ahead_max_4 == 5'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_109; // @[Util.scala:19:28]
assign _one_ahead_T_109 = _GEN_42; // @[Util.scala:19:28]
wire _one_ahead_T_117; // @[Util.scala:29:12]
assign _one_ahead_T_117 = _GEN_42; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_110 = _one_ahead_T_108 | _one_ahead_T_109; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_112 = ~_one_ahead_T_111; // @[Util.scala:19:11]
wire _one_ahead_T_113 = ~_one_ahead_T_110; // @[Util.scala:19:{11,21}]
wire [3:0] _one_ahead_T_115 = _one_ahead_T_114[3:0]; // @[Util.scala:27:15]
wire [5:0] _GEN_43 = {1'h0, one_ahead_max_4}; // @[Util.scala:18:28, :30:17]
wire [5:0] _one_ahead_T_118 = _GEN_43 - 6'h1; // @[Util.scala:30:17]
wire [4:0] _one_ahead_T_119 = _one_ahead_T_118[4:0]; // @[Util.scala:30:17]
wire [5:0] _one_ahead_T_120 = {1'h0, _one_ahead_T_119} + 6'h1; // @[Util.scala:30:{17,21}]
wire [4:0] _one_ahead_T_121 = _one_ahead_T_120[4:0]; // @[Util.scala:30:21]
wire _one_ahead_T_122 = _GEN_14 >= _one_ahead_T_121; // @[Util.scala:30:{10,21}]
wire _one_ahead_T_124 = _one_ahead_T_122; // @[Util.scala:30:{10,27}]
wire [5:0] _one_ahead_T_125 = _GEN_43 - _GEN_39; // @[Util.scala:30:{17,54}]
wire [4:0] _one_ahead_T_126 = _one_ahead_T_125[4:0]; // @[Util.scala:30:54]
wire [5:0] _one_ahead_T_127 = 6'h1 - {1'h0, _one_ahead_T_126}; // @[Util.scala:30:{47,54}]
wire [4:0] _one_ahead_T_128 = _one_ahead_T_127[4:0]; // @[Util.scala:30:47]
wire [5:0] _one_ahead_T_129 = {1'h0, _one_ahead_T_128} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _one_ahead_T_130 = _one_ahead_T_129[4:0]; // @[Util.scala:30:59]
wire [4:0] _one_ahead_T_131 = _one_ahead_T_124 ? _one_ahead_T_130 : {1'h0, _one_ahead_T_115}; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_132 = _one_ahead_T_117 ? 5'h0 : _one_ahead_T_131; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_133 = _one_ahead_T_132; // @[Mux.scala:126:16]
wire _one_ahead_T_134 = _GEN_31 == _one_ahead_T_133; // @[Mux.scala:126:16]
wire one_ahead_0_2 = d_fire_started & _one_ahead_T_134; // @[ExecuteController.scala:241:31, :347:{45,56}]
wire [4:0] one_ahead_max_5 = _one_ahead_max_T_5[4:0]; // @[Util.scala:18:28]
wire _one_ahead_T_135 = |one_ahead_max_5; // @[Util.scala:18:28, :19:14]
wire _GEN_44 = one_ahead_max_5 == 5'h0; // @[Util.scala:18:28, :19:28]
wire _one_ahead_T_136; // @[Util.scala:19:28]
assign _one_ahead_T_136 = _GEN_44; // @[Util.scala:19:28]
wire _one_ahead_T_144; // @[Util.scala:29:12]
assign _one_ahead_T_144 = _GEN_44; // @[Util.scala:19:28, :29:12]
wire _one_ahead_T_137 = _one_ahead_T_135 | _one_ahead_T_136; // @[Util.scala:19:{14,21,28}]
wire _one_ahead_T_139 = ~_one_ahead_T_138; // @[Util.scala:19:11]
wire _one_ahead_T_140 = ~_one_ahead_T_137; // @[Util.scala:19:{11,21}]
wire [3:0] _one_ahead_T_142 = _one_ahead_T_141[3:0]; // @[Util.scala:27:15]
wire [5:0] _GEN_45 = {1'h0, one_ahead_max_5}; // @[Util.scala:18:28, :30:17]
wire [5:0] _one_ahead_T_145 = _GEN_45 - 6'h1; // @[Util.scala:30:17]
wire [4:0] _one_ahead_T_146 = _one_ahead_T_145[4:0]; // @[Util.scala:30:17]
wire [5:0] _one_ahead_T_147 = {1'h0, _one_ahead_T_146} + 6'h1; // @[Util.scala:30:{17,21}]
wire [4:0] _one_ahead_T_148 = _one_ahead_T_147[4:0]; // @[Util.scala:30:21]
wire _one_ahead_T_149 = _GEN_15 >= _one_ahead_T_148; // @[Util.scala:30:{10,21}]
wire _one_ahead_T_151 = _one_ahead_T_149; // @[Util.scala:30:{10,27}]
wire [5:0] _one_ahead_T_152 = _GEN_45 - _GEN_29; // @[Util.scala:30:{17,54}]
wire [4:0] _one_ahead_T_153 = _one_ahead_T_152[4:0]; // @[Util.scala:30:54]
wire [5:0] _one_ahead_T_154 = 6'h1 - {1'h0, _one_ahead_T_153}; // @[Util.scala:30:{47,54}]
wire [4:0] _one_ahead_T_155 = _one_ahead_T_154[4:0]; // @[Util.scala:30:47]
wire [5:0] _one_ahead_T_156 = {1'h0, _one_ahead_T_155} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _one_ahead_T_157 = _one_ahead_T_156[4:0]; // @[Util.scala:30:59]
wire [4:0] _one_ahead_T_158 = _one_ahead_T_151 ? _one_ahead_T_157 : {1'h0, _one_ahead_T_142}; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_159 = _one_ahead_T_144 ? 5'h0 : _one_ahead_T_158; // @[Mux.scala:126:16]
wire [4:0] _one_ahead_T_160 = _one_ahead_T_159; // @[Mux.scala:126:16]
wire _one_ahead_T_161 = _GEN_31 == _one_ahead_T_160; // @[Mux.scala:126:16]
wire one_ahead_1_2 = d_fire_started & _one_ahead_T_161; // @[ExecuteController.scala:241:31, :347:{45,56}]
wire must_wait_for_1_2 = one_ahead_1_2; // @[ExecuteController.scala:347:45, :353:26]
wire _must_wait_for_T_9 = _must_wait_for_T_8 & same_counter_0_2; // @[ExecuteController.scala:345:62, :353:{13,19}]
wire must_wait_for_0_2 = _must_wait_for_T_9 | one_ahead_0_2; // @[ExecuteController.scala:347:45, :353:{19,26}]
wire d_valid = ~(must_wait_for_0_2 | must_wait_for_1_2); // @[ExecuteController.scala:353:26, :356:{5,29}]
wire _read_d_T_1 = d_valid; // @[ExecuteController.scala:356:5, :426:26]
wire _read_d_T_8 = d_valid; // @[ExecuteController.scala:356:5, :426:26]
wire _read_d_T_15 = d_valid; // @[ExecuteController.scala:356:5, :426:26]
wire _read_d_T_22 = d_valid; // @[ExecuteController.scala:356:5, :426:26]
wire a_fire = a_valid & a_ready; // @[ExecuteController.scala:329:25, :356:5, :359:24]
wire d_fire = d_valid & d_ready; // @[ExecuteController.scala:331:25, :356:5, :361:24]
wire _firing_T = start_inputting_a | start_inputting_b; // @[ExecuteController.scala:267:35, :268:35, :363:34]
wire firing = _firing_T | start_inputting_d; // @[ExecuteController.scala:269:35, :363:{34,55}]
wire _T_40 = firing & a_fire & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :359:24, :363:55, :368:{22,32}]
wire [4:0] a_fire_counter_max = _a_fire_counter_max_T[4:0]; // @[Util.scala:18:28]
wire _a_fire_counter_T = |a_fire_counter_max; // @[Util.scala:18:28, :19:14]
wire _GEN_46 = a_fire_counter_max == 5'h0; // @[Util.scala:18:28, :19:28]
wire _a_fire_counter_T_1; // @[Util.scala:19:28]
assign _a_fire_counter_T_1 = _GEN_46; // @[Util.scala:19:28]
wire _a_fire_counter_T_9; // @[Util.scala:29:12]
assign _a_fire_counter_T_9 = _GEN_46; // @[Util.scala:19:28, :29:12]
wire _a_fire_counter_T_2 = _a_fire_counter_T | _a_fire_counter_T_1; // @[Util.scala:19:{14,21,28}]
wire _a_fire_counter_T_4 = ~_a_fire_counter_T_3; // @[Util.scala:19:11]
wire _a_fire_counter_T_5 = ~_a_fire_counter_T_2; // @[Util.scala:19:{11,21}]
wire [3:0] _a_fire_counter_T_7 = _a_fire_counter_T_6[3:0]; // @[Util.scala:27:15]
wire [5:0] _GEN_47 = {1'h0, a_fire_counter_max}; // @[Util.scala:18:28, :30:17]
wire [5:0] _a_fire_counter_T_10 = _GEN_47 - 6'h1; // @[Util.scala:30:17]
wire [4:0] _a_fire_counter_T_11 = _a_fire_counter_T_10[4:0]; // @[Util.scala:30:17]
wire [5:0] _a_fire_counter_T_12 = {1'h0, _a_fire_counter_T_11} + 6'h1; // @[Util.scala:30:{17,21}]
wire [4:0] _a_fire_counter_T_13 = _a_fire_counter_T_12[4:0]; // @[Util.scala:30:21]
wire _a_fire_counter_T_14 = _GEN_14 >= _a_fire_counter_T_13; // @[Util.scala:30:{10,21}]
wire _a_fire_counter_T_16 = _a_fire_counter_T_14; // @[Util.scala:30:{10,27}]
wire [5:0] _a_fire_counter_T_17 = _GEN_47 - _GEN_39; // @[Util.scala:30:{17,54}]
wire [4:0] _a_fire_counter_T_18 = _a_fire_counter_T_17[4:0]; // @[Util.scala:30:54]
wire [5:0] _a_fire_counter_T_19 = 6'h1 - {1'h0, _a_fire_counter_T_18}; // @[Util.scala:30:{47,54}]
wire [4:0] _a_fire_counter_T_20 = _a_fire_counter_T_19[4:0]; // @[Util.scala:30:47]
wire [5:0] _a_fire_counter_T_21 = {1'h0, _a_fire_counter_T_20} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _a_fire_counter_T_22 = _a_fire_counter_T_21[4:0]; // @[Util.scala:30:59]
wire [4:0] _a_fire_counter_T_23 = _a_fire_counter_T_16 ? _a_fire_counter_T_22 : {1'h0, _a_fire_counter_T_7}; // @[Mux.scala:126:16]
wire [4:0] _a_fire_counter_T_24 = _a_fire_counter_T_9 ? 5'h0 : _a_fire_counter_T_23; // @[Mux.scala:126:16]
wire [4:0] _a_fire_counter_T_25 = _a_fire_counter_T_24; // @[Mux.scala:126:16]
wire [4:0] _a_addr_offset_T_1 = _a_addr_offset_T[4:0]; // @[ExecuteController.scala:370:56]
wire _a_addr_offset_T_2 = _GEN_14 == _a_addr_offset_T_1; // @[ExecuteController.scala:310:47, :370:{41,56}]
wire [20:0] _a_addr_offset_T_3 = _GEN_11 + {5'h0, a_addr_stride}; // @[LocalAddr.scala:51:25]
wire [19:0] _a_addr_offset_T_4 = _a_addr_offset_T_3[19:0]; // @[ExecuteController.scala:370:82]
wire [19:0] _a_addr_offset_T_5 = _a_addr_offset_T_2 ? 20'h0 : _a_addr_offset_T_4; // @[ExecuteController.scala:370:{25,41,82}]
wire _T_43 = firing & b_fire & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :360:24, :363:55, :376:{22,32}]
wire [4:0] b_fire_counter_max = _b_fire_counter_max_T[4:0]; // @[Util.scala:18:28]
wire _b_fire_counter_T = |b_fire_counter_max; // @[Util.scala:18:28, :19:14]
wire _GEN_48 = b_fire_counter_max == 5'h0; // @[Util.scala:18:28, :19:28]
wire _b_fire_counter_T_1; // @[Util.scala:19:28]
assign _b_fire_counter_T_1 = _GEN_48; // @[Util.scala:19:28]
wire _b_fire_counter_T_9; // @[Util.scala:29:12]
assign _b_fire_counter_T_9 = _GEN_48; // @[Util.scala:19:28, :29:12]
wire _b_fire_counter_T_2 = _b_fire_counter_T | _b_fire_counter_T_1; // @[Util.scala:19:{14,21,28}]
wire _b_fire_counter_T_4 = ~_b_fire_counter_T_3; // @[Util.scala:19:11]
wire _b_fire_counter_T_5 = ~_b_fire_counter_T_2; // @[Util.scala:19:{11,21}]
wire [3:0] _b_fire_counter_T_7 = _b_fire_counter_T_6[3:0]; // @[Util.scala:27:15]
wire [5:0] _GEN_49 = {1'h0, b_fire_counter_max}; // @[Util.scala:18:28, :30:17]
wire [5:0] _b_fire_counter_T_10 = _GEN_49 - 6'h1; // @[Util.scala:30:17]
wire [4:0] _b_fire_counter_T_11 = _b_fire_counter_T_10[4:0]; // @[Util.scala:30:17]
wire [5:0] _b_fire_counter_T_12 = {1'h0, _b_fire_counter_T_11} + 6'h1; // @[Util.scala:30:{17,21}]
wire [4:0] _b_fire_counter_T_13 = _b_fire_counter_T_12[4:0]; // @[Util.scala:30:21]
wire _b_fire_counter_T_14 = _GEN_15 >= _b_fire_counter_T_13; // @[Util.scala:30:{10,21}]
wire _b_fire_counter_T_16 = _b_fire_counter_T_14; // @[Util.scala:30:{10,27}]
wire [5:0] _b_fire_counter_T_17 = _GEN_49 - _GEN_29; // @[Util.scala:30:{17,54}]
wire [4:0] _b_fire_counter_T_18 = _b_fire_counter_T_17[4:0]; // @[Util.scala:30:54]
wire [5:0] _b_fire_counter_T_19 = 6'h1 - {1'h0, _b_fire_counter_T_18}; // @[Util.scala:30:{47,54}]
wire [4:0] _b_fire_counter_T_20 = _b_fire_counter_T_19[4:0]; // @[Util.scala:30:47]
wire [5:0] _b_fire_counter_T_21 = {1'h0, _b_fire_counter_T_20} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _b_fire_counter_T_22 = _b_fire_counter_T_21[4:0]; // @[Util.scala:30:59]
wire [4:0] _b_fire_counter_T_23 = _b_fire_counter_T_16 ? _b_fire_counter_T_22 : {1'h0, _b_fire_counter_T_7}; // @[Mux.scala:126:16]
wire [4:0] _b_fire_counter_T_24 = _b_fire_counter_T_9 ? 5'h0 : _b_fire_counter_T_23; // @[Mux.scala:126:16]
wire [4:0] _b_fire_counter_T_25 = _b_fire_counter_T_24; // @[Mux.scala:126:16]
wire _T_46 = firing & d_fire & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :361:24, :363:55, :383:{22,32}]
wire [4:0] d_fire_counter_max = _d_fire_counter_max_T[4:0]; // @[Util.scala:18:28]
wire _d_fire_counter_T = |d_fire_counter_max; // @[Util.scala:18:28, :19:14]
wire _GEN_50 = d_fire_counter_max == 5'h0; // @[Util.scala:18:28, :19:28]
wire _d_fire_counter_T_1; // @[Util.scala:19:28]
assign _d_fire_counter_T_1 = _GEN_50; // @[Util.scala:19:28]
wire _d_fire_counter_T_9; // @[Util.scala:29:12]
assign _d_fire_counter_T_9 = _GEN_50; // @[Util.scala:19:28, :29:12]
wire _d_fire_counter_T_2 = _d_fire_counter_T | _d_fire_counter_T_1; // @[Util.scala:19:{14,21,28}]
wire _d_fire_counter_T_4 = ~_d_fire_counter_T_3; // @[Util.scala:19:11]
wire _d_fire_counter_T_5 = ~_d_fire_counter_T_2; // @[Util.scala:19:{11,21}]
wire [3:0] _d_fire_counter_T_7 = _d_fire_counter_T_6[3:0]; // @[Util.scala:27:15]
wire [5:0] _GEN_51 = {1'h0, d_fire_counter_max}; // @[Util.scala:18:28, :30:17]
wire [5:0] _d_fire_counter_T_10 = _GEN_51 - 6'h1; // @[Util.scala:30:17]
wire [4:0] _d_fire_counter_T_11 = _d_fire_counter_T_10[4:0]; // @[Util.scala:30:17]
wire [5:0] _d_fire_counter_T_12 = {1'h0, _d_fire_counter_T_11} + 6'h1; // @[Util.scala:30:{17,21}]
wire [4:0] _d_fire_counter_T_13 = _d_fire_counter_T_12[4:0]; // @[Util.scala:30:21]
wire _d_fire_counter_T_14 = _GEN_31 >= _d_fire_counter_T_13; // @[Util.scala:27:15, :30:{10,21}]
wire _d_fire_counter_T_16 = _d_fire_counter_T_14; // @[Util.scala:30:{10,27}]
wire [5:0] _d_fire_counter_T_17 = _GEN_51 - _GEN_12; // @[Util.scala:30:{17,54}]
wire [4:0] _d_fire_counter_T_18 = _d_fire_counter_T_17[4:0]; // @[Util.scala:30:54]
wire [5:0] _d_fire_counter_T_19 = 6'h1 - {1'h0, _d_fire_counter_T_18}; // @[Util.scala:30:{47,54}]
wire [4:0] _d_fire_counter_T_20 = _d_fire_counter_T_19[4:0]; // @[Util.scala:30:47]
wire [5:0] _d_fire_counter_T_21 = {1'h0, _d_fire_counter_T_20} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _d_fire_counter_T_22 = _d_fire_counter_T_21[4:0]; // @[Util.scala:30:59]
wire [4:0] _d_fire_counter_T_23 = _d_fire_counter_T_16 ? _d_fire_counter_T_22 : {1'h0, _d_fire_counter_T_7}; // @[Mux.scala:126:16]
wire [4:0] _d_fire_counter_T_24 = _d_fire_counter_T_9 ? 5'h0 : _d_fire_counter_T_23; // @[Mux.scala:126:16]
wire [4:0] _d_fire_counter_T_25 = _d_fire_counter_T_24; // @[Mux.scala:126:16]
wire _mul_pre_counter_sub_T = |mul_pre_counter_sub; // @[ExecuteController.scala:305:36, :398:52]
wire [3:0] _mul_pre_counter_sub_T_1 = {1'h0, mul_pre_counter_sub} - 4'h1; // @[ExecuteController.scala:305:36, :398:80]
wire [2:0] _mul_pre_counter_sub_T_2 = _mul_pre_counter_sub_T_1[2:0]; // @[ExecuteController.scala:398:80]
wire [2:0] _mul_pre_counter_sub_T_3 = _mul_pre_counter_sub_T ? _mul_pre_counter_sub_T_2 : 3'h0; // @[ExecuteController.scala:398:{31,52,80}]
wire [4:0] _about_to_fire_all_rows_T_1 = _about_to_fire_all_rows_T[4:0]; // @[ExecuteController.scala:405:64]
wire _about_to_fire_all_rows_T_2 = _GEN_14 == _about_to_fire_all_rows_T_1; // @[ExecuteController.scala:310:47, :405:{49,64}]
wire _about_to_fire_all_rows_T_3 = _about_to_fire_all_rows_T_2 & a_fire; // @[ExecuteController.scala:359:24, :405:{49,70}]
wire _about_to_fire_all_rows_T_5 = _about_to_fire_all_rows_T_3 | _about_to_fire_all_rows_T_4; // @[ExecuteController.scala:405:{70,81,99}]
wire [4:0] _about_to_fire_all_rows_T_7 = _about_to_fire_all_rows_T_6[4:0]; // @[ExecuteController.scala:406:37]
wire _about_to_fire_all_rows_T_8 = _GEN_15 == _about_to_fire_all_rows_T_7; // @[ExecuteController.scala:311:47, :406:{22,37}]
wire _about_to_fire_all_rows_T_9 = _about_to_fire_all_rows_T_8 & b_fire; // @[ExecuteController.scala:360:24, :406:{22,43}]
wire _about_to_fire_all_rows_T_11 = _about_to_fire_all_rows_T_9 | _about_to_fire_all_rows_T_10; // @[ExecuteController.scala:406:{43,54,72}]
wire _about_to_fire_all_rows_T_12 = _about_to_fire_all_rows_T_5 & _about_to_fire_all_rows_T_11; // @[ExecuteController.scala:405:{81,108}, :406:54]
wire [4:0] _about_to_fire_all_rows_T_14 = _about_to_fire_all_rows_T_13[4:0]; // @[ExecuteController.scala:407:37]
wire _about_to_fire_all_rows_T_15 = _GEN_31 == _about_to_fire_all_rows_T_14; // @[Util.scala:27:15]
wire _about_to_fire_all_rows_T_16 = _about_to_fire_all_rows_T_15 & d_fire; // @[ExecuteController.scala:361:24, :407:{22,43}]
wire _about_to_fire_all_rows_T_18 = _about_to_fire_all_rows_T_16 | _about_to_fire_all_rows_T_17; // @[ExecuteController.scala:407:{43,54,72}]
wire _about_to_fire_all_rows_T_19 = _about_to_fire_all_rows_T_12 & _about_to_fire_all_rows_T_18; // @[ExecuteController.scala:405:108, :406:81, :407:54]
wire _about_to_fire_all_rows_T_20 = a_fire_started | b_fire_started; // @[ExecuteController.scala:240:31, :242:31, :408:21]
wire _about_to_fire_all_rows_T_21 = _about_to_fire_all_rows_T_20 | d_fire_started; // @[ExecuteController.scala:241:31, :408:{21,39}]
wire _about_to_fire_all_rows_T_22 = _about_to_fire_all_rows_T_19 & _about_to_fire_all_rows_T_21; // @[ExecuteController.scala:406:81, :407:81, :408:39]
wire about_to_fire_all_rows = _about_to_fire_all_rows_T_22 & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :407:81, :408:58]
wire [4:0] _d_fire_counter_mulpre_T = _GEN_31 - {2'h0, mul_pre_counter_sub}; // @[Util.scala:27:15]
wire [3:0] _d_fire_counter_mulpre_T_1 = _d_fire_counter_mulpre_T[3:0]; // @[ExecuteController.scala:419:45]
wire _read_a_T_2 = dataAbank == 2'h0; // @[LocalAddr.scala:33:79]
wire _read_a_T_3 = _read_a_T_1 & _read_a_T_2; // @[ExecuteController.scala:424:{26,46,59}]
wire _read_a_T_4 = _read_a_T_3 & start_inputting_a; // @[ExecuteController.scala:267:35, :424:{46,67}]
wire _read_a_T_5 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_T_6 = _read_a_T_4 & _read_a_T_5; // @[ExecuteController.scala:424:{67,88,91}]
wire _read_a_T_7 = _read_a_T_6 & a_row_is_not_all_zeros; // @[ExecuteController.scala:310:47, :424:{88,109}]
wire read_a = _read_a_T_7; // @[ExecuteController.scala:424:{109,135}]
wire _io_srams_read_0_req_valid_T = read_a; // @[ExecuteController.scala:424:135, :435:45]
wire _read_b_T_2 = dataBbank == 2'h0; // @[LocalAddr.scala:33:79]
wire _read_b_T_3 = _read_b_T_1 & _read_b_T_2; // @[ExecuteController.scala:425:{26,46,59}]
wire _read_b_T_4 = _read_b_T_3 & start_inputting_b; // @[ExecuteController.scala:268:35, :425:{46,67}]
wire _read_d_T_2 = dataDbank == 2'h0; // @[LocalAddr.scala:33:79]
wire _read_d_T_3 = _read_d_T_1 & _read_d_T_2; // @[ExecuteController.scala:426:{26,46,59}]
wire _read_d_T_4 = _read_d_T_3 & start_inputting_d; // @[ExecuteController.scala:269:35, :426:{46,67}]
wire _read_d_T_5 = ~preload_zeros; // @[LocalAddr.scala:43:96]
wire _read_d_T_6 = _read_d_T_4 & _read_d_T_5; // @[ExecuteController.scala:426:{67,88,91}]
wire read_d = _read_d_T_6 & d_row_is_not_all_zeros; // @[ExecuteController.scala:312:68, :426:{88,106}]
wire _io_srams_read_0_req_valid_T_1 = _io_srams_read_0_req_valid_T | read_d; // @[ExecuteController.scala:426:106, :435:{45,55}]
assign _io_srams_read_0_req_valid_T_2 = _io_srams_read_0_req_valid_T_1 & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :435:{55,66}]
assign io_srams_read_0_req_valid_0 = _io_srams_read_0_req_valid_T_2; // @[ExecuteController.scala:12:7, :435:66]
wire [11:0] _io_srams_read_0_req_bits_addr_T = a_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T = a_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T = a_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T = a_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [12:0] _GEN_52 = {9'h0, a_fire_counter}; // @[ExecuteController.scala:236:27, :437:72]
wire [12:0] _io_srams_read_0_req_bits_addr_T_1 = {1'h0, _io_srams_read_0_req_bits_addr_T} + _GEN_52; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_0_req_bits_addr_T_2 = _io_srams_read_0_req_bits_addr_T_1[11:0]; // @[ExecuteController.scala:437:72]
wire [12:0] _GEN_53 = {9'h0, b_fire_counter} + 13'hFFF; // @[ExecuteController.scala:237:27, :438:47]
wire [12:0] _io_srams_read_0_req_bits_addr_T_4; // @[ExecuteController.scala:438:47]
assign _io_srams_read_0_req_bits_addr_T_4 = _GEN_53; // @[ExecuteController.scala:438:47]
wire [12:0] _io_srams_read_1_req_bits_addr_T_4; // @[ExecuteController.scala:438:47]
assign _io_srams_read_1_req_bits_addr_T_4 = _GEN_53; // @[ExecuteController.scala:438:47]
wire [12:0] _io_srams_read_2_req_bits_addr_T_4; // @[ExecuteController.scala:438:47]
assign _io_srams_read_2_req_bits_addr_T_4 = _GEN_53; // @[ExecuteController.scala:438:47]
wire [12:0] _io_srams_read_3_req_bits_addr_T_4; // @[ExecuteController.scala:438:47]
assign _io_srams_read_3_req_bits_addr_T_4 = _GEN_53; // @[ExecuteController.scala:438:47]
wire [11:0] _io_srams_read_0_req_bits_addr_T_5 = _io_srams_read_0_req_bits_addr_T_4[11:0]; // @[ExecuteController.scala:438:47]
wire [11:0] _io_srams_read_0_req_bits_addr_T_6 = d_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T_6 = d_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T_6 = d_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T_6 = d_address_rs1_data[11:0]; // @[LocalAddr.scala:34:36]
wire [12:0] _io_srams_read_0_req_bits_addr_T_7 = {1'h0, _io_srams_read_0_req_bits_addr_T_6} + 13'h10; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_0_req_bits_addr_T_8 = _io_srams_read_0_req_bits_addr_T_7[11:0]; // @[ExecuteController.scala:439:45]
wire [12:0] _io_srams_read_0_req_bits_addr_T_9 = {1'h0, _io_srams_read_0_req_bits_addr_T_8} - 13'h1; // @[ExecuteController.scala:439:{45,60}]
wire [11:0] _io_srams_read_0_req_bits_addr_T_10 = _io_srams_read_0_req_bits_addr_T_9[11:0]; // @[ExecuteController.scala:439:60]
wire [12:0] _GEN_54 = {9'h0, d_fire_counter_mulpre}; // @[ExecuteController.scala:417:39, :439:66]
wire [12:0] _io_srams_read_0_req_bits_addr_T_11 = {1'h0, _io_srams_read_0_req_bits_addr_T_10} - _GEN_54; // @[ExecuteController.scala:439:{60,66}]
wire [11:0] _io_srams_read_0_req_bits_addr_T_12 = _io_srams_read_0_req_bits_addr_T_11[11:0]; // @[ExecuteController.scala:439:66]
wire [11:0] _io_srams_read_0_req_bits_addr_T_13 = read_d ? _io_srams_read_0_req_bits_addr_T_12 : _io_srams_read_0_req_bits_addr_T_2; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_0_req_bits_addr_T_14 = _io_srams_read_0_req_bits_addr_T_13; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_0_req_bits_addr_T_15 = a_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_1_req_bits_addr_T_15 = a_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_2_req_bits_addr_T_15 = a_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_3_req_bits_addr_T_15 = a_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_0_req_bits_addr_T_16 = b_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_1_req_bits_addr_T_16 = b_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_2_req_bits_addr_T_16 = b_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_3_req_bits_addr_T_16 = b_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_0_req_bits_addr_T_17 = d_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_1_req_bits_addr_T_17 = d_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_2_req_bits_addr_T_17 = d_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_3_req_bits_addr_T_17 = d_address_data[11:0]; // @[LocalAddr.scala:34:36, :50:26]
wire [11:0] _io_srams_read_0_req_bits_addr_T_18 = read_d ? _io_srams_read_0_req_bits_addr_T_17 : _io_srams_read_0_req_bits_addr_T_15; // @[Mux.scala:126:16]
assign _io_srams_read_0_req_bits_addr_T_19 = _io_srams_read_0_req_bits_addr_T_18; // @[Mux.scala:126:16]
assign io_srams_read_0_req_bits_addr_0 = _io_srams_read_0_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _read_a_T_12 = dataAbank == 2'h1; // @[LocalAddr.scala:33:79]
wire _read_a_T_13 = _read_a_T_11 & _read_a_T_12; // @[ExecuteController.scala:424:{26,46,59}]
wire _read_a_T_14 = _read_a_T_13 & start_inputting_a; // @[ExecuteController.scala:267:35, :424:{46,67}]
wire _read_a_T_15 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_T_16 = _read_a_T_14 & _read_a_T_15; // @[ExecuteController.scala:424:{67,88,91}]
wire _read_a_T_17 = _read_a_T_16 & a_row_is_not_all_zeros; // @[ExecuteController.scala:310:47, :424:{88,109}]
wire read_a_1 = _read_a_T_17; // @[ExecuteController.scala:424:{109,135}]
wire _io_srams_read_1_req_valid_T = read_a_1; // @[ExecuteController.scala:424:135, :435:45]
wire _read_b_T_9 = dataBbank == 2'h1; // @[LocalAddr.scala:33:79]
wire _read_b_T_10 = _read_b_T_8 & _read_b_T_9; // @[ExecuteController.scala:425:{26,46,59}]
wire _read_b_T_11 = _read_b_T_10 & start_inputting_b; // @[ExecuteController.scala:268:35, :425:{46,67}]
wire _read_d_T_9 = dataDbank == 2'h1; // @[LocalAddr.scala:33:79]
wire _read_d_T_10 = _read_d_T_8 & _read_d_T_9; // @[ExecuteController.scala:426:{26,46,59}]
wire _read_d_T_11 = _read_d_T_10 & start_inputting_d; // @[ExecuteController.scala:269:35, :426:{46,67}]
wire _read_d_T_12 = ~preload_zeros; // @[LocalAddr.scala:43:96]
wire _read_d_T_13 = _read_d_T_11 & _read_d_T_12; // @[ExecuteController.scala:426:{67,88,91}]
wire read_d_1 = _read_d_T_13 & d_row_is_not_all_zeros; // @[ExecuteController.scala:312:68, :426:{88,106}]
wire _io_srams_read_1_req_valid_T_1 = _io_srams_read_1_req_valid_T | read_d_1; // @[ExecuteController.scala:426:106, :435:{45,55}]
assign _io_srams_read_1_req_valid_T_2 = _io_srams_read_1_req_valid_T_1 & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :435:{55,66}]
assign io_srams_read_1_req_valid_0 = _io_srams_read_1_req_valid_T_2; // @[ExecuteController.scala:12:7, :435:66]
wire [12:0] _io_srams_read_1_req_bits_addr_T_1 = {1'h0, _io_srams_read_1_req_bits_addr_T} + _GEN_52; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T_2 = _io_srams_read_1_req_bits_addr_T_1[11:0]; // @[ExecuteController.scala:437:72]
wire [11:0] _io_srams_read_1_req_bits_addr_T_5 = _io_srams_read_1_req_bits_addr_T_4[11:0]; // @[ExecuteController.scala:438:47]
wire [12:0] _io_srams_read_1_req_bits_addr_T_7 = {1'h0, _io_srams_read_1_req_bits_addr_T_6} + 13'h10; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_1_req_bits_addr_T_8 = _io_srams_read_1_req_bits_addr_T_7[11:0]; // @[ExecuteController.scala:439:45]
wire [12:0] _io_srams_read_1_req_bits_addr_T_9 = {1'h0, _io_srams_read_1_req_bits_addr_T_8} - 13'h1; // @[ExecuteController.scala:439:{45,60}]
wire [11:0] _io_srams_read_1_req_bits_addr_T_10 = _io_srams_read_1_req_bits_addr_T_9[11:0]; // @[ExecuteController.scala:439:60]
wire [12:0] _io_srams_read_1_req_bits_addr_T_11 = {1'h0, _io_srams_read_1_req_bits_addr_T_10} - _GEN_54; // @[ExecuteController.scala:439:{60,66}]
wire [11:0] _io_srams_read_1_req_bits_addr_T_12 = _io_srams_read_1_req_bits_addr_T_11[11:0]; // @[ExecuteController.scala:439:66]
wire [11:0] _io_srams_read_1_req_bits_addr_T_13 = read_d_1 ? _io_srams_read_1_req_bits_addr_T_12 : _io_srams_read_1_req_bits_addr_T_2; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_1_req_bits_addr_T_14 = _io_srams_read_1_req_bits_addr_T_13; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_1_req_bits_addr_T_18 = read_d_1 ? _io_srams_read_1_req_bits_addr_T_17 : _io_srams_read_1_req_bits_addr_T_15; // @[Mux.scala:126:16]
assign _io_srams_read_1_req_bits_addr_T_19 = _io_srams_read_1_req_bits_addr_T_18; // @[Mux.scala:126:16]
assign io_srams_read_1_req_bits_addr_0 = _io_srams_read_1_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _read_a_T_22 = dataAbank == 2'h2; // @[LocalAddr.scala:33:79]
wire _read_a_T_23 = _read_a_T_21 & _read_a_T_22; // @[ExecuteController.scala:424:{26,46,59}]
wire _read_a_T_24 = _read_a_T_23 & start_inputting_a; // @[ExecuteController.scala:267:35, :424:{46,67}]
wire _read_a_T_25 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_T_26 = _read_a_T_24 & _read_a_T_25; // @[ExecuteController.scala:424:{67,88,91}]
wire _read_a_T_27 = _read_a_T_26 & a_row_is_not_all_zeros; // @[ExecuteController.scala:310:47, :424:{88,109}]
wire read_a_2 = _read_a_T_27; // @[ExecuteController.scala:424:{109,135}]
wire _io_srams_read_2_req_valid_T = read_a_2; // @[ExecuteController.scala:424:135, :435:45]
wire _read_b_T_16 = dataBbank == 2'h2; // @[LocalAddr.scala:33:79]
wire _read_b_T_17 = _read_b_T_15 & _read_b_T_16; // @[ExecuteController.scala:425:{26,46,59}]
wire _read_b_T_18 = _read_b_T_17 & start_inputting_b; // @[ExecuteController.scala:268:35, :425:{46,67}]
wire _read_d_T_16 = dataDbank == 2'h2; // @[LocalAddr.scala:33:79]
wire _read_d_T_17 = _read_d_T_15 & _read_d_T_16; // @[ExecuteController.scala:426:{26,46,59}]
wire _read_d_T_18 = _read_d_T_17 & start_inputting_d; // @[ExecuteController.scala:269:35, :426:{46,67}]
wire _read_d_T_19 = ~preload_zeros; // @[LocalAddr.scala:43:96]
wire _read_d_T_20 = _read_d_T_18 & _read_d_T_19; // @[ExecuteController.scala:426:{67,88,91}]
wire read_d_2 = _read_d_T_20 & d_row_is_not_all_zeros; // @[ExecuteController.scala:312:68, :426:{88,106}]
wire _io_srams_read_2_req_valid_T_1 = _io_srams_read_2_req_valid_T | read_d_2; // @[ExecuteController.scala:426:106, :435:{45,55}]
assign _io_srams_read_2_req_valid_T_2 = _io_srams_read_2_req_valid_T_1 & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :435:{55,66}]
assign io_srams_read_2_req_valid_0 = _io_srams_read_2_req_valid_T_2; // @[ExecuteController.scala:12:7, :435:66]
wire [12:0] _io_srams_read_2_req_bits_addr_T_1 = {1'h0, _io_srams_read_2_req_bits_addr_T} + _GEN_52; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T_2 = _io_srams_read_2_req_bits_addr_T_1[11:0]; // @[ExecuteController.scala:437:72]
wire [11:0] _io_srams_read_2_req_bits_addr_T_5 = _io_srams_read_2_req_bits_addr_T_4[11:0]; // @[ExecuteController.scala:438:47]
wire [12:0] _io_srams_read_2_req_bits_addr_T_7 = {1'h0, _io_srams_read_2_req_bits_addr_T_6} + 13'h10; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_2_req_bits_addr_T_8 = _io_srams_read_2_req_bits_addr_T_7[11:0]; // @[ExecuteController.scala:439:45]
wire [12:0] _io_srams_read_2_req_bits_addr_T_9 = {1'h0, _io_srams_read_2_req_bits_addr_T_8} - 13'h1; // @[ExecuteController.scala:439:{45,60}]
wire [11:0] _io_srams_read_2_req_bits_addr_T_10 = _io_srams_read_2_req_bits_addr_T_9[11:0]; // @[ExecuteController.scala:439:60]
wire [12:0] _io_srams_read_2_req_bits_addr_T_11 = {1'h0, _io_srams_read_2_req_bits_addr_T_10} - _GEN_54; // @[ExecuteController.scala:439:{60,66}]
wire [11:0] _io_srams_read_2_req_bits_addr_T_12 = _io_srams_read_2_req_bits_addr_T_11[11:0]; // @[ExecuteController.scala:439:66]
wire [11:0] _io_srams_read_2_req_bits_addr_T_13 = read_d_2 ? _io_srams_read_2_req_bits_addr_T_12 : _io_srams_read_2_req_bits_addr_T_2; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_2_req_bits_addr_T_14 = _io_srams_read_2_req_bits_addr_T_13; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_2_req_bits_addr_T_18 = read_d_2 ? _io_srams_read_2_req_bits_addr_T_17 : _io_srams_read_2_req_bits_addr_T_15; // @[Mux.scala:126:16]
assign _io_srams_read_2_req_bits_addr_T_19 = _io_srams_read_2_req_bits_addr_T_18; // @[Mux.scala:126:16]
assign io_srams_read_2_req_bits_addr_0 = _io_srams_read_2_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _read_a_T_32 = &dataAbank; // @[LocalAddr.scala:33:79]
wire _read_a_T_33 = _read_a_T_31 & _read_a_T_32; // @[ExecuteController.scala:424:{26,46,59}]
wire _read_a_T_34 = _read_a_T_33 & start_inputting_a; // @[ExecuteController.scala:267:35, :424:{46,67}]
wire _read_a_T_35 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_T_36 = _read_a_T_34 & _read_a_T_35; // @[ExecuteController.scala:424:{67,88,91}]
wire _read_a_T_37 = _read_a_T_36 & a_row_is_not_all_zeros; // @[ExecuteController.scala:310:47, :424:{88,109}]
wire read_a_3 = _read_a_T_37; // @[ExecuteController.scala:424:{109,135}]
wire _io_srams_read_3_req_valid_T = read_a_3; // @[ExecuteController.scala:424:135, :435:45]
wire _read_b_T_23 = &dataBbank; // @[LocalAddr.scala:33:79]
wire _read_b_T_24 = _read_b_T_22 & _read_b_T_23; // @[ExecuteController.scala:425:{26,46,59}]
wire _read_b_T_25 = _read_b_T_24 & start_inputting_b; // @[ExecuteController.scala:268:35, :425:{46,67}]
wire _read_d_T_23 = &dataDbank; // @[LocalAddr.scala:33:79]
wire _read_d_T_24 = _read_d_T_22 & _read_d_T_23; // @[ExecuteController.scala:426:{26,46,59}]
wire _read_d_T_25 = _read_d_T_24 & start_inputting_d; // @[ExecuteController.scala:269:35, :426:{46,67}]
wire _read_d_T_26 = ~preload_zeros; // @[LocalAddr.scala:43:96]
wire _read_d_T_27 = _read_d_T_25 & _read_d_T_26; // @[ExecuteController.scala:426:{67,88,91}]
wire read_d_3 = _read_d_T_27 & d_row_is_not_all_zeros; // @[ExecuteController.scala:312:68, :426:{88,106}]
wire _io_srams_read_3_req_valid_T_1 = _io_srams_read_3_req_valid_T | read_d_3; // @[ExecuteController.scala:426:106, :435:{45,55}]
assign _io_srams_read_3_req_valid_T_2 = _io_srams_read_3_req_valid_T_1 & _mesh_cntl_signals_q_io_enq_ready; // @[ExecuteController.scala:178:35, :435:{55,66}]
assign io_srams_read_3_req_valid_0 = _io_srams_read_3_req_valid_T_2; // @[ExecuteController.scala:12:7, :435:66]
wire [12:0] _io_srams_read_3_req_bits_addr_T_1 = {1'h0, _io_srams_read_3_req_bits_addr_T} + _GEN_52; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T_2 = _io_srams_read_3_req_bits_addr_T_1[11:0]; // @[ExecuteController.scala:437:72]
wire [11:0] _io_srams_read_3_req_bits_addr_T_5 = _io_srams_read_3_req_bits_addr_T_4[11:0]; // @[ExecuteController.scala:438:47]
wire [12:0] _io_srams_read_3_req_bits_addr_T_7 = {1'h0, _io_srams_read_3_req_bits_addr_T_6} + 13'h10; // @[LocalAddr.scala:34:36]
wire [11:0] _io_srams_read_3_req_bits_addr_T_8 = _io_srams_read_3_req_bits_addr_T_7[11:0]; // @[ExecuteController.scala:439:45]
wire [12:0] _io_srams_read_3_req_bits_addr_T_9 = {1'h0, _io_srams_read_3_req_bits_addr_T_8} - 13'h1; // @[ExecuteController.scala:439:{45,60}]
wire [11:0] _io_srams_read_3_req_bits_addr_T_10 = _io_srams_read_3_req_bits_addr_T_9[11:0]; // @[ExecuteController.scala:439:60]
wire [12:0] _io_srams_read_3_req_bits_addr_T_11 = {1'h0, _io_srams_read_3_req_bits_addr_T_10} - _GEN_54; // @[ExecuteController.scala:439:{60,66}]
wire [11:0] _io_srams_read_3_req_bits_addr_T_12 = _io_srams_read_3_req_bits_addr_T_11[11:0]; // @[ExecuteController.scala:439:66]
wire [11:0] _io_srams_read_3_req_bits_addr_T_13 = read_d_3 ? _io_srams_read_3_req_bits_addr_T_12 : _io_srams_read_3_req_bits_addr_T_2; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_3_req_bits_addr_T_14 = _io_srams_read_3_req_bits_addr_T_13; // @[Mux.scala:126:16]
wire [11:0] _io_srams_read_3_req_bits_addr_T_18 = read_d_3 ? _io_srams_read_3_req_bits_addr_T_17 : _io_srams_read_3_req_bits_addr_T_15; // @[Mux.scala:126:16]
assign _io_srams_read_3_req_bits_addr_T_19 = _io_srams_read_3_req_bits_addr_T_18; // @[Mux.scala:126:16]
assign io_srams_read_3_req_bits_addr_0 = _io_srams_read_3_req_bits_addr_T_19; // @[Mux.scala:126:16]
wire _read_a_from_acc_T_1 = ~dataABankAcc; // @[LocalAddr.scala:35:82]
wire _read_a_from_acc_T_4 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_b_from_acc_T_1 = ~dataBBankAcc; // @[LocalAddr.scala:35:82]
wire _read_d_from_acc_T_1 = ~dataDBankAcc; // @[LocalAddr.scala:35:82]
wire _read_d_from_acc_T_4 = ~preload_zeros; // @[LocalAddr.scala:43:96]
wire _read_a_from_acc_T_13 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_d_from_acc_T_10 = ~preload_zeros; // @[LocalAddr.scala:43:96]
assign d_ready = ~(read_d_3 & ~io_srams_read_3_req_ready_0 | read_d_2 & ~io_srams_read_2_req_ready_0 | read_d_1 & ~io_srams_read_1_req_ready_0) & ~(read_d & ~io_srams_read_0_req_ready_0); // @[ExecuteController.scala:12:7, :331:25, :426:106, :429:{16,19,48}, :430:11, :463:45, :464:11]
wire _read_a_T_40 = a_valid & start_inputting_a; // @[ExecuteController.scala:267:35, :356:5, :506:26]
wire _read_a_T_41 = ~multiply_garbage; // @[LocalAddr.scala:43:96]
wire _read_a_T_42 = _read_a_T_40 & _read_a_T_41; // @[ExecuteController.scala:506:{26,47,50}]
wire _read_a_T_43 = _read_a_T_42; // @[ExecuteController.scala:506:{47,68}]
assign a_ready = ~(read_a_3 & ~io_srams_read_3_req_ready_0 | read_a_2 & ~io_srams_read_2_req_ready_0 | read_a_1 & ~io_srams_read_1_req_ready_0) & ~(read_a & ~io_srams_read_0_req_ready_0); // @[ExecuteController.scala:12:7, :329:25, :424:135, :429:{16,19,48}, :430:11, :463:45, :464:11, :508:43, :509:15]
wire _T_100 = control_state == 2'h0; // @[ExecuteController.scala:74:30, :532:26]
wire _T_105 = DoConfig & ~matmul_in_progress & ~(pending_completed_rob_ids_0_valid | pending_completed_rob_ids_1_valid); // @[ExecuteController.scala:83:28, :175:38, :230:82, :541:{23,26,46,49,98}]
wire [31:0] _config_ex_rs1_T_9; // @[ExecuteController.scala:542:47]
wire [15:0] _config_ex_rs1_T_8; // @[ExecuteController.scala:542:47]
wire [5:0] _config_ex_rs1_T_7; // @[ExecuteController.scala:542:47]
wire _config_ex_rs1_T_6; // @[ExecuteController.scala:542:47]
wire _config_ex_rs1_T_5; // @[ExecuteController.scala:542:47]
wire _config_ex_rs1_T_4; // @[ExecuteController.scala:542:47]
wire [1:0] _config_ex_rs1_T_3; // @[ExecuteController.scala:542:47]
wire [1:0] _config_ex_rs1_T_2; // @[ExecuteController.scala:542:47]
wire _config_ex_rs1_T_1; // @[ExecuteController.scala:542:47]
wire [1:0] _config_ex_rs1_T; // @[ExecuteController.scala:542:47]
wire [31:0] config_ex_rs1_acc_scale; // @[ExecuteController.scala:542:47]
wire [15:0] config_ex_rs1_a_stride; // @[ExecuteController.scala:542:47]
wire [5:0] config_ex_rs1__spacer1; // @[ExecuteController.scala:542:47]
wire config_ex_rs1_b_transpose; // @[ExecuteController.scala:542:47]
wire config_ex_rs1_a_transpose; // @[ExecuteController.scala:542:47]
wire config_ex_rs1_set_only_strides; // @[ExecuteController.scala:542:47]
wire [1:0] config_ex_rs1__spacer0; // @[ExecuteController.scala:542:47]
wire [1:0] config_ex_rs1_activation; // @[ExecuteController.scala:542:47]
wire config_ex_rs1_dataflow; // @[ExecuteController.scala:542:47]
wire [1:0] config_ex_rs1_cmd_type; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T = _config_ex_rs1_WIRE[1:0]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_cmd_type = _config_ex_rs1_T; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_1 = _config_ex_rs1_WIRE[2]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_dataflow = _config_ex_rs1_T_1; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_2 = _config_ex_rs1_WIRE[4:3]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_activation = _config_ex_rs1_T_2; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_3 = _config_ex_rs1_WIRE[6:5]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1__spacer0 = _config_ex_rs1_T_3; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_4 = _config_ex_rs1_WIRE[7]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_set_only_strides = _config_ex_rs1_T_4; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_5 = _config_ex_rs1_WIRE[8]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_a_transpose = _config_ex_rs1_T_5; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_6 = _config_ex_rs1_WIRE[9]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_b_transpose = _config_ex_rs1_T_6; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_7 = _config_ex_rs1_WIRE[15:10]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1__spacer1 = _config_ex_rs1_T_7; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_8 = _config_ex_rs1_WIRE[31:16]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_a_stride = _config_ex_rs1_T_8; // @[ExecuteController.scala:542:47]
assign _config_ex_rs1_T_9 = _config_ex_rs1_WIRE[63:32]; // @[ExecuteController.scala:542:47]
assign config_ex_rs1_acc_scale = _config_ex_rs1_T_9; // @[ExecuteController.scala:542:47]
wire [15:0] _config_ex_rs2_T_2; // @[ExecuteController.scala:543:47]
wire [15:0] _config_ex_rs2_T_1; // @[ExecuteController.scala:543:47]
wire [31:0] _config_ex_rs2_T; // @[ExecuteController.scala:543:47]
wire [15:0] config_ex_rs2_c_stride; // @[ExecuteController.scala:543:47]
wire [15:0] config_ex_rs2_relu6_shift; // @[ExecuteController.scala:543:47]
wire [31:0] config_ex_rs2_in_shift; // @[ExecuteController.scala:543:47]
assign _config_ex_rs2_T = _config_ex_rs2_WIRE[31:0]; // @[ExecuteController.scala:543:47]
assign config_ex_rs2_in_shift = _config_ex_rs2_T; // @[ExecuteController.scala:543:47]
assign _config_ex_rs2_T_1 = _config_ex_rs2_WIRE[47:32]; // @[ExecuteController.scala:543:47]
assign config_ex_rs2_relu6_shift = _config_ex_rs2_T_1; // @[ExecuteController.scala:543:47]
assign _config_ex_rs2_T_2 = _config_ex_rs2_WIRE[63:48]; // @[ExecuteController.scala:543:47]
assign config_ex_rs2_c_stride = _config_ex_rs2_T_2; // @[ExecuteController.scala:543:47]
wire [1:0] config_cmd_type = rs1s_0[1:0]; // @[ExecuteController.scala:80:21, :545:40]
wire [31:0] _acc_scale_T = rs1s_0[63:32]; // @[ExecuteController.scala:80:21, :555:35]
wire [31:0] _acc_scale_WIRE_1 = _acc_scale_T; // @[ExecuteController.scala:555:{35,58}]
wire [31:0] _acc_scale_T_1; // @[ExecuteController.scala:555:58]
assign _acc_scale_T_1 = _acc_scale_WIRE_1; // @[ExecuteController.scala:555:58]
wire [31:0] _acc_scale_WIRE_bits = _acc_scale_T_1; // @[ExecuteController.scala:555:58]
wire [7:0] _ocol_T = _cmd_q_io_deq_bits_0_cmd_rs2[63:56]; // @[MultiHeadedQueue.scala:53:19]
wire _GEN_55 = _cmd_q_io_deq_valid_0 & _T_105; // @[MultiHeadedQueue.scala:53:19]
wire _GEN_56 = _T_100 & _GEN_55; // @[ExecuteController.scala:97:21, :532:26, :540:7, :541:105, :547:48]
wire [7:0] _kdim2_T = _cmd_q_io_deq_bits_0_cmd_rs2[55:48]; // @[MultiHeadedQueue.scala:53:19]
wire [3:0] _krow_T = _cmd_q_io_deq_bits_0_cmd_rs2[47:44]; // @[MultiHeadedQueue.scala:53:19]
wire [8:0] _channel_T = _cmd_q_io_deq_bits_0_cmd_rs2[31:23]; // @[MultiHeadedQueue.scala:53:19]
wire [2:0] _weight_stride_T = _cmd_q_io_deq_bits_0_cmd_rs2[22:20]; // @[MultiHeadedQueue.scala:53:19]
wire _weight_double_bank_T = _cmd_q_io_deq_bits_0_cmd_rs1[58]; // @[MultiHeadedQueue.scala:53:19]
wire _weight_triple_bank_T = _cmd_q_io_deq_bits_0_cmd_rs1[59]; // @[MultiHeadedQueue.scala:53:19]
wire [3:0] _row_left_T = _cmd_q_io_deq_bits_0_cmd_rs1[57:54]; // @[MultiHeadedQueue.scala:53:19]
wire [11:0] _row_turn_T = _cmd_q_io_deq_bits_0_cmd_rs1[53:42]; // @[MultiHeadedQueue.scala:53:19]
wire _GEN_57 = _GEN_56 & _cmd_q_io_deq_bits_0_rob_id_valid; // @[MultiHeadedQueue.scala:53:19]
wire _T_111 = DoPreloads_0 & _cmd_q_io_deq_valid_1; // @[MultiHeadedQueue.scala:53:19]
wire _GEN_58 = _T_100 & _cmd_q_io_deq_valid_0; // @[MultiHeadedQueue.scala:53:19]
assign performing_single_preload = _GEN_58 & ~_T_105 & _T_111 | _performing_single_preload_T_1; // @[ExecuteController.scala:281:{43,67}, :532:26, :535:30, :540:7, :541:{23,46,105}, :585:{33,103}]
wire _T_118 = DoComputes_0 & _cmd_q_io_deq_valid_1 & DoPreloads_1 & (~third_instruction_needed | _cmd_q_io_deq_valid_2); // @[MultiHeadedQueue.scala:53:19]
wire _GEN_59 = _T_105 | _T_111; // @[ExecuteController.scala:536:23, :541:{23,46,105}, :585:{33,103}, :601:9]
assign performing_mul_pre = _GEN_58 & ~_GEN_59 & _T_118 | _performing_mul_pre_T_1; // @[ExecuteController.scala:281:43, :283:{36,53}, :532:26, :536:23, :540:7, :541:105, :585:103, :600:{33,49,66}, :601:9]
wire _GEN_60 = _T_105 | _T_111 | _T_118; // @[ExecuteController.scala:537:26, :541:{23,46,105}, :585:{33,103}, :600:{33,49,66}, :601:9, :613:34]
assign performing_single_mul = _GEN_58 & ~_GEN_60 & DoComputes_0 | _performing_single_mul_T_1; // @[ExecuteController.scala:84:63, :281:43, :282:{39,59}, :532:26, :537:26, :540:7, :541:105, :585:103, :601:9, :613:34]
wire _start_inputting_a_T = ~a_should_be_fed_into_transposer; // @[ExecuteController.scala:123:44, :289:5, :617:32]
wire _GEN_61 = c_address_rs2_is_acc_addr & c_address_rs2_accumulate; // @[LocalAddr.scala:43:48]
wire _pending_completed_rob_ids_0_valid_T; // @[LocalAddr.scala:43:48]
assign _pending_completed_rob_ids_0_valid_T = _GEN_61; // @[LocalAddr.scala:43:48]
wire _pending_completed_rob_ids_1_valid_T; // @[LocalAddr.scala:43:48]
assign _pending_completed_rob_ids_1_valid_T = _GEN_61; // @[LocalAddr.scala:43:48]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_1; // @[LocalAddr.scala:43:48]
assign _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_1 = _GEN_61; // @[LocalAddr.scala:43:48]
wire _pending_completed_rob_ids_0_valid_T_1 = _pending_completed_rob_ids_0_valid_T & c_address_rs2_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _pending_completed_rob_ids_0_valid_T_2 = &c_address_rs2_data; // @[LocalAddr.scala:43:91]
wire _pending_completed_rob_ids_0_valid_T_3 = _pending_completed_rob_ids_0_valid_T_1 & _pending_completed_rob_ids_0_valid_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _pending_completed_rob_ids_0_valid_T_5 = _pending_completed_rob_ids_0_valid_T_3 & _pending_completed_rob_ids_0_valid_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _pending_completed_rob_ids_0_valid_T_6 = _cmd_q_io_deq_bits_0_rob_id_valid & _pending_completed_rob_ids_0_valid_T_5; // @[MultiHeadedQueue.scala:53:19]
wire _in_prop_flush_qual1_T_6; // @[ExecuteController.scala:647:47]
wire _in_prop_flush_qual1_T_5; // @[ExecuteController.scala:647:47]
wire _in_prop_flush_qual1_T_4; // @[ExecuteController.scala:647:47]
wire [2:0] _in_prop_flush_qual1_WIRE_2; // @[ExecuteController.scala:647:47]
wire [10:0] _in_prop_flush_qual1_T_2; // @[ExecuteController.scala:647:47]
wire _in_prop_flush_qual1_T_1; // @[ExecuteController.scala:647:47]
wire [13:0] _in_prop_flush_qual1_T; // @[ExecuteController.scala:647:47]
wire _in_prop_flush_T_4 = in_prop_flush_qual1_garbage_bit; // @[LocalAddr.scala:44:48]
wire in_prop_flush_qual1_is_acc_addr; // @[ExecuteController.scala:647:47]
wire in_prop_flush_qual1_accumulate; // @[ExecuteController.scala:647:47]
wire in_prop_flush_qual1_read_full_acc_row; // @[ExecuteController.scala:647:47]
wire [2:0] in_prop_flush_qual1_norm_cmd; // @[ExecuteController.scala:647:47]
wire [10:0] in_prop_flush_qual1_garbage; // @[ExecuteController.scala:647:47]
wire [13:0] in_prop_flush_qual1_data; // @[ExecuteController.scala:647:47]
wire [31:0] _in_prop_flush_qual1_WIRE = rs2s_0[31:0]; // @[ExecuteController.scala:81:21, :647:47]
assign _in_prop_flush_qual1_T = _in_prop_flush_qual1_WIRE[13:0]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_data = _in_prop_flush_qual1_T; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_T_1 = _in_prop_flush_qual1_WIRE[14]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_garbage_bit = _in_prop_flush_qual1_T_1; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_T_2 = _in_prop_flush_qual1_WIRE[25:15]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_garbage = _in_prop_flush_qual1_T_2; // @[ExecuteController.scala:647:47]
wire [2:0] _in_prop_flush_qual1_T_3 = _in_prop_flush_qual1_WIRE[28:26]; // @[ExecuteController.scala:647:47]
wire [2:0] _in_prop_flush_qual1_WIRE_1 = _in_prop_flush_qual1_T_3; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_WIRE_2 = _in_prop_flush_qual1_WIRE_1; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_norm_cmd = _in_prop_flush_qual1_WIRE_2; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_T_4 = _in_prop_flush_qual1_WIRE[29]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_read_full_acc_row = _in_prop_flush_qual1_T_4; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_T_5 = _in_prop_flush_qual1_WIRE[30]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_accumulate = _in_prop_flush_qual1_T_5; // @[ExecuteController.scala:647:47]
assign _in_prop_flush_qual1_T_6 = _in_prop_flush_qual1_WIRE[31]; // @[ExecuteController.scala:647:47]
assign in_prop_flush_qual1_is_acc_addr = _in_prop_flush_qual1_T_6; // @[ExecuteController.scala:647:47]
wire _in_prop_flush_T = in_prop_flush_qual1_is_acc_addr & in_prop_flush_qual1_accumulate; // @[LocalAddr.scala:43:48]
wire _in_prop_flush_T_1 = _in_prop_flush_T & in_prop_flush_qual1_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _in_prop_flush_T_2 = &in_prop_flush_qual1_data; // @[LocalAddr.scala:43:91]
wire _in_prop_flush_T_3 = _in_prop_flush_T_1 & _in_prop_flush_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _in_prop_flush_T_5 = _in_prop_flush_T_3 & _in_prop_flush_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _in_prop_flush_T_6 = ~_in_prop_flush_T_5; // @[LocalAddr.scala:43:96]
assign start_inputting_d = _T_100 ? _cmd_q_io_deq_valid_0 & ~_T_105 & (_T_111 | _T_118) : _T_615 & (perform_single_preload | perform_mul_pre); // @[MultiHeadedQueue.scala:53:19]
wire _pending_completed_rob_ids_1_valid_T_1 = _pending_completed_rob_ids_1_valid_T & c_address_rs2_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _pending_completed_rob_ids_1_valid_T_2 = &c_address_rs2_data; // @[LocalAddr.scala:43:91]
wire _pending_completed_rob_ids_1_valid_T_3 = _pending_completed_rob_ids_1_valid_T_1 & _pending_completed_rob_ids_1_valid_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _pending_completed_rob_ids_1_valid_T_5 = _pending_completed_rob_ids_1_valid_T_3 & _pending_completed_rob_ids_1_valid_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _pending_completed_rob_ids_1_valid_T_6 = _cmd_q_io_deq_bits_1_rob_id_valid & _pending_completed_rob_ids_1_valid_T_5; // @[MultiHeadedQueue.scala:53:19]
wire _in_prop_flush_qual2_T_6; // @[ExecuteController.scala:666:47]
wire _in_prop_flush_qual2_T_5; // @[ExecuteController.scala:666:47]
wire _in_prop_flush_qual2_T_4; // @[ExecuteController.scala:666:47]
wire [2:0] _in_prop_flush_qual2_WIRE_2; // @[ExecuteController.scala:666:47]
wire [10:0] _in_prop_flush_qual2_T_2; // @[ExecuteController.scala:666:47]
wire _in_prop_flush_qual2_T_1; // @[ExecuteController.scala:666:47]
wire [13:0] _in_prop_flush_qual2_T; // @[ExecuteController.scala:666:47]
wire _in_prop_flush_T_11 = in_prop_flush_qual2_garbage_bit; // @[LocalAddr.scala:44:48]
wire in_prop_flush_qual2_is_acc_addr; // @[ExecuteController.scala:666:47]
wire in_prop_flush_qual2_accumulate; // @[ExecuteController.scala:666:47]
wire in_prop_flush_qual2_read_full_acc_row; // @[ExecuteController.scala:666:47]
wire [2:0] in_prop_flush_qual2_norm_cmd; // @[ExecuteController.scala:666:47]
wire [10:0] in_prop_flush_qual2_garbage; // @[ExecuteController.scala:666:47]
wire [13:0] in_prop_flush_qual2_data; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T = _in_prop_flush_qual2_WIRE[13:0]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_data = _in_prop_flush_qual2_T; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T_1 = _in_prop_flush_qual2_WIRE[14]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_garbage_bit = _in_prop_flush_qual2_T_1; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T_2 = _in_prop_flush_qual2_WIRE[25:15]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_garbage = _in_prop_flush_qual2_T_2; // @[ExecuteController.scala:666:47]
wire [2:0] _in_prop_flush_qual2_T_3 = _in_prop_flush_qual2_WIRE[28:26]; // @[ExecuteController.scala:666:47]
wire [2:0] _in_prop_flush_qual2_WIRE_1 = _in_prop_flush_qual2_T_3; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_WIRE_2 = _in_prop_flush_qual2_WIRE_1; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_norm_cmd = _in_prop_flush_qual2_WIRE_2; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T_4 = _in_prop_flush_qual2_WIRE[29]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_read_full_acc_row = _in_prop_flush_qual2_T_4; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T_5 = _in_prop_flush_qual2_WIRE[30]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_accumulate = _in_prop_flush_qual2_T_5; // @[ExecuteController.scala:666:47]
assign _in_prop_flush_qual2_T_6 = _in_prop_flush_qual2_WIRE[31]; // @[ExecuteController.scala:666:47]
assign in_prop_flush_qual2_is_acc_addr = _in_prop_flush_qual2_T_6; // @[ExecuteController.scala:666:47]
wire _in_prop_flush_T_7 = in_prop_flush_qual2_is_acc_addr & in_prop_flush_qual2_accumulate; // @[LocalAddr.scala:43:48]
wire _in_prop_flush_T_8 = _in_prop_flush_T_7 & in_prop_flush_qual2_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _in_prop_flush_T_9 = &in_prop_flush_qual2_data; // @[LocalAddr.scala:43:91]
wire _in_prop_flush_T_10 = _in_prop_flush_T_8 & _in_prop_flush_T_9; // @[LocalAddr.scala:43:{62,83,91}]
wire _in_prop_flush_T_12 = _in_prop_flush_T_10 & _in_prop_flush_T_11; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _in_prop_flush_T_13 = ~_in_prop_flush_T_12; // @[LocalAddr.scala:43:96]
wire _start_inputting_a_T_1 = ~a_should_be_fed_into_transposer; // @[ExecuteController.scala:123:44, :289:5, :672:30]
assign start_inputting_a = _T_100 ? _cmd_q_io_deq_valid_0 & ~_T_105 & (_T_111 ? a_should_be_fed_into_transposer : _T_118 | DoComputes_0 & _start_inputting_a_T) : _T_615 & (perform_single_preload ? a_should_be_fed_into_transposer : perform_mul_pre | perform_single_mul & _start_inputting_a_T_1); // @[MultiHeadedQueue.scala:53:19]
wire _GEN_62 = perform_mul_pre | perform_single_mul; // @[ExecuteController.scala:278:35, :279:32, :652:34, :654:27, :671:37]
assign start_inputting_b = _T_100 ? _cmd_q_io_deq_valid_0 & ~_GEN_59 & (_T_118 | DoComputes_0) : _T_615 & ~perform_single_preload & _GEN_62; // @[MultiHeadedQueue.scala:53:19]
wire _computing_T = performing_mul_pre | performing_single_mul; // @[ExecuteController.scala:282:39, :283:36, :696:38]
wire computing = _computing_T | performing_single_preload; // @[ExecuteController.scala:281:43, :696:{38,63}]
wire [4:0] _mesh_cntl_signals_q_io_enq_bits_a_unpadded_cols_T = a_row_is_not_all_zeros ? a_cols : 5'h0; // @[ExecuteController.scala:161:19, :310:47, :775:57]
wire [4:0] _mesh_cntl_signals_q_io_enq_bits_b_unpadded_cols_T = b_row_is_not_all_zeros ? b_cols : 5'h0; // @[ExecuteController.scala:163:19, :311:47, :776:57]
wire [4:0] _mesh_cntl_signals_q_io_enq_bits_d_unpadded_cols_T = d_row_is_not_all_zeros ? d_cols : 5'h0; // @[ExecuteController.scala:165:19, :312:68, :777:57]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T = ~performing_single_mul; // @[ExecuteController.scala:282:39, :792:51]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_2 = _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_1 & c_address_rs2_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_3 = &c_address_rs2_data; // @[LocalAddr.scala:43:91]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_4 = _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_2 & _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_3; // @[LocalAddr.scala:43:{62,83,91}]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_6 = _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_4 & _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_5; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_7 = ~_mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_6; // @[LocalAddr.scala:43:96]
wire _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_8 = _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T & _mesh_cntl_signals_q_io_enq_bits_rob_id_valid_T_7; // @[ExecuteController.scala:792:{51,74,77}]
wire [3:0][5:0] _GEN_63 = {{_cmd_q_io_deq_bits_0_rob_id_bits}, {_cmd_q_io_deq_bits_2_rob_id_bits}, {_cmd_q_io_deq_bits_1_rob_id_bits}, {_cmd_q_io_deq_bits_0_rob_id_bits}}; // @[MultiHeadedQueue.scala:53:19]
wire _mesh_cntl_signals_q_io_enq_bits_prop_T = ~performing_single_preload & in_prop; // @[ExecuteController.scala:90:27, :281:43, :796:46]
wire _mesh_cntl_signals_q_io_enq_bits_first_T = ~a_fire_started; // @[ExecuteController.scala:240:31, :801:44]
wire _mesh_cntl_signals_q_io_enq_bits_first_T_1 = ~b_fire_started; // @[ExecuteController.scala:242:31, :801:63]
wire _mesh_cntl_signals_q_io_enq_bits_first_T_2 = _mesh_cntl_signals_q_io_enq_bits_first_T & _mesh_cntl_signals_q_io_enq_bits_first_T_1; // @[ExecuteController.scala:801:{44,60,63}]
wire _mesh_cntl_signals_q_io_enq_bits_first_T_3 = ~d_fire_started; // @[ExecuteController.scala:241:31, :801:82]
wire _mesh_cntl_signals_q_io_enq_bits_first_T_4 = _mesh_cntl_signals_q_io_enq_bits_first_T_2 & _mesh_cntl_signals_q_io_enq_bits_first_T_3; // @[ExecuteController.scala:801:{60,79,82}]
wire [15:0] im2ColData_lo_lo_lo = {_im2ColData_T_1, _im2ColData_T}; // @[ExecuteController.scala:805:49]
wire [15:0] im2ColData_lo_lo_hi = {_im2ColData_T_3, _im2ColData_T_2}; // @[ExecuteController.scala:805:49]
wire [31:0] im2ColData_lo_lo = {im2ColData_lo_lo_hi, im2ColData_lo_lo_lo}; // @[ExecuteController.scala:805:49]
wire [15:0] im2ColData_lo_hi_lo = {_im2ColData_T_5, _im2ColData_T_4}; // @[ExecuteController.scala:805:49]
wire [15:0] im2ColData_lo_hi_hi = {_im2ColData_T_7, _im2ColData_T_6}; // @[ExecuteController.scala:805:49]
wire [31:0] im2ColData_lo_hi = {im2ColData_lo_hi_hi, im2ColData_lo_hi_lo}; // @[ExecuteController.scala:805:49]
wire [63:0] im2ColData_lo = {im2ColData_lo_hi, im2ColData_lo_lo}; // @[ExecuteController.scala:805:49]
wire [15:0] im2ColData_hi_lo_lo = {_im2ColData_T_9, _im2ColData_T_8}; // @[ExecuteController.scala:805:49]
wire [15:0] im2ColData_hi_lo_hi = {_im2ColData_T_11, _im2ColData_T_10}; // @[ExecuteController.scala:805:49]
wire [31:0] im2ColData_hi_lo = {im2ColData_hi_lo_hi, im2ColData_hi_lo_lo}; // @[ExecuteController.scala:805:49]
wire [15:0] im2ColData_hi_hi_lo = {_im2ColData_T_13, _im2ColData_T_12}; // @[ExecuteController.scala:805:49]
wire [15:0] im2ColData_hi_hi_hi = {_im2ColData_T_15, _im2ColData_T_14}; // @[ExecuteController.scala:805:49]
wire [31:0] im2ColData_hi_hi = {im2ColData_hi_hi_hi, im2ColData_hi_hi_lo}; // @[ExecuteController.scala:805:49]
wire [63:0] im2ColData_hi = {im2ColData_hi_hi, im2ColData_hi_lo}; // @[ExecuteController.scala:805:49]
wire [127:0] im2ColData = {im2ColData_hi, im2ColData_lo}; // @[ExecuteController.scala:805:49]
wire _readValid_T_1 = ~io_srams_read_0_resp_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :807:95]
wire _readValid_T_2 = _readValid_T & _readValid_T_1; // @[ExecuteController.scala:807:{73,92,95}]
wire readValid_0 = _readValid_T_2; // @[ExecuteController.scala:807:{26,92}]
wire _readValid_T_4 = ~io_srams_read_1_resp_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :807:95]
wire _readValid_T_5 = _readValid_T_3 & _readValid_T_4; // @[ExecuteController.scala:807:{73,92,95}]
wire readValid_1 = _readValid_T_5; // @[ExecuteController.scala:807:{26,92}]
wire _readValid_T_7 = ~io_srams_read_2_resp_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :807:95]
wire _readValid_T_8 = _readValid_T_6 & _readValid_T_7; // @[ExecuteController.scala:807:{73,92,95}]
wire readValid_2 = _readValid_T_8; // @[ExecuteController.scala:807:{26,92}]
wire _readValid_T_10 = ~io_srams_read_3_resp_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :807:95]
wire _readValid_T_11 = _readValid_T_9 & _readValid_T_10; // @[ExecuteController.scala:807:{73,92,95}]
wire readValid_3 = _readValid_T_11; // @[ExecuteController.scala:807:{26,92}]
wire _accReadValid_T_1 = ~io_acc_read_resp_0_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :808:95]
wire _accReadValid_T_4 = ~io_acc_read_resp_1_bits_fromDMA_0; // @[ExecuteController.scala:12:7, :808:95]
wire _mesh_cntl_signals_q_io_deq_ready_T = ~_mesh_cntl_signals_q_io_deq_bits_a_fire; // @[ExecuteController.scala:178:35, :811:40]
wire _mesh_cntl_signals_q_io_deq_ready_T_1 = _mesh_io_a_ready & mesh_io_a_valid; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_2 = _mesh_cntl_signals_q_io_deq_ready_T | _mesh_cntl_signals_q_io_deq_ready_T_1; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_3 = ~_mesh_io_a_ready; // @[ExecuteController.scala:186:20, :811:74]
wire _mesh_cntl_signals_q_io_deq_ready_T_4 = _mesh_cntl_signals_q_io_deq_ready_T_2 | _mesh_cntl_signals_q_io_deq_ready_T_3; // @[ExecuteController.scala:811:{53,71,74}]
wire _mesh_cntl_signals_q_io_deq_ready_T_5 = ~_mesh_cntl_signals_q_io_deq_bits_b_fire; // @[ExecuteController.scala:178:35, :812:6]
wire _mesh_cntl_signals_q_io_deq_ready_T_6 = _mesh_io_b_ready & mesh_io_b_valid; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_7 = _mesh_cntl_signals_q_io_deq_ready_T_5 | _mesh_cntl_signals_q_io_deq_ready_T_6; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_8 = ~_mesh_io_b_ready; // @[ExecuteController.scala:186:20, :812:40]
wire _mesh_cntl_signals_q_io_deq_ready_T_9 = _mesh_cntl_signals_q_io_deq_ready_T_7 | _mesh_cntl_signals_q_io_deq_ready_T_8; // @[ExecuteController.scala:812:{19,37,40}]
wire _mesh_cntl_signals_q_io_deq_ready_T_10 = _mesh_cntl_signals_q_io_deq_ready_T_4 & _mesh_cntl_signals_q_io_deq_ready_T_9; // @[ExecuteController.scala:811:{71,92}, :812:37]
wire _mesh_cntl_signals_q_io_deq_ready_T_11 = ~_mesh_cntl_signals_q_io_deq_bits_d_fire; // @[ExecuteController.scala:178:35, :813:6]
wire _mesh_cntl_signals_q_io_deq_ready_T_12 = _mesh_io_d_ready & mesh_io_d_valid; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_13 = _mesh_cntl_signals_q_io_deq_ready_T_11 | _mesh_cntl_signals_q_io_deq_ready_T_12; // @[Decoupled.scala:51:35]
wire _mesh_cntl_signals_q_io_deq_ready_T_14 = ~_mesh_io_d_ready; // @[ExecuteController.scala:186:20, :813:40]
wire _mesh_cntl_signals_q_io_deq_ready_T_15 = _mesh_cntl_signals_q_io_deq_ready_T_13 | _mesh_cntl_signals_q_io_deq_ready_T_14; // @[ExecuteController.scala:813:{19,37,40}]
wire _mesh_cntl_signals_q_io_deq_ready_T_16 = _mesh_cntl_signals_q_io_deq_ready_T_10 & _mesh_cntl_signals_q_io_deq_ready_T_15; // @[ExecuteController.scala:811:92, :812:58, :813:37]
wire _mesh_cntl_signals_q_io_deq_ready_T_17 = ~_mesh_cntl_signals_q_io_deq_bits_first; // @[ExecuteController.scala:178:35, :814:6]
wire _mesh_cntl_signals_q_io_deq_ready_T_18 = _mesh_cntl_signals_q_io_deq_ready_T_17 | _mesh_io_req_ready; // @[ExecuteController.scala:186:20, :814:{6,18}]
wire _mesh_cntl_signals_q_io_deq_ready_T_19 = _mesh_cntl_signals_q_io_deq_ready_T_16 & _mesh_cntl_signals_q_io_deq_ready_T_18; // @[ExecuteController.scala:812:58, :813:58, :814:18]
wire _dataA_valid_T = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols == 5'h0; // @[ExecuteController.scala:178:35, :816:60]
wire _dataA_valid_T_1 = _mesh_cntl_signals_q_io_deq_bits_a_garbage | _dataA_valid_T; // @[ExecuteController.scala:178:35, :816:{36,60}]
wire [3:0] _GEN_64 = {{readValid_3}, {readValid_2}, {readValid_1}, {readValid_0}}; // @[ExecuteController.scala:807:26, :816:108]
wire _dataA_valid_T_2 = ~_mesh_cntl_signals_q_io_deq_bits_a_read_from_acc & _GEN_64[_mesh_cntl_signals_q_io_deq_bits_a_bank]; // @[ExecuteController.scala:178:35, :816:108]
wire _dataA_valid_T_3 = ~_mesh_cntl_signals_q_io_deq_bits_im2colling & _dataA_valid_T_2; // @[ExecuteController.scala:178:35, :816:{74,108}]
wire dataA_valid = _dataA_valid_T_1 | _dataA_valid_T_3; // @[ExecuteController.scala:816:{36,68,74}]
wire _dataB_valid_T = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols == 5'h0; // @[ExecuteController.scala:178:35, :818:60]
wire _dataB_valid_T_1 = _mesh_cntl_signals_q_io_deq_bits_b_garbage | _dataB_valid_T; // @[ExecuteController.scala:178:35, :818:{36,60}]
wire _dataB_valid_T_2 = ~_mesh_cntl_signals_q_io_deq_bits_b_read_from_acc & _GEN_64[_mesh_cntl_signals_q_io_deq_bits_b_bank]; // @[Mux.scala:126:16]
wire _dataB_valid_T_3 = ~_mesh_cntl_signals_q_io_deq_bits_accumulate_zeros & _dataB_valid_T_2; // @[Mux.scala:126:16]
wire dataB_valid = _dataB_valid_T_1 | _dataB_valid_T_3; // @[Mux.scala:126:16]
wire _dataD_valid_T = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols == 5'h0; // @[ExecuteController.scala:178:35, :822:60]
wire _dataD_valid_T_1 = _mesh_cntl_signals_q_io_deq_bits_d_garbage | _dataD_valid_T; // @[ExecuteController.scala:178:35, :822:{36,60}]
wire _dataD_valid_T_2 = ~_mesh_cntl_signals_q_io_deq_bits_d_read_from_acc & _GEN_64[_mesh_cntl_signals_q_io_deq_bits_d_bank]; // @[Mux.scala:126:16]
wire _dataD_valid_T_3 = ~_mesh_cntl_signals_q_io_deq_bits_preload_zeros & _dataD_valid_T_2; // @[Mux.scala:126:16]
wire dataD_valid = _dataD_valid_T_1 | _dataD_valid_T_3; // @[Mux.scala:126:16]
reg [4:0] preload_zero_counter; // @[ExecuteController.scala:828:37]
wire _preload_zero_counter_T = dataA_valid & dataD_valid; // @[ExecuteController.scala:816:68, :822:68, :830:92]
wire _preload_zero_counter_T_1 = _preload_zero_counter_T & _mesh_cntl_signals_q_io_deq_bits_preload_zeros; // @[ExecuteController.scala:178:35, :830:{92,107}]
wire _preload_zero_counter_T_2 = _mesh_cntl_signals_q_io_deq_bits_perform_single_preload | _mesh_cntl_signals_q_io_deq_bits_perform_mul_pre; // @[ExecuteController.scala:178:35, :830:161]
wire _preload_zero_counter_T_3 = _preload_zero_counter_T_1 & _preload_zero_counter_T_2; // @[ExecuteController.scala:830:{107,129,161}]
wire _preload_zero_counter_T_8 = ~_preload_zero_counter_T_7; // @[Util.scala:19:11]
wire [5:0] _GEN_65 = {1'h0, preload_zero_counter}; // @[Util.scala:27:15]
wire [5:0] _preload_zero_counter_T_10 = _GEN_65 + 6'h1; // @[Util.scala:27:15]
wire [4:0] _preload_zero_counter_T_11 = _preload_zero_counter_T_10[4:0]; // @[Util.scala:27:15]
wire _preload_zero_counter_T_12 = ~_preload_zero_counter_T_3; // @[Util.scala:28:8]
wire _preload_zero_counter_T_18 = preload_zero_counter > 5'hE; // @[Util.scala:30:10]
wire _preload_zero_counter_T_20 = _preload_zero_counter_T_18; // @[Util.scala:30:{10,27}]
wire [5:0] _preload_zero_counter_T_21 = 6'hF - _GEN_65; // @[Util.scala:27:15, :30:54]
wire [4:0] _preload_zero_counter_T_22 = _preload_zero_counter_T_21[4:0]; // @[Util.scala:30:54]
wire [5:0] _preload_zero_counter_T_23 = 6'h1 - {1'h0, _preload_zero_counter_T_22}; // @[Util.scala:30:{47,54}]
wire [4:0] _preload_zero_counter_T_24 = _preload_zero_counter_T_23[4:0]; // @[Util.scala:30:47]
wire [5:0] _preload_zero_counter_T_25 = {1'h0, _preload_zero_counter_T_24} - 6'h1; // @[Util.scala:30:{47,59}]
wire [4:0] _preload_zero_counter_T_26 = _preload_zero_counter_T_25[4:0]; // @[Util.scala:30:59]
wire [4:0] _preload_zero_counter_T_27 = _preload_zero_counter_T_20 ? _preload_zero_counter_T_26 : _preload_zero_counter_T_11; // @[Mux.scala:126:16]
wire [4:0] _preload_zero_counter_T_28 = _preload_zero_counter_T_27; // @[Mux.scala:126:16]
wire [4:0] _preload_zero_counter_T_29 = _preload_zero_counter_T_12 ? preload_zero_counter : _preload_zero_counter_T_28; // @[Mux.scala:126:16]
wire [3:0][127:0] _GEN_66 = {{readData_3}, {readData_2}, {readData_1}, {readData_0}}; // @[ExecuteController.scala:803:25, :832:60]
wire [127:0] _dataA_unpadded_T = _mesh_cntl_signals_q_io_deq_bits_a_read_from_acc ? _GEN_66[{1'h0, _mesh_cntl_signals_q_io_deq_bits_a_bank_acc}] : _GEN_66[_mesh_cntl_signals_q_io_deq_bits_a_bank]; // @[ExecuteController.scala:178:35, :832:60]
wire [127:0] dataA_unpadded = _mesh_cntl_signals_q_io_deq_bits_im2colling ? im2ColData : _dataA_unpadded_T; // @[ExecuteController.scala:178:35, :805:49, :832:{27,60}]
wire [127:0] _dataA_WIRE_1 = dataA_unpadded; // @[ExecuteController.scala:832:27, :836:46]
wire [127:0] _dataB_unpadded_T = _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc ? _GEN_66[{1'h0, _mesh_cntl_signals_q_io_deq_bits_b_bank_acc}] : _GEN_66[_mesh_cntl_signals_q_io_deq_bits_b_bank]; // @[Mux.scala:126:16]
wire [127:0] dataB_unpadded = _mesh_cntl_signals_q_io_deq_bits_accumulate_zeros ? 128'h0 : _dataB_unpadded_T; // @[Mux.scala:126:16]
wire [127:0] _dataB_WIRE_1 = dataB_unpadded; // @[Mux.scala:126:16]
wire [127:0] _dataD_unpadded_T = _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc ? _GEN_66[{1'h0, _mesh_cntl_signals_q_io_deq_bits_d_bank_acc}] : _GEN_66[_mesh_cntl_signals_q_io_deq_bits_d_bank]; // @[Mux.scala:126:16]
wire [127:0] dataD_unpadded = _mesh_cntl_signals_q_io_deq_bits_preload_zeros ? 128'h0 : _dataD_unpadded_T; // @[Mux.scala:126:16]
wire [127:0] _dataD_WIRE_1 = dataD_unpadded; // @[Mux.scala:126:16]
wire [7:0] _dataA_T_1; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_3; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_5; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_7; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_9; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_11; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_13; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_15; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_17; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_19; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_21; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_23; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_25; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_27; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_29; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_31; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T = _dataA_WIRE_1[7:0]; // @[ExecuteController.scala:836:46]
assign _dataA_T_1 = _dataA_T; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_0 = _dataA_T_1; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_2 = _dataA_WIRE_1[15:8]; // @[ExecuteController.scala:836:46]
assign _dataA_T_3 = _dataA_T_2; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_1_0 = _dataA_T_3; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_4 = _dataA_WIRE_1[23:16]; // @[ExecuteController.scala:836:46]
assign _dataA_T_5 = _dataA_T_4; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_2 = _dataA_T_5; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_6 = _dataA_WIRE_1[31:24]; // @[ExecuteController.scala:836:46]
assign _dataA_T_7 = _dataA_T_6; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_3 = _dataA_T_7; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_8 = _dataA_WIRE_1[39:32]; // @[ExecuteController.scala:836:46]
assign _dataA_T_9 = _dataA_T_8; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_4 = _dataA_T_9; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_10 = _dataA_WIRE_1[47:40]; // @[ExecuteController.scala:836:46]
assign _dataA_T_11 = _dataA_T_10; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_5 = _dataA_T_11; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_12 = _dataA_WIRE_1[55:48]; // @[ExecuteController.scala:836:46]
assign _dataA_T_13 = _dataA_T_12; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_6 = _dataA_T_13; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_14 = _dataA_WIRE_1[63:56]; // @[ExecuteController.scala:836:46]
assign _dataA_T_15 = _dataA_T_14; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_7 = _dataA_T_15; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_16 = _dataA_WIRE_1[71:64]; // @[ExecuteController.scala:836:46]
assign _dataA_T_17 = _dataA_T_16; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_8 = _dataA_T_17; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_18 = _dataA_WIRE_1[79:72]; // @[ExecuteController.scala:836:46]
assign _dataA_T_19 = _dataA_T_18; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_9 = _dataA_T_19; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_20 = _dataA_WIRE_1[87:80]; // @[ExecuteController.scala:836:46]
assign _dataA_T_21 = _dataA_T_20; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_10 = _dataA_T_21; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_22 = _dataA_WIRE_1[95:88]; // @[ExecuteController.scala:836:46]
assign _dataA_T_23 = _dataA_T_22; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_11 = _dataA_T_23; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_24 = _dataA_WIRE_1[103:96]; // @[ExecuteController.scala:836:46]
assign _dataA_T_25 = _dataA_T_24; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_12 = _dataA_T_25; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_26 = _dataA_WIRE_1[111:104]; // @[ExecuteController.scala:836:46]
assign _dataA_T_27 = _dataA_T_26; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_13 = _dataA_T_27; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_28 = _dataA_WIRE_1[119:112]; // @[ExecuteController.scala:836:46]
assign _dataA_T_29 = _dataA_T_28; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_14 = _dataA_T_29; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_T_30 = _dataA_WIRE_1[127:120]; // @[ExecuteController.scala:836:46]
assign _dataA_T_31 = _dataA_T_30; // @[ExecuteController.scala:836:46]
wire [7:0] _dataA_WIRE_15 = _dataA_T_31; // @[ExecuteController.scala:836:46]
wire _dataA_T_32 = |_mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_33 = _dataA_T_32 ? _dataA_WIRE_0 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_0 = _dataA_T_33; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_34 = |(_mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols[4:1]); // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_35 = _dataA_T_34 ? _dataA_WIRE_1_0 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_1 = _dataA_T_35; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_36 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'h2; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_37 = _dataA_T_36 ? _dataA_WIRE_2 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_2 = _dataA_T_37; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_38 = |(_mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols[4:2]); // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_39 = _dataA_T_38 ? _dataA_WIRE_3 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_3 = _dataA_T_39; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_40 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'h4; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_41 = _dataA_T_40 ? _dataA_WIRE_4 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_4 = _dataA_T_41; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_42 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'h5; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_43 = _dataA_T_42 ? _dataA_WIRE_5 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_5 = _dataA_T_43; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_44 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'h6; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_45 = _dataA_T_44 ? _dataA_WIRE_6 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_6 = _dataA_T_45; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_46 = |(_mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols[4:3]); // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_47 = _dataA_T_46 ? _dataA_WIRE_7 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_7 = _dataA_T_47; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_48 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'h8; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_49 = _dataA_T_48 ? _dataA_WIRE_8 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_8 = _dataA_T_49; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_50 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'h9; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_51 = _dataA_T_50 ? _dataA_WIRE_9 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_9 = _dataA_T_51; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_52 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'hA; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_53 = _dataA_T_52 ? _dataA_WIRE_10 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_10 = _dataA_T_53; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_54 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'hB; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_55 = _dataA_T_54 ? _dataA_WIRE_11 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_11 = _dataA_T_55; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_56 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'hC; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_57 = _dataA_T_56 ? _dataA_WIRE_12 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_12 = _dataA_T_57; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_58 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'hD; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_59 = _dataA_T_58 ? _dataA_WIRE_13 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_13 = _dataA_T_59; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_60 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols > 5'hE; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_61 = _dataA_T_60 ? _dataA_WIRE_14 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_14 = _dataA_T_61; // @[ExecuteController.scala:836:{22,112}]
wire _dataA_T_62 = _mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols[4]; // @[ExecuteController.scala:178:35, :836:117]
wire [7:0] _dataA_T_63 = _dataA_T_62 ? _dataA_WIRE_15 : 8'h0; // @[ExecuteController.scala:836:{46,112,117}]
wire [7:0] dataA_15 = _dataA_T_63; // @[ExecuteController.scala:836:{22,112}]
wire [7:0] _dataB_T_1; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_3; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_5; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_7; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_9; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_11; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_13; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_15; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_17; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_19; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_21; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_23; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_25; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_27; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_29; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_31; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T = _dataB_WIRE_1[7:0]; // @[ExecuteController.scala:837:46]
assign _dataB_T_1 = _dataB_T; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_0 = _dataB_T_1; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_2 = _dataB_WIRE_1[15:8]; // @[ExecuteController.scala:837:46]
assign _dataB_T_3 = _dataB_T_2; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_1_0 = _dataB_T_3; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_4 = _dataB_WIRE_1[23:16]; // @[ExecuteController.scala:837:46]
assign _dataB_T_5 = _dataB_T_4; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_2 = _dataB_T_5; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_6 = _dataB_WIRE_1[31:24]; // @[ExecuteController.scala:837:46]
assign _dataB_T_7 = _dataB_T_6; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_3 = _dataB_T_7; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_8 = _dataB_WIRE_1[39:32]; // @[ExecuteController.scala:837:46]
assign _dataB_T_9 = _dataB_T_8; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_4 = _dataB_T_9; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_10 = _dataB_WIRE_1[47:40]; // @[ExecuteController.scala:837:46]
assign _dataB_T_11 = _dataB_T_10; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_5 = _dataB_T_11; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_12 = _dataB_WIRE_1[55:48]; // @[ExecuteController.scala:837:46]
assign _dataB_T_13 = _dataB_T_12; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_6 = _dataB_T_13; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_14 = _dataB_WIRE_1[63:56]; // @[ExecuteController.scala:837:46]
assign _dataB_T_15 = _dataB_T_14; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_7 = _dataB_T_15; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_16 = _dataB_WIRE_1[71:64]; // @[ExecuteController.scala:837:46]
assign _dataB_T_17 = _dataB_T_16; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_8 = _dataB_T_17; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_18 = _dataB_WIRE_1[79:72]; // @[ExecuteController.scala:837:46]
assign _dataB_T_19 = _dataB_T_18; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_9 = _dataB_T_19; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_20 = _dataB_WIRE_1[87:80]; // @[ExecuteController.scala:837:46]
assign _dataB_T_21 = _dataB_T_20; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_10 = _dataB_T_21; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_22 = _dataB_WIRE_1[95:88]; // @[ExecuteController.scala:837:46]
assign _dataB_T_23 = _dataB_T_22; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_11 = _dataB_T_23; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_24 = _dataB_WIRE_1[103:96]; // @[ExecuteController.scala:837:46]
assign _dataB_T_25 = _dataB_T_24; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_12 = _dataB_T_25; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_26 = _dataB_WIRE_1[111:104]; // @[ExecuteController.scala:837:46]
assign _dataB_T_27 = _dataB_T_26; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_13 = _dataB_T_27; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_28 = _dataB_WIRE_1[119:112]; // @[ExecuteController.scala:837:46]
assign _dataB_T_29 = _dataB_T_28; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_14 = _dataB_T_29; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_T_30 = _dataB_WIRE_1[127:120]; // @[ExecuteController.scala:837:46]
assign _dataB_T_31 = _dataB_T_30; // @[ExecuteController.scala:837:46]
wire [7:0] _dataB_WIRE_15 = _dataB_T_31; // @[ExecuteController.scala:837:46]
wire _dataB_T_32 = |_mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_33 = _dataB_T_32 ? _dataB_WIRE_0 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_0 = _dataB_T_33; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_34 = |(_mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols[4:1]); // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_35 = _dataB_T_34 ? _dataB_WIRE_1_0 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_1 = _dataB_T_35; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_36 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'h2; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_37 = _dataB_T_36 ? _dataB_WIRE_2 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_2 = _dataB_T_37; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_38 = |(_mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols[4:2]); // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_39 = _dataB_T_38 ? _dataB_WIRE_3 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_3 = _dataB_T_39; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_40 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'h4; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_41 = _dataB_T_40 ? _dataB_WIRE_4 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_4 = _dataB_T_41; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_42 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'h5; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_43 = _dataB_T_42 ? _dataB_WIRE_5 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_5 = _dataB_T_43; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_44 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'h6; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_45 = _dataB_T_44 ? _dataB_WIRE_6 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_6 = _dataB_T_45; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_46 = |(_mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols[4:3]); // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_47 = _dataB_T_46 ? _dataB_WIRE_7 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_7 = _dataB_T_47; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_48 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'h8; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_49 = _dataB_T_48 ? _dataB_WIRE_8 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_8 = _dataB_T_49; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_50 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'h9; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_51 = _dataB_T_50 ? _dataB_WIRE_9 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_9 = _dataB_T_51; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_52 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'hA; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_53 = _dataB_T_52 ? _dataB_WIRE_10 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_10 = _dataB_T_53; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_54 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'hB; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_55 = _dataB_T_54 ? _dataB_WIRE_11 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_11 = _dataB_T_55; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_56 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'hC; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_57 = _dataB_T_56 ? _dataB_WIRE_12 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_12 = _dataB_T_57; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_58 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'hD; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_59 = _dataB_T_58 ? _dataB_WIRE_13 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_13 = _dataB_T_59; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_60 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols > 5'hE; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_61 = _dataB_T_60 ? _dataB_WIRE_14 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_14 = _dataB_T_61; // @[ExecuteController.scala:837:{22,112}]
wire _dataB_T_62 = _mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols[4]; // @[ExecuteController.scala:178:35, :837:117]
wire [7:0] _dataB_T_63 = _dataB_T_62 ? _dataB_WIRE_15 : 8'h0; // @[ExecuteController.scala:837:{46,112,117}]
wire [7:0] dataB_15 = _dataB_T_63; // @[ExecuteController.scala:837:{22,112}]
wire [7:0] _dataD_T_1; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_3; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_5; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_7; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_9; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_11; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_13; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_15; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_17; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_19; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_21; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_23; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_25; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_27; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_29; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_31; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T = _dataD_WIRE_1[7:0]; // @[ExecuteController.scala:838:46]
assign _dataD_T_1 = _dataD_T; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_0 = _dataD_T_1; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_2 = _dataD_WIRE_1[15:8]; // @[ExecuteController.scala:838:46]
assign _dataD_T_3 = _dataD_T_2; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_1_0 = _dataD_T_3; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_4 = _dataD_WIRE_1[23:16]; // @[ExecuteController.scala:838:46]
assign _dataD_T_5 = _dataD_T_4; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_2 = _dataD_T_5; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_6 = _dataD_WIRE_1[31:24]; // @[ExecuteController.scala:838:46]
assign _dataD_T_7 = _dataD_T_6; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_3 = _dataD_T_7; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_8 = _dataD_WIRE_1[39:32]; // @[ExecuteController.scala:838:46]
assign _dataD_T_9 = _dataD_T_8; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_4 = _dataD_T_9; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_10 = _dataD_WIRE_1[47:40]; // @[ExecuteController.scala:838:46]
assign _dataD_T_11 = _dataD_T_10; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_5 = _dataD_T_11; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_12 = _dataD_WIRE_1[55:48]; // @[ExecuteController.scala:838:46]
assign _dataD_T_13 = _dataD_T_12; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_6 = _dataD_T_13; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_14 = _dataD_WIRE_1[63:56]; // @[ExecuteController.scala:838:46]
assign _dataD_T_15 = _dataD_T_14; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_7 = _dataD_T_15; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_16 = _dataD_WIRE_1[71:64]; // @[ExecuteController.scala:838:46]
assign _dataD_T_17 = _dataD_T_16; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_8 = _dataD_T_17; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_18 = _dataD_WIRE_1[79:72]; // @[ExecuteController.scala:838:46]
assign _dataD_T_19 = _dataD_T_18; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_9 = _dataD_T_19; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_20 = _dataD_WIRE_1[87:80]; // @[ExecuteController.scala:838:46]
assign _dataD_T_21 = _dataD_T_20; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_10 = _dataD_T_21; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_22 = _dataD_WIRE_1[95:88]; // @[ExecuteController.scala:838:46]
assign _dataD_T_23 = _dataD_T_22; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_11 = _dataD_T_23; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_24 = _dataD_WIRE_1[103:96]; // @[ExecuteController.scala:838:46]
assign _dataD_T_25 = _dataD_T_24; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_12 = _dataD_T_25; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_26 = _dataD_WIRE_1[111:104]; // @[ExecuteController.scala:838:46]
assign _dataD_T_27 = _dataD_T_26; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_13 = _dataD_T_27; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_28 = _dataD_WIRE_1[119:112]; // @[ExecuteController.scala:838:46]
assign _dataD_T_29 = _dataD_T_28; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_14 = _dataD_T_29; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_T_30 = _dataD_WIRE_1[127:120]; // @[ExecuteController.scala:838:46]
assign _dataD_T_31 = _dataD_T_30; // @[ExecuteController.scala:838:46]
wire [7:0] _dataD_WIRE_15 = _dataD_T_31; // @[ExecuteController.scala:838:46]
wire _dataD_T_32 = |_mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_33 = _dataD_T_32 ? _dataD_WIRE_0 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_0 = _dataD_T_33; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_34 = |(_mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols[4:1]); // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_35 = _dataD_T_34 ? _dataD_WIRE_1_0 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_1 = _dataD_T_35; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_36 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'h2; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_37 = _dataD_T_36 ? _dataD_WIRE_2 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_2 = _dataD_T_37; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_38 = |(_mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols[4:2]); // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_39 = _dataD_T_38 ? _dataD_WIRE_3 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_3 = _dataD_T_39; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_40 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'h4; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_41 = _dataD_T_40 ? _dataD_WIRE_4 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_4 = _dataD_T_41; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_42 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'h5; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_43 = _dataD_T_42 ? _dataD_WIRE_5 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_5 = _dataD_T_43; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_44 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'h6; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_45 = _dataD_T_44 ? _dataD_WIRE_6 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_6 = _dataD_T_45; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_46 = |(_mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols[4:3]); // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_47 = _dataD_T_46 ? _dataD_WIRE_7 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_7 = _dataD_T_47; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_48 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'h8; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_49 = _dataD_T_48 ? _dataD_WIRE_8 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_8 = _dataD_T_49; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_50 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'h9; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_51 = _dataD_T_50 ? _dataD_WIRE_9 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_9 = _dataD_T_51; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_52 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'hA; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_53 = _dataD_T_52 ? _dataD_WIRE_10 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_10 = _dataD_T_53; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_54 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'hB; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_55 = _dataD_T_54 ? _dataD_WIRE_11 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_11 = _dataD_T_55; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_56 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'hC; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_57 = _dataD_T_56 ? _dataD_WIRE_12 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_12 = _dataD_T_57; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_58 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'hD; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_59 = _dataD_T_58 ? _dataD_WIRE_13 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_13 = _dataD_T_59; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_60 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols > 5'hE; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_61 = _dataD_T_60 ? _dataD_WIRE_14 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_14 = _dataD_T_61; // @[ExecuteController.scala:838:{22,112}]
wire _dataD_T_62 = _mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols[4]; // @[ExecuteController.scala:178:35, :838:117]
wire [7:0] _dataD_T_63 = _dataD_T_62 ? _dataD_WIRE_15 : 8'h0; // @[ExecuteController.scala:838:{46,112,117}]
wire [7:0] dataD_15 = _dataD_T_63; // @[ExecuteController.scala:838:{22,112}]
wire _mesh_io_req_valid_T_1 = _mesh_cntl_signals_q_io_deq_ready_T_19 & _mesh_cntl_signals_q_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_138 = _mesh_cntl_signals_q_io_deq_bits_a_fire & _mesh_cntl_signals_q_io_deq_ready_T_1 & ~_mesh_cntl_signals_q_io_deq_bits_a_garbage & (|_mesh_cntl_signals_q_io_deq_bits_a_unpadded_cols) & ~_mesh_cntl_signals_q_io_deq_bits_im2colling; // @[Decoupled.scala:51:35]
wire _io_acc_read_resp_ready_T = ~(_mesh_cntl_signals_q_io_deq_bits_a_bank_acc ? io_acc_read_resp_1_bits_fromDMA_0 : io_acc_read_resp_0_bits_fromDMA_0); // @[ExecuteController.scala:12:7, :178:35, :844:52]
wire [3:0] _GEN_67 = {{io_srams_read_3_resp_bits_fromDMA_0}, {io_srams_read_2_resp_bits_fromDMA_0}, {io_srams_read_1_resp_bits_fromDMA_0}, {io_srams_read_0_resp_bits_fromDMA_0}}; // @[ExecuteController.scala:12:7, :846:50]
wire _io_srams_read_resp_ready_T = ~_GEN_67[_mesh_cntl_signals_q_io_deq_bits_a_bank]; // @[ExecuteController.scala:178:35, :846:50]
wire _T_146 = _mesh_cntl_signals_q_io_deq_bits_b_fire & _mesh_cntl_signals_q_io_deq_ready_T_6 & ~_mesh_cntl_signals_q_io_deq_bits_b_garbage & ~_mesh_cntl_signals_q_io_deq_bits_accumulate_zeros & (|_mesh_cntl_signals_q_io_deq_bits_b_unpadded_cols); // @[Decoupled.scala:51:35]
wire _io_acc_read_resp_ready_T_1 = ~(_mesh_cntl_signals_q_io_deq_bits_b_bank_acc ? io_acc_read_resp_1_bits_fromDMA_0 : io_acc_read_resp_0_bits_fromDMA_0); // @[ExecuteController.scala:12:7, :178:35, :852:52]
wire _io_srams_read_resp_ready_T_1 = ~_GEN_67[_mesh_cntl_signals_q_io_deq_bits_b_bank]; // @[ExecuteController.scala:178:35, :846:50, :854:50]
wire _T_154 = _mesh_cntl_signals_q_io_deq_bits_d_fire & _mesh_cntl_signals_q_io_deq_ready_T_12 & ~_mesh_cntl_signals_q_io_deq_bits_d_garbage & ~_mesh_cntl_signals_q_io_deq_bits_preload_zeros & (|_mesh_cntl_signals_q_io_deq_bits_d_unpadded_cols); // @[Decoupled.scala:51:35]
wire _io_acc_read_resp_ready_T_2 = ~(_mesh_cntl_signals_q_io_deq_bits_d_bank_acc ? io_acc_read_resp_1_bits_fromDMA_0 : io_acc_read_resp_0_bits_fromDMA_0); // @[ExecuteController.scala:12:7, :178:35, :860:52]
wire _io_srams_read_resp_ready_T_2 = ~_GEN_67[_mesh_cntl_signals_q_io_deq_bits_d_bank]; // @[ExecuteController.scala:178:35, :846:50, :862:50]
assign io_srams_read_0_resp_ready_0 = _mesh_io_req_valid_T_1 & (~_T_154 | _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc | (|_mesh_cntl_signals_q_io_deq_bits_d_bank) ? (~_T_146 | _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc | (|_mesh_cntl_signals_q_io_deq_bits_b_bank) ? _T_138 & ~_mesh_cntl_signals_q_io_deq_bits_a_read_from_acc & _mesh_cntl_signals_q_io_deq_bits_a_bank == 2'h0 & _io_srams_read_resp_ready_T : _io_srams_read_resp_ready_T_1) : _io_srams_read_resp_ready_T_2); // @[Decoupled.scala:51:35]
assign io_srams_read_1_resp_ready_0 = _mesh_io_req_valid_T_1 & (~_T_154 | _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_d_bank != 2'h1 ? (~_T_146 | _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_b_bank != 2'h1 ? _T_138 & ~_mesh_cntl_signals_q_io_deq_bits_a_read_from_acc & _mesh_cntl_signals_q_io_deq_bits_a_bank == 2'h1 & _io_srams_read_resp_ready_T : _io_srams_read_resp_ready_T_1) : _io_srams_read_resp_ready_T_2); // @[Decoupled.scala:51:35]
assign io_srams_read_2_resp_ready_0 = _mesh_io_req_valid_T_1 & (~_T_154 | _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_d_bank != 2'h2 ? (~_T_146 | _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_b_bank != 2'h2 ? _T_138 & ~_mesh_cntl_signals_q_io_deq_bits_a_read_from_acc & _mesh_cntl_signals_q_io_deq_bits_a_bank == 2'h2 & _io_srams_read_resp_ready_T : _io_srams_read_resp_ready_T_1) : _io_srams_read_resp_ready_T_2); // @[Decoupled.scala:51:35]
assign io_srams_read_3_resp_ready_0 = _mesh_io_req_valid_T_1 & (~_T_154 | _mesh_cntl_signals_q_io_deq_bits_d_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_d_bank != 2'h3 ? (~_T_146 | _mesh_cntl_signals_q_io_deq_bits_b_read_from_acc | _mesh_cntl_signals_q_io_deq_bits_b_bank != 2'h3 ? _T_138 & ~_mesh_cntl_signals_q_io_deq_bits_a_read_from_acc & (&_mesh_cntl_signals_q_io_deq_bits_a_bank) & _io_srams_read_resp_ready_T : _io_srams_read_resp_ready_T_1) : _io_srams_read_resp_ready_T_2); // @[Decoupled.scala:51:35]
wire _mesh_io_a_valid_T = _mesh_cntl_signals_q_io_deq_bits_a_fire & dataA_valid; // @[ExecuteController.scala:178:35, :816:68, :875:36]
assign mesh_io_a_valid = _mesh_cntl_signals_q_io_deq_valid & _mesh_io_a_valid_T; // @[ExecuteController.scala:178:35, :189:19, :873:21, :875:{21,36}]
wire _mesh_io_b_valid_T = _mesh_cntl_signals_q_io_deq_bits_b_fire & dataB_valid; // @[ExecuteController.scala:178:35, :818:68, :876:36]
assign mesh_io_b_valid = _mesh_cntl_signals_q_io_deq_valid & _mesh_io_b_valid_T; // @[ExecuteController.scala:178:35, :190:19, :873:21, :876:{21,36}]
wire _mesh_io_d_valid_T = _mesh_cntl_signals_q_io_deq_bits_d_fire & dataD_valid; // @[ExecuteController.scala:178:35, :822:68, :877:36]
assign mesh_io_d_valid = _mesh_cntl_signals_q_io_deq_valid & _mesh_io_d_valid_T; // @[ExecuteController.scala:178:35, :191:19, :873:21, :877:{21,36}]
wire [15:0] _GEN_68 = {dataA_1, dataA_0}; // @[ExecuteController.scala:836:22, :879:37]
wire [15:0] lo_lo_lo; // @[ExecuteController.scala:879:37]
assign lo_lo_lo = _GEN_68; // @[ExecuteController.scala:879:37]
wire [15:0] lo_lo_lo_3; // @[ExecuteController.scala:891:66]
assign lo_lo_lo_3 = _GEN_68; // @[ExecuteController.scala:879:37, :891:66]
wire [15:0] lo_lo_lo_5; // @[ExecuteController.scala:896:71]
assign lo_lo_lo_5 = _GEN_68; // @[ExecuteController.scala:879:37, :896:71]
wire [15:0] _GEN_69 = {dataA_3, dataA_2}; // @[ExecuteController.scala:836:22, :879:37]
wire [15:0] lo_lo_hi; // @[ExecuteController.scala:879:37]
assign lo_lo_hi = _GEN_69; // @[ExecuteController.scala:879:37]
wire [15:0] lo_lo_hi_3; // @[ExecuteController.scala:891:66]
assign lo_lo_hi_3 = _GEN_69; // @[ExecuteController.scala:879:37, :891:66]
wire [15:0] lo_lo_hi_5; // @[ExecuteController.scala:896:71]
assign lo_lo_hi_5 = _GEN_69; // @[ExecuteController.scala:879:37, :896:71]
wire [31:0] lo_lo = {lo_lo_hi, lo_lo_lo}; // @[ExecuteController.scala:879:37]
wire [15:0] _GEN_70 = {dataA_5, dataA_4}; // @[ExecuteController.scala:836:22, :879:37]
wire [15:0] lo_hi_lo; // @[ExecuteController.scala:879:37]
assign lo_hi_lo = _GEN_70; // @[ExecuteController.scala:879:37]
wire [15:0] lo_hi_lo_3; // @[ExecuteController.scala:891:66]
assign lo_hi_lo_3 = _GEN_70; // @[ExecuteController.scala:879:37, :891:66]
wire [15:0] lo_hi_lo_5; // @[ExecuteController.scala:896:71]
assign lo_hi_lo_5 = _GEN_70; // @[ExecuteController.scala:879:37, :896:71]
wire [15:0] _GEN_71 = {dataA_7, dataA_6}; // @[ExecuteController.scala:836:22, :879:37]
wire [15:0] lo_hi_hi; // @[ExecuteController.scala:879:37]
assign lo_hi_hi = _GEN_71; // @[ExecuteController.scala:879:37]
wire [15:0] lo_hi_hi_3; // @[ExecuteController.scala:891:66]
assign lo_hi_hi_3 = _GEN_71; // @[ExecuteController.scala:879:37, :891:66]
wire [15:0] lo_hi_hi_5; // @[ExecuteController.scala:896:71]
assign lo_hi_hi_5 = _GEN_71; // @[ExecuteController.scala:879:37, :896:71]
wire [31:0] lo_hi = {lo_hi_hi, lo_hi_lo}; // @[ExecuteController.scala:879:37]
wire [63:0] lo = {lo_hi, lo_lo}; // @[ExecuteController.scala:879:37]
wire [15:0] _GEN_72 = {dataA_9, dataA_8}; // @[ExecuteController.scala:836:22, :879:37]
wire [15:0] hi_lo_lo; // @[ExecuteController.scala:879:37]
assign hi_lo_lo = _GEN_72; // @[ExecuteController.scala:879:37]
wire [15:0] hi_lo_lo_3; // @[ExecuteController.scala:891:66]
assign hi_lo_lo_3 = _GEN_72; // @[ExecuteController.scala:879:37, :891:66]
wire [15:0] hi_lo_lo_5; // @[ExecuteController.scala:896:71]
assign hi_lo_lo_5 = _GEN_72; // @[ExecuteController.scala:879:37, :896:71]
wire [15:0] _GEN_73 = {dataA_11, dataA_10}; // @[ExecuteController.scala:836:22, :879:37]
wire [15:0] hi_lo_hi; // @[ExecuteController.scala:879:37]
assign hi_lo_hi = _GEN_73; // @[ExecuteController.scala:879:37]
wire [15:0] hi_lo_hi_3; // @[ExecuteController.scala:891:66]
assign hi_lo_hi_3 = _GEN_73; // @[ExecuteController.scala:879:37, :891:66]
wire [15:0] hi_lo_hi_5; // @[ExecuteController.scala:896:71]
assign hi_lo_hi_5 = _GEN_73; // @[ExecuteController.scala:879:37, :896:71]
wire [31:0] hi_lo = {hi_lo_hi, hi_lo_lo}; // @[ExecuteController.scala:879:37]
wire [15:0] _GEN_74 = {dataA_13, dataA_12}; // @[ExecuteController.scala:836:22, :879:37]
wire [15:0] hi_hi_lo; // @[ExecuteController.scala:879:37]
assign hi_hi_lo = _GEN_74; // @[ExecuteController.scala:879:37]
wire [15:0] hi_hi_lo_3; // @[ExecuteController.scala:891:66]
assign hi_hi_lo_3 = _GEN_74; // @[ExecuteController.scala:879:37, :891:66]
wire [15:0] hi_hi_lo_5; // @[ExecuteController.scala:896:71]
assign hi_hi_lo_5 = _GEN_74; // @[ExecuteController.scala:879:37, :896:71]
wire [15:0] _GEN_75 = {dataA_15, dataA_14}; // @[ExecuteController.scala:836:22, :879:37]
wire [15:0] hi_hi_hi; // @[ExecuteController.scala:879:37]
assign hi_hi_hi = _GEN_75; // @[ExecuteController.scala:879:37]
wire [15:0] hi_hi_hi_3; // @[ExecuteController.scala:891:66]
assign hi_hi_hi_3 = _GEN_75; // @[ExecuteController.scala:879:37, :891:66]
wire [15:0] hi_hi_hi_5; // @[ExecuteController.scala:896:71]
assign hi_hi_hi_5 = _GEN_75; // @[ExecuteController.scala:879:37, :896:71]
wire [31:0] hi_hi = {hi_hi_hi, hi_hi_lo}; // @[ExecuteController.scala:879:37]
wire [63:0] hi = {hi_hi, hi_lo}; // @[ExecuteController.scala:879:37]
wire [15:0] _GEN_76 = {dataB_1, dataB_0}; // @[ExecuteController.scala:837:22, :880:37]
wire [15:0] lo_lo_lo_1; // @[ExecuteController.scala:880:37]
assign lo_lo_lo_1 = _GEN_76; // @[ExecuteController.scala:880:37]
wire [15:0] lo_lo_lo_4; // @[ExecuteController.scala:892:66]
assign lo_lo_lo_4 = _GEN_76; // @[ExecuteController.scala:880:37, :892:66]
wire [15:0] lo_lo_lo_6; // @[ExecuteController.scala:897:71]
assign lo_lo_lo_6 = _GEN_76; // @[ExecuteController.scala:880:37, :897:71]
wire [15:0] _GEN_77 = {dataB_3, dataB_2}; // @[ExecuteController.scala:837:22, :880:37]
wire [15:0] lo_lo_hi_1; // @[ExecuteController.scala:880:37]
assign lo_lo_hi_1 = _GEN_77; // @[ExecuteController.scala:880:37]
wire [15:0] lo_lo_hi_4; // @[ExecuteController.scala:892:66]
assign lo_lo_hi_4 = _GEN_77; // @[ExecuteController.scala:880:37, :892:66]
wire [15:0] lo_lo_hi_6; // @[ExecuteController.scala:897:71]
assign lo_lo_hi_6 = _GEN_77; // @[ExecuteController.scala:880:37, :897:71]
wire [31:0] lo_lo_1 = {lo_lo_hi_1, lo_lo_lo_1}; // @[ExecuteController.scala:880:37]
wire [15:0] _GEN_78 = {dataB_5, dataB_4}; // @[ExecuteController.scala:837:22, :880:37]
wire [15:0] lo_hi_lo_1; // @[ExecuteController.scala:880:37]
assign lo_hi_lo_1 = _GEN_78; // @[ExecuteController.scala:880:37]
wire [15:0] lo_hi_lo_4; // @[ExecuteController.scala:892:66]
assign lo_hi_lo_4 = _GEN_78; // @[ExecuteController.scala:880:37, :892:66]
wire [15:0] lo_hi_lo_6; // @[ExecuteController.scala:897:71]
assign lo_hi_lo_6 = _GEN_78; // @[ExecuteController.scala:880:37, :897:71]
wire [15:0] _GEN_79 = {dataB_7, dataB_6}; // @[ExecuteController.scala:837:22, :880:37]
wire [15:0] lo_hi_hi_1; // @[ExecuteController.scala:880:37]
assign lo_hi_hi_1 = _GEN_79; // @[ExecuteController.scala:880:37]
wire [15:0] lo_hi_hi_4; // @[ExecuteController.scala:892:66]
assign lo_hi_hi_4 = _GEN_79; // @[ExecuteController.scala:880:37, :892:66]
wire [15:0] lo_hi_hi_6; // @[ExecuteController.scala:897:71]
assign lo_hi_hi_6 = _GEN_79; // @[ExecuteController.scala:880:37, :897:71]
wire [31:0] lo_hi_1 = {lo_hi_hi_1, lo_hi_lo_1}; // @[ExecuteController.scala:880:37]
wire [63:0] lo_1 = {lo_hi_1, lo_lo_1}; // @[ExecuteController.scala:880:37]
wire [15:0] _GEN_80 = {dataB_9, dataB_8}; // @[ExecuteController.scala:837:22, :880:37]
wire [15:0] hi_lo_lo_1; // @[ExecuteController.scala:880:37]
assign hi_lo_lo_1 = _GEN_80; // @[ExecuteController.scala:880:37]
wire [15:0] hi_lo_lo_4; // @[ExecuteController.scala:892:66]
assign hi_lo_lo_4 = _GEN_80; // @[ExecuteController.scala:880:37, :892:66]
wire [15:0] hi_lo_lo_6; // @[ExecuteController.scala:897:71]
assign hi_lo_lo_6 = _GEN_80; // @[ExecuteController.scala:880:37, :897:71]
wire [15:0] _GEN_81 = {dataB_11, dataB_10}; // @[ExecuteController.scala:837:22, :880:37]
wire [15:0] hi_lo_hi_1; // @[ExecuteController.scala:880:37]
assign hi_lo_hi_1 = _GEN_81; // @[ExecuteController.scala:880:37]
wire [15:0] hi_lo_hi_4; // @[ExecuteController.scala:892:66]
assign hi_lo_hi_4 = _GEN_81; // @[ExecuteController.scala:880:37, :892:66]
wire [15:0] hi_lo_hi_6; // @[ExecuteController.scala:897:71]
assign hi_lo_hi_6 = _GEN_81; // @[ExecuteController.scala:880:37, :897:71]
wire [31:0] hi_lo_1 = {hi_lo_hi_1, hi_lo_lo_1}; // @[ExecuteController.scala:880:37]
wire [15:0] _GEN_82 = {dataB_13, dataB_12}; // @[ExecuteController.scala:837:22, :880:37]
wire [15:0] hi_hi_lo_1; // @[ExecuteController.scala:880:37]
assign hi_hi_lo_1 = _GEN_82; // @[ExecuteController.scala:880:37]
wire [15:0] hi_hi_lo_4; // @[ExecuteController.scala:892:66]
assign hi_hi_lo_4 = _GEN_82; // @[ExecuteController.scala:880:37, :892:66]
wire [15:0] hi_hi_lo_6; // @[ExecuteController.scala:897:71]
assign hi_hi_lo_6 = _GEN_82; // @[ExecuteController.scala:880:37, :897:71]
wire [15:0] _GEN_83 = {dataB_15, dataB_14}; // @[ExecuteController.scala:837:22, :880:37]
wire [15:0] hi_hi_hi_1; // @[ExecuteController.scala:880:37]
assign hi_hi_hi_1 = _GEN_83; // @[ExecuteController.scala:880:37]
wire [15:0] hi_hi_hi_4; // @[ExecuteController.scala:892:66]
assign hi_hi_hi_4 = _GEN_83; // @[ExecuteController.scala:880:37, :892:66]
wire [15:0] hi_hi_hi_6; // @[ExecuteController.scala:897:71]
assign hi_hi_hi_6 = _GEN_83; // @[ExecuteController.scala:880:37, :897:71]
wire [31:0] hi_hi_1 = {hi_hi_hi_1, hi_hi_lo_1}; // @[ExecuteController.scala:880:37]
wire [63:0] hi_1 = {hi_hi_1, hi_lo_1}; // @[ExecuteController.scala:880:37]
wire [15:0] lo_lo_lo_2 = {dataD_1, dataD_0}; // @[ExecuteController.scala:838:22, :881:37]
wire [15:0] lo_lo_hi_2 = {dataD_3, dataD_2}; // @[ExecuteController.scala:838:22, :881:37]
wire [31:0] lo_lo_2 = {lo_lo_hi_2, lo_lo_lo_2}; // @[ExecuteController.scala:881:37]
wire [15:0] lo_hi_lo_2 = {dataD_5, dataD_4}; // @[ExecuteController.scala:838:22, :881:37]
wire [15:0] lo_hi_hi_2 = {dataD_7, dataD_6}; // @[ExecuteController.scala:838:22, :881:37]
wire [31:0] lo_hi_2 = {lo_hi_hi_2, lo_hi_lo_2}; // @[ExecuteController.scala:881:37]
wire [63:0] lo_2 = {lo_hi_2, lo_lo_2}; // @[ExecuteController.scala:881:37]
wire [15:0] hi_lo_lo_2 = {dataD_9, dataD_8}; // @[ExecuteController.scala:838:22, :881:37]
wire [15:0] hi_lo_hi_2 = {dataD_11, dataD_10}; // @[ExecuteController.scala:838:22, :881:37]
wire [31:0] hi_lo_2 = {hi_lo_hi_2, hi_lo_lo_2}; // @[ExecuteController.scala:881:37]
wire [15:0] hi_hi_lo_2 = {dataD_13, dataD_12}; // @[ExecuteController.scala:838:22, :881:37]
wire [15:0] hi_hi_hi_2 = {dataD_15, dataD_14}; // @[ExecuteController.scala:838:22, :881:37]
wire [31:0] hi_hi_2 = {hi_hi_hi_2, hi_hi_lo_2}; // @[ExecuteController.scala:881:37]
wire [63:0] hi_2 = {hi_hi_2, hi_lo_2}; // @[ExecuteController.scala:881:37]
wire _mesh_io_req_valid_T_2 = _mesh_cntl_signals_q_io_deq_bits_a_fire | _mesh_cntl_signals_q_io_deq_bits_b_fire; // @[ExecuteController.scala:178:35, :883:74]
wire _mesh_io_req_valid_T_3 = _mesh_io_req_valid_T_2 | _mesh_cntl_signals_q_io_deq_bits_d_fire; // @[ExecuteController.scala:178:35, :883:{74,89}]
wire _mesh_io_req_valid_T_4 = _mesh_io_req_valid_T_1 & _mesh_io_req_valid_T_3; // @[Decoupled.scala:51:35]
wire mesh_io_req_valid = _mesh_cntl_signals_q_io_deq_valid ? _mesh_io_req_valid_T_4 : _mesh_io_req_valid_T; // @[ExecuteController.scala:178:35, :192:{21,38}, :873:21, :883:{23,58}]
wire _T_302 = _mesh_cntl_signals_q_io_deq_valid & _mesh_cntl_signals_q_io_deq_bits_perform_single_preload; // @[ExecuteController.scala:178:35, :890:20]
wire [31:0] lo_lo_3 = {lo_lo_hi_3, lo_lo_lo_3}; // @[ExecuteController.scala:891:66]
wire [31:0] lo_hi_3 = {lo_hi_hi_3, lo_hi_lo_3}; // @[ExecuteController.scala:891:66]
wire [63:0] lo_3 = {lo_hi_3, lo_lo_3}; // @[ExecuteController.scala:891:66]
wire [31:0] hi_lo_3 = {hi_lo_hi_3, hi_lo_lo_3}; // @[ExecuteController.scala:891:66]
wire [31:0] hi_hi_3 = {hi_hi_hi_3, hi_hi_lo_3}; // @[ExecuteController.scala:891:66]
wire [63:0] hi_3 = {hi_hi_3, hi_lo_3}; // @[ExecuteController.scala:891:66]
wire [127:0] _T_320 = a_should_be_fed_into_transposer ? {hi_3, lo_3} : 128'h0; // @[ExecuteController.scala:123:44, :891:{26,66}]
wire [31:0] lo_lo_4 = {lo_lo_hi_4, lo_lo_lo_4}; // @[ExecuteController.scala:892:66]
wire [31:0] lo_hi_4 = {lo_hi_hi_4, lo_hi_lo_4}; // @[ExecuteController.scala:892:66]
wire [63:0] lo_4 = {lo_hi_4, lo_lo_4}; // @[ExecuteController.scala:892:66]
wire [31:0] hi_lo_4 = {hi_lo_hi_4, hi_lo_lo_4}; // @[ExecuteController.scala:892:66]
wire [31:0] hi_hi_4 = {hi_hi_hi_4, hi_hi_lo_4}; // @[ExecuteController.scala:892:66]
wire [63:0] hi_4 = {hi_hi_4, hi_lo_4}; // @[ExecuteController.scala:892:66]
wire _T_403 = _mesh_cntl_signals_q_io_deq_valid & _mesh_cntl_signals_q_io_deq_bits_perform_single_mul; // @[ExecuteController.scala:178:35, :895:20]
wire [31:0] lo_lo_5 = {lo_lo_hi_5, lo_lo_lo_5}; // @[ExecuteController.scala:896:71]
wire [31:0] lo_hi_5 = {lo_hi_hi_5, lo_hi_lo_5}; // @[ExecuteController.scala:896:71]
wire [63:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[ExecuteController.scala:896:71]
wire [31:0] hi_lo_5 = {hi_lo_hi_5, hi_lo_lo_5}; // @[ExecuteController.scala:896:71]
wire [31:0] hi_hi_5 = {hi_hi_hi_5, hi_hi_lo_5}; // @[ExecuteController.scala:896:71]
wire [63:0] hi_5 = {hi_hi_5, hi_lo_5}; // @[ExecuteController.scala:896:71]
wire [127:0] _T_421 = a_should_be_fed_into_transposer ? 128'h0 : {hi_5, lo_5}; // @[ExecuteController.scala:123:44, :896:{26,71}]
wire [31:0] lo_lo_6 = {lo_lo_hi_6, lo_lo_lo_6}; // @[ExecuteController.scala:897:71]
wire [31:0] lo_hi_6 = {lo_hi_hi_6, lo_hi_lo_6}; // @[ExecuteController.scala:897:71]
wire [63:0] lo_6 = {lo_hi_6, lo_lo_6}; // @[ExecuteController.scala:897:71]
wire [31:0] hi_lo_6 = {hi_lo_hi_6, hi_lo_lo_6}; // @[ExecuteController.scala:897:71]
wire [31:0] hi_hi_6 = {hi_hi_hi_6, hi_hi_lo_6}; // @[ExecuteController.scala:897:71]
wire [63:0] hi_6 = {hi_hi_6, hi_lo_6}; // @[ExecuteController.scala:897:71]
reg [3:0] output_counter; // @[ExecuteController.scala:903:31]
wire [19:0] _GEN_84 = {16'h0, output_counter} * {4'h0, c_addr_stride}; // @[ExecuteController.scala:249:26, :903:31, :907:106]
wire [19:0] _w_address_T_1; // @[ExecuteController.scala:907:106]
assign _w_address_T_1 = _GEN_84; // @[ExecuteController.scala:907:106]
wire [19:0] _w_address_T_4; // @[ExecuteController.scala:908:78]
assign _w_address_T_4 = _GEN_84; // @[ExecuteController.scala:907:106, :908:78]
wire w_address_is_acc_addr = w_address_result_is_acc_addr; // @[LocalAddr.scala:50:26]
assign w_address_accumulate = w_address_result_accumulate; // @[LocalAddr.scala:50:26]
wire w_address_read_full_acc_row = w_address_result_read_full_acc_row; // @[LocalAddr.scala:50:26]
wire [2:0] w_address_norm_cmd = w_address_result_norm_cmd; // @[LocalAddr.scala:50:26]
wire [10:0] w_address_garbage = w_address_result_garbage; // @[LocalAddr.scala:50:26]
wire w_address_garbage_bit = w_address_result_garbage_bit; // @[LocalAddr.scala:50:26]
wire [13:0] w_address_result_data; // @[LocalAddr.scala:50:26]
wire [13:0] w_address_data = w_address_result_data; // @[LocalAddr.scala:50:26]
wire [20:0] _GEN_85 = {7'h0, _mesh_io_resp_bits_tag_addr_data}; // @[LocalAddr.scala:51:25]
wire [20:0] _w_address_result_data_T = _GEN_85 + {1'h0, _w_address_T_1}; // @[LocalAddr.scala:51:25]
wire [19:0] _w_address_result_data_T_1 = _w_address_result_data_T[19:0]; // @[LocalAddr.scala:51:25]
assign w_address_result_data = _w_address_result_data_T_1[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}]
wire [5:0] _GEN_86 = {1'h0, _mesh_io_resp_bits_total_rows} - 6'h1; // @[ExecuteController.scala:186:20, :908:55]
wire [5:0] _w_address_T_2; // @[ExecuteController.scala:908:55]
assign _w_address_T_2 = _GEN_86; // @[ExecuteController.scala:908:55]
wire [5:0] _write_this_row_T_2; // @[ExecuteController.scala:920:25]
assign _write_this_row_T_2 = _GEN_86; // @[ExecuteController.scala:908:55, :920:25]
wire [5:0] _output_counter_max_T; // @[Util.scala:18:28]
assign _output_counter_max_T = _GEN_86; // @[Util.scala:18:28]
wire [4:0] _w_address_T_3 = _w_address_T_2[4:0]; // @[ExecuteController.scala:908:55]
wire [20:0] _w_address_T_5 = {16'h0, _w_address_T_3} - {1'h0, _w_address_T_4}; // @[ExecuteController.scala:907:106, :908:{55,61,78}]
wire [19:0] _w_address_T_6 = _w_address_T_5[19:0]; // @[ExecuteController.scala:908:61]
wire w_address_result_1_is_acc_addr; // @[LocalAddr.scala:50:26]
wire w_address_result_1_accumulate; // @[LocalAddr.scala:50:26]
wire w_address_result_1_read_full_acc_row; // @[LocalAddr.scala:50:26]
wire [2:0] w_address_result_1_norm_cmd; // @[LocalAddr.scala:50:26]
wire [10:0] w_address_result_1_garbage; // @[LocalAddr.scala:50:26]
wire w_address_result_1_garbage_bit; // @[LocalAddr.scala:50:26]
wire [13:0] w_address_result_1_data; // @[LocalAddr.scala:50:26]
wire [20:0] _w_address_result_data_T_2 = _GEN_85 + {1'h0, _w_address_T_6}; // @[LocalAddr.scala:51:25]
wire [19:0] _w_address_result_data_T_3 = _w_address_result_data_T_2[19:0]; // @[LocalAddr.scala:51:25]
assign w_address_result_1_data = _w_address_result_data_T_3[13:0]; // @[LocalAddr.scala:50:26, :51:{17,25}]
assign io_acc_write_0_bits_acc_0 = w_address_accumulate; // @[ExecuteController.scala:12:7, :907:22]
assign io_acc_write_1_bits_acc_0 = w_address_accumulate; // @[ExecuteController.scala:12:7, :907:22]
wire _w_bank_T = w_address_data[9]; // @[LocalAddr.scala:35:82]
wire [1:0] _w_bank_T_1 = w_address_data[13:12]; // @[LocalAddr.scala:33:79]
wire [1:0] w_bank = w_address_is_acc_addr ? {1'h0, _w_bank_T} : _w_bank_T_1; // @[LocalAddr.scala:33:79, :35:82]
wire [8:0] _w_row_T = w_address_data[8:0]; // @[LocalAddr.scala:36:37]
wire [11:0] _w_row_T_1 = w_address_data[11:0]; // @[LocalAddr.scala:34:36]
wire [11:0] w_row = w_address_is_acc_addr ? {3'h0, _w_row_T} : _w_row_T_1; // @[LocalAddr.scala:34:36, :36:37]
wire _is_garbage_addr_T = _mesh_io_resp_bits_tag_addr_is_acc_addr & _mesh_io_resp_bits_tag_addr_accumulate; // @[LocalAddr.scala:43:48]
wire _is_garbage_addr_T_1 = _is_garbage_addr_T & _mesh_io_resp_bits_tag_addr_read_full_acc_row; // @[LocalAddr.scala:43:{48,62}]
wire _is_garbage_addr_T_2 = &_mesh_io_resp_bits_tag_addr_data; // @[LocalAddr.scala:43:91]
wire _is_garbage_addr_T_3 = _is_garbage_addr_T_1 & _is_garbage_addr_T_2; // @[LocalAddr.scala:43:{62,83,91}]
wire _is_garbage_addr_T_4; // @[LocalAddr.scala:44:48]
wire is_garbage_addr = _is_garbage_addr_T_3 & _is_garbage_addr_T_4; // @[LocalAddr.scala:43:{83,96}, :44:48]
wire [4:0] _GEN_87 = {1'h0, output_counter}; // @[ExecuteController.scala:903:31, :919:82]
wire _write_this_row_T_1 = _GEN_87 < _mesh_io_resp_bits_tag_rows; // @[ExecuteController.scala:186:20, :919:82]
wire write_this_row = _write_this_row_T_1; // @[ExecuteController.scala:919:{27,82}]
wire [4:0] _write_this_row_T_3 = _write_this_row_T_2[4:0]; // @[ExecuteController.scala:920:25]
wire [5:0] _GEN_88 = {2'h0, output_counter}; // @[ExecuteController.scala:903:31, :920:31]
wire [5:0] _write_this_row_T_4 = {1'h0, _write_this_row_T_3} - _GEN_88; // @[ExecuteController.scala:920:{25,31}]
wire [4:0] _write_this_row_T_5 = _write_this_row_T_4[4:0]; // @[ExecuteController.scala:920:31]
wire _write_this_row_T_6 = _write_this_row_T_5 < _mesh_io_resp_bits_tag_rows; // @[ExecuteController.scala:186:20, :920:{31,48}]
assign w_mask_0 = |_mesh_io_resp_bits_tag_cols; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_0_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_1_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_2_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_3_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_0_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_1_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_2_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_3_0 = w_mask_0; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_1 = |(_mesh_io_resp_bits_tag_cols[4:1]); // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_4_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_5_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_6_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_7_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_4_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_5_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_6_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_7_0 = w_mask_1; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_2 = _mesh_io_resp_bits_tag_cols > 5'h2; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_8_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_9_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_10_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_11_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_8_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_9_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_10_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_11_0 = w_mask_2; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_3 = |(_mesh_io_resp_bits_tag_cols[4:2]); // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_12_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_13_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_14_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_15_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_12_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_13_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_14_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_15_0 = w_mask_3; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_4 = _mesh_io_resp_bits_tag_cols > 5'h4; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_16_0 = w_mask_4; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_17_0 = w_mask_4; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_18_0 = w_mask_4; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_19_0 = w_mask_4; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_16_0 = w_mask_4; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_17_0 = w_mask_4; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_18_0 = w_mask_4; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_19_0 = w_mask_4; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_5 = _mesh_io_resp_bits_tag_cols > 5'h5; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_20_0 = w_mask_5; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_21_0 = w_mask_5; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_22_0 = w_mask_5; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_23_0 = w_mask_5; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_20_0 = w_mask_5; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_21_0 = w_mask_5; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_22_0 = w_mask_5; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_23_0 = w_mask_5; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_6 = _mesh_io_resp_bits_tag_cols > 5'h6; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_24_0 = w_mask_6; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_25_0 = w_mask_6; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_26_0 = w_mask_6; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_27_0 = w_mask_6; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_24_0 = w_mask_6; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_25_0 = w_mask_6; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_26_0 = w_mask_6; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_27_0 = w_mask_6; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_7 = |(_mesh_io_resp_bits_tag_cols[4:3]); // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_28_0 = w_mask_7; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_29_0 = w_mask_7; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_30_0 = w_mask_7; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_31_0 = w_mask_7; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_28_0 = w_mask_7; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_29_0 = w_mask_7; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_30_0 = w_mask_7; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_31_0 = w_mask_7; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_8 = _mesh_io_resp_bits_tag_cols > 5'h8; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_32_0 = w_mask_8; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_33_0 = w_mask_8; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_34_0 = w_mask_8; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_35_0 = w_mask_8; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_32_0 = w_mask_8; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_33_0 = w_mask_8; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_34_0 = w_mask_8; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_35_0 = w_mask_8; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_9 = _mesh_io_resp_bits_tag_cols > 5'h9; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_36_0 = w_mask_9; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_37_0 = w_mask_9; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_38_0 = w_mask_9; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_39_0 = w_mask_9; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_36_0 = w_mask_9; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_37_0 = w_mask_9; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_38_0 = w_mask_9; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_39_0 = w_mask_9; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_10 = _mesh_io_resp_bits_tag_cols > 5'hA; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_40_0 = w_mask_10; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_41_0 = w_mask_10; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_42_0 = w_mask_10; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_43_0 = w_mask_10; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_40_0 = w_mask_10; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_41_0 = w_mask_10; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_42_0 = w_mask_10; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_43_0 = w_mask_10; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_11 = _mesh_io_resp_bits_tag_cols > 5'hB; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_44_0 = w_mask_11; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_45_0 = w_mask_11; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_46_0 = w_mask_11; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_47_0 = w_mask_11; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_44_0 = w_mask_11; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_45_0 = w_mask_11; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_46_0 = w_mask_11; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_47_0 = w_mask_11; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_12 = _mesh_io_resp_bits_tag_cols > 5'hC; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_48_0 = w_mask_12; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_49_0 = w_mask_12; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_50_0 = w_mask_12; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_51_0 = w_mask_12; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_48_0 = w_mask_12; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_49_0 = w_mask_12; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_50_0 = w_mask_12; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_51_0 = w_mask_12; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_13 = _mesh_io_resp_bits_tag_cols > 5'hD; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_52_0 = w_mask_13; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_53_0 = w_mask_13; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_54_0 = w_mask_13; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_55_0 = w_mask_13; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_52_0 = w_mask_13; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_53_0 = w_mask_13; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_54_0 = w_mask_13; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_55_0 = w_mask_13; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_14 = _mesh_io_resp_bits_tag_cols > 5'hE; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_56_0 = w_mask_14; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_57_0 = w_mask_14; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_58_0 = w_mask_14; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_59_0 = w_mask_14; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_56_0 = w_mask_14; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_57_0 = w_mask_14; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_58_0 = w_mask_14; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_59_0 = w_mask_14; // @[ExecuteController.scala:12:7, :921:45]
assign w_mask_15 = _mesh_io_resp_bits_tag_cols[4]; // @[ExecuteController.scala:186:20, :921:45]
assign io_acc_write_0_bits_mask_60_0 = w_mask_15; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_61_0 = w_mask_15; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_62_0 = w_mask_15; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_0_bits_mask_63_0 = w_mask_15; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_60_0 = w_mask_15; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_61_0 = w_mask_15; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_62_0 = w_mask_15; // @[ExecuteController.scala:12:7, :921:45]
assign io_acc_write_1_bits_mask_63_0 = w_mask_15; // @[ExecuteController.scala:12:7, :921:45]
wire _GEN_89 = $signed(_mesh_io_resp_bits_data_0_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T = _GEN_89; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_80; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_80 = _GEN_89; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_160; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_160 = _GEN_89; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_240; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_240 = _GEN_89; // @[Arithmetic.scala:125:33]
wire _GEN_90 = $signed(_mesh_io_resp_bits_data_0_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_1; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_1 = _GEN_90; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_81; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_81 = _GEN_90; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_161; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_161 = _GEN_90; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_241; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_241 = _GEN_90; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_2 = _activated_wdata_e_clipped_T_1 ? 20'hFFF80 : _mesh_io_resp_bits_data_0_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_3 = _activated_wdata_e_clipped_T ? 20'h7F : _activated_wdata_e_clipped_T_2; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_4 = _activated_wdata_e_clipped_T_3[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped = _activated_wdata_e_clipped_T_4; // @[Arithmetic.scala:125:{81,99}]
wire _GEN_91 = activation == 3'h1; // @[ExecuteController.scala:118:54, :928:21]
wire _activated_wdata_e_act_T; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_3; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_3 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_6; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_6 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_9; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_9 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_12; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_12 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_15; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_15 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_18; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_18 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_21; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_21 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_24; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_24 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_27; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_27 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_30; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_30 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_33; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_33 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_36; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_36 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_39; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_39 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_42; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_42 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_45; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_45 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_48; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_48 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_51; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_51 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_54; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_54 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_57; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_57 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_60; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_60 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_63; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_63 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_66; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_66 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_69; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_69 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_72; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_72 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_75; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_75 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_78; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_78 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_81; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_81 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_84; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_84 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_87; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_87 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_90; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_90 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_93; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_93 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_96; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_96 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_99; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_99 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_102; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_102 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_105; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_105 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_108; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_108 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_111; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_111 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_114; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_114 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_117; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_117 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_120; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_120 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_123; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_123 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_126; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_126 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_129; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_129 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_132; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_132 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_135; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_135 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_138; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_138 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_141; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_141 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_144; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_144 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_147; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_147 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_150; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_150 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_153; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_153 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_156; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_156 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_159; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_159 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_162; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_162 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_165; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_165 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_168; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_168 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_171; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_171 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_174; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_174 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_177; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_177 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_180; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_180 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_183; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_183 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_186; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_186 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_189; // @[ExecuteController.scala:928:21]
assign _activated_wdata_e_act_T_189 = _GEN_91; // @[ExecuteController.scala:928:21]
wire _activated_wdata_e_act_T_1 = $signed(activated_wdata_e_clipped) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_2 = _activated_wdata_e_act_T_1 ? activated_wdata_e_clipped : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act = _activated_wdata_e_act_T ? _activated_wdata_e_act_T_2 : activated_wdata_e_clipped; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_0 = activated_wdata_e_act; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_0_0 = _activated_wdata_WIRE_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_92 = $signed(_mesh_io_resp_bits_data_1_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_5; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_5 = _GEN_92; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_85; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_85 = _GEN_92; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_165; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_165 = _GEN_92; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_245; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_245 = _GEN_92; // @[Arithmetic.scala:125:33]
wire _GEN_93 = $signed(_mesh_io_resp_bits_data_1_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_6; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_6 = _GEN_93; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_86; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_86 = _GEN_93; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_166; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_166 = _GEN_93; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_246; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_246 = _GEN_93; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_7 = _activated_wdata_e_clipped_T_6 ? 20'hFFF80 : _mesh_io_resp_bits_data_1_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_8 = _activated_wdata_e_clipped_T_5 ? 20'h7F : _activated_wdata_e_clipped_T_7; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_9 = _activated_wdata_e_clipped_T_8[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_1 = _activated_wdata_e_clipped_T_9; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_4 = $signed(activated_wdata_e_clipped_1) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_5 = _activated_wdata_e_act_T_4 ? activated_wdata_e_clipped_1 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_1 = _activated_wdata_e_act_T_3 ? _activated_wdata_e_act_T_5 : activated_wdata_e_clipped_1; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_1_0 = activated_wdata_e_act_1; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_0 = _activated_wdata_WIRE_1_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_94 = $signed(_mesh_io_resp_bits_data_2_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_10; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_10 = _GEN_94; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_90; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_90 = _GEN_94; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_170; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_170 = _GEN_94; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_250; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_250 = _GEN_94; // @[Arithmetic.scala:125:33]
wire _GEN_95 = $signed(_mesh_io_resp_bits_data_2_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_11; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_11 = _GEN_95; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_91; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_91 = _GEN_95; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_171; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_171 = _GEN_95; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_251; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_251 = _GEN_95; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_12 = _activated_wdata_e_clipped_T_11 ? 20'hFFF80 : _mesh_io_resp_bits_data_2_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_13 = _activated_wdata_e_clipped_T_10 ? 20'h7F : _activated_wdata_e_clipped_T_12; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_14 = _activated_wdata_e_clipped_T_13[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_2 = _activated_wdata_e_clipped_T_14; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_7 = $signed(activated_wdata_e_clipped_2) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_8 = _activated_wdata_e_act_T_7 ? activated_wdata_e_clipped_2 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_2 = _activated_wdata_e_act_T_6 ? _activated_wdata_e_act_T_8 : activated_wdata_e_clipped_2; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_2_0 = activated_wdata_e_act_2; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_0 = _activated_wdata_WIRE_2_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_96 = $signed(_mesh_io_resp_bits_data_3_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_15; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_15 = _GEN_96; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_95; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_95 = _GEN_96; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_175; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_175 = _GEN_96; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_255; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_255 = _GEN_96; // @[Arithmetic.scala:125:33]
wire _GEN_97 = $signed(_mesh_io_resp_bits_data_3_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_16; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_16 = _GEN_97; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_96; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_96 = _GEN_97; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_176; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_176 = _GEN_97; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_256; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_256 = _GEN_97; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_17 = _activated_wdata_e_clipped_T_16 ? 20'hFFF80 : _mesh_io_resp_bits_data_3_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_18 = _activated_wdata_e_clipped_T_15 ? 20'h7F : _activated_wdata_e_clipped_T_17; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_19 = _activated_wdata_e_clipped_T_18[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_3 = _activated_wdata_e_clipped_T_19; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_10 = $signed(activated_wdata_e_clipped_3) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_11 = _activated_wdata_e_act_T_10 ? activated_wdata_e_clipped_3 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_3 = _activated_wdata_e_act_T_9 ? _activated_wdata_e_act_T_11 : activated_wdata_e_clipped_3; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_3_0 = activated_wdata_e_act_3; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_0 = _activated_wdata_WIRE_3_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_98 = $signed(_mesh_io_resp_bits_data_4_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_20; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_20 = _GEN_98; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_100; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_100 = _GEN_98; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_180; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_180 = _GEN_98; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_260; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_260 = _GEN_98; // @[Arithmetic.scala:125:33]
wire _GEN_99 = $signed(_mesh_io_resp_bits_data_4_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_21; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_21 = _GEN_99; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_101; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_101 = _GEN_99; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_181; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_181 = _GEN_99; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_261; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_261 = _GEN_99; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_22 = _activated_wdata_e_clipped_T_21 ? 20'hFFF80 : _mesh_io_resp_bits_data_4_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_23 = _activated_wdata_e_clipped_T_20 ? 20'h7F : _activated_wdata_e_clipped_T_22; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_24 = _activated_wdata_e_clipped_T_23[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_4 = _activated_wdata_e_clipped_T_24; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_13 = $signed(activated_wdata_e_clipped_4) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_14 = _activated_wdata_e_act_T_13 ? activated_wdata_e_clipped_4 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_4 = _activated_wdata_e_act_T_12 ? _activated_wdata_e_act_T_14 : activated_wdata_e_clipped_4; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_4_0 = activated_wdata_e_act_4; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_4_0 = _activated_wdata_WIRE_4_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_100 = $signed(_mesh_io_resp_bits_data_5_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_25; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_25 = _GEN_100; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_105; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_105 = _GEN_100; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_185; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_185 = _GEN_100; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_265; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_265 = _GEN_100; // @[Arithmetic.scala:125:33]
wire _GEN_101 = $signed(_mesh_io_resp_bits_data_5_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_26; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_26 = _GEN_101; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_106; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_106 = _GEN_101; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_186; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_186 = _GEN_101; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_266; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_266 = _GEN_101; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_27 = _activated_wdata_e_clipped_T_26 ? 20'hFFF80 : _mesh_io_resp_bits_data_5_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_28 = _activated_wdata_e_clipped_T_25 ? 20'h7F : _activated_wdata_e_clipped_T_27; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_29 = _activated_wdata_e_clipped_T_28[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_5 = _activated_wdata_e_clipped_T_29; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_16 = $signed(activated_wdata_e_clipped_5) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_17 = _activated_wdata_e_act_T_16 ? activated_wdata_e_clipped_5 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_5 = _activated_wdata_e_act_T_15 ? _activated_wdata_e_act_T_17 : activated_wdata_e_clipped_5; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_5_0 = activated_wdata_e_act_5; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_5_0 = _activated_wdata_WIRE_5_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_102 = $signed(_mesh_io_resp_bits_data_6_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_30; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_30 = _GEN_102; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_110; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_110 = _GEN_102; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_190; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_190 = _GEN_102; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_270; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_270 = _GEN_102; // @[Arithmetic.scala:125:33]
wire _GEN_103 = $signed(_mesh_io_resp_bits_data_6_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_31; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_31 = _GEN_103; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_111; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_111 = _GEN_103; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_191; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_191 = _GEN_103; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_271; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_271 = _GEN_103; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_32 = _activated_wdata_e_clipped_T_31 ? 20'hFFF80 : _mesh_io_resp_bits_data_6_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_33 = _activated_wdata_e_clipped_T_30 ? 20'h7F : _activated_wdata_e_clipped_T_32; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_34 = _activated_wdata_e_clipped_T_33[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_6 = _activated_wdata_e_clipped_T_34; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_19 = $signed(activated_wdata_e_clipped_6) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_20 = _activated_wdata_e_act_T_19 ? activated_wdata_e_clipped_6 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_6 = _activated_wdata_e_act_T_18 ? _activated_wdata_e_act_T_20 : activated_wdata_e_clipped_6; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_6_0 = activated_wdata_e_act_6; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_6_0 = _activated_wdata_WIRE_6_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_104 = $signed(_mesh_io_resp_bits_data_7_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_35; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_35 = _GEN_104; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_115; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_115 = _GEN_104; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_195; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_195 = _GEN_104; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_275; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_275 = _GEN_104; // @[Arithmetic.scala:125:33]
wire _GEN_105 = $signed(_mesh_io_resp_bits_data_7_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_36; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_36 = _GEN_105; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_116; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_116 = _GEN_105; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_196; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_196 = _GEN_105; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_276; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_276 = _GEN_105; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_37 = _activated_wdata_e_clipped_T_36 ? 20'hFFF80 : _mesh_io_resp_bits_data_7_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_38 = _activated_wdata_e_clipped_T_35 ? 20'h7F : _activated_wdata_e_clipped_T_37; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_39 = _activated_wdata_e_clipped_T_38[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_7 = _activated_wdata_e_clipped_T_39; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_22 = $signed(activated_wdata_e_clipped_7) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_23 = _activated_wdata_e_act_T_22 ? activated_wdata_e_clipped_7 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_7 = _activated_wdata_e_act_T_21 ? _activated_wdata_e_act_T_23 : activated_wdata_e_clipped_7; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_7_0 = activated_wdata_e_act_7; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_7_0 = _activated_wdata_WIRE_7_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_106 = $signed(_mesh_io_resp_bits_data_8_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_40; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_40 = _GEN_106; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_120; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_120 = _GEN_106; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_200; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_200 = _GEN_106; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_280; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_280 = _GEN_106; // @[Arithmetic.scala:125:33]
wire _GEN_107 = $signed(_mesh_io_resp_bits_data_8_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_41; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_41 = _GEN_107; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_121; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_121 = _GEN_107; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_201; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_201 = _GEN_107; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_281; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_281 = _GEN_107; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_42 = _activated_wdata_e_clipped_T_41 ? 20'hFFF80 : _mesh_io_resp_bits_data_8_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_43 = _activated_wdata_e_clipped_T_40 ? 20'h7F : _activated_wdata_e_clipped_T_42; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_44 = _activated_wdata_e_clipped_T_43[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_8 = _activated_wdata_e_clipped_T_44; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_25 = $signed(activated_wdata_e_clipped_8) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_26 = _activated_wdata_e_act_T_25 ? activated_wdata_e_clipped_8 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_8 = _activated_wdata_e_act_T_24 ? _activated_wdata_e_act_T_26 : activated_wdata_e_clipped_8; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_8_0 = activated_wdata_e_act_8; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_8_0 = _activated_wdata_WIRE_8_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_108 = $signed(_mesh_io_resp_bits_data_9_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_45; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_45 = _GEN_108; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_125; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_125 = _GEN_108; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_205; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_205 = _GEN_108; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_285; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_285 = _GEN_108; // @[Arithmetic.scala:125:33]
wire _GEN_109 = $signed(_mesh_io_resp_bits_data_9_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_46; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_46 = _GEN_109; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_126; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_126 = _GEN_109; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_206; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_206 = _GEN_109; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_286; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_286 = _GEN_109; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_47 = _activated_wdata_e_clipped_T_46 ? 20'hFFF80 : _mesh_io_resp_bits_data_9_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_48 = _activated_wdata_e_clipped_T_45 ? 20'h7F : _activated_wdata_e_clipped_T_47; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_49 = _activated_wdata_e_clipped_T_48[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_9 = _activated_wdata_e_clipped_T_49; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_28 = $signed(activated_wdata_e_clipped_9) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_29 = _activated_wdata_e_act_T_28 ? activated_wdata_e_clipped_9 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_9 = _activated_wdata_e_act_T_27 ? _activated_wdata_e_act_T_29 : activated_wdata_e_clipped_9; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_9_0 = activated_wdata_e_act_9; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_9_0 = _activated_wdata_WIRE_9_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_110 = $signed(_mesh_io_resp_bits_data_10_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_50; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_50 = _GEN_110; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_130; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_130 = _GEN_110; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_210; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_210 = _GEN_110; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_290; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_290 = _GEN_110; // @[Arithmetic.scala:125:33]
wire _GEN_111 = $signed(_mesh_io_resp_bits_data_10_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_51; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_51 = _GEN_111; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_131; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_131 = _GEN_111; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_211; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_211 = _GEN_111; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_291; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_291 = _GEN_111; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_52 = _activated_wdata_e_clipped_T_51 ? 20'hFFF80 : _mesh_io_resp_bits_data_10_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_53 = _activated_wdata_e_clipped_T_50 ? 20'h7F : _activated_wdata_e_clipped_T_52; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_54 = _activated_wdata_e_clipped_T_53[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_10 = _activated_wdata_e_clipped_T_54; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_31 = $signed(activated_wdata_e_clipped_10) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_32 = _activated_wdata_e_act_T_31 ? activated_wdata_e_clipped_10 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_10 = _activated_wdata_e_act_T_30 ? _activated_wdata_e_act_T_32 : activated_wdata_e_clipped_10; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_10_0 = activated_wdata_e_act_10; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_10_0 = _activated_wdata_WIRE_10_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_112 = $signed(_mesh_io_resp_bits_data_11_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_55; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_55 = _GEN_112; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_135; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_135 = _GEN_112; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_215; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_215 = _GEN_112; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_295; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_295 = _GEN_112; // @[Arithmetic.scala:125:33]
wire _GEN_113 = $signed(_mesh_io_resp_bits_data_11_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_56; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_56 = _GEN_113; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_136; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_136 = _GEN_113; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_216; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_216 = _GEN_113; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_296; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_296 = _GEN_113; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_57 = _activated_wdata_e_clipped_T_56 ? 20'hFFF80 : _mesh_io_resp_bits_data_11_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_58 = _activated_wdata_e_clipped_T_55 ? 20'h7F : _activated_wdata_e_clipped_T_57; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_59 = _activated_wdata_e_clipped_T_58[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_11 = _activated_wdata_e_clipped_T_59; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_34 = $signed(activated_wdata_e_clipped_11) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_35 = _activated_wdata_e_act_T_34 ? activated_wdata_e_clipped_11 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_11 = _activated_wdata_e_act_T_33 ? _activated_wdata_e_act_T_35 : activated_wdata_e_clipped_11; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_11_0 = activated_wdata_e_act_11; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_11_0 = _activated_wdata_WIRE_11_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_114 = $signed(_mesh_io_resp_bits_data_12_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_60; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_60 = _GEN_114; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_140; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_140 = _GEN_114; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_220; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_220 = _GEN_114; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_300; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_300 = _GEN_114; // @[Arithmetic.scala:125:33]
wire _GEN_115 = $signed(_mesh_io_resp_bits_data_12_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_61; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_61 = _GEN_115; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_141; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_141 = _GEN_115; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_221; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_221 = _GEN_115; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_301; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_301 = _GEN_115; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_62 = _activated_wdata_e_clipped_T_61 ? 20'hFFF80 : _mesh_io_resp_bits_data_12_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_63 = _activated_wdata_e_clipped_T_60 ? 20'h7F : _activated_wdata_e_clipped_T_62; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_64 = _activated_wdata_e_clipped_T_63[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_12 = _activated_wdata_e_clipped_T_64; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_37 = $signed(activated_wdata_e_clipped_12) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_38 = _activated_wdata_e_act_T_37 ? activated_wdata_e_clipped_12 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_12 = _activated_wdata_e_act_T_36 ? _activated_wdata_e_act_T_38 : activated_wdata_e_clipped_12; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_12_0 = activated_wdata_e_act_12; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_12_0 = _activated_wdata_WIRE_12_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_116 = $signed(_mesh_io_resp_bits_data_13_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_65; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_65 = _GEN_116; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_145; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_145 = _GEN_116; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_225; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_225 = _GEN_116; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_305; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_305 = _GEN_116; // @[Arithmetic.scala:125:33]
wire _GEN_117 = $signed(_mesh_io_resp_bits_data_13_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_66; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_66 = _GEN_117; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_146; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_146 = _GEN_117; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_226; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_226 = _GEN_117; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_306; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_306 = _GEN_117; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_67 = _activated_wdata_e_clipped_T_66 ? 20'hFFF80 : _mesh_io_resp_bits_data_13_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_68 = _activated_wdata_e_clipped_T_65 ? 20'h7F : _activated_wdata_e_clipped_T_67; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_69 = _activated_wdata_e_clipped_T_68[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_13 = _activated_wdata_e_clipped_T_69; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_40 = $signed(activated_wdata_e_clipped_13) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_41 = _activated_wdata_e_act_T_40 ? activated_wdata_e_clipped_13 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_13 = _activated_wdata_e_act_T_39 ? _activated_wdata_e_act_T_41 : activated_wdata_e_clipped_13; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_13_0 = activated_wdata_e_act_13; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_13_0 = _activated_wdata_WIRE_13_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_118 = $signed(_mesh_io_resp_bits_data_14_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_70; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_70 = _GEN_118; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_150; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_150 = _GEN_118; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_230; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_230 = _GEN_118; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_310; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_310 = _GEN_118; // @[Arithmetic.scala:125:33]
wire _GEN_119 = $signed(_mesh_io_resp_bits_data_14_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_71; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_71 = _GEN_119; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_151; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_151 = _GEN_119; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_231; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_231 = _GEN_119; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_311; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_311 = _GEN_119; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_72 = _activated_wdata_e_clipped_T_71 ? 20'hFFF80 : _mesh_io_resp_bits_data_14_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_73 = _activated_wdata_e_clipped_T_70 ? 20'h7F : _activated_wdata_e_clipped_T_72; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_74 = _activated_wdata_e_clipped_T_73[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_14 = _activated_wdata_e_clipped_T_74; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_43 = $signed(activated_wdata_e_clipped_14) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_44 = _activated_wdata_e_act_T_43 ? activated_wdata_e_clipped_14 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_14 = _activated_wdata_e_act_T_42 ? _activated_wdata_e_act_T_44 : activated_wdata_e_clipped_14; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_14_0 = activated_wdata_e_act_14; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_14_0 = _activated_wdata_WIRE_14_0; // @[ExecuteController.scala:925:{34,74}]
wire _GEN_120 = $signed(_mesh_io_resp_bits_data_15_0) > 20'sh7F; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_75; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_75 = _GEN_120; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_155; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_155 = _GEN_120; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_235; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_235 = _GEN_120; // @[Arithmetic.scala:125:33]
wire _activated_wdata_e_clipped_T_315; // @[Arithmetic.scala:125:33]
assign _activated_wdata_e_clipped_T_315 = _GEN_120; // @[Arithmetic.scala:125:33]
wire _GEN_121 = $signed(_mesh_io_resp_bits_data_15_0) < -20'sh80; // @[ExecuteController.scala:186:20]
wire _activated_wdata_e_clipped_T_76; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_76 = _GEN_121; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_156; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_156 = _GEN_121; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_236; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_236 = _GEN_121; // @[Arithmetic.scala:125:60]
wire _activated_wdata_e_clipped_T_316; // @[Arithmetic.scala:125:60]
assign _activated_wdata_e_clipped_T_316 = _GEN_121; // @[Arithmetic.scala:125:60]
wire [19:0] _activated_wdata_e_clipped_T_77 = _activated_wdata_e_clipped_T_76 ? 20'hFFF80 : _mesh_io_resp_bits_data_15_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_78 = _activated_wdata_e_clipped_T_75 ? 20'h7F : _activated_wdata_e_clipped_T_77; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_79 = _activated_wdata_e_clipped_T_78[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_15 = _activated_wdata_e_clipped_T_79; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_46 = $signed(activated_wdata_e_clipped_15) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_47 = _activated_wdata_e_act_T_46 ? activated_wdata_e_clipped_15 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_15 = _activated_wdata_e_act_T_45 ? _activated_wdata_e_act_T_47 : activated_wdata_e_clipped_15; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_15_0 = activated_wdata_e_act_15; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_15_0 = _activated_wdata_WIRE_15_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_82 = _activated_wdata_e_clipped_T_81 ? 20'hFFF80 : _mesh_io_resp_bits_data_0_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_83 = _activated_wdata_e_clipped_T_80 ? 20'h7F : _activated_wdata_e_clipped_T_82; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_84 = _activated_wdata_e_clipped_T_83[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_16 = _activated_wdata_e_clipped_T_84; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_49 = $signed(activated_wdata_e_clipped_16) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_50 = _activated_wdata_e_act_T_49 ? activated_wdata_e_clipped_16 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_16 = _activated_wdata_e_act_T_48 ? _activated_wdata_e_act_T_50 : activated_wdata_e_clipped_16; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_16_0 = activated_wdata_e_act_16; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_0_0 = _activated_wdata_WIRE_16_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_87 = _activated_wdata_e_clipped_T_86 ? 20'hFFF80 : _mesh_io_resp_bits_data_1_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_88 = _activated_wdata_e_clipped_T_85 ? 20'h7F : _activated_wdata_e_clipped_T_87; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_89 = _activated_wdata_e_clipped_T_88[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_17 = _activated_wdata_e_clipped_T_89; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_52 = $signed(activated_wdata_e_clipped_17) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_53 = _activated_wdata_e_act_T_52 ? activated_wdata_e_clipped_17 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_17 = _activated_wdata_e_act_T_51 ? _activated_wdata_e_act_T_53 : activated_wdata_e_clipped_17; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_17_0 = activated_wdata_e_act_17; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_1_0 = _activated_wdata_WIRE_17_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_92 = _activated_wdata_e_clipped_T_91 ? 20'hFFF80 : _mesh_io_resp_bits_data_2_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_93 = _activated_wdata_e_clipped_T_90 ? 20'h7F : _activated_wdata_e_clipped_T_92; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_94 = _activated_wdata_e_clipped_T_93[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_18 = _activated_wdata_e_clipped_T_94; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_55 = $signed(activated_wdata_e_clipped_18) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_56 = _activated_wdata_e_act_T_55 ? activated_wdata_e_clipped_18 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_18 = _activated_wdata_e_act_T_54 ? _activated_wdata_e_act_T_56 : activated_wdata_e_clipped_18; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_18_0 = activated_wdata_e_act_18; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_2_0 = _activated_wdata_WIRE_18_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_97 = _activated_wdata_e_clipped_T_96 ? 20'hFFF80 : _mesh_io_resp_bits_data_3_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_98 = _activated_wdata_e_clipped_T_95 ? 20'h7F : _activated_wdata_e_clipped_T_97; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_99 = _activated_wdata_e_clipped_T_98[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_19 = _activated_wdata_e_clipped_T_99; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_58 = $signed(activated_wdata_e_clipped_19) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_59 = _activated_wdata_e_act_T_58 ? activated_wdata_e_clipped_19 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_19 = _activated_wdata_e_act_T_57 ? _activated_wdata_e_act_T_59 : activated_wdata_e_clipped_19; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_19_0 = activated_wdata_e_act_19; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_3_0 = _activated_wdata_WIRE_19_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_102 = _activated_wdata_e_clipped_T_101 ? 20'hFFF80 : _mesh_io_resp_bits_data_4_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_103 = _activated_wdata_e_clipped_T_100 ? 20'h7F : _activated_wdata_e_clipped_T_102; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_104 = _activated_wdata_e_clipped_T_103[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_20 = _activated_wdata_e_clipped_T_104; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_61 = $signed(activated_wdata_e_clipped_20) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_62 = _activated_wdata_e_act_T_61 ? activated_wdata_e_clipped_20 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_20 = _activated_wdata_e_act_T_60 ? _activated_wdata_e_act_T_62 : activated_wdata_e_clipped_20; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_20_0 = activated_wdata_e_act_20; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_4_0 = _activated_wdata_WIRE_20_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_107 = _activated_wdata_e_clipped_T_106 ? 20'hFFF80 : _mesh_io_resp_bits_data_5_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_108 = _activated_wdata_e_clipped_T_105 ? 20'h7F : _activated_wdata_e_clipped_T_107; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_109 = _activated_wdata_e_clipped_T_108[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_21 = _activated_wdata_e_clipped_T_109; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_64 = $signed(activated_wdata_e_clipped_21) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_65 = _activated_wdata_e_act_T_64 ? activated_wdata_e_clipped_21 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_21 = _activated_wdata_e_act_T_63 ? _activated_wdata_e_act_T_65 : activated_wdata_e_clipped_21; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_21_0 = activated_wdata_e_act_21; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_5_0 = _activated_wdata_WIRE_21_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_112 = _activated_wdata_e_clipped_T_111 ? 20'hFFF80 : _mesh_io_resp_bits_data_6_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_113 = _activated_wdata_e_clipped_T_110 ? 20'h7F : _activated_wdata_e_clipped_T_112; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_114 = _activated_wdata_e_clipped_T_113[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_22 = _activated_wdata_e_clipped_T_114; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_67 = $signed(activated_wdata_e_clipped_22) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_68 = _activated_wdata_e_act_T_67 ? activated_wdata_e_clipped_22 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_22 = _activated_wdata_e_act_T_66 ? _activated_wdata_e_act_T_68 : activated_wdata_e_clipped_22; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_22_0 = activated_wdata_e_act_22; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_6_0 = _activated_wdata_WIRE_22_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_117 = _activated_wdata_e_clipped_T_116 ? 20'hFFF80 : _mesh_io_resp_bits_data_7_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_118 = _activated_wdata_e_clipped_T_115 ? 20'h7F : _activated_wdata_e_clipped_T_117; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_119 = _activated_wdata_e_clipped_T_118[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_23 = _activated_wdata_e_clipped_T_119; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_70 = $signed(activated_wdata_e_clipped_23) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_71 = _activated_wdata_e_act_T_70 ? activated_wdata_e_clipped_23 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_23 = _activated_wdata_e_act_T_69 ? _activated_wdata_e_act_T_71 : activated_wdata_e_clipped_23; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_23_0 = activated_wdata_e_act_23; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_7_0 = _activated_wdata_WIRE_23_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_122 = _activated_wdata_e_clipped_T_121 ? 20'hFFF80 : _mesh_io_resp_bits_data_8_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_123 = _activated_wdata_e_clipped_T_120 ? 20'h7F : _activated_wdata_e_clipped_T_122; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_124 = _activated_wdata_e_clipped_T_123[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_24 = _activated_wdata_e_clipped_T_124; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_73 = $signed(activated_wdata_e_clipped_24) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_74 = _activated_wdata_e_act_T_73 ? activated_wdata_e_clipped_24 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_24 = _activated_wdata_e_act_T_72 ? _activated_wdata_e_act_T_74 : activated_wdata_e_clipped_24; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_24_0 = activated_wdata_e_act_24; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_8_0 = _activated_wdata_WIRE_24_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_127 = _activated_wdata_e_clipped_T_126 ? 20'hFFF80 : _mesh_io_resp_bits_data_9_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_128 = _activated_wdata_e_clipped_T_125 ? 20'h7F : _activated_wdata_e_clipped_T_127; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_129 = _activated_wdata_e_clipped_T_128[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_25 = _activated_wdata_e_clipped_T_129; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_76 = $signed(activated_wdata_e_clipped_25) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_77 = _activated_wdata_e_act_T_76 ? activated_wdata_e_clipped_25 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_25 = _activated_wdata_e_act_T_75 ? _activated_wdata_e_act_T_77 : activated_wdata_e_clipped_25; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_25_0 = activated_wdata_e_act_25; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_9_0 = _activated_wdata_WIRE_25_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_132 = _activated_wdata_e_clipped_T_131 ? 20'hFFF80 : _mesh_io_resp_bits_data_10_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_133 = _activated_wdata_e_clipped_T_130 ? 20'h7F : _activated_wdata_e_clipped_T_132; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_134 = _activated_wdata_e_clipped_T_133[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_26 = _activated_wdata_e_clipped_T_134; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_79 = $signed(activated_wdata_e_clipped_26) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_80 = _activated_wdata_e_act_T_79 ? activated_wdata_e_clipped_26 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_26 = _activated_wdata_e_act_T_78 ? _activated_wdata_e_act_T_80 : activated_wdata_e_clipped_26; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_26_0 = activated_wdata_e_act_26; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_10_0 = _activated_wdata_WIRE_26_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_137 = _activated_wdata_e_clipped_T_136 ? 20'hFFF80 : _mesh_io_resp_bits_data_11_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_138 = _activated_wdata_e_clipped_T_135 ? 20'h7F : _activated_wdata_e_clipped_T_137; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_139 = _activated_wdata_e_clipped_T_138[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_27 = _activated_wdata_e_clipped_T_139; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_82 = $signed(activated_wdata_e_clipped_27) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_83 = _activated_wdata_e_act_T_82 ? activated_wdata_e_clipped_27 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_27 = _activated_wdata_e_act_T_81 ? _activated_wdata_e_act_T_83 : activated_wdata_e_clipped_27; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_27_0 = activated_wdata_e_act_27; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_11_0 = _activated_wdata_WIRE_27_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_142 = _activated_wdata_e_clipped_T_141 ? 20'hFFF80 : _mesh_io_resp_bits_data_12_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_143 = _activated_wdata_e_clipped_T_140 ? 20'h7F : _activated_wdata_e_clipped_T_142; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_144 = _activated_wdata_e_clipped_T_143[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_28 = _activated_wdata_e_clipped_T_144; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_85 = $signed(activated_wdata_e_clipped_28) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_86 = _activated_wdata_e_act_T_85 ? activated_wdata_e_clipped_28 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_28 = _activated_wdata_e_act_T_84 ? _activated_wdata_e_act_T_86 : activated_wdata_e_clipped_28; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_28_0 = activated_wdata_e_act_28; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_12_0 = _activated_wdata_WIRE_28_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_147 = _activated_wdata_e_clipped_T_146 ? 20'hFFF80 : _mesh_io_resp_bits_data_13_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_148 = _activated_wdata_e_clipped_T_145 ? 20'h7F : _activated_wdata_e_clipped_T_147; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_149 = _activated_wdata_e_clipped_T_148[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_29 = _activated_wdata_e_clipped_T_149; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_88 = $signed(activated_wdata_e_clipped_29) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_89 = _activated_wdata_e_act_T_88 ? activated_wdata_e_clipped_29 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_29 = _activated_wdata_e_act_T_87 ? _activated_wdata_e_act_T_89 : activated_wdata_e_clipped_29; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_29_0 = activated_wdata_e_act_29; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_13_0 = _activated_wdata_WIRE_29_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_152 = _activated_wdata_e_clipped_T_151 ? 20'hFFF80 : _mesh_io_resp_bits_data_14_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_153 = _activated_wdata_e_clipped_T_150 ? 20'h7F : _activated_wdata_e_clipped_T_152; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_154 = _activated_wdata_e_clipped_T_153[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_30 = _activated_wdata_e_clipped_T_154; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_91 = $signed(activated_wdata_e_clipped_30) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_92 = _activated_wdata_e_act_T_91 ? activated_wdata_e_clipped_30 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_30 = _activated_wdata_e_act_T_90 ? _activated_wdata_e_act_T_92 : activated_wdata_e_clipped_30; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_30_0 = activated_wdata_e_act_30; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_14_0 = _activated_wdata_WIRE_30_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_157 = _activated_wdata_e_clipped_T_156 ? 20'hFFF80 : _mesh_io_resp_bits_data_15_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_158 = _activated_wdata_e_clipped_T_155 ? 20'h7F : _activated_wdata_e_clipped_T_157; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_159 = _activated_wdata_e_clipped_T_158[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_31 = _activated_wdata_e_clipped_T_159; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_94 = $signed(activated_wdata_e_clipped_31) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_95 = _activated_wdata_e_act_T_94 ? activated_wdata_e_clipped_31 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_31 = _activated_wdata_e_act_T_93 ? _activated_wdata_e_act_T_95 : activated_wdata_e_clipped_31; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_31_0 = activated_wdata_e_act_31; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_1_15_0 = _activated_wdata_WIRE_31_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_162 = _activated_wdata_e_clipped_T_161 ? 20'hFFF80 : _mesh_io_resp_bits_data_0_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_163 = _activated_wdata_e_clipped_T_160 ? 20'h7F : _activated_wdata_e_clipped_T_162; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_164 = _activated_wdata_e_clipped_T_163[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_32 = _activated_wdata_e_clipped_T_164; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_97 = $signed(activated_wdata_e_clipped_32) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_98 = _activated_wdata_e_act_T_97 ? activated_wdata_e_clipped_32 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_32 = _activated_wdata_e_act_T_96 ? _activated_wdata_e_act_T_98 : activated_wdata_e_clipped_32; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_32_0 = activated_wdata_e_act_32; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_0_0 = _activated_wdata_WIRE_32_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_167 = _activated_wdata_e_clipped_T_166 ? 20'hFFF80 : _mesh_io_resp_bits_data_1_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_168 = _activated_wdata_e_clipped_T_165 ? 20'h7F : _activated_wdata_e_clipped_T_167; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_169 = _activated_wdata_e_clipped_T_168[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_33 = _activated_wdata_e_clipped_T_169; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_100 = $signed(activated_wdata_e_clipped_33) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_101 = _activated_wdata_e_act_T_100 ? activated_wdata_e_clipped_33 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_33 = _activated_wdata_e_act_T_99 ? _activated_wdata_e_act_T_101 : activated_wdata_e_clipped_33; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_33_0 = activated_wdata_e_act_33; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_1_0 = _activated_wdata_WIRE_33_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_172 = _activated_wdata_e_clipped_T_171 ? 20'hFFF80 : _mesh_io_resp_bits_data_2_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_173 = _activated_wdata_e_clipped_T_170 ? 20'h7F : _activated_wdata_e_clipped_T_172; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_174 = _activated_wdata_e_clipped_T_173[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_34 = _activated_wdata_e_clipped_T_174; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_103 = $signed(activated_wdata_e_clipped_34) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_104 = _activated_wdata_e_act_T_103 ? activated_wdata_e_clipped_34 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_34 = _activated_wdata_e_act_T_102 ? _activated_wdata_e_act_T_104 : activated_wdata_e_clipped_34; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_34_0 = activated_wdata_e_act_34; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_2_0 = _activated_wdata_WIRE_34_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_177 = _activated_wdata_e_clipped_T_176 ? 20'hFFF80 : _mesh_io_resp_bits_data_3_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_178 = _activated_wdata_e_clipped_T_175 ? 20'h7F : _activated_wdata_e_clipped_T_177; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_179 = _activated_wdata_e_clipped_T_178[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_35 = _activated_wdata_e_clipped_T_179; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_106 = $signed(activated_wdata_e_clipped_35) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_107 = _activated_wdata_e_act_T_106 ? activated_wdata_e_clipped_35 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_35 = _activated_wdata_e_act_T_105 ? _activated_wdata_e_act_T_107 : activated_wdata_e_clipped_35; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_35_0 = activated_wdata_e_act_35; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_3_0 = _activated_wdata_WIRE_35_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_182 = _activated_wdata_e_clipped_T_181 ? 20'hFFF80 : _mesh_io_resp_bits_data_4_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_183 = _activated_wdata_e_clipped_T_180 ? 20'h7F : _activated_wdata_e_clipped_T_182; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_184 = _activated_wdata_e_clipped_T_183[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_36 = _activated_wdata_e_clipped_T_184; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_109 = $signed(activated_wdata_e_clipped_36) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_110 = _activated_wdata_e_act_T_109 ? activated_wdata_e_clipped_36 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_36 = _activated_wdata_e_act_T_108 ? _activated_wdata_e_act_T_110 : activated_wdata_e_clipped_36; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_36_0 = activated_wdata_e_act_36; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_4_0 = _activated_wdata_WIRE_36_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_187 = _activated_wdata_e_clipped_T_186 ? 20'hFFF80 : _mesh_io_resp_bits_data_5_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_188 = _activated_wdata_e_clipped_T_185 ? 20'h7F : _activated_wdata_e_clipped_T_187; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_189 = _activated_wdata_e_clipped_T_188[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_37 = _activated_wdata_e_clipped_T_189; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_112 = $signed(activated_wdata_e_clipped_37) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_113 = _activated_wdata_e_act_T_112 ? activated_wdata_e_clipped_37 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_37 = _activated_wdata_e_act_T_111 ? _activated_wdata_e_act_T_113 : activated_wdata_e_clipped_37; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_37_0 = activated_wdata_e_act_37; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_5_0 = _activated_wdata_WIRE_37_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_192 = _activated_wdata_e_clipped_T_191 ? 20'hFFF80 : _mesh_io_resp_bits_data_6_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_193 = _activated_wdata_e_clipped_T_190 ? 20'h7F : _activated_wdata_e_clipped_T_192; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_194 = _activated_wdata_e_clipped_T_193[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_38 = _activated_wdata_e_clipped_T_194; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_115 = $signed(activated_wdata_e_clipped_38) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_116 = _activated_wdata_e_act_T_115 ? activated_wdata_e_clipped_38 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_38 = _activated_wdata_e_act_T_114 ? _activated_wdata_e_act_T_116 : activated_wdata_e_clipped_38; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_38_0 = activated_wdata_e_act_38; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_6_0 = _activated_wdata_WIRE_38_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_197 = _activated_wdata_e_clipped_T_196 ? 20'hFFF80 : _mesh_io_resp_bits_data_7_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_198 = _activated_wdata_e_clipped_T_195 ? 20'h7F : _activated_wdata_e_clipped_T_197; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_199 = _activated_wdata_e_clipped_T_198[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_39 = _activated_wdata_e_clipped_T_199; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_118 = $signed(activated_wdata_e_clipped_39) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_119 = _activated_wdata_e_act_T_118 ? activated_wdata_e_clipped_39 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_39 = _activated_wdata_e_act_T_117 ? _activated_wdata_e_act_T_119 : activated_wdata_e_clipped_39; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_39_0 = activated_wdata_e_act_39; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_7_0 = _activated_wdata_WIRE_39_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_202 = _activated_wdata_e_clipped_T_201 ? 20'hFFF80 : _mesh_io_resp_bits_data_8_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_203 = _activated_wdata_e_clipped_T_200 ? 20'h7F : _activated_wdata_e_clipped_T_202; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_204 = _activated_wdata_e_clipped_T_203[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_40 = _activated_wdata_e_clipped_T_204; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_121 = $signed(activated_wdata_e_clipped_40) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_122 = _activated_wdata_e_act_T_121 ? activated_wdata_e_clipped_40 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_40 = _activated_wdata_e_act_T_120 ? _activated_wdata_e_act_T_122 : activated_wdata_e_clipped_40; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_40_0 = activated_wdata_e_act_40; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_8_0 = _activated_wdata_WIRE_40_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_207 = _activated_wdata_e_clipped_T_206 ? 20'hFFF80 : _mesh_io_resp_bits_data_9_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_208 = _activated_wdata_e_clipped_T_205 ? 20'h7F : _activated_wdata_e_clipped_T_207; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_209 = _activated_wdata_e_clipped_T_208[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_41 = _activated_wdata_e_clipped_T_209; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_124 = $signed(activated_wdata_e_clipped_41) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_125 = _activated_wdata_e_act_T_124 ? activated_wdata_e_clipped_41 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_41 = _activated_wdata_e_act_T_123 ? _activated_wdata_e_act_T_125 : activated_wdata_e_clipped_41; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_41_0 = activated_wdata_e_act_41; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_9_0 = _activated_wdata_WIRE_41_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_212 = _activated_wdata_e_clipped_T_211 ? 20'hFFF80 : _mesh_io_resp_bits_data_10_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_213 = _activated_wdata_e_clipped_T_210 ? 20'h7F : _activated_wdata_e_clipped_T_212; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_214 = _activated_wdata_e_clipped_T_213[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_42 = _activated_wdata_e_clipped_T_214; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_127 = $signed(activated_wdata_e_clipped_42) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_128 = _activated_wdata_e_act_T_127 ? activated_wdata_e_clipped_42 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_42 = _activated_wdata_e_act_T_126 ? _activated_wdata_e_act_T_128 : activated_wdata_e_clipped_42; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_42_0 = activated_wdata_e_act_42; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_10_0 = _activated_wdata_WIRE_42_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_217 = _activated_wdata_e_clipped_T_216 ? 20'hFFF80 : _mesh_io_resp_bits_data_11_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_218 = _activated_wdata_e_clipped_T_215 ? 20'h7F : _activated_wdata_e_clipped_T_217; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_219 = _activated_wdata_e_clipped_T_218[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_43 = _activated_wdata_e_clipped_T_219; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_130 = $signed(activated_wdata_e_clipped_43) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_131 = _activated_wdata_e_act_T_130 ? activated_wdata_e_clipped_43 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_43 = _activated_wdata_e_act_T_129 ? _activated_wdata_e_act_T_131 : activated_wdata_e_clipped_43; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_43_0 = activated_wdata_e_act_43; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_11_0 = _activated_wdata_WIRE_43_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_222 = _activated_wdata_e_clipped_T_221 ? 20'hFFF80 : _mesh_io_resp_bits_data_12_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_223 = _activated_wdata_e_clipped_T_220 ? 20'h7F : _activated_wdata_e_clipped_T_222; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_224 = _activated_wdata_e_clipped_T_223[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_44 = _activated_wdata_e_clipped_T_224; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_133 = $signed(activated_wdata_e_clipped_44) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_134 = _activated_wdata_e_act_T_133 ? activated_wdata_e_clipped_44 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_44 = _activated_wdata_e_act_T_132 ? _activated_wdata_e_act_T_134 : activated_wdata_e_clipped_44; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_44_0 = activated_wdata_e_act_44; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_12_0 = _activated_wdata_WIRE_44_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_227 = _activated_wdata_e_clipped_T_226 ? 20'hFFF80 : _mesh_io_resp_bits_data_13_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_228 = _activated_wdata_e_clipped_T_225 ? 20'h7F : _activated_wdata_e_clipped_T_227; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_229 = _activated_wdata_e_clipped_T_228[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_45 = _activated_wdata_e_clipped_T_229; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_136 = $signed(activated_wdata_e_clipped_45) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_137 = _activated_wdata_e_act_T_136 ? activated_wdata_e_clipped_45 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_45 = _activated_wdata_e_act_T_135 ? _activated_wdata_e_act_T_137 : activated_wdata_e_clipped_45; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_45_0 = activated_wdata_e_act_45; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_13_0 = _activated_wdata_WIRE_45_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_232 = _activated_wdata_e_clipped_T_231 ? 20'hFFF80 : _mesh_io_resp_bits_data_14_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_233 = _activated_wdata_e_clipped_T_230 ? 20'h7F : _activated_wdata_e_clipped_T_232; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_234 = _activated_wdata_e_clipped_T_233[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_46 = _activated_wdata_e_clipped_T_234; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_139 = $signed(activated_wdata_e_clipped_46) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_140 = _activated_wdata_e_act_T_139 ? activated_wdata_e_clipped_46 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_46 = _activated_wdata_e_act_T_138 ? _activated_wdata_e_act_T_140 : activated_wdata_e_clipped_46; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_46_0 = activated_wdata_e_act_46; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_14_0 = _activated_wdata_WIRE_46_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_237 = _activated_wdata_e_clipped_T_236 ? 20'hFFF80 : _mesh_io_resp_bits_data_15_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_238 = _activated_wdata_e_clipped_T_235 ? 20'h7F : _activated_wdata_e_clipped_T_237; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_239 = _activated_wdata_e_clipped_T_238[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_47 = _activated_wdata_e_clipped_T_239; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_142 = $signed(activated_wdata_e_clipped_47) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_143 = _activated_wdata_e_act_T_142 ? activated_wdata_e_clipped_47 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_47 = _activated_wdata_e_act_T_141 ? _activated_wdata_e_act_T_143 : activated_wdata_e_clipped_47; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_47_0 = activated_wdata_e_act_47; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_2_15_0 = _activated_wdata_WIRE_47_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_242 = _activated_wdata_e_clipped_T_241 ? 20'hFFF80 : _mesh_io_resp_bits_data_0_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_243 = _activated_wdata_e_clipped_T_240 ? 20'h7F : _activated_wdata_e_clipped_T_242; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_244 = _activated_wdata_e_clipped_T_243[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_48 = _activated_wdata_e_clipped_T_244; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_145 = $signed(activated_wdata_e_clipped_48) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_146 = _activated_wdata_e_act_T_145 ? activated_wdata_e_clipped_48 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_48 = _activated_wdata_e_act_T_144 ? _activated_wdata_e_act_T_146 : activated_wdata_e_clipped_48; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_48_0 = activated_wdata_e_act_48; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_0_0 = _activated_wdata_WIRE_48_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_247 = _activated_wdata_e_clipped_T_246 ? 20'hFFF80 : _mesh_io_resp_bits_data_1_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_248 = _activated_wdata_e_clipped_T_245 ? 20'h7F : _activated_wdata_e_clipped_T_247; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_249 = _activated_wdata_e_clipped_T_248[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_49 = _activated_wdata_e_clipped_T_249; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_148 = $signed(activated_wdata_e_clipped_49) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_149 = _activated_wdata_e_act_T_148 ? activated_wdata_e_clipped_49 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_49 = _activated_wdata_e_act_T_147 ? _activated_wdata_e_act_T_149 : activated_wdata_e_clipped_49; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_49_0 = activated_wdata_e_act_49; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_1_0 = _activated_wdata_WIRE_49_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_252 = _activated_wdata_e_clipped_T_251 ? 20'hFFF80 : _mesh_io_resp_bits_data_2_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_253 = _activated_wdata_e_clipped_T_250 ? 20'h7F : _activated_wdata_e_clipped_T_252; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_254 = _activated_wdata_e_clipped_T_253[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_50 = _activated_wdata_e_clipped_T_254; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_151 = $signed(activated_wdata_e_clipped_50) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_152 = _activated_wdata_e_act_T_151 ? activated_wdata_e_clipped_50 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_50 = _activated_wdata_e_act_T_150 ? _activated_wdata_e_act_T_152 : activated_wdata_e_clipped_50; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_50_0 = activated_wdata_e_act_50; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_2_0 = _activated_wdata_WIRE_50_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_257 = _activated_wdata_e_clipped_T_256 ? 20'hFFF80 : _mesh_io_resp_bits_data_3_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_258 = _activated_wdata_e_clipped_T_255 ? 20'h7F : _activated_wdata_e_clipped_T_257; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_259 = _activated_wdata_e_clipped_T_258[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_51 = _activated_wdata_e_clipped_T_259; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_154 = $signed(activated_wdata_e_clipped_51) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_155 = _activated_wdata_e_act_T_154 ? activated_wdata_e_clipped_51 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_51 = _activated_wdata_e_act_T_153 ? _activated_wdata_e_act_T_155 : activated_wdata_e_clipped_51; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_51_0 = activated_wdata_e_act_51; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_3_0 = _activated_wdata_WIRE_51_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_262 = _activated_wdata_e_clipped_T_261 ? 20'hFFF80 : _mesh_io_resp_bits_data_4_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_263 = _activated_wdata_e_clipped_T_260 ? 20'h7F : _activated_wdata_e_clipped_T_262; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_264 = _activated_wdata_e_clipped_T_263[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_52 = _activated_wdata_e_clipped_T_264; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_157 = $signed(activated_wdata_e_clipped_52) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_158 = _activated_wdata_e_act_T_157 ? activated_wdata_e_clipped_52 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_52 = _activated_wdata_e_act_T_156 ? _activated_wdata_e_act_T_158 : activated_wdata_e_clipped_52; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_52_0 = activated_wdata_e_act_52; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_4_0 = _activated_wdata_WIRE_52_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_267 = _activated_wdata_e_clipped_T_266 ? 20'hFFF80 : _mesh_io_resp_bits_data_5_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_268 = _activated_wdata_e_clipped_T_265 ? 20'h7F : _activated_wdata_e_clipped_T_267; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_269 = _activated_wdata_e_clipped_T_268[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_53 = _activated_wdata_e_clipped_T_269; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_160 = $signed(activated_wdata_e_clipped_53) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_161 = _activated_wdata_e_act_T_160 ? activated_wdata_e_clipped_53 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_53 = _activated_wdata_e_act_T_159 ? _activated_wdata_e_act_T_161 : activated_wdata_e_clipped_53; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_53_0 = activated_wdata_e_act_53; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_5_0 = _activated_wdata_WIRE_53_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_272 = _activated_wdata_e_clipped_T_271 ? 20'hFFF80 : _mesh_io_resp_bits_data_6_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_273 = _activated_wdata_e_clipped_T_270 ? 20'h7F : _activated_wdata_e_clipped_T_272; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_274 = _activated_wdata_e_clipped_T_273[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_54 = _activated_wdata_e_clipped_T_274; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_163 = $signed(activated_wdata_e_clipped_54) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_164 = _activated_wdata_e_act_T_163 ? activated_wdata_e_clipped_54 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_54 = _activated_wdata_e_act_T_162 ? _activated_wdata_e_act_T_164 : activated_wdata_e_clipped_54; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_54_0 = activated_wdata_e_act_54; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_6_0 = _activated_wdata_WIRE_54_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_277 = _activated_wdata_e_clipped_T_276 ? 20'hFFF80 : _mesh_io_resp_bits_data_7_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_278 = _activated_wdata_e_clipped_T_275 ? 20'h7F : _activated_wdata_e_clipped_T_277; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_279 = _activated_wdata_e_clipped_T_278[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_55 = _activated_wdata_e_clipped_T_279; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_166 = $signed(activated_wdata_e_clipped_55) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_167 = _activated_wdata_e_act_T_166 ? activated_wdata_e_clipped_55 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_55 = _activated_wdata_e_act_T_165 ? _activated_wdata_e_act_T_167 : activated_wdata_e_clipped_55; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_55_0 = activated_wdata_e_act_55; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_7_0 = _activated_wdata_WIRE_55_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_282 = _activated_wdata_e_clipped_T_281 ? 20'hFFF80 : _mesh_io_resp_bits_data_8_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_283 = _activated_wdata_e_clipped_T_280 ? 20'h7F : _activated_wdata_e_clipped_T_282; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_284 = _activated_wdata_e_clipped_T_283[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_56 = _activated_wdata_e_clipped_T_284; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_169 = $signed(activated_wdata_e_clipped_56) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_170 = _activated_wdata_e_act_T_169 ? activated_wdata_e_clipped_56 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_56 = _activated_wdata_e_act_T_168 ? _activated_wdata_e_act_T_170 : activated_wdata_e_clipped_56; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_56_0 = activated_wdata_e_act_56; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_8_0 = _activated_wdata_WIRE_56_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_287 = _activated_wdata_e_clipped_T_286 ? 20'hFFF80 : _mesh_io_resp_bits_data_9_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_288 = _activated_wdata_e_clipped_T_285 ? 20'h7F : _activated_wdata_e_clipped_T_287; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_289 = _activated_wdata_e_clipped_T_288[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_57 = _activated_wdata_e_clipped_T_289; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_172 = $signed(activated_wdata_e_clipped_57) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_173 = _activated_wdata_e_act_T_172 ? activated_wdata_e_clipped_57 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_57 = _activated_wdata_e_act_T_171 ? _activated_wdata_e_act_T_173 : activated_wdata_e_clipped_57; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_57_0 = activated_wdata_e_act_57; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_9_0 = _activated_wdata_WIRE_57_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_292 = _activated_wdata_e_clipped_T_291 ? 20'hFFF80 : _mesh_io_resp_bits_data_10_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_293 = _activated_wdata_e_clipped_T_290 ? 20'h7F : _activated_wdata_e_clipped_T_292; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_294 = _activated_wdata_e_clipped_T_293[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_58 = _activated_wdata_e_clipped_T_294; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_175 = $signed(activated_wdata_e_clipped_58) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_176 = _activated_wdata_e_act_T_175 ? activated_wdata_e_clipped_58 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_58 = _activated_wdata_e_act_T_174 ? _activated_wdata_e_act_T_176 : activated_wdata_e_clipped_58; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_58_0 = activated_wdata_e_act_58; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_10_0 = _activated_wdata_WIRE_58_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_297 = _activated_wdata_e_clipped_T_296 ? 20'hFFF80 : _mesh_io_resp_bits_data_11_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_298 = _activated_wdata_e_clipped_T_295 ? 20'h7F : _activated_wdata_e_clipped_T_297; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_299 = _activated_wdata_e_clipped_T_298[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_59 = _activated_wdata_e_clipped_T_299; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_178 = $signed(activated_wdata_e_clipped_59) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_179 = _activated_wdata_e_act_T_178 ? activated_wdata_e_clipped_59 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_59 = _activated_wdata_e_act_T_177 ? _activated_wdata_e_act_T_179 : activated_wdata_e_clipped_59; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_59_0 = activated_wdata_e_act_59; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_11_0 = _activated_wdata_WIRE_59_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_302 = _activated_wdata_e_clipped_T_301 ? 20'hFFF80 : _mesh_io_resp_bits_data_12_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_303 = _activated_wdata_e_clipped_T_300 ? 20'h7F : _activated_wdata_e_clipped_T_302; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_304 = _activated_wdata_e_clipped_T_303[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_60 = _activated_wdata_e_clipped_T_304; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_181 = $signed(activated_wdata_e_clipped_60) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_182 = _activated_wdata_e_act_T_181 ? activated_wdata_e_clipped_60 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_60 = _activated_wdata_e_act_T_180 ? _activated_wdata_e_act_T_182 : activated_wdata_e_clipped_60; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_60_0 = activated_wdata_e_act_60; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_12_0 = _activated_wdata_WIRE_60_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_307 = _activated_wdata_e_clipped_T_306 ? 20'hFFF80 : _mesh_io_resp_bits_data_13_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_308 = _activated_wdata_e_clipped_T_305 ? 20'h7F : _activated_wdata_e_clipped_T_307; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_309 = _activated_wdata_e_clipped_T_308[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_61 = _activated_wdata_e_clipped_T_309; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_184 = $signed(activated_wdata_e_clipped_61) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_185 = _activated_wdata_e_act_T_184 ? activated_wdata_e_clipped_61 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_61 = _activated_wdata_e_act_T_183 ? _activated_wdata_e_act_T_185 : activated_wdata_e_clipped_61; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_61_0 = activated_wdata_e_act_61; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_13_0 = _activated_wdata_WIRE_61_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_312 = _activated_wdata_e_clipped_T_311 ? 20'hFFF80 : _mesh_io_resp_bits_data_14_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_313 = _activated_wdata_e_clipped_T_310 ? 20'h7F : _activated_wdata_e_clipped_T_312; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_314 = _activated_wdata_e_clipped_T_313[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_62 = _activated_wdata_e_clipped_T_314; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_187 = $signed(activated_wdata_e_clipped_62) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_188 = _activated_wdata_e_act_T_187 ? activated_wdata_e_clipped_62 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_62 = _activated_wdata_e_act_T_186 ? _activated_wdata_e_act_T_188 : activated_wdata_e_clipped_62; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_62_0 = activated_wdata_e_act_62; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_14_0 = _activated_wdata_WIRE_62_0; // @[ExecuteController.scala:925:{34,74}]
wire [19:0] _activated_wdata_e_clipped_T_317 = _activated_wdata_e_clipped_T_316 ? 20'hFFF80 : _mesh_io_resp_bits_data_15_0; // @[Mux.scala:126:16]
wire [19:0] _activated_wdata_e_clipped_T_318 = _activated_wdata_e_clipped_T_315 ? 20'h7F : _activated_wdata_e_clipped_T_317; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_e_clipped_T_319 = _activated_wdata_e_clipped_T_318[7:0]; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_e_clipped_63 = _activated_wdata_e_clipped_T_319; // @[Arithmetic.scala:125:{81,99}]
wire _activated_wdata_e_act_T_190 = $signed(activated_wdata_e_clipped_63) > -8'sh1; // @[Arithmetic.scala:125:99, :128:42]
wire [7:0] _activated_wdata_e_act_T_191 = _activated_wdata_e_act_T_190 ? activated_wdata_e_clipped_63 : 8'h0; // @[Arithmetic.scala:125:99, :128:{36,42}]
wire [7:0] activated_wdata_e_act_63 = _activated_wdata_e_act_T_189 ? _activated_wdata_e_act_T_191 : activated_wdata_e_clipped_63; // @[Mux.scala:126:16]
wire [7:0] _activated_wdata_WIRE_63_0 = activated_wdata_e_act_63; // @[Mux.scala:126:16]
wire [7:0] activated_wdata_3_15_0 = _activated_wdata_WIRE_63_0; // @[ExecuteController.scala:925:{34,74}]
wire _io_acc_write_0_valid_T = w_bank == 2'h0; // @[ExecuteController.scala:911:19, :949:65]
wire _io_acc_write_0_valid_T_1 = start_array_outputting & _io_acc_write_0_valid_T; // @[ExecuteController.scala:270:40, :949:{55,65}]
wire _io_acc_write_0_valid_T_2 = _io_acc_write_0_valid_T_1 & w_address_is_acc_addr; // @[ExecuteController.scala:907:22, :949:{55,73}]
wire _io_acc_write_0_valid_T_3 = ~is_garbage_addr; // @[LocalAddr.scala:43:96]
wire _io_acc_write_0_valid_T_4 = _io_acc_write_0_valid_T_2 & _io_acc_write_0_valid_T_3; // @[ExecuteController.scala:949:{73,89,92}]
assign _io_acc_write_0_valid_T_5 = _io_acc_write_0_valid_T_4 & write_this_row; // @[ExecuteController.scala:919:27, :949:{89,109}]
assign io_acc_write_0_valid_0 = _io_acc_write_0_valid_T_5; // @[ExecuteController.scala:12:7, :949:109]
assign io_acc_write_0_bits_addr_0 = w_row[8:0]; // @[ExecuteController.scala:12:7, :912:18, :950:33]
assign io_acc_write_1_bits_addr_0 = w_row[8:0]; // @[ExecuteController.scala:12:7, :912:18, :950:33]
wire sign = _mesh_io_resp_bits_data_0_0[19]; // @[ExecuteController.scala:186:20]
wire sign_16 = _mesh_io_resp_bits_data_0_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_122 = {2{sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_7; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_7 = _GEN_122; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_7; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_7 = _GEN_122; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_7; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_7 = _GEN_122; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_7; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_7 = _GEN_122; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_7 = {lo_lo_hi_7, sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_7 = {lo_hi_hi_7, sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_7 = {lo_hi_7, lo_lo_7}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_7 = {hi_lo_hi_7, sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_7 = {hi_hi_hi_7, sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_7 = {hi_hi_7, hi_lo_7}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_8; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_0_0_0 = {hi_7, lo_7, lo_8}; // @[ExecuteController.scala:12:7]
wire sign_1 = _mesh_io_resp_bits_data_1_0[19]; // @[ExecuteController.scala:186:20]
wire sign_17 = _mesh_io_resp_bits_data_1_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_123 = {2{sign_1}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_8; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_8 = _GEN_123; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_8; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_8 = _GEN_123; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_8; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_8 = _GEN_123; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_8; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_8 = _GEN_123; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_8 = {lo_lo_hi_8, sign_1}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_8 = {lo_hi_hi_8, sign_1}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_9 = {lo_hi_8, lo_lo_8}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_8 = {hi_lo_hi_8, sign_1}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_8 = {hi_hi_hi_8, sign_1}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_8 = {hi_hi_8, hi_lo_8}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_10; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_1_0_0 = {hi_8, lo_9, lo_10}; // @[ExecuteController.scala:12:7]
wire sign_2 = _mesh_io_resp_bits_data_2_0[19]; // @[ExecuteController.scala:186:20]
wire sign_18 = _mesh_io_resp_bits_data_2_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_124 = {2{sign_2}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_9; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_9 = _GEN_124; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_9; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_9 = _GEN_124; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_9; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_9 = _GEN_124; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_9; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_9 = _GEN_124; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_9 = {lo_lo_hi_9, sign_2}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_9 = {lo_hi_hi_9, sign_2}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_11 = {lo_hi_9, lo_lo_9}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_9 = {hi_lo_hi_9, sign_2}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_9 = {hi_hi_hi_9, sign_2}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_9 = {hi_hi_9, hi_lo_9}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_12; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_2_0_0 = {hi_9, lo_11, lo_12}; // @[ExecuteController.scala:12:7]
wire sign_3 = _mesh_io_resp_bits_data_3_0[19]; // @[ExecuteController.scala:186:20]
wire sign_19 = _mesh_io_resp_bits_data_3_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_125 = {2{sign_3}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_10; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_10 = _GEN_125; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_10; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_10 = _GEN_125; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_10; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_10 = _GEN_125; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_10; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_10 = _GEN_125; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_10 = {lo_lo_hi_10, sign_3}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_10 = {lo_hi_hi_10, sign_3}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_13 = {lo_hi_10, lo_lo_10}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_10 = {hi_lo_hi_10, sign_3}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_10 = {hi_hi_hi_10, sign_3}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_10 = {hi_hi_10, hi_lo_10}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_14; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_3_0_0 = {hi_10, lo_13, lo_14}; // @[ExecuteController.scala:12:7]
wire sign_4 = _mesh_io_resp_bits_data_4_0[19]; // @[ExecuteController.scala:186:20]
wire sign_20 = _mesh_io_resp_bits_data_4_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_126 = {2{sign_4}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_11; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_11 = _GEN_126; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_11; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_11 = _GEN_126; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_11; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_11 = _GEN_126; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_11; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_11 = _GEN_126; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_11 = {lo_lo_hi_11, sign_4}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_11 = {lo_hi_hi_11, sign_4}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_15 = {lo_hi_11, lo_lo_11}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_11 = {hi_lo_hi_11, sign_4}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_11 = {hi_hi_hi_11, sign_4}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_11 = {hi_hi_11, hi_lo_11}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_16; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_4_0_0 = {hi_11, lo_15, lo_16}; // @[ExecuteController.scala:12:7]
wire sign_5 = _mesh_io_resp_bits_data_5_0[19]; // @[ExecuteController.scala:186:20]
wire sign_21 = _mesh_io_resp_bits_data_5_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_127 = {2{sign_5}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_12; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_12 = _GEN_127; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_12; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_12 = _GEN_127; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_12; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_12 = _GEN_127; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_12; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_12 = _GEN_127; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_12 = {lo_lo_hi_12, sign_5}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_12 = {lo_hi_hi_12, sign_5}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_17 = {lo_hi_12, lo_lo_12}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_12 = {hi_lo_hi_12, sign_5}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_12 = {hi_hi_hi_12, sign_5}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_12 = {hi_hi_12, hi_lo_12}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_18; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_5_0_0 = {hi_12, lo_17, lo_18}; // @[ExecuteController.scala:12:7]
wire sign_6 = _mesh_io_resp_bits_data_6_0[19]; // @[ExecuteController.scala:186:20]
wire sign_22 = _mesh_io_resp_bits_data_6_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_128 = {2{sign_6}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_13; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_13 = _GEN_128; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_13; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_13 = _GEN_128; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_13; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_13 = _GEN_128; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_13; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_13 = _GEN_128; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_13 = {lo_lo_hi_13, sign_6}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_13 = {lo_hi_hi_13, sign_6}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_19 = {lo_hi_13, lo_lo_13}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_13 = {hi_lo_hi_13, sign_6}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_13 = {hi_hi_hi_13, sign_6}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_13 = {hi_hi_13, hi_lo_13}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_20; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_6_0_0 = {hi_13, lo_19, lo_20}; // @[ExecuteController.scala:12:7]
wire sign_7 = _mesh_io_resp_bits_data_7_0[19]; // @[ExecuteController.scala:186:20]
wire sign_23 = _mesh_io_resp_bits_data_7_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_129 = {2{sign_7}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_14; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_14 = _GEN_129; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_14; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_14 = _GEN_129; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_14; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_14 = _GEN_129; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_14; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_14 = _GEN_129; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_14 = {lo_lo_hi_14, sign_7}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_14 = {lo_hi_hi_14, sign_7}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_21 = {lo_hi_14, lo_lo_14}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_14 = {hi_lo_hi_14, sign_7}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_14 = {hi_hi_hi_14, sign_7}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_14 = {hi_hi_14, hi_lo_14}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_22; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_7_0_0 = {hi_14, lo_21, lo_22}; // @[ExecuteController.scala:12:7]
wire sign_8 = _mesh_io_resp_bits_data_8_0[19]; // @[ExecuteController.scala:186:20]
wire sign_24 = _mesh_io_resp_bits_data_8_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_130 = {2{sign_8}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_15; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_15 = _GEN_130; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_15; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_15 = _GEN_130; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_15; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_15 = _GEN_130; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_15; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_15 = _GEN_130; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_15 = {lo_lo_hi_15, sign_8}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_15 = {lo_hi_hi_15, sign_8}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_23 = {lo_hi_15, lo_lo_15}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_15 = {hi_lo_hi_15, sign_8}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_15 = {hi_hi_hi_15, sign_8}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_15 = {hi_hi_15, hi_lo_15}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_24; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_8_0_0 = {hi_15, lo_23, lo_24}; // @[ExecuteController.scala:12:7]
wire sign_9 = _mesh_io_resp_bits_data_9_0[19]; // @[ExecuteController.scala:186:20]
wire sign_25 = _mesh_io_resp_bits_data_9_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_131 = {2{sign_9}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_16; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_16 = _GEN_131; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_16; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_16 = _GEN_131; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_16; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_16 = _GEN_131; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_16; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_16 = _GEN_131; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_16 = {lo_lo_hi_16, sign_9}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_16 = {lo_hi_hi_16, sign_9}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_25 = {lo_hi_16, lo_lo_16}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_16 = {hi_lo_hi_16, sign_9}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_16 = {hi_hi_hi_16, sign_9}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_16 = {hi_hi_16, hi_lo_16}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_26; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_9_0_0 = {hi_16, lo_25, lo_26}; // @[ExecuteController.scala:12:7]
wire sign_10 = _mesh_io_resp_bits_data_10_0[19]; // @[ExecuteController.scala:186:20]
wire sign_26 = _mesh_io_resp_bits_data_10_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_132 = {2{sign_10}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_17; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_17 = _GEN_132; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_17; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_17 = _GEN_132; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_17; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_17 = _GEN_132; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_17; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_17 = _GEN_132; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_17 = {lo_lo_hi_17, sign_10}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_17 = {lo_hi_hi_17, sign_10}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_27 = {lo_hi_17, lo_lo_17}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_17 = {hi_lo_hi_17, sign_10}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_17 = {hi_hi_hi_17, sign_10}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_17 = {hi_hi_17, hi_lo_17}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_28; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_10_0_0 = {hi_17, lo_27, lo_28}; // @[ExecuteController.scala:12:7]
wire sign_11 = _mesh_io_resp_bits_data_11_0[19]; // @[ExecuteController.scala:186:20]
wire sign_27 = _mesh_io_resp_bits_data_11_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_133 = {2{sign_11}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_18; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_18 = _GEN_133; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_18; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_18 = _GEN_133; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_18; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_18 = _GEN_133; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_18; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_18 = _GEN_133; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_18 = {lo_lo_hi_18, sign_11}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_18 = {lo_hi_hi_18, sign_11}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_29 = {lo_hi_18, lo_lo_18}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_18 = {hi_lo_hi_18, sign_11}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_18 = {hi_hi_hi_18, sign_11}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_18 = {hi_hi_18, hi_lo_18}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_30; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_11_0_0 = {hi_18, lo_29, lo_30}; // @[ExecuteController.scala:12:7]
wire sign_12 = _mesh_io_resp_bits_data_12_0[19]; // @[ExecuteController.scala:186:20]
wire sign_28 = _mesh_io_resp_bits_data_12_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_134 = {2{sign_12}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_19; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_19 = _GEN_134; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_19; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_19 = _GEN_134; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_19; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_19 = _GEN_134; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_19; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_19 = _GEN_134; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_19 = {lo_lo_hi_19, sign_12}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_19 = {lo_hi_hi_19, sign_12}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_31 = {lo_hi_19, lo_lo_19}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_19 = {hi_lo_hi_19, sign_12}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_19 = {hi_hi_hi_19, sign_12}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_19 = {hi_hi_19, hi_lo_19}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_32; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_12_0_0 = {hi_19, lo_31, lo_32}; // @[ExecuteController.scala:12:7]
wire sign_13 = _mesh_io_resp_bits_data_13_0[19]; // @[ExecuteController.scala:186:20]
wire sign_29 = _mesh_io_resp_bits_data_13_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_135 = {2{sign_13}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_20; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_20 = _GEN_135; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_20; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_20 = _GEN_135; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_20; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_20 = _GEN_135; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_20; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_20 = _GEN_135; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_20 = {lo_lo_hi_20, sign_13}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_20 = {lo_hi_hi_20, sign_13}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_33 = {lo_hi_20, lo_lo_20}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_20 = {hi_lo_hi_20, sign_13}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_20 = {hi_hi_hi_20, sign_13}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_20 = {hi_hi_20, hi_lo_20}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_34; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_13_0_0 = {hi_20, lo_33, lo_34}; // @[ExecuteController.scala:12:7]
wire sign_14 = _mesh_io_resp_bits_data_14_0[19]; // @[ExecuteController.scala:186:20]
wire sign_30 = _mesh_io_resp_bits_data_14_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_136 = {2{sign_14}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_21; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_21 = _GEN_136; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_21; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_21 = _GEN_136; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_21; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_21 = _GEN_136; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_21; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_21 = _GEN_136; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_21 = {lo_lo_hi_21, sign_14}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_21 = {lo_hi_hi_21, sign_14}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_35 = {lo_hi_21, lo_lo_21}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_21 = {hi_lo_hi_21, sign_14}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_21 = {hi_hi_hi_21, sign_14}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_21 = {hi_hi_21, hi_lo_21}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_36; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_14_0_0 = {hi_21, lo_35, lo_36}; // @[ExecuteController.scala:12:7]
wire sign_15 = _mesh_io_resp_bits_data_15_0[19]; // @[ExecuteController.scala:186:20]
wire sign_31 = _mesh_io_resp_bits_data_15_0[19]; // @[ExecuteController.scala:186:20]
wire [1:0] _GEN_137 = {2{sign_15}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_22; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_22 = _GEN_137; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_22; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_22 = _GEN_137; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_22; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_22 = _GEN_137; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_22; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_22 = _GEN_137; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_22 = {lo_lo_hi_22, sign_15}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_22 = {lo_hi_hi_22, sign_15}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_37 = {lo_hi_22, lo_lo_22}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_22 = {hi_lo_hi_22, sign_15}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_22 = {hi_hi_hi_22, sign_15}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_22 = {hi_hi_22, hi_lo_22}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_38; // @[Arithmetic.scala:118:14]
assign io_acc_write_0_bits_data_15_0_0 = {hi_22, lo_37, lo_38}; // @[ExecuteController.scala:12:7]
wire _io_acc_write_1_valid_T = w_bank == 2'h1; // @[ExecuteController.scala:911:19, :949:65]
wire _io_acc_write_1_valid_T_1 = start_array_outputting & _io_acc_write_1_valid_T; // @[ExecuteController.scala:270:40, :949:{55,65}]
wire _io_acc_write_1_valid_T_2 = _io_acc_write_1_valid_T_1 & w_address_is_acc_addr; // @[ExecuteController.scala:907:22, :949:{55,73}]
wire _io_acc_write_1_valid_T_3 = ~is_garbage_addr; // @[LocalAddr.scala:43:96]
wire _io_acc_write_1_valid_T_4 = _io_acc_write_1_valid_T_2 & _io_acc_write_1_valid_T_3; // @[ExecuteController.scala:949:{73,89,92}]
assign _io_acc_write_1_valid_T_5 = _io_acc_write_1_valid_T_4 & write_this_row; // @[ExecuteController.scala:919:27, :949:{89,109}]
assign io_acc_write_1_valid_0 = _io_acc_write_1_valid_T_5; // @[ExecuteController.scala:12:7, :949:109]
wire [1:0] _GEN_138 = {2{sign_16}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_23; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_23 = _GEN_138; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_23; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_23 = _GEN_138; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_23; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_23 = _GEN_138; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_23; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_23 = _GEN_138; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_23 = {lo_lo_hi_23, sign_16}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_23 = {lo_hi_hi_23, sign_16}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_39 = {lo_hi_23, lo_lo_23}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_23 = {hi_lo_hi_23, sign_16}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_23 = {hi_hi_hi_23, sign_16}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_23 = {hi_hi_23, hi_lo_23}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_40; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_0_0_0 = {hi_23, lo_39, lo_40}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_139 = {2{sign_17}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_24; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_24 = _GEN_139; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_24; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_24 = _GEN_139; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_24; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_24 = _GEN_139; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_24; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_24 = _GEN_139; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_24 = {lo_lo_hi_24, sign_17}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_24 = {lo_hi_hi_24, sign_17}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_41 = {lo_hi_24, lo_lo_24}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_24 = {hi_lo_hi_24, sign_17}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_24 = {hi_hi_hi_24, sign_17}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_24 = {hi_hi_24, hi_lo_24}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_42; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_1_0_0 = {hi_24, lo_41, lo_42}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_140 = {2{sign_18}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_25; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_25 = _GEN_140; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_25; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_25 = _GEN_140; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_25; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_25 = _GEN_140; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_25; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_25 = _GEN_140; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_25 = {lo_lo_hi_25, sign_18}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_25 = {lo_hi_hi_25, sign_18}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_43 = {lo_hi_25, lo_lo_25}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_25 = {hi_lo_hi_25, sign_18}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_25 = {hi_hi_hi_25, sign_18}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_25 = {hi_hi_25, hi_lo_25}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_44; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_2_0_0 = {hi_25, lo_43, lo_44}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_141 = {2{sign_19}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_26; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_26 = _GEN_141; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_26; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_26 = _GEN_141; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_26; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_26 = _GEN_141; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_26; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_26 = _GEN_141; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_26 = {lo_lo_hi_26, sign_19}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_26 = {lo_hi_hi_26, sign_19}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_45 = {lo_hi_26, lo_lo_26}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_26 = {hi_lo_hi_26, sign_19}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_26 = {hi_hi_hi_26, sign_19}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_26 = {hi_hi_26, hi_lo_26}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_46; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_3_0_0 = {hi_26, lo_45, lo_46}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_142 = {2{sign_20}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_27; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_27 = _GEN_142; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_27; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_27 = _GEN_142; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_27; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_27 = _GEN_142; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_27; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_27 = _GEN_142; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_27 = {lo_lo_hi_27, sign_20}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_27 = {lo_hi_hi_27, sign_20}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_47 = {lo_hi_27, lo_lo_27}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_27 = {hi_lo_hi_27, sign_20}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_27 = {hi_hi_hi_27, sign_20}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_27 = {hi_hi_27, hi_lo_27}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_48; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_4_0_0 = {hi_27, lo_47, lo_48}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_143 = {2{sign_21}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_28; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_28 = _GEN_143; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_28; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_28 = _GEN_143; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_28; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_28 = _GEN_143; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_28; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_28 = _GEN_143; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_28 = {lo_lo_hi_28, sign_21}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_28 = {lo_hi_hi_28, sign_21}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_49 = {lo_hi_28, lo_lo_28}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_28 = {hi_lo_hi_28, sign_21}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_28 = {hi_hi_hi_28, sign_21}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_28 = {hi_hi_28, hi_lo_28}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_50; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_5_0_0 = {hi_28, lo_49, lo_50}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_144 = {2{sign_22}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_29; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_29 = _GEN_144; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_29; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_29 = _GEN_144; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_29; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_29 = _GEN_144; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_29; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_29 = _GEN_144; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_29 = {lo_lo_hi_29, sign_22}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_29 = {lo_hi_hi_29, sign_22}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_51 = {lo_hi_29, lo_lo_29}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_29 = {hi_lo_hi_29, sign_22}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_29 = {hi_hi_hi_29, sign_22}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_29 = {hi_hi_29, hi_lo_29}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_52; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_6_0_0 = {hi_29, lo_51, lo_52}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_145 = {2{sign_23}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_30; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_30 = _GEN_145; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_30; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_30 = _GEN_145; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_30; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_30 = _GEN_145; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_30; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_30 = _GEN_145; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_30 = {lo_lo_hi_30, sign_23}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_30 = {lo_hi_hi_30, sign_23}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_53 = {lo_hi_30, lo_lo_30}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_30 = {hi_lo_hi_30, sign_23}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_30 = {hi_hi_hi_30, sign_23}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_30 = {hi_hi_30, hi_lo_30}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_54; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_7_0_0 = {hi_30, lo_53, lo_54}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_146 = {2{sign_24}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_31; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_31 = _GEN_146; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_31; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_31 = _GEN_146; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_31; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_31 = _GEN_146; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_31; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_31 = _GEN_146; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_31 = {lo_lo_hi_31, sign_24}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_31 = {lo_hi_hi_31, sign_24}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_55 = {lo_hi_31, lo_lo_31}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_31 = {hi_lo_hi_31, sign_24}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_31 = {hi_hi_hi_31, sign_24}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_31 = {hi_hi_31, hi_lo_31}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_56; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_8_0_0 = {hi_31, lo_55, lo_56}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_147 = {2{sign_25}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_32; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_32 = _GEN_147; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_32; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_32 = _GEN_147; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_32; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_32 = _GEN_147; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_32; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_32 = _GEN_147; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_32 = {lo_lo_hi_32, sign_25}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_32 = {lo_hi_hi_32, sign_25}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_57 = {lo_hi_32, lo_lo_32}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_32 = {hi_lo_hi_32, sign_25}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_32 = {hi_hi_hi_32, sign_25}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_32 = {hi_hi_32, hi_lo_32}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_58; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_9_0_0 = {hi_32, lo_57, lo_58}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_148 = {2{sign_26}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_33; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_33 = _GEN_148; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_33; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_33 = _GEN_148; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_33; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_33 = _GEN_148; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_33; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_33 = _GEN_148; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_33 = {lo_lo_hi_33, sign_26}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_33 = {lo_hi_hi_33, sign_26}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_59 = {lo_hi_33, lo_lo_33}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_33 = {hi_lo_hi_33, sign_26}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_33 = {hi_hi_hi_33, sign_26}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_33 = {hi_hi_33, hi_lo_33}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_60; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_10_0_0 = {hi_33, lo_59, lo_60}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_149 = {2{sign_27}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_34; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_34 = _GEN_149; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_34; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_34 = _GEN_149; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_34; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_34 = _GEN_149; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_34; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_34 = _GEN_149; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_34 = {lo_lo_hi_34, sign_27}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_34 = {lo_hi_hi_34, sign_27}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_61 = {lo_hi_34, lo_lo_34}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_34 = {hi_lo_hi_34, sign_27}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_34 = {hi_hi_hi_34, sign_27}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_34 = {hi_hi_34, hi_lo_34}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_62; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_11_0_0 = {hi_34, lo_61, lo_62}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_150 = {2{sign_28}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_35; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_35 = _GEN_150; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_35; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_35 = _GEN_150; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_35; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_35 = _GEN_150; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_35; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_35 = _GEN_150; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_35 = {lo_lo_hi_35, sign_28}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_35 = {lo_hi_hi_35, sign_28}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_63 = {lo_hi_35, lo_lo_35}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_35 = {hi_lo_hi_35, sign_28}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_35 = {hi_hi_hi_35, sign_28}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_35 = {hi_hi_35, hi_lo_35}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_64; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_12_0_0 = {hi_35, lo_63, lo_64}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_151 = {2{sign_29}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_36; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_36 = _GEN_151; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_36; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_36 = _GEN_151; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_36; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_36 = _GEN_151; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_36; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_36 = _GEN_151; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_36 = {lo_lo_hi_36, sign_29}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_36 = {lo_hi_hi_36, sign_29}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_65 = {lo_hi_36, lo_lo_36}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_36 = {hi_lo_hi_36, sign_29}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_36 = {hi_hi_hi_36, sign_29}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_36 = {hi_hi_36, hi_lo_36}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_66; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_13_0_0 = {hi_36, lo_65, lo_66}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_152 = {2{sign_30}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_37; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_37 = _GEN_152; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_37; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_37 = _GEN_152; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_37; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_37 = _GEN_152; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_37; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_37 = _GEN_152; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_37 = {lo_lo_hi_37, sign_30}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_37 = {lo_hi_hi_37, sign_30}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_67 = {lo_hi_37, lo_lo_37}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_37 = {hi_lo_hi_37, sign_30}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_37 = {hi_hi_hi_37, sign_30}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_37 = {hi_hi_37, hi_lo_37}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_68; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_14_0_0 = {hi_37, lo_67, lo_68}; // @[ExecuteController.scala:12:7]
wire [1:0] _GEN_153 = {2{sign_31}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] lo_lo_hi_38; // @[Arithmetic.scala:118:18]
assign lo_lo_hi_38 = _GEN_153; // @[Arithmetic.scala:118:18]
wire [1:0] lo_hi_hi_38; // @[Arithmetic.scala:118:18]
assign lo_hi_hi_38 = _GEN_153; // @[Arithmetic.scala:118:18]
wire [1:0] hi_lo_hi_38; // @[Arithmetic.scala:118:18]
assign hi_lo_hi_38 = _GEN_153; // @[Arithmetic.scala:118:18]
wire [1:0] hi_hi_hi_38; // @[Arithmetic.scala:118:18]
assign hi_hi_hi_38 = _GEN_153; // @[Arithmetic.scala:118:18]
wire [2:0] lo_lo_38 = {lo_lo_hi_38, sign_31}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] lo_hi_38 = {lo_hi_hi_38, sign_31}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] lo_69 = {lo_hi_38, lo_lo_38}; // @[Arithmetic.scala:118:18]
wire [2:0] hi_lo_38 = {hi_lo_hi_38, sign_31}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] hi_hi_38 = {hi_hi_hi_38, sign_31}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] hi_38 = {hi_hi_38, hi_lo_38}; // @[Arithmetic.scala:118:18]
wire [19:0] lo_70; // @[Arithmetic.scala:118:14]
assign io_acc_write_1_bits_data_15_0_0 = {hi_38, lo_69, lo_70}; // @[ExecuteController.scala:12:7]
wire mesh_completed_rob_id_fire; // @[ExecuteController.scala:966:44]
wire _T_612 = _mesh_io_resp_valid & _mesh_io_resp_bits_tag_rob_id_valid; // @[ExecuteController.scala:186:20, :970:26]
wire [4:0] output_counter_max = _output_counter_max_T[4:0]; // @[Util.scala:18:28]
wire _output_counter_T = |output_counter_max; // @[Util.scala:18:28, :19:14]
wire _GEN_154 = output_counter_max == 5'h0; // @[Util.scala:18:28, :19:28]
wire _output_counter_T_1; // @[Util.scala:19:28]
assign _output_counter_T_1 = _GEN_154; // @[Util.scala:19:28]
wire _output_counter_T_9; // @[Util.scala:29:12]
assign _output_counter_T_9 = _GEN_154; // @[Util.scala:19:28, :29:12]
wire _output_counter_T_2 = _output_counter_T | _output_counter_T_1; // @[Util.scala:19:{14,21,28}]
wire _output_counter_T_4 = ~_output_counter_T_3; // @[Util.scala:19:11]
wire _output_counter_T_5 = ~_output_counter_T_2; // @[Util.scala:19:{11,21}]
|
Generate the Verilog code corresponding to the following Chisel files.
File ResetCatchAndSync.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.{withClockAndReset, withReset}
/** Reset: asynchronous assert,
* synchronous de-assert
*
*/
class ResetCatchAndSync (sync: Int = 3) extends Module {
override def desiredName = s"ResetCatchAndSync_d${sync}"
val io = IO(new Bundle {
val sync_reset = Output(Bool())
val psd = Input(new PSDTestMode())
})
// Bypass both the resets to the flops themselves (to prevent DFT holes on
// those flops) and on the output of the synchronizer circuit (to control
// reset to any flops this circuit drives).
val post_psd_reset = Mux(io.psd.test_mode, io.psd.test_mode_reset, reset.asBool)
withReset(post_psd_reset) {
io.sync_reset := Mux(io.psd.test_mode, io.psd.test_mode_reset,
~AsyncResetSynchronizerShiftReg(true.B, sync))
}
}
object ResetCatchAndSync {
def apply(clk: Clock, rst: Bool, sync: Int = 3, name: Option[String] = None,
psd: Option[PSDTestMode] = None): Bool = {
withClockAndReset(clk, rst) {
val catcher = Module (new ResetCatchAndSync(sync))
if (name.isDefined) {catcher.suggestName(name.get)}
catcher.io.psd <> psd.getOrElse(WireDefault(0.U.asTypeOf(new PSDTestMode())))
catcher.io.sync_reset
}
}
def apply(clk: Clock, rst: Bool, sync: Int, name: String): Bool = apply(clk, rst, sync, Some(name))
def apply(clk: Clock, rst: Bool, name: String): Bool = apply(clk, rst, name = Some(name))
def apply(clk: Clock, rst: Bool, sync: Int, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, sync, Some(name), Some(psd))
def apply(clk: Clock, rst: Bool, name: String, psd: PSDTestMode): Bool =
apply(clk, rst, name = Some(name), psd = Some(psd))
}
File ResetSynchronizer.scala:
// See LICENSE for license details.
package freechips.rocketchip.prci
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.lazymodule._
import freechips.rocketchip.util.ResetCatchAndSync
/**
* Synchronizes the reset of a diplomatic clock-reset pair to its accompanying clock.
*/
class ResetSynchronizer(implicit p: Parameters) extends LazyModule {
val node = ClockAdapterNode()
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
(node.out zip node.in).map { case ((o, _), (i, _)) =>
o.clock := i.clock
o.reset := ResetCatchAndSync(i.clock, i.reset.asBool)
}
}
}
object ResetSynchronizer {
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ResetSynchronizer()).node
}
/**
* Instantiates a reset synchronizer on all clock-reset pairs in a clock group.
*/
class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule {
val node = ClockGroupAdapterNode()
lazy val module = new Impl
class Impl extends LazyRawModuleImp(this) {
(node.out zip node.in).map { case ((oG, _), (iG, _)) =>
(oG.member.data zip iG.member.data).foreach { case (o, i) =>
o.clock := i.clock
o.reset := ResetCatchAndSync(i.clock, i.reset.asBool)
}
}
}
}
object ClockGroupResetSynchronizer {
def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
File MixedNode.scala:
package org.chipsalliance.diplomacy.nodes
import chisel3.{Data, DontCare, Wire}
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.{Field, Parameters}
import org.chipsalliance.diplomacy.ValName
import org.chipsalliance.diplomacy.sourceLine
/** One side metadata of a [[Dangle]].
*
* Describes one side of an edge going into or out of a [[BaseNode]].
*
* @param serial
* the global [[BaseNode.serial]] number of the [[BaseNode]] that this [[HalfEdge]] connects to.
* @param index
* the `index` in the [[BaseNode]]'s input or output port list that this [[HalfEdge]] belongs to.
*/
case class HalfEdge(serial: Int, index: Int) extends Ordered[HalfEdge] {
import scala.math.Ordered.orderingToOrdered
def compare(that: HalfEdge): Int = HalfEdge.unapply(this).compare(HalfEdge.unapply(that))
}
/** [[Dangle]] captures the `IO` information of a [[LazyModule]] and which two [[BaseNode]]s the [[Edges]]/[[Bundle]]
* connects.
*
* [[Dangle]]s are generated by [[BaseNode.instantiate]] using [[MixedNode.danglesOut]] and [[MixedNode.danglesIn]] ,
* [[LazyModuleImp.instantiate]] connects those that go to internal or explicit IO connections in a [[LazyModule]].
*
* @param source
* the source [[HalfEdge]] of this [[Dangle]], which captures the source [[BaseNode]] and the port `index` within
* that [[BaseNode]].
* @param sink
* sink [[HalfEdge]] of this [[Dangle]], which captures the sink [[BaseNode]] and the port `index` within that
* [[BaseNode]].
* @param flipped
* flip or not in [[AutoBundle.makeElements]]. If true this corresponds to `danglesOut`, if false it corresponds to
* `danglesIn`.
* @param dataOpt
* actual [[Data]] for the hardware connection. Can be empty if this belongs to a cloned module
*/
case class Dangle(source: HalfEdge, sink: HalfEdge, flipped: Boolean, name: String, dataOpt: Option[Data]) {
def data = dataOpt.get
}
/** [[Edges]] is a collection of parameters describing the functionality and connection for an interface, which is often
* derived from the interconnection protocol and can inform the parameterization of the hardware bundles that actually
* implement the protocol.
*/
case class Edges[EI, EO](in: Seq[EI], out: Seq[EO])
/** A field available in [[Parameters]] used to determine whether [[InwardNodeImp.monitor]] will be called. */
case object MonitorsEnabled extends Field[Boolean](true)
/** When rendering the edge in a graphical format, flip the order in which the edges' source and sink are presented.
*
* For example, when rendering graphML, yEd by default tries to put the source node vertically above the sink node, but
* [[RenderFlipped]] inverts this relationship. When a particular [[LazyModule]] contains both source nodes and sink
* nodes, flipping the rendering of one node's edge will usual produce a more concise visual layout for the
* [[LazyModule]].
*/
case object RenderFlipped extends Field[Boolean](false)
/** The sealed node class in the package, all node are derived from it.
*
* @param inner
* Sink interface implementation.
* @param outer
* Source interface implementation.
* @param valName
* val name of this node.
* @tparam DI
* Downward-flowing parameters received on the inner side of the node. It is usually a brunch of parameters
* describing the protocol parameters from a source. For an [[InwardNode]], it is determined by the connected
* [[OutwardNode]]. Since it can be connected to multiple sources, this parameter is always a Seq of source port
* parameters.
* @tparam UI
* Upward-flowing parameters generated by the inner side of the node. It is usually a brunch of parameters describing
* the protocol parameters of a sink. For an [[InwardNode]], it is determined itself.
* @tparam EI
* Edge Parameters describing a connection on the inner side of the node. It is usually a brunch of transfers
* specified for a sink according to protocol.
* @tparam BI
* Bundle type used when connecting to the inner side of the node. It is a hardware interface of this sink interface.
* It should extends from [[chisel3.Data]], which represents the real hardware.
* @tparam DO
* Downward-flowing parameters generated on the outer side of the node. It is usually a brunch of parameters
* describing the protocol parameters of a source. For an [[OutwardNode]], it is determined itself.
* @tparam UO
* Upward-flowing parameters received by the outer side of the node. It is usually a brunch of parameters describing
* the protocol parameters from a sink. For an [[OutwardNode]], it is determined by the connected [[InwardNode]].
* Since it can be connected to multiple sinks, this parameter is always a Seq of sink port parameters.
* @tparam EO
* Edge Parameters describing a connection on the outer side of the node. It is usually a brunch of transfers
* specified for a source according to protocol.
* @tparam BO
* Bundle type used when connecting to the outer side of the node. It is a hardware interface of this source
* interface. It should extends from [[chisel3.Data]], which represents the real hardware.
*
* @note
* Call Graph of [[MixedNode]]
* - line `─`: source is process by a function and generate pass to others
* - Arrow `→`: target of arrow is generated by source
*
* {{{
* (from the other node)
* ┌─────────────────────────────────────────────────────────[[InwardNode.uiParams]]─────────────┐
* ↓ │
* (binding node when elaboration) [[OutwardNode.uoParams]]────────────────────────[[MixedNode.mapParamsU]]→──────────┐ │
* [[InwardNode.accPI]] │ │ │
* │ │ (based on protocol) │
* │ │ [[MixedNode.inner.edgeI]] │
* │ │ ↓ │
* ↓ │ │ │
* (immobilize after elaboration) (inward port from [[OutwardNode]]) │ ↓ │
* [[InwardNode.iBindings]]──┐ [[MixedNode.iDirectPorts]]────────────────────→[[MixedNode.iPorts]] [[InwardNode.uiParams]] │
* │ │ ↑ │ │ │
* │ │ │ [[OutwardNode.doParams]] │ │
* │ │ │ (from the other node) │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* │ │ │ └────────┬──────────────┤ │
* │ │ │ │ │ │
* │ │ │ │ (based on protocol) │
* │ │ │ │ [[MixedNode.inner.edgeI]] │
* │ │ │ │ │ │
* │ │ (from the other node) │ ↓ │
* │ └───[[OutwardNode.oPortMapping]] [[OutwardNode.oStar]] │ [[MixedNode.edgesIn]]───┐ │
* │ ↑ ↑ │ │ ↓ │
* │ │ │ │ │ [[MixedNode.in]] │
* │ │ │ │ ↓ ↑ │
* │ (solve star connection) │ │ │ [[MixedNode.bundleIn]]──┘ │
* ├───[[MixedNode.resolveStar]]→─┼─────────────────────────────┤ └────────────────────────────────────┐ │
* │ │ │ [[MixedNode.bundleOut]]─┐ │ │
* │ │ │ ↑ ↓ │ │
* │ │ │ │ [[MixedNode.out]] │ │
* │ ↓ ↓ │ ↑ │ │
* │ ┌─────[[InwardNode.iPortMapping]] [[InwardNode.iStar]] [[MixedNode.edgesOut]]──┘ │ │
* │ │ (from the other node) ↑ │ │
* │ │ │ │ │ │
* │ │ │ [[MixedNode.outer.edgeO]] │ │
* │ │ │ (based on protocol) │ │
* │ │ │ │ │ │
* │ │ │ ┌────────────────────────────────────────┤ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* │ │ │ │ │ │ │
* (immobilize after elaboration)│ ↓ │ │ │ │
* [[OutwardNode.oBindings]]─┘ [[MixedNode.oDirectPorts]]───→[[MixedNode.oPorts]] [[OutwardNode.doParams]] │ │
* ↑ (inward port from [[OutwardNode]]) │ │ │ │
* │ ┌─────────────────────────────────────────┤ │ │ │
* │ │ │ │ │ │
* │ │ │ │ │ │
* [[OutwardNode.accPO]] │ ↓ │ │ │
* (binding node when elaboration) │ [[InwardNode.diParams]]─────→[[MixedNode.mapParamsD]]────────────────────────────┘ │ │
* │ ↑ │ │
* │ └──────────────────────────────────────────────────────────────────────────────────────────┘ │
* └──────────────────────────────────────────────────────────────────────────────────────────────────────────┘
* }}}
*/
abstract class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
val inner: InwardNodeImp[DI, UI, EI, BI],
val outer: OutwardNodeImp[DO, UO, EO, BO]
)(
implicit valName: ValName)
extends BaseNode
with NodeHandle[DI, UI, EI, BI, DO, UO, EO, BO]
with InwardNode[DI, UI, BI]
with OutwardNode[DO, UO, BO] {
// Generate a [[NodeHandle]] with inward and outward node are both this node.
val inward = this
val outward = this
/** Debug info of nodes binding. */
def bindingInfo: String = s"""$iBindingInfo
|$oBindingInfo
|""".stripMargin
/** Debug info of ports connecting. */
def connectedPortsInfo: String = s"""${oPorts.size} outward ports connected: [${oPorts.map(_._2.name).mkString(",")}]
|${iPorts.size} inward ports connected: [${iPorts.map(_._2.name).mkString(",")}]
|""".stripMargin
/** Debug info of parameters propagations. */
def parametersInfo: String = s"""${doParams.size} downstream outward parameters: [${doParams.mkString(",")}]
|${uoParams.size} upstream outward parameters: [${uoParams.mkString(",")}]
|${diParams.size} downstream inward parameters: [${diParams.mkString(",")}]
|${uiParams.size} upstream inward parameters: [${uiParams.mkString(",")}]
|""".stripMargin
/** For a given node, converts [[OutwardNode.accPO]] and [[InwardNode.accPI]] to [[MixedNode.oPortMapping]] and
* [[MixedNode.iPortMapping]].
*
* Given counts of known inward and outward binding and inward and outward star bindings, return the resolved inward
* stars and outward stars.
*
* This method will also validate the arguments and throw a runtime error if the values are unsuitable for this type
* of node.
*
* @param iKnown
* Number of known-size ([[BIND_ONCE]]) input bindings.
* @param oKnown
* Number of known-size ([[BIND_ONCE]]) output bindings.
* @param iStar
* Number of unknown size ([[BIND_STAR]]) input bindings.
* @param oStar
* Number of unknown size ([[BIND_STAR]]) output bindings.
* @return
* A Tuple of the resolved number of input and output connections.
*/
protected[diplomacy] def resolveStar(iKnown: Int, oKnown: Int, iStar: Int, oStar: Int): (Int, Int)
/** Function to generate downward-flowing outward params from the downward-flowing input params and the current output
* ports.
*
* @param n
* The size of the output sequence to generate.
* @param p
* Sequence of downward-flowing input parameters of this node.
* @return
* A `n`-sized sequence of downward-flowing output edge parameters.
*/
protected[diplomacy] def mapParamsD(n: Int, p: Seq[DI]): Seq[DO]
/** Function to generate upward-flowing input parameters from the upward-flowing output parameters [[uiParams]].
*
* @param n
* Size of the output sequence.
* @param p
* Upward-flowing output edge parameters.
* @return
* A n-sized sequence of upward-flowing input edge parameters.
*/
protected[diplomacy] def mapParamsU(n: Int, p: Seq[UO]): Seq[UI]
/** @return
* The sink cardinality of the node, the number of outputs bound with [[BIND_QUERY]] summed with inputs bound with
* [[BIND_STAR]].
*/
protected[diplomacy] lazy val sinkCard: Int = oBindings.count(_._3 == BIND_QUERY) + iBindings.count(_._3 == BIND_STAR)
/** @return
* The source cardinality of this node, the number of inputs bound with [[BIND_QUERY]] summed with the number of
* output bindings bound with [[BIND_STAR]].
*/
protected[diplomacy] lazy val sourceCard: Int =
iBindings.count(_._3 == BIND_QUERY) + oBindings.count(_._3 == BIND_STAR)
/** @return list of nodes involved in flex bindings with this node. */
protected[diplomacy] lazy val flexes: Seq[BaseNode] =
oBindings.filter(_._3 == BIND_FLEX).map(_._2) ++ iBindings.filter(_._3 == BIND_FLEX).map(_._2)
/** Resolves the flex to be either source or sink and returns the offset where the [[BIND_STAR]] operators begin
* greedily taking up the remaining connections.
*
* @return
* A value >= 0 if it is sink cardinality, a negative value for source cardinality. The magnitude of the return
* value is not relevant.
*/
protected[diplomacy] lazy val flexOffset: Int = {
/** Recursively performs a depth-first search of the [[flexes]], [[BaseNode]]s connected to this node with flex
* operators. The algorithm bottoms out when we either get to a node we have already visited or when we get to a
* connection that is not a flex and can set the direction for us. Otherwise, recurse by visiting the `flexes` of
* each node in the current set and decide whether they should be added to the set or not.
*
* @return
* the mapping of [[BaseNode]] indexed by their serial numbers.
*/
def DFS(v: BaseNode, visited: Map[Int, BaseNode]): Map[Int, BaseNode] = {
if (visited.contains(v.serial) || !v.flexibleArityDirection) {
visited
} else {
v.flexes.foldLeft(visited + (v.serial -> v))((sum, n) => DFS(n, sum))
}
}
/** Determine which [[BaseNode]] are involved in resolving the flex connections to/from this node.
*
* @example
* {{{
* a :*=* b :*=* c
* d :*=* b
* e :*=* f
* }}}
*
* `flexSet` for `a`, `b`, `c`, or `d` will be `Set(a, b, c, d)` `flexSet` for `e` or `f` will be `Set(e,f)`
*/
val flexSet = DFS(this, Map()).values
/** The total number of :*= operators where we're on the left. */
val allSink = flexSet.map(_.sinkCard).sum
/** The total number of :=* operators used when we're on the right. */
val allSource = flexSet.map(_.sourceCard).sum
require(
allSink == 0 || allSource == 0,
s"The nodes ${flexSet.map(_.name)} which are inter-connected by :*=* have ${allSink} :*= operators and ${allSource} :=* operators connected to them, making it impossible to determine cardinality inference direction."
)
allSink - allSource
}
/** @return A value >= 0 if it is sink cardinality, a negative value for source cardinality. */
protected[diplomacy] def edgeArityDirection(n: BaseNode): Int = {
if (flexibleArityDirection) flexOffset
else if (n.flexibleArityDirection) n.flexOffset
else 0
}
/** For a node which is connected between two nodes, select the one that will influence the direction of the flex
* resolution.
*/
protected[diplomacy] def edgeAritySelect(n: BaseNode, l: => Int, r: => Int): Int = {
val dir = edgeArityDirection(n)
if (dir < 0) l
else if (dir > 0) r
else 1
}
/** Ensure that the same node is not visited twice in resolving `:*=`, etc operators. */
private var starCycleGuard = false
/** Resolve all the star operators into concrete indicies. As connections are being made, some may be "star"
* connections which need to be resolved. In some way to determine how many actual edges they correspond to. We also
* need to build up the ranges of edges which correspond to each binding operator, so that We can apply the correct
* edge parameters and later build up correct bundle connections.
*
* [[oPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that oPort (binding
* operator). [[iPortMapping]]: `Seq[(Int, Int)]` where each item is the range of edges corresponding to that iPort
* (binding operator). [[oStar]]: `Int` the value to return for this node `N` for any `N :*= foo` or `N :*=* foo :*=
* bar` [[iStar]]: `Int` the value to return for this node `N` for any `foo :=* N` or `bar :=* foo :*=* N`
*/
protected[diplomacy] lazy val (
oPortMapping: Seq[(Int, Int)],
iPortMapping: Seq[(Int, Int)],
oStar: Int,
iStar: Int
) = {
try {
if (starCycleGuard) throw StarCycleException()
starCycleGuard = true
// For a given node N...
// Number of foo :=* N
// + Number of bar :=* foo :*=* N
val oStars = oBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) < 0)
}
// Number of N :*= foo
// + Number of N :*=* foo :*= bar
val iStars = iBindings.count { case (_, n, b, _, _) =>
b == BIND_STAR || (b == BIND_FLEX && edgeArityDirection(n) > 0)
}
// 1 for foo := N
// + bar.iStar for bar :*= foo :*=* N
// + foo.iStar for foo :*= N
// + 0 for foo :=* N
val oKnown = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, 0, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => 0
}
}.sum
// 1 for N := foo
// + bar.oStar for N :*=* foo :=* bar
// + foo.oStar for N :=* foo
// + 0 for N :*= foo
val iKnown = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, 0)
case BIND_QUERY => n.oStar
case BIND_STAR => 0
}
}.sum
// Resolve star depends on the node subclass to implement the algorithm for this.
val (iStar, oStar) = resolveStar(iKnown, oKnown, iStars, oStars)
// Cumulative list of resolved outward binding range starting points
val oSum = oBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, oStar, n.iStar)
case BIND_QUERY => n.iStar
case BIND_STAR => oStar
}
}.scanLeft(0)(_ + _)
// Cumulative list of resolved inward binding range starting points
val iSum = iBindings.map { case (_, n, b, _, _) =>
b match {
case BIND_ONCE => 1
case BIND_FLEX => edgeAritySelect(n, n.oStar, iStar)
case BIND_QUERY => n.oStar
case BIND_STAR => iStar
}
}.scanLeft(0)(_ + _)
// Create ranges for each binding based on the running sums and return
// those along with resolved values for the star operations.
(oSum.init.zip(oSum.tail), iSum.init.zip(iSum.tail), oStar, iStar)
} catch {
case c: StarCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Sequence of inward ports.
*
* This should be called after all star bindings are resolved.
*
* Each element is: `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding.
* `n` Instance of inward node. `p` View of [[Parameters]] where this connection was made. `s` Source info where this
* connection was made in the source code.
*/
protected[diplomacy] lazy val oDirectPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] =
oBindings.flatMap { case (i, n, _, p, s) =>
// for each binding operator in this node, look at what it connects to
val (start, end) = n.iPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
/** Sequence of outward ports.
*
* This should be called after all star bindings are resolved.
*
* `j` Port index of this binding in the Node's [[oPortMapping]] on the other side of the binding. `n` Instance of
* outward node. `p` View of [[Parameters]] where this connection was made. `s` [[SourceInfo]] where this connection
* was made in the source code.
*/
protected[diplomacy] lazy val iDirectPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] =
iBindings.flatMap { case (i, n, _, p, s) =>
// query this port index range of this node in the other side of node.
val (start, end) = n.oPortMapping(i)
(start until end).map { j => (j, n, p, s) }
}
// Ephemeral nodes ( which have non-None iForward/oForward) have in_degree = out_degree
// Thus, there must exist an Eulerian path and the below algorithms terminate
@scala.annotation.tailrec
private def oTrace(
tuple: (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)
): (Int, InwardNode[DO, UO, BO], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.iForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => oTrace((j, m, p, s))
}
}
@scala.annotation.tailrec
private def iTrace(
tuple: (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)
): (Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo) = tuple match {
case (i, n, p, s) => n.oForward(i) match {
case None => (i, n, p, s)
case Some((j, m)) => iTrace((j, m, p, s))
}
}
/** Final output ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - Numeric index of this binding in the [[InwardNode]] on the other end.
* - [[InwardNode]] on the other end of this binding.
* - A view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val oPorts: Seq[(Int, InwardNode[DO, UO, BO], Parameters, SourceInfo)] = oDirectPorts.map(oTrace)
/** Final input ports after all stars and port forwarding (e.g. [[EphemeralNode]]s) have been resolved.
*
* Each Port is a tuple of:
* - numeric index of this binding in [[OutwardNode]] on the other end.
* - [[OutwardNode]] on the other end of this binding.
* - a view of [[Parameters]] where the binding occurred.
* - [[SourceInfo]] for source-level error reporting.
*/
lazy val iPorts: Seq[(Int, OutwardNode[DI, UI, BI], Parameters, SourceInfo)] = iDirectPorts.map(iTrace)
private var oParamsCycleGuard = false
protected[diplomacy] lazy val diParams: Seq[DI] = iPorts.map { case (i, n, _, _) => n.doParams(i) }
protected[diplomacy] lazy val doParams: Seq[DO] = {
try {
if (oParamsCycleGuard) throw DownwardCycleException()
oParamsCycleGuard = true
val o = mapParamsD(oPorts.size, diParams)
require(
o.size == oPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of outward ports should equal the number of produced outward parameters.
|$context
|$connectedPortsInfo
|Downstreamed inward parameters: [${diParams.mkString(",")}]
|Produced outward parameters: [${o.mkString(",")}]
|""".stripMargin
)
o.map(outer.mixO(_, this))
} catch {
case c: DownwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
private var iParamsCycleGuard = false
protected[diplomacy] lazy val uoParams: Seq[UO] = oPorts.map { case (o, n, _, _) => n.uiParams(o) }
protected[diplomacy] lazy val uiParams: Seq[UI] = {
try {
if (iParamsCycleGuard) throw UpwardCycleException()
iParamsCycleGuard = true
val i = mapParamsU(iPorts.size, uoParams)
require(
i.size == iPorts.size,
s"""Diplomacy has detected a problem with your graph:
|At the following node, the number of inward ports should equal the number of produced inward parameters.
|$context
|$connectedPortsInfo
|Upstreamed outward parameters: [${uoParams.mkString(",")}]
|Produced inward parameters: [${i.mkString(",")}]
|""".stripMargin
)
i.map(inner.mixI(_, this))
} catch {
case c: UpwardCycleException => throw c.copy(loop = context +: c.loop)
}
}
/** Outward edge parameters. */
protected[diplomacy] lazy val edgesOut: Seq[EO] =
(oPorts.zip(doParams)).map { case ((i, n, p, s), o) => outer.edgeO(o, n.uiParams(i), p, s) }
/** Inward edge parameters. */
protected[diplomacy] lazy val edgesIn: Seq[EI] =
(iPorts.zip(uiParams)).map { case ((o, n, p, s), i) => inner.edgeI(n.doParams(o), i, p, s) }
/** A tuple of the input edge parameters and output edge parameters for the edges bound to this node.
*
* If you need to access to the edges of a foreign Node, use this method (in/out create bundles).
*/
lazy val edges: Edges[EI, EO] = Edges(edgesIn, edgesOut)
/** Create actual Wires corresponding to the Bundles parameterized by the outward edges of this node. */
protected[diplomacy] lazy val bundleOut: Seq[BO] = edgesOut.map { e =>
val x = Wire(outer.bundleO(e)).suggestName(s"${valName.value}Out")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
/** Create actual Wires corresponding to the Bundles parameterized by the inward edges of this node. */
protected[diplomacy] lazy val bundleIn: Seq[BI] = edgesIn.map { e =>
val x = Wire(inner.bundleI(e)).suggestName(s"${valName.value}In")
// TODO: Don't care unconnected forwarded diplomatic signals for compatibility issue,
// In the future, we should add an option to decide whether allowing unconnected in the LazyModule
x := DontCare
x
}
private def emptyDanglesOut: Seq[Dangle] = oPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(serial, i),
sink = HalfEdge(n.serial, j),
flipped = false,
name = wirePrefix + "out",
dataOpt = None
)
}
private def emptyDanglesIn: Seq[Dangle] = iPorts.zipWithIndex.map { case ((j, n, _, _), i) =>
Dangle(
source = HalfEdge(n.serial, j),
sink = HalfEdge(serial, i),
flipped = true,
name = wirePrefix + "in",
dataOpt = None
)
}
/** Create the [[Dangle]]s which describe the connections from this node output to other nodes inputs. */
protected[diplomacy] def danglesOut: Seq[Dangle] = emptyDanglesOut.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleOut(i)))
}
/** Create the [[Dangle]]s which describe the connections from this node input from other nodes outputs. */
protected[diplomacy] def danglesIn: Seq[Dangle] = emptyDanglesIn.zipWithIndex.map { case (d, i) =>
d.copy(dataOpt = Some(bundleIn(i)))
}
private[diplomacy] var instantiated = false
/** Gather Bundle and edge parameters of outward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def out: Seq[(BO, EO)] = {
require(
instantiated,
s"$name.out should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleOut.zip(edgesOut)
}
/** Gather Bundle and edge parameters of inward ports.
*
* Accessors to the result of negotiation to be used within [[LazyModuleImp]] Code. Should only be used within
* [[LazyModuleImp]] code or after its instantiation has completed.
*/
def in: Seq[(BI, EI)] = {
require(
instantiated,
s"$name.in should not be called until after instantiation of its parent LazyModule.module has begun"
)
bundleIn.zip(edgesIn)
}
/** Actually instantiate this node during [[LazyModuleImp]] evaluation. Mark that it's safe to use the Bundle wires,
* instantiate monitors on all input ports if appropriate, and return all the dangles of this node.
*/
protected[diplomacy] def instantiate(): Seq[Dangle] = {
instantiated = true
if (!circuitIdentity) {
(iPorts.zip(in)).foreach { case ((_, _, p, _), (b, e)) => if (p(MonitorsEnabled)) inner.monitor(b, e) }
}
danglesOut ++ danglesIn
}
protected[diplomacy] def cloneDangles(): Seq[Dangle] = emptyDanglesOut ++ emptyDanglesIn
/** Connects the outward part of a node with the inward part of this node. */
protected[diplomacy] def bind(
h: OutwardNode[DI, UI, BI],
binding: NodeBinding
)(
implicit p: Parameters,
sourceInfo: SourceInfo
): Unit = {
val x = this // x := y
val y = h
sourceLine(sourceInfo, " at ", "")
val i = x.iPushed
val o = y.oPushed
y.oPush(
i,
x,
binding match {
case BIND_ONCE => BIND_ONCE
case BIND_FLEX => BIND_FLEX
case BIND_STAR => BIND_QUERY
case BIND_QUERY => BIND_STAR
}
)
x.iPush(o, y, binding)
}
/* Metadata for printing the node graph. */
def inputs: Seq[(OutwardNode[DI, UI, BI], RenderedEdge)] = (iPorts.zip(edgesIn)).map { case ((_, n, p, _), e) =>
val re = inner.render(e)
(n, re.copy(flipped = re.flipped != p(RenderFlipped)))
}
/** Metadata for printing the node graph */
def outputs: Seq[(InwardNode[DO, UO, BO], RenderedEdge)] = oPorts.map { case (i, n, _, _) => (n, n.inputs(i)._2) }
}
|
module ClockGroupResetSynchronizer( // @[ResetSynchronizer.scala:35:9]
input auto_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25]
);
wire auto_in_member_allClocks_uncore_clock_0 = auto_in_member_allClocks_uncore_clock; // @[ResetSynchronizer.scala:35:9]
wire auto_in_member_allClocks_uncore_reset_0 = auto_in_member_allClocks_uncore_reset; // @[ResetSynchronizer.scala:35:9]
wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31]
wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31]
wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25]
wire _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:63]
wire _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_1_test_mode = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire _nodeOut_member_allClocks_uncore_reset_catcher_io_psd_WIRE_1_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:41:50]
wire nodeIn_member_allClocks_uncore_clock = auto_in_member_allClocks_uncore_clock_0; // @[ResetSynchronizer.scala:35:9]
wire nodeIn_member_allClocks_uncore_reset = auto_in_member_allClocks_uncore_reset_0; // @[ResetSynchronizer.scala:35:9]
wire nodeOut_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17]
wire nodeOut_member_allClocks_uncore_reset; // @[MixedNode.scala:542:17]
wire auto_out_member_allClocks_uncore_clock_0; // @[ResetSynchronizer.scala:35:9]
wire auto_out_member_allClocks_uncore_reset_0; // @[ResetSynchronizer.scala:35:9]
assign nodeOut_member_allClocks_uncore_clock = nodeIn_member_allClocks_uncore_clock; // @[MixedNode.scala:542:17, :551:17]
wire _nodeOut_member_allClocks_uncore_reset_T = nodeIn_member_allClocks_uncore_reset; // @[ResetSynchronizer.scala:39:55]
assign auto_out_member_allClocks_uncore_clock_0 = nodeOut_member_allClocks_uncore_clock; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_uncore_reset_0 = nodeOut_member_allClocks_uncore_reset; // @[ResetSynchronizer.scala:35:9]
ResetCatchAndSync_d3_2 nodeOut_member_allClocks_uncore_reset_catcher ( // @[ResetCatchAndSync.scala:39:28]
.clock (nodeIn_member_allClocks_uncore_clock), // @[MixedNode.scala:551:17]
.reset (_nodeOut_member_allClocks_uncore_reset_T), // @[ResetSynchronizer.scala:39:55]
.io_sync_reset (nodeOut_member_allClocks_uncore_reset)
); // @[ResetCatchAndSync.scala:39:28]
assign auto_out_member_allClocks_uncore_clock = auto_out_member_allClocks_uncore_clock_0; // @[ResetSynchronizer.scala:35:9]
assign auto_out_member_allClocks_uncore_reset = auto_out_member_allClocks_uncore_reset_0; // @[ResetSynchronizer.scala:35:9]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File DMACommandTracker.scala:
package gemmini
import chisel3._
import chisel3.util._
// This module is meant to go inside the Load controller, where it can track which commands are currently
// in flight and which are completed
class DMACommandTracker[T <: Data](val nCmds: Int, val maxBytes: Int, tag_t: => T) extends Module {
def cmd_id_t = UInt((log2Ceil(nCmds) max 1).W)
val io = IO(new Bundle {
// TODO is there an existing decoupled interface in the standard library which matches this use-case?
val alloc = new Bundle {
val valid = Input(Bool())
val ready = Output(Bool())
class BitsT(tag_t: => T, cmd_id_t: UInt) extends Bundle {
// This was only spun off as its own class to resolve CloneType errors
val tag = Input(tag_t.cloneType)
val bytes_to_read = Input(UInt(log2Up(maxBytes+1).W))
val cmd_id = Output(cmd_id_t.cloneType)
}
val bits = new BitsT(tag_t.cloneType, cmd_id_t.cloneType)
def fire(dummy: Int = 0) = valid && ready
}
class RequestReturnedT(cmd_id_t: UInt) extends Bundle {
// This was only spun off as its own class to resolve CloneType errors
val bytes_read = UInt(log2Up(maxBytes+1).W)
val cmd_id = cmd_id_t.cloneType
}
val request_returned = Flipped(Valid(new RequestReturnedT(cmd_id_t.cloneType)))
class CmdCompletedT(cmd_id_t: UInt, tag_t: T) extends Bundle {
val cmd_id = cmd_id_t.cloneType
val tag = tag_t.cloneType
}
val cmd_completed = Decoupled(new CmdCompletedT(cmd_id_t.cloneType, tag_t.cloneType))
val busy = Output(Bool())
})
class Entry extends Bundle {
val valid = Bool()
val tag = tag_t.cloneType
val bytes_left = UInt(log2Up(maxBytes+1).W)
def init(dummy: Int = 0): Unit = {
valid := false.B
}
}
// val cmds = RegInit(VecInit(Seq.fill(nCmds)(entry_init)))
val cmds = Reg(Vec(nCmds, new Entry))
val cmd_valids = cmds.map(_.valid)
val next_empty_alloc = MuxCase(0.U, cmd_valids.zipWithIndex.map { case (v, i) => (!v) -> i.U })
io.alloc.ready := !cmd_valids.reduce(_ && _)
io.alloc.bits.cmd_id := next_empty_alloc
io.busy := cmd_valids.reduce(_ || _)
val cmd_completed_id = MuxCase(0.U, cmds.zipWithIndex.map { case (cmd, i) =>
(cmd.valid && cmd.bytes_left === 0.U) -> i.U
})
io.cmd_completed.valid := cmds.map(cmd => cmd.valid && cmd.bytes_left === 0.U).reduce(_ || _)
io.cmd_completed.bits.cmd_id := cmd_completed_id
io.cmd_completed.bits.tag := cmds(cmd_completed_id).tag
when (io.alloc.fire()) {
cmds(next_empty_alloc).valid := true.B
cmds(next_empty_alloc).tag := io.alloc.bits.tag
cmds(next_empty_alloc).bytes_left := io.alloc.bits.bytes_to_read
}
when (io.request_returned.fire) {
val cmd_id = io.request_returned.bits.cmd_id
cmds(cmd_id).bytes_left := cmds(cmd_id).bytes_left - io.request_returned.bits.bytes_read
assert(cmds(cmd_id).valid)
assert(cmds(cmd_id).bytes_left >= io.request_returned.bits.bytes_read)
}
when (io.cmd_completed.fire) {
cmds(io.cmd_completed.bits.cmd_id).valid := false.B
}
when (reset.asBool) {
cmds.foreach(_.init())
}
}
|
module DMACommandTracker_1( // @[DMACommandTracker.scala:9:7]
input clock, // @[DMACommandTracker.scala:9:7]
input reset, // @[DMACommandTracker.scala:9:7]
input io_alloc_valid, // @[DMACommandTracker.scala:12:14]
output io_alloc_ready, // @[DMACommandTracker.scala:12:14]
input [5:0] io_alloc_bits_tag_rob_id, // @[DMACommandTracker.scala:12:14]
input [14:0] io_alloc_bits_bytes_to_read, // @[DMACommandTracker.scala:12:14]
output [2:0] io_alloc_bits_cmd_id, // @[DMACommandTracker.scala:12:14]
input io_request_returned_valid, // @[DMACommandTracker.scala:12:14]
input [2:0] io_request_returned_bits_cmd_id, // @[DMACommandTracker.scala:12:14]
input io_cmd_completed_ready, // @[DMACommandTracker.scala:12:14]
output io_cmd_completed_valid, // @[DMACommandTracker.scala:12:14]
output [5:0] io_cmd_completed_bits_tag_rob_id, // @[DMACommandTracker.scala:12:14]
output io_busy // @[DMACommandTracker.scala:12:14]
);
wire io_alloc_valid_0 = io_alloc_valid; // @[DMACommandTracker.scala:9:7]
wire [5:0] io_alloc_bits_tag_rob_id_0 = io_alloc_bits_tag_rob_id; // @[DMACommandTracker.scala:9:7]
wire [14:0] io_alloc_bits_bytes_to_read_0 = io_alloc_bits_bytes_to_read; // @[DMACommandTracker.scala:9:7]
wire io_request_returned_valid_0 = io_request_returned_valid; // @[DMACommandTracker.scala:9:7]
wire [2:0] io_request_returned_bits_cmd_id_0 = io_request_returned_bits_cmd_id; // @[DMACommandTracker.scala:9:7]
wire io_cmd_completed_ready_0 = io_cmd_completed_ready; // @[DMACommandTracker.scala:9:7]
wire [14:0] io_request_returned_bits_bytes_read = 15'h1; // @[DMACommandTracker.scala:9:7]
wire _io_alloc_ready_T_4; // @[DMACommandTracker.scala:66:21]
wire [2:0] next_empty_alloc; // @[Mux.scala:126:16]
wire _io_cmd_completed_valid_T_13; // @[DMACommandTracker.scala:74:91]
wire [2:0] cmd_completed_id; // @[Mux.scala:126:16]
wire _io_busy_T_3; // @[DMACommandTracker.scala:69:34]
wire [2:0] io_alloc_bits_cmd_id_0; // @[DMACommandTracker.scala:9:7]
wire io_alloc_ready_0; // @[DMACommandTracker.scala:9:7]
wire [5:0] io_cmd_completed_bits_tag_rob_id_0; // @[DMACommandTracker.scala:9:7]
wire [2:0] io_cmd_completed_bits_cmd_id; // @[DMACommandTracker.scala:9:7]
wire io_cmd_completed_valid_0; // @[DMACommandTracker.scala:9:7]
wire io_busy_0; // @[DMACommandTracker.scala:9:7]
reg cmds_0_valid; // @[DMACommandTracker.scala:61:17]
reg [5:0] cmds_0_tag_rob_id; // @[DMACommandTracker.scala:61:17]
reg [14:0] cmds_0_bytes_left; // @[DMACommandTracker.scala:61:17]
reg cmds_1_valid; // @[DMACommandTracker.scala:61:17]
reg [5:0] cmds_1_tag_rob_id; // @[DMACommandTracker.scala:61:17]
reg [14:0] cmds_1_bytes_left; // @[DMACommandTracker.scala:61:17]
reg cmds_2_valid; // @[DMACommandTracker.scala:61:17]
reg [5:0] cmds_2_tag_rob_id; // @[DMACommandTracker.scala:61:17]
reg [14:0] cmds_2_bytes_left; // @[DMACommandTracker.scala:61:17]
reg cmds_3_valid; // @[DMACommandTracker.scala:61:17]
reg [5:0] cmds_3_tag_rob_id; // @[DMACommandTracker.scala:61:17]
reg [14:0] cmds_3_bytes_left; // @[DMACommandTracker.scala:61:17]
reg cmds_4_valid; // @[DMACommandTracker.scala:61:17]
reg [5:0] cmds_4_tag_rob_id; // @[DMACommandTracker.scala:61:17]
reg [14:0] cmds_4_bytes_left; // @[DMACommandTracker.scala:61:17]
wire _next_empty_alloc_T = ~cmds_0_valid; // @[DMACommandTracker.scala:61:17, :64:85]
wire _next_empty_alloc_T_1 = ~cmds_1_valid; // @[DMACommandTracker.scala:61:17, :64:85]
wire _next_empty_alloc_T_2 = ~cmds_2_valid; // @[DMACommandTracker.scala:61:17, :64:85]
wire _next_empty_alloc_T_3 = ~cmds_3_valid; // @[DMACommandTracker.scala:61:17, :64:85]
wire _next_empty_alloc_T_4 = ~cmds_4_valid; // @[DMACommandTracker.scala:61:17, :64:85]
wire [2:0] _next_empty_alloc_T_5 = {_next_empty_alloc_T_4, 2'h0}; // @[Mux.scala:126:16]
wire [2:0] _next_empty_alloc_T_6 = _next_empty_alloc_T_3 ? 3'h3 : _next_empty_alloc_T_5; // @[Mux.scala:126:16]
wire [2:0] _next_empty_alloc_T_7 = _next_empty_alloc_T_2 ? 3'h2 : _next_empty_alloc_T_6; // @[Mux.scala:126:16]
wire [2:0] _next_empty_alloc_T_8 = _next_empty_alloc_T_1 ? 3'h1 : _next_empty_alloc_T_7; // @[Mux.scala:126:16]
assign next_empty_alloc = _next_empty_alloc_T ? 3'h0 : _next_empty_alloc_T_8; // @[Mux.scala:126:16]
assign io_alloc_bits_cmd_id_0 = next_empty_alloc; // @[Mux.scala:126:16]
wire _io_alloc_ready_T = cmds_0_valid & cmds_1_valid; // @[DMACommandTracker.scala:61:17, :66:42]
wire _io_alloc_ready_T_1 = _io_alloc_ready_T & cmds_2_valid; // @[DMACommandTracker.scala:61:17, :66:42]
wire _io_alloc_ready_T_2 = _io_alloc_ready_T_1 & cmds_3_valid; // @[DMACommandTracker.scala:61:17, :66:42]
wire _io_alloc_ready_T_3 = _io_alloc_ready_T_2 & cmds_4_valid; // @[DMACommandTracker.scala:61:17, :66:42]
assign _io_alloc_ready_T_4 = ~_io_alloc_ready_T_3; // @[DMACommandTracker.scala:66:{21,42}]
assign io_alloc_ready_0 = _io_alloc_ready_T_4; // @[DMACommandTracker.scala:9:7, :66:21]
wire _io_busy_T = cmds_0_valid | cmds_1_valid; // @[DMACommandTracker.scala:61:17, :69:34]
wire _io_busy_T_1 = _io_busy_T | cmds_2_valid; // @[DMACommandTracker.scala:61:17, :69:34]
wire _io_busy_T_2 = _io_busy_T_1 | cmds_3_valid; // @[DMACommandTracker.scala:61:17, :69:34]
assign _io_busy_T_3 = _io_busy_T_2 | cmds_4_valid; // @[DMACommandTracker.scala:61:17, :69:34]
assign io_busy_0 = _io_busy_T_3; // @[DMACommandTracker.scala:9:7, :69:34]
wire _GEN = cmds_0_bytes_left == 15'h0; // @[DMACommandTracker.scala:61:17, :72:34]
wire _cmd_completed_id_T; // @[DMACommandTracker.scala:72:34]
assign _cmd_completed_id_T = _GEN; // @[DMACommandTracker.scala:72:34]
wire _io_cmd_completed_valid_T; // @[DMACommandTracker.scala:74:73]
assign _io_cmd_completed_valid_T = _GEN; // @[DMACommandTracker.scala:72:34, :74:73]
wire _cmd_completed_id_T_1 = cmds_0_valid & _cmd_completed_id_T; // @[DMACommandTracker.scala:61:17, :72:{16,34}]
wire _GEN_0 = cmds_1_bytes_left == 15'h0; // @[DMACommandTracker.scala:61:17, :72:34]
wire _cmd_completed_id_T_2; // @[DMACommandTracker.scala:72:34]
assign _cmd_completed_id_T_2 = _GEN_0; // @[DMACommandTracker.scala:72:34]
wire _io_cmd_completed_valid_T_2; // @[DMACommandTracker.scala:74:73]
assign _io_cmd_completed_valid_T_2 = _GEN_0; // @[DMACommandTracker.scala:72:34, :74:73]
wire _cmd_completed_id_T_3 = cmds_1_valid & _cmd_completed_id_T_2; // @[DMACommandTracker.scala:61:17, :72:{16,34}]
wire _GEN_1 = cmds_2_bytes_left == 15'h0; // @[DMACommandTracker.scala:61:17, :72:34]
wire _cmd_completed_id_T_4; // @[DMACommandTracker.scala:72:34]
assign _cmd_completed_id_T_4 = _GEN_1; // @[DMACommandTracker.scala:72:34]
wire _io_cmd_completed_valid_T_4; // @[DMACommandTracker.scala:74:73]
assign _io_cmd_completed_valid_T_4 = _GEN_1; // @[DMACommandTracker.scala:72:34, :74:73]
wire _cmd_completed_id_T_5 = cmds_2_valid & _cmd_completed_id_T_4; // @[DMACommandTracker.scala:61:17, :72:{16,34}]
wire _GEN_2 = cmds_3_bytes_left == 15'h0; // @[DMACommandTracker.scala:61:17, :72:34]
wire _cmd_completed_id_T_6; // @[DMACommandTracker.scala:72:34]
assign _cmd_completed_id_T_6 = _GEN_2; // @[DMACommandTracker.scala:72:34]
wire _io_cmd_completed_valid_T_6; // @[DMACommandTracker.scala:74:73]
assign _io_cmd_completed_valid_T_6 = _GEN_2; // @[DMACommandTracker.scala:72:34, :74:73]
wire _cmd_completed_id_T_7 = cmds_3_valid & _cmd_completed_id_T_6; // @[DMACommandTracker.scala:61:17, :72:{16,34}]
wire _GEN_3 = cmds_4_bytes_left == 15'h0; // @[DMACommandTracker.scala:61:17, :72:34]
wire _cmd_completed_id_T_8; // @[DMACommandTracker.scala:72:34]
assign _cmd_completed_id_T_8 = _GEN_3; // @[DMACommandTracker.scala:72:34]
wire _io_cmd_completed_valid_T_8; // @[DMACommandTracker.scala:74:73]
assign _io_cmd_completed_valid_T_8 = _GEN_3; // @[DMACommandTracker.scala:72:34, :74:73]
wire _cmd_completed_id_T_9 = cmds_4_valid & _cmd_completed_id_T_8; // @[DMACommandTracker.scala:61:17, :72:{16,34}]
wire [2:0] _cmd_completed_id_T_10 = {_cmd_completed_id_T_9, 2'h0}; // @[Mux.scala:126:16]
wire [2:0] _cmd_completed_id_T_11 = _cmd_completed_id_T_7 ? 3'h3 : _cmd_completed_id_T_10; // @[Mux.scala:126:16]
wire [2:0] _cmd_completed_id_T_12 = _cmd_completed_id_T_5 ? 3'h2 : _cmd_completed_id_T_11; // @[Mux.scala:126:16]
wire [2:0] _cmd_completed_id_T_13 = _cmd_completed_id_T_3 ? 3'h1 : _cmd_completed_id_T_12; // @[Mux.scala:126:16]
assign cmd_completed_id = _cmd_completed_id_T_1 ? 3'h0 : _cmd_completed_id_T_13; // @[Mux.scala:126:16]
assign io_cmd_completed_bits_cmd_id = cmd_completed_id; // @[Mux.scala:126:16]
wire _io_cmd_completed_valid_T_1 = cmds_0_valid & _io_cmd_completed_valid_T; // @[DMACommandTracker.scala:61:17, :74:{55,73}]
wire _io_cmd_completed_valid_T_3 = cmds_1_valid & _io_cmd_completed_valid_T_2; // @[DMACommandTracker.scala:61:17, :74:{55,73}]
wire _io_cmd_completed_valid_T_5 = cmds_2_valid & _io_cmd_completed_valid_T_4; // @[DMACommandTracker.scala:61:17, :74:{55,73}]
wire _io_cmd_completed_valid_T_7 = cmds_3_valid & _io_cmd_completed_valid_T_6; // @[DMACommandTracker.scala:61:17, :74:{55,73}]
wire _io_cmd_completed_valid_T_9 = cmds_4_valid & _io_cmd_completed_valid_T_8; // @[DMACommandTracker.scala:61:17, :74:{55,73}]
wire _io_cmd_completed_valid_T_10 = _io_cmd_completed_valid_T_1 | _io_cmd_completed_valid_T_3; // @[DMACommandTracker.scala:74:{55,91}]
wire _io_cmd_completed_valid_T_11 = _io_cmd_completed_valid_T_10 | _io_cmd_completed_valid_T_5; // @[DMACommandTracker.scala:74:{55,91}]
wire _io_cmd_completed_valid_T_12 = _io_cmd_completed_valid_T_11 | _io_cmd_completed_valid_T_7; // @[DMACommandTracker.scala:74:{55,91}]
assign _io_cmd_completed_valid_T_13 = _io_cmd_completed_valid_T_12 | _io_cmd_completed_valid_T_9; // @[DMACommandTracker.scala:74:{55,91}]
assign io_cmd_completed_valid_0 = _io_cmd_completed_valid_T_13; // @[DMACommandTracker.scala:9:7, :74:91]
wire [7:0][5:0] _GEN_4 = {{cmds_0_tag_rob_id}, {cmds_0_tag_rob_id}, {cmds_0_tag_rob_id}, {cmds_4_tag_rob_id}, {cmds_3_tag_rob_id}, {cmds_2_tag_rob_id}, {cmds_1_tag_rob_id}, {cmds_0_tag_rob_id}}; // @[DMACommandTracker.scala:61:17, :76:29]
assign io_cmd_completed_bits_tag_rob_id_0 = _GEN_4[cmd_completed_id]; // @[Mux.scala:126:16]
wire [7:0] _GEN_5 = {{cmds_0_valid}, {cmds_0_valid}, {cmds_0_valid}, {cmds_4_valid}, {cmds_3_valid}, {cmds_2_valid}, {cmds_1_valid}, {cmds_0_valid}}; // @[DMACommandTracker.scala:61:17, :86:56]
wire [7:0][14:0] _GEN_6 = {{cmds_0_bytes_left}, {cmds_0_bytes_left}, {cmds_0_bytes_left}, {cmds_4_bytes_left}, {cmds_3_bytes_left}, {cmds_2_bytes_left}, {cmds_1_bytes_left}, {cmds_0_bytes_left}}; // @[DMACommandTracker.scala:61:17, :86:56]
wire [15:0] _cmds_bytes_left_T = {1'h0, _GEN_6[io_request_returned_bits_cmd_id_0]} - 16'h1; // @[DMACommandTracker.scala:9:7, :86:56]
wire [14:0] _cmds_bytes_left_T_1 = _cmds_bytes_left_T[14:0]; // @[DMACommandTracker.scala:86:56]
wire _GEN_7 = io_request_returned_valid_0 & ~reset; // @[DMACommandTracker.scala:9:7, :88:11]
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File SynchronizerReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util.{RegEnable, Cat}
/** These wrap behavioral
* shift and next registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
*
* These are built up of *ResetSynchronizerPrimitiveShiftReg,
* intended to be replaced by the integrator's metastable flops chains or replaced
* at this level if they have a multi-bit wide synchronizer primitive.
* The different types vary in their reset behavior:
* NonSyncResetSynchronizerShiftReg -- Register array which does not have a reset pin
* AsyncResetSynchronizerShiftReg -- Asynchronously reset register array, constructed from W instantiations of D deep
* 1-bit-wide shift registers.
* SyncResetSynchronizerShiftReg -- Synchronously reset register array, constructed similarly to AsyncResetSynchronizerShiftReg
*
* [Inferred]ResetSynchronizerShiftReg -- TBD reset type by chisel3 reset inference.
*
* ClockCrossingReg -- Not made up of SynchronizerPrimitiveShiftReg. This is for single-deep flops which cross
* Clock Domains.
*/
object SynchronizerResetType extends Enumeration {
val NonSync, Inferred, Sync, Async = Value
}
// Note: this should not be used directly.
// Use the companion object to generate this with the correct reset type mixin.
private class SynchronizerPrimitiveShiftReg(
sync: Int,
init: Boolean,
resetType: SynchronizerResetType.Value)
extends AbstractPipelineReg(1) {
val initInt = if (init) 1 else 0
val initPostfix = resetType match {
case SynchronizerResetType.NonSync => ""
case _ => s"_i${initInt}"
}
override def desiredName = s"${resetType.toString}ResetSynchronizerPrimitiveShiftReg_d${sync}${initPostfix}"
val chain = List.tabulate(sync) { i =>
val reg = if (resetType == SynchronizerResetType.NonSync) Reg(Bool()) else RegInit(init.B)
reg.suggestName(s"sync_$i")
}
chain.last := io.d.asBool
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink := source
}
io.q := chain.head.asUInt
}
private object SynchronizerPrimitiveShiftReg {
def apply (in: Bool, sync: Int, init: Boolean, resetType: SynchronizerResetType.Value): Bool = {
val gen: () => SynchronizerPrimitiveShiftReg = resetType match {
case SynchronizerResetType.NonSync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
case SynchronizerResetType.Async =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireAsyncReset
case SynchronizerResetType.Sync =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType) with RequireSyncReset
case SynchronizerResetType.Inferred =>
() => new SynchronizerPrimitiveShiftReg(sync, init, resetType)
}
AbstractPipelineReg(gen(), in)
}
}
// Note: This module may end up with a non-AsyncReset type reset.
// But the Primitives within will always have AsyncReset type.
class AsyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int)
extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"AsyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asAsyncReset){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Async)
}
}
io.q := Cat(output.reverse)
}
object AsyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
// Note: This module may end up with a non-Bool type reset.
// But the Primitives within will always have Bool reset type.
@deprecated("SyncResetSynchronizerShiftReg is unecessary with Chisel3 inferred resets. Use ResetSynchronizerShiftReg which will use the inferred reset type.", "rocket-chip 1.2")
class SyncResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SyncResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
withReset(reset.asBool){
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Sync)
}
}
io.q := Cat(output.reverse)
}
object SyncResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SyncResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class ResetSynchronizerShiftReg(w: Int = 1, sync: Int, init: Int) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"ResetSynchronizerShiftReg_w${w}_d${sync}_i${init}"
val output = Seq.tabulate(w) { i =>
val initBit = ((init >> i) & 1) > 0
SynchronizerPrimitiveShiftReg(io.d(i), sync, initBit, SynchronizerResetType.Inferred)
}
io.q := Cat(output.reverse)
}
object ResetSynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, init: Int, name: Option[String] = None): T =
AbstractPipelineReg(new ResetSynchronizerShiftReg(in.getWidth, sync, init), in, name)
def apply [T <: Data](in: T, sync: Int, name: Option[String]): T =
apply (in, sync, 0, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, 0, None)
def apply [T <: Data](in: T, sync: Int, init: T, name: Option[String]): T =
apply(in, sync, init.litValue.toInt, name)
def apply [T <: Data](in: T, sync: Int, init: T): T =
apply (in, sync, init.litValue.toInt, None)
}
class SynchronizerShiftReg(w: Int = 1, sync: Int = 3) extends AbstractPipelineReg(w) {
require(sync > 1, s"Sync must be greater than 1, not ${sync}.")
override def desiredName = s"SynchronizerShiftReg_w${w}_d${sync}"
val output = Seq.tabulate(w) { i =>
SynchronizerPrimitiveShiftReg(io.d(i), sync, false, SynchronizerResetType.NonSync)
}
io.q := Cat(output.reverse)
}
object SynchronizerShiftReg {
def apply [T <: Data](in: T, sync: Int, name: Option[String] = None): T =
if (sync == 0) in else AbstractPipelineReg(new SynchronizerShiftReg(in.getWidth, sync), in, name)
def apply [T <: Data](in: T, sync: Int): T =
apply (in, sync, None)
def apply [T <: Data](in: T): T =
apply (in, 3, None)
}
class ClockCrossingReg(w: Int = 1, doInit: Boolean) extends Module {
override def desiredName = s"ClockCrossingReg_w${w}"
val io = IO(new Bundle{
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
val en = Input(Bool())
})
val cdc_reg = if (doInit) RegEnable(io.d, 0.U(w.W), io.en) else RegEnable(io.d, io.en)
io.q := cdc_reg
}
object ClockCrossingReg {
def apply [T <: Data](in: T, en: Bool, doInit: Boolean, name: Option[String] = None): T = {
val cdc_reg = Module(new ClockCrossingReg(in.getWidth, doInit))
name.foreach{ cdc_reg.suggestName(_) }
cdc_reg.io.d := in.asUInt
cdc_reg.io.en := en
cdc_reg.io.q.asTypeOf(in)
}
}
|
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_159( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge)
|
Generate the Verilog code corresponding to the following Chisel files.
File Nodes.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.util.{AsyncQueueParams,RationalDirection}
case object TLMonitorBuilder extends Field[TLMonitorArgs => TLMonitorBase](args => new TLMonitor(args))
object TLImp extends NodeImp[TLMasterPortParameters, TLSlavePortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
{
def edgeO(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeOut(pd, pu, p, sourceInfo)
def edgeI(pd: TLMasterPortParameters, pu: TLSlavePortParameters, p: Parameters, sourceInfo: SourceInfo) = new TLEdgeIn (pd, pu, p, sourceInfo)
def bundleO(eo: TLEdgeOut) = TLBundle(eo.bundle)
def bundleI(ei: TLEdgeIn) = TLBundle(ei.bundle)
def render(ei: TLEdgeIn) = RenderedEdge(colour = "#000000" /* black */, label = (ei.manager.beatBytes * 8).toString)
override def monitor(bundle: TLBundle, edge: TLEdgeIn): Unit = {
val monitor = Module(edge.params(TLMonitorBuilder)(TLMonitorArgs(edge)))
monitor.io.in := bundle
}
override def mixO(pd: TLMasterPortParameters, node: OutwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLMasterPortParameters =
pd.v1copy(clients = pd.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) })
override def mixI(pu: TLSlavePortParameters, node: InwardNode[TLMasterPortParameters, TLSlavePortParameters, TLBundle]): TLSlavePortParameters =
pu.v1copy(managers = pu.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) })
}
trait TLFormatNode extends FormatNode[TLEdgeIn, TLEdgeOut]
case class TLClientNode(portParams: Seq[TLMasterPortParameters])(implicit valName: ValName) extends SourceNode(TLImp)(portParams) with TLFormatNode
case class TLManagerNode(portParams: Seq[TLSlavePortParameters])(implicit valName: ValName) extends SinkNode(TLImp)(portParams) with TLFormatNode
case class TLAdapterNode(
clientFn: TLMasterPortParameters => TLMasterPortParameters = { s => s },
managerFn: TLSlavePortParameters => TLSlavePortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLJunctionNode(
clientFn: Seq[TLMasterPortParameters] => Seq[TLMasterPortParameters],
managerFn: Seq[TLSlavePortParameters] => Seq[TLSlavePortParameters])(
implicit valName: ValName)
extends JunctionNode(TLImp)(clientFn, managerFn) with TLFormatNode
case class TLIdentityNode()(implicit valName: ValName) extends IdentityNode(TLImp)() with TLFormatNode
object TLNameNode {
def apply(name: ValName) = TLIdentityNode()(name)
def apply(name: Option[String]): TLIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLIdentityNode = apply(Some(name))
}
case class TLEphemeralNode()(implicit valName: ValName) extends EphemeralNode(TLImp)()
object TLTempNode {
def apply(): TLEphemeralNode = TLEphemeralNode()(ValName("temp"))
}
case class TLNexusNode(
clientFn: Seq[TLMasterPortParameters] => TLMasterPortParameters,
managerFn: Seq[TLSlavePortParameters] => TLSlavePortParameters)(
implicit valName: ValName)
extends NexusNode(TLImp)(clientFn, managerFn) with TLFormatNode
abstract class TLCustomNode(implicit valName: ValName)
extends CustomNode(TLImp) with TLFormatNode
// Asynchronous crossings
trait TLAsyncFormatNode extends FormatNode[TLAsyncEdgeParameters, TLAsyncEdgeParameters]
object TLAsyncImp extends SimpleNodeImp[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncEdgeParameters, TLAsyncBundle]
{
def edge(pd: TLAsyncClientPortParameters, pu: TLAsyncManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLAsyncEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLAsyncEdgeParameters) = new TLAsyncBundle(e.bundle)
def render(e: TLAsyncEdgeParameters) = RenderedEdge(colour = "#ff0000" /* red */, label = e.manager.async.depth.toString)
override def mixO(pd: TLAsyncClientPortParameters, node: OutwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLAsyncManagerPortParameters, node: InwardNode[TLAsyncClientPortParameters, TLAsyncManagerPortParameters, TLAsyncBundle]): TLAsyncManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLAsyncAdapterNode(
clientFn: TLAsyncClientPortParameters => TLAsyncClientPortParameters = { s => s },
managerFn: TLAsyncManagerPortParameters => TLAsyncManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLAsyncImp)(clientFn, managerFn) with TLAsyncFormatNode
case class TLAsyncIdentityNode()(implicit valName: ValName) extends IdentityNode(TLAsyncImp)() with TLAsyncFormatNode
object TLAsyncNameNode {
def apply(name: ValName) = TLAsyncIdentityNode()(name)
def apply(name: Option[String]): TLAsyncIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLAsyncIdentityNode = apply(Some(name))
}
case class TLAsyncSourceNode(sync: Option[Int])(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLAsyncImp)(
dFn = { p => TLAsyncClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = p.base.minLatency + sync.getOrElse(p.async.sync)) }) with FormatNode[TLEdgeIn, TLAsyncEdgeParameters] // discard cycles in other clock domain
case class TLAsyncSinkNode(async: AsyncQueueParams)(implicit valName: ValName)
extends MixedAdapterNode(TLAsyncImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = p.base.minLatency + async.sync) },
uFn = { p => TLAsyncManagerPortParameters(async, p) }) with FormatNode[TLAsyncEdgeParameters, TLEdgeOut]
// Rationally related crossings
trait TLRationalFormatNode extends FormatNode[TLRationalEdgeParameters, TLRationalEdgeParameters]
object TLRationalImp extends SimpleNodeImp[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalEdgeParameters, TLRationalBundle]
{
def edge(pd: TLRationalClientPortParameters, pu: TLRationalManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLRationalEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLRationalEdgeParameters) = new TLRationalBundle(e.bundle)
def render(e: TLRationalEdgeParameters) = RenderedEdge(colour = "#00ff00" /* green */)
override def mixO(pd: TLRationalClientPortParameters, node: OutwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLRationalManagerPortParameters, node: InwardNode[TLRationalClientPortParameters, TLRationalManagerPortParameters, TLRationalBundle]): TLRationalManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLRationalAdapterNode(
clientFn: TLRationalClientPortParameters => TLRationalClientPortParameters = { s => s },
managerFn: TLRationalManagerPortParameters => TLRationalManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLRationalImp)(clientFn, managerFn) with TLRationalFormatNode
case class TLRationalIdentityNode()(implicit valName: ValName) extends IdentityNode(TLRationalImp)() with TLRationalFormatNode
object TLRationalNameNode {
def apply(name: ValName) = TLRationalIdentityNode()(name)
def apply(name: Option[String]): TLRationalIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLRationalIdentityNode = apply(Some(name))
}
case class TLRationalSourceNode()(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLRationalImp)(
dFn = { p => TLRationalClientPortParameters(p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLRationalEdgeParameters] // discard cycles from other clock domain
case class TLRationalSinkNode(direction: RationalDirection)(implicit valName: ValName)
extends MixedAdapterNode(TLRationalImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLRationalManagerPortParameters(direction, p) }) with FormatNode[TLRationalEdgeParameters, TLEdgeOut]
// Credited version of TileLink channels
trait TLCreditedFormatNode extends FormatNode[TLCreditedEdgeParameters, TLCreditedEdgeParameters]
object TLCreditedImp extends SimpleNodeImp[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedEdgeParameters, TLCreditedBundle]
{
def edge(pd: TLCreditedClientPortParameters, pu: TLCreditedManagerPortParameters, p: Parameters, sourceInfo: SourceInfo) = TLCreditedEdgeParameters(pd, pu, p, sourceInfo)
def bundle(e: TLCreditedEdgeParameters) = new TLCreditedBundle(e.bundle)
def render(e: TLCreditedEdgeParameters) = RenderedEdge(colour = "#ffff00" /* yellow */, e.delay.toString)
override def mixO(pd: TLCreditedClientPortParameters, node: OutwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedClientPortParameters =
pd.copy(base = pd.base.v1copy(clients = pd.base.clients.map { c => c.v1copy (nodePath = node +: c.nodePath) }))
override def mixI(pu: TLCreditedManagerPortParameters, node: InwardNode[TLCreditedClientPortParameters, TLCreditedManagerPortParameters, TLCreditedBundle]): TLCreditedManagerPortParameters =
pu.copy(base = pu.base.v1copy(managers = pu.base.managers.map { m => m.v1copy (nodePath = node +: m.nodePath) }))
}
case class TLCreditedAdapterNode(
clientFn: TLCreditedClientPortParameters => TLCreditedClientPortParameters = { s => s },
managerFn: TLCreditedManagerPortParameters => TLCreditedManagerPortParameters = { s => s })(
implicit valName: ValName)
extends AdapterNode(TLCreditedImp)(clientFn, managerFn) with TLCreditedFormatNode
case class TLCreditedIdentityNode()(implicit valName: ValName) extends IdentityNode(TLCreditedImp)() with TLCreditedFormatNode
object TLCreditedNameNode {
def apply(name: ValName) = TLCreditedIdentityNode()(name)
def apply(name: Option[String]): TLCreditedIdentityNode = apply(ValName(name.getOrElse("with_no_name")))
def apply(name: String): TLCreditedIdentityNode = apply(Some(name))
}
case class TLCreditedSourceNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLImp, TLCreditedImp)(
dFn = { p => TLCreditedClientPortParameters(delay, p) },
uFn = { p => p.base.v1copy(minLatency = 1) }) with FormatNode[TLEdgeIn, TLCreditedEdgeParameters] // discard cycles from other clock domain
case class TLCreditedSinkNode(delay: TLCreditedDelay)(implicit valName: ValName)
extends MixedAdapterNode(TLCreditedImp, TLImp)(
dFn = { p => p.base.v1copy(minLatency = 1) },
uFn = { p => TLCreditedManagerPortParameters(delay, p) }) with FormatNode[TLCreditedEdgeParameters, TLEdgeOut]
File RegisterRouter.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{AddressSet, TransferSizes}
import freechips.rocketchip.resources.{Device, Resource, ResourceBindings}
import freechips.rocketchip.prci.{NoCrossing}
import freechips.rocketchip.regmapper.{RegField, RegMapper, RegMapperParams, RegMapperInput, RegisterRouter}
import freechips.rocketchip.util.{BundleField, ControlKey, ElaborationArtefacts, GenRegDescsAnno}
import scala.math.min
class TLRegisterRouterExtraBundle(val sourceBits: Int, val sizeBits: Int) extends Bundle {
val source = UInt((sourceBits max 1).W)
val size = UInt((sizeBits max 1).W)
}
case object TLRegisterRouterExtra extends ControlKey[TLRegisterRouterExtraBundle]("tlrr_extra")
case class TLRegisterRouterExtraField(sourceBits: Int, sizeBits: Int) extends BundleField[TLRegisterRouterExtraBundle](TLRegisterRouterExtra, Output(new TLRegisterRouterExtraBundle(sourceBits, sizeBits)), x => {
x.size := 0.U
x.source := 0.U
})
/** TLRegisterNode is a specialized TL SinkNode that encapsulates MMIO registers.
* It provides functionality for describing and outputting metdata about the registers in several formats.
* It also provides a concrete implementation of a regmap function that will be used
* to wire a map of internal registers associated with this node to the node's interconnect port.
*/
case class TLRegisterNode(
address: Seq[AddressSet],
device: Device,
deviceKey: String = "reg/control",
concurrency: Int = 0,
beatBytes: Int = 4,
undefZero: Boolean = true,
executable: Boolean = false)(
implicit valName: ValName)
extends SinkNode(TLImp)(Seq(TLSlavePortParameters.v1(
Seq(TLSlaveParameters.v1(
address = address,
resources = Seq(Resource(device, deviceKey)),
executable = executable,
supportsGet = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsPutFull = TransferSizes(1, beatBytes),
fifoId = Some(0))), // requests are handled in order
beatBytes = beatBytes,
minLatency = min(concurrency, 1)))) with TLFormatNode // the Queue adds at most one cycle
{
val size = 1 << log2Ceil(1 + address.map(_.max).max - address.map(_.base).min)
require (size >= beatBytes)
address.foreach { case a =>
require (a.widen(size-1).base == address.head.widen(size-1).base,
s"TLRegisterNode addresses (${address}) must be aligned to its size ${size}")
}
// Calling this method causes the matching TL2 bundle to be
// configured to route all requests to the listed RegFields.
def regmap(mapping: RegField.Map*) = {
val (bundleIn, edge) = this.in(0)
val a = bundleIn.a
val d = bundleIn.d
val fields = TLRegisterRouterExtraField(edge.bundle.sourceBits, edge.bundle.sizeBits) +: a.bits.params.echoFields
val params = RegMapperParams(log2Up(size/beatBytes), beatBytes, fields)
val in = Wire(Decoupled(new RegMapperInput(params)))
in.bits.read := a.bits.opcode === TLMessages.Get
in.bits.index := edge.addr_hi(a.bits)
in.bits.data := a.bits.data
in.bits.mask := a.bits.mask
Connectable.waiveUnmatched(in.bits.extra, a.bits.echo) match {
case (lhs, rhs) => lhs :<= rhs
}
val a_extra = in.bits.extra(TLRegisterRouterExtra)
a_extra.source := a.bits.source
a_extra.size := a.bits.size
// Invoke the register map builder
val out = RegMapper(beatBytes, concurrency, undefZero, in, mapping:_*)
// No flow control needed
in.valid := a.valid
a.ready := in.ready
d.valid := out.valid
out.ready := d.ready
// We must restore the size to enable width adapters to work
val d_extra = out.bits.extra(TLRegisterRouterExtra)
d.bits := edge.AccessAck(toSource = d_extra.source, lgSize = d_extra.size)
// avoid a Mux on the data bus by manually overriding two fields
d.bits.data := out.bits.data
Connectable.waiveUnmatched(d.bits.echo, out.bits.extra) match {
case (lhs, rhs) => lhs :<= rhs
}
d.bits.opcode := Mux(out.bits.read, TLMessages.AccessAckData, TLMessages.AccessAck)
// Tie off unused channels
bundleIn.b.valid := false.B
bundleIn.c.ready := true.B
bundleIn.e.ready := true.B
genRegDescsJson(mapping:_*)
}
def genRegDescsJson(mapping: RegField.Map*): Unit = {
// Dump out the register map for documentation purposes.
val base = address.head.base
val baseHex = s"0x${base.toInt.toHexString}"
val name = s"${device.describe(ResourceBindings()).name}.At${baseHex}"
val json = GenRegDescsAnno.serialize(base, name, mapping:_*)
var suffix = 0
while( ElaborationArtefacts.contains(s"${baseHex}.${suffix}.regmap.json")) {
suffix = suffix + 1
}
ElaborationArtefacts.add(s"${baseHex}.${suffix}.regmap.json", json)
val module = Module.currentModule.get.asInstanceOf[RawModule]
GenRegDescsAnno.anno(
module,
base,
mapping:_*)
}
}
/** Mix HasTLControlRegMap into any subclass of RegisterRouter to gain helper functions for attaching a device control register map to TileLink.
* - The intended use case is that controlNode will diplomatically publish a SW-visible device's memory-mapped control registers.
* - Use the clock crossing helper controlXing to externally connect controlNode to a TileLink interconnect.
* - Use the mapping helper function regmap to internally fill out the space of device control registers.
*/
trait HasTLControlRegMap { this: RegisterRouter =>
protected val controlNode = TLRegisterNode(
address = address,
device = device,
deviceKey = "reg/control",
concurrency = concurrency,
beatBytes = beatBytes,
undefZero = undefZero,
executable = executable)
// Externally, this helper should be used to connect the register control port to a bus
val controlXing: TLInwardClockCrossingHelper = this.crossIn(controlNode)
// Backwards-compatibility default node accessor with no clock crossing
lazy val node: TLInwardNode = controlXing(NoCrossing)
// Internally, this function should be used to populate the control port with registers
protected def regmap(mapping: RegField.Map*): Unit = { controlNode.regmap(mapping:_*) }
}
File TileResetSetter.scala:
package chipyard.clocking
import chisel3._
import chisel3.util._
import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.subsystem._
// Currently only works if all tiles are already driven by independent clock groups
// TODO: After https://github.com/chipsalliance/rocket-chip/pull/2842 is merged, we should
// always put all tiles on independent clock groups
class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters)
extends LazyModule {
val device = new SimpleDevice("tile-reset-setter", Nil)
val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
val clockNode = ClockGroupIdentityNode()
lazy val module = new LazyModuleImp(this) {
val nTiles = p(TilesLocated(InSubsystem)).size
require (nTiles <= 4096 / 4)
val tile_async_resets = Wire(Vec(nTiles, Reset()))
val r_tile_resets = (0 until nTiles).map({ i =>
tile_async_resets(i) := true.B.asAsyncReset // Remove this line after https://github.com/chipsalliance/rocket-chip/pull/2842
withReset (tile_async_resets(i)) {
Module(new AsyncResetRegVec(w=1, init=(if (initResetHarts.contains(i)) 1 else 0)))
}
})
if (nTiles > 0)
tlNode.regmap((0 until nTiles).map({ i =>
i * 4 -> Seq(RegField.rwReg(1, r_tile_resets(i).io))
}): _*)
val tileMap = tileNames.zipWithIndex.map({ case (n, i) =>
n -> (tile_async_resets(i), r_tile_resets(i).io.q, address + i * 4)
})
(clockNode.out zip clockNode.in).map { case ((o, _), (i, _)) =>
(o.member.elements zip i.member.elements).foreach { case ((name, oD), (_, iD)) =>
oD.clock := iD.clock
oD.reset := iD.reset
for ((n, (rIn, rOut, addr)) <- tileMap) {
if (name.contains(n)) {
println(s"${addr.toString(16)}: Tile $name reset control")
// Async because the reset coming out of the AsyncResetRegVec is
// clocked to the bus this is attached to, not the clock in this
// clock bundle. We expect a ClockGroupResetSynchronizer downstream
// to synchronize the resets
// Also, this or enforces that the tiles come out of reset after the reset of the system
oD.reset := (rOut.asBool || iD.reset.asBool).asAsyncReset
rIn := iD.reset
}
}
}
}
}
}
File LazyModuleImp.scala:
package org.chipsalliance.diplomacy.lazymodule
import chisel3.{withClockAndReset, Module, RawModule, Reset, _}
import chisel3.experimental.{ChiselAnnotation, CloneModuleAsRecord, SourceInfo}
import firrtl.passes.InlineAnnotation
import org.chipsalliance.cde.config.Parameters
import org.chipsalliance.diplomacy.nodes.Dangle
import scala.collection.immutable.SortedMap
/** Trait describing the actual [[Module]] implementation wrapped by a [[LazyModule]].
*
* This is the actual Chisel module that is lazily-evaluated in the second phase of Diplomacy.
*/
sealed trait LazyModuleImpLike extends RawModule {
/** [[LazyModule]] that contains this instance. */
val wrapper: LazyModule
/** IOs that will be automatically "punched" for this instance. */
val auto: AutoBundle
/** The metadata that describes the [[HalfEdge]]s which generated [[auto]]. */
protected[diplomacy] val dangles: Seq[Dangle]
// [[wrapper.module]] had better not be accessed while LazyModules are still being built!
require(
LazyModule.scope.isEmpty,
s"${wrapper.name}.module was constructed before LazyModule() was run on ${LazyModule.scope.get.name}"
)
/** Set module name. Defaults to the containing LazyModule's desiredName. */
override def desiredName: String = wrapper.desiredName
suggestName(wrapper.suggestedName)
/** [[Parameters]] for chisel [[Module]]s. */
implicit val p: Parameters = wrapper.p
/** instantiate this [[LazyModule]], return [[AutoBundle]] and a unconnected [[Dangle]]s from this module and
* submodules.
*/
protected[diplomacy] def instantiate(): (AutoBundle, List[Dangle]) = {
// 1. It will recursively append [[wrapper.children]] into [[chisel3.internal.Builder]],
// 2. return [[Dangle]]s from each module.
val childDangles = wrapper.children.reverse.flatMap { c =>
implicit val sourceInfo: SourceInfo = c.info
c.cloneProto.map { cp =>
// If the child is a clone, then recursively set cloneProto of its children as well
def assignCloneProtos(bases: Seq[LazyModule], clones: Seq[LazyModule]): Unit = {
require(bases.size == clones.size)
(bases.zip(clones)).map { case (l, r) =>
require(l.getClass == r.getClass, s"Cloned children class mismatch ${l.name} != ${r.name}")
l.cloneProto = Some(r)
assignCloneProtos(l.children, r.children)
}
}
assignCloneProtos(c.children, cp.children)
// Clone the child module as a record, and get its [[AutoBundle]]
val clone = CloneModuleAsRecord(cp.module).suggestName(c.suggestedName)
val clonedAuto = clone("auto").asInstanceOf[AutoBundle]
// Get the empty [[Dangle]]'s of the cloned child
val rawDangles = c.cloneDangles()
require(rawDangles.size == clonedAuto.elements.size)
// Assign the [[AutoBundle]] fields of the cloned record to the empty [[Dangle]]'s
val dangles = (rawDangles.zip(clonedAuto.elements)).map { case (d, (_, io)) => d.copy(dataOpt = Some(io)) }
dangles
}.getOrElse {
// For non-clones, instantiate the child module
val mod = try {
Module(c.module)
} catch {
case e: ChiselException => {
println(s"Chisel exception caught when instantiating ${c.name} within ${this.name} at ${c.line}")
throw e
}
}
mod.dangles
}
}
// Ask each node in this [[LazyModule]] to call [[BaseNode.instantiate]].
// This will result in a sequence of [[Dangle]] from these [[BaseNode]]s.
val nodeDangles = wrapper.nodes.reverse.flatMap(_.instantiate())
// Accumulate all the [[Dangle]]s from this node and any accumulated from its [[wrapper.children]]
val allDangles = nodeDangles ++ childDangles
// Group [[allDangles]] by their [[source]].
val pairing = SortedMap(allDangles.groupBy(_.source).toSeq: _*)
// For each [[source]] set of [[Dangle]]s of size 2, ensure that these
// can be connected as a source-sink pair (have opposite flipped value).
// Make the connection and mark them as [[done]].
val done = Set() ++ pairing.values.filter(_.size == 2).map {
case Seq(a, b) =>
require(a.flipped != b.flipped)
// @todo <> in chisel3 makes directionless connection.
if (a.flipped) {
a.data <> b.data
} else {
b.data <> a.data
}
a.source
case _ => None
}
// Find all [[Dangle]]s which are still not connected. These will end up as [[AutoBundle]] [[IO]] ports on the module.
val forward = allDangles.filter(d => !done(d.source))
// Generate [[AutoBundle]] IO from [[forward]].
val auto = IO(new AutoBundle(forward.map { d => (d.name, d.data, d.flipped) }: _*))
// Pass the [[Dangle]]s which remained and were used to generate the [[AutoBundle]] I/O ports up to the [[parent]] [[LazyModule]]
val dangles = (forward.zip(auto.elements)).map { case (d, (_, io)) =>
if (d.flipped) {
d.data <> io
} else {
io <> d.data
}
d.copy(dataOpt = Some(io), name = wrapper.suggestedName + "_" + d.name)
}
// Push all [[LazyModule.inModuleBody]] to [[chisel3.internal.Builder]].
wrapper.inModuleBody.reverse.foreach {
_()
}
if (wrapper.shouldBeInlined) {
chisel3.experimental.annotate(new ChiselAnnotation {
def toFirrtl = InlineAnnotation(toNamed)
})
}
// Return [[IO]] and [[Dangle]] of this [[LazyModuleImp]].
(auto, dangles)
}
}
/** Actual description of a [[Module]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyModuleImp(val wrapper: LazyModule) extends Module with LazyModuleImpLike {
/** Instantiate hardware of this `Module`. */
val (auto, dangles) = instantiate()
}
/** Actual description of a [[RawModule]] which can be instantiated by a call to [[LazyModule.module]].
*
* @param wrapper
* the [[LazyModule]] from which the `.module` call is being made.
*/
class LazyRawModuleImp(val wrapper: LazyModule) extends RawModule with LazyModuleImpLike {
// These wires are the default clock+reset for all LazyModule children.
// It is recommended to drive these even if you manually drive the [[clock]] and [[reset]] of all of the
// [[LazyRawModuleImp]] children.
// Otherwise, anonymous children ([[Monitor]]s for example) will not have their [[clock]] and/or [[reset]] driven properly.
/** drive clock explicitly. */
val childClock: Clock = Wire(Clock())
/** drive reset explicitly. */
val childReset: Reset = Wire(Reset())
// the default is that these are disabled
childClock := false.B.asClock
childReset := chisel3.DontCare
def provideImplicitClockToLazyChildren: Boolean = false
val (auto, dangles) =
if (provideImplicitClockToLazyChildren) {
withClockAndReset(childClock, childReset) { instantiate() }
} else {
instantiate()
}
}
|
module TileResetSetter( // @[TileResetSetter.scala:26:25]
input clock, // @[TileResetSetter.scala:26:25]
input reset, // @[TileResetSetter.scala:26:25]
input auto_clock_in_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25]
output auto_clock_out_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [10:0] auto_tl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [20:0] auto_tl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_tl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_tl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [10:0] auto_tl_in_d_bits_source // @[LazyModuleImp.scala:107:25]
);
wire [2:0] tlNodeIn_d_bits_opcode = {2'h0, auto_tl_in_a_bits_opcode == 3'h4}; // @[RegisterRouter.scala:74:36, :105:19]
TLMonitor_60 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (auto_tl_in_d_ready),
.io_in_a_valid (auto_tl_in_a_valid),
.io_in_a_bits_opcode (auto_tl_in_a_bits_opcode),
.io_in_a_bits_param (auto_tl_in_a_bits_param),
.io_in_a_bits_size (auto_tl_in_a_bits_size),
.io_in_a_bits_source (auto_tl_in_a_bits_source),
.io_in_a_bits_address (auto_tl_in_a_bits_address),
.io_in_a_bits_mask (auto_tl_in_a_bits_mask),
.io_in_a_bits_corrupt (auto_tl_in_a_bits_corrupt),
.io_in_d_ready (auto_tl_in_d_ready),
.io_in_d_valid (auto_tl_in_a_valid),
.io_in_d_bits_opcode (tlNodeIn_d_bits_opcode), // @[RegisterRouter.scala:105:19]
.io_in_d_bits_size (auto_tl_in_a_bits_size),
.io_in_d_bits_source (auto_tl_in_a_bits_source)
); // @[Nodes.scala:27:25]
assign auto_clock_out_member_allClocks_uncore_clock = auto_clock_in_member_allClocks_uncore_clock; // @[TileResetSetter.scala:26:25]
assign auto_clock_out_member_allClocks_uncore_reset = auto_clock_in_member_allClocks_uncore_reset; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_a_ready = auto_tl_in_d_ready; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_valid = auto_tl_in_a_valid; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_opcode = tlNodeIn_d_bits_opcode; // @[RegisterRouter.scala:105:19]
assign auto_tl_in_d_bits_size = auto_tl_in_a_bits_size; // @[TileResetSetter.scala:26:25]
assign auto_tl_in_d_bits_source = auto_tl_in_a_bits_source; // @[TileResetSetter.scala:26:25]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_143( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_158 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File bim.scala:
package boom.v4.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v4.common._
import boom.v4.util.{BoomCoreStringPrefix, WrapInc}
import scala.math.min
class BIMMeta(implicit p: Parameters) extends BoomBundle()(p)
with HasBoomFrontendParameters
{
val bims = Vec(bankWidth, UInt(2.W))
}
case class BoomBIMParams(
nSets: Int = 2048,
nCols: Int = 8,
singlePorted: Boolean = true,
useFlops: Boolean = false,
slow: Boolean = false
)
class BIMBranchPredictorBank(params: BoomBIMParams = BoomBIMParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
override val nSets = params.nSets
val nCols = params.nCols
val nSetsPerCol = nSets / nCols
require(isPow2(nSets))
require(isPow2(nCols))
require(nCols < nSets)
require(nCols > 1)
val nWrBypassEntries = 2
def bimWrite(v: UInt, taken: Bool): UInt = {
val old_bim_sat_taken = v === 3.U
val old_bim_sat_ntaken = v === 0.U
Mux(old_bim_sat_taken && taken, 3.U,
Mux(old_bim_sat_ntaken && !taken, 0.U,
Mux(taken, v + 1.U, v - 1.U)))
}
val s2_meta = Wire(new BIMMeta)
override val metaSz = s2_meta.asUInt.getWidth
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSetsPerCol).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSetsPerCol-1).U) { doing_reset := false.B }
val mems = (0 until nCols) map {c => (f"bim_col$c", nSetsPerCol, bankWidth * 2)}
val s0_col_mask = UIntToOH(s0_idx(log2Ceil(nCols)-1,0)) & Fill(nCols, s0_valid)
val s1_col_mask = RegNext(s0_col_mask)
val s0_col_idx = s0_idx >> log2Ceil(nCols)
val s1_col_idx = RegNext(s0_col_idx)
val s2_req_rdata_all = Wire(Vec(nCols, Vec(bankWidth, UInt(2.W))))
val s2_req_rdata = Mux1H(RegNext(s1_col_mask), s2_req_rdata_all)
val s2_resp = Wire(Vec(bankWidth, Bool()))
for (w <- 0 until bankWidth) {
s2_resp(w) := s2_valid && s2_req_rdata(w)(1) && !doing_reset
s2_meta.bims(w) := s2_req_rdata(w)
if (!params.slow) {
io.resp.f2(w).taken := s2_resp(w)
}
io.resp.f3(w).taken := RegNext(s2_resp(w))
}
io.f3_meta := RegNext(s2_meta.asUInt)
val s1_update_wdata = Wire(Vec(bankWidth, UInt(2.W)))
val s1_update_wmask = Wire(Vec(bankWidth, Bool()))
val s1_update_meta = s1_update.bits.meta.asTypeOf(new BIMMeta)
val s1_update_col_mask = UIntToOH(s1_update_idx(log2Ceil(nCols)-1,0))
val s1_update_col_idx = s1_update_idx >> log2Ceil(nCols)
val wrbypass_idxs = Reg(Vec(nWrBypassEntries, UInt(log2Ceil(nSets).W)))
val wrbypass = Reg(Vec(nWrBypassEntries, Vec(bankWidth, UInt(2.W))))
val wrbypass_enq_idx = RegInit(0.U(log2Ceil(nWrBypassEntries).W))
val wrbypass_hits = VecInit((0 until nWrBypassEntries) map { i =>
!doing_reset &&
wrbypass_idxs(i) === s1_update_idx(log2Ceil(nSets)-1,0)
})
val wrbypass_hit = wrbypass_hits.reduce(_||_)
val wrbypass_hit_idx = PriorityEncoder(wrbypass_hits)
for (w <- 0 until bankWidth) {
s1_update_wmask(w) := false.B
s1_update_wdata(w) := DontCare
val update_pc = s1_update.bits.pc + (w << 1).U
when (s1_update.bits.br_mask(w) ||
(s1_update.bits.cfi_idx.valid && s1_update.bits.cfi_idx.bits === w.U)) {
val was_taken = (
s1_update.bits.cfi_idx.valid &&
(s1_update.bits.cfi_idx.bits === w.U) &&
(
(s1_update.bits.cfi_is_br && s1_update.bits.br_mask(w) && s1_update.bits.cfi_taken) ||
s1_update.bits.cfi_is_jal
)
)
val old_bim_value = Mux(wrbypass_hit, wrbypass(wrbypass_hit_idx)(w), s1_update_meta.bims(w))
s1_update_wmask(w) := true.B
s1_update_wdata(w) := bimWrite(old_bim_value, was_taken)
}
}
for (c <- 0 until nCols) {
val rdata = Wire(Vec(bankWidth, UInt(2.W)))
rdata := DontCare
val (ren, ridx) = if (params.slow) (s1_col_mask(c), s1_col_idx) else (s0_col_mask(c), s0_col_idx)
val wen = WireInit(doing_reset || (s1_update.valid && s1_update.bits.is_commit_update && s1_update_col_mask(c) && !ren))
if (params.slow) {
s2_req_rdata_all(c) := rdata
} else {
s2_req_rdata_all(c) := RegNext(rdata)
}
if (params.useFlops) {
val data = Reg(Vec(nSetsPerCol, Vec(bankWidth, UInt(2.W))))
when (wen && doing_reset) {
data(reset_idx) := VecInit(Seq.fill(bankWidth) { 2.U })
} .elsewhen (wen) {
for (i <- 0 until bankWidth) {
when (s1_update_wmask(i)) {
data(s1_update_col_idx)(i) := s1_update_wdata(i)
}
}
}
when (RegNext(ren) && !(wen && params.singlePorted.B)) {
rdata := data(RegNext(ridx))
}
} else {
val data = SyncReadMem(nSetsPerCol, Vec(bankWidth, UInt(2.W)))
data.suggestName(s"bim_col_${c}")
val r = if (params.singlePorted) data.read(ridx, ren && !wen) else data.read(ridx, ren)
rdata := r
when (wen) {
val widx = Mux(doing_reset, reset_idx, s1_update_col_idx)
val wdata = Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 2.U }), s1_update_wdata)
val wmask = Mux(doing_reset, (~(0.U(bankWidth.W))), s1_update_wmask.asUInt)
data.write(widx, wdata, wmask.asBools)
}
}
}
when (s1_update_wmask.reduce(_||_) && s1_update.valid && s1_update.bits.is_commit_update) {
when (wrbypass_hit) {
wrbypass(wrbypass_hit_idx) := s1_update_wdata
} .otherwise {
wrbypass(wrbypass_enq_idx) := s1_update_wdata
wrbypass_idxs(wrbypass_enq_idx) := s1_update_idx
wrbypass_enq_idx := WrapInc(wrbypass_enq_idx, nWrBypassEntries)
}
}
}
|
module bim_col_7( // @[bim.scala:157:29]
input [7:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [7:0] RW0_wdata,
output [7:0] RW0_rdata,
input [3:0] RW0_wmask
);
bim_col_0_ext bim_col_0_ext ( // @[bim.scala:157:29]
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
); // @[bim.scala:157:29]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File OutputUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
import constellation.noc.{HasNoCParams}
class OutputCreditAlloc extends Bundle {
val alloc = Bool()
val tail = Bool()
}
class OutputChannelStatus(implicit val p: Parameters) extends Bundle with HasNoCParams {
val occupied = Bool()
def available = !occupied
val flow = new FlowRoutingBundle
}
class OutputChannelAlloc(implicit val p: Parameters) extends Bundle with HasNoCParams {
val alloc = Bool()
val flow = new FlowRoutingBundle
}
class AbstractOutputUnitIO(
val inParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val cParam: BaseChannelParams
)(implicit val p: Parameters) extends Bundle with HasRouterInputParams {
val nodeId = cParam.srcId
val nVirtualChannels = cParam.nVirtualChannels
val in = Flipped(Vec(cParam.srcSpeedup, Valid(new Flit(cParam.payloadBits))))
val credit_available = Output(Vec(nVirtualChannels, Bool()))
val channel_status = Output(Vec(nVirtualChannels, new OutputChannelStatus))
val allocs = Input(Vec(nVirtualChannels, new OutputChannelAlloc))
val credit_alloc = Input(Vec(nVirtualChannels, new OutputCreditAlloc))
}
abstract class AbstractOutputUnit(
val inParams: Seq[ChannelParams],
val ingressParams: Seq[IngressChannelParams],
val cParam: BaseChannelParams
)(implicit val p: Parameters) extends Module with HasRouterInputParams with HasNoCParams {
val nodeId = cParam.srcId
def io: AbstractOutputUnitIO
}
class OutputUnit(inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: ChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class OutputUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = new Channel(cParam.asInstanceOf[ChannelParams])
}
val io = IO(new OutputUnitIO)
class OutputState(val bufferSize: Int) extends Bundle {
val occupied = Bool()
val c = UInt(log2Up(1+bufferSize).W)
val flow = new FlowRoutingBundle
}
val states = Reg(MixedVec(cParam.virtualChannelParams.map { u => new OutputState(u.bufferSize) }))
(states zip io.channel_status).map { case (s,a) =>
a.occupied := s.occupied
a.flow := s.flow
}
io.out.flit := io.in
states.zipWithIndex.map { case (s,i) => if (cParam.virtualChannelParams(i).traversable) {
when (io.out.vc_free(i)) {
assert(s.occupied)
s.occupied := false.B
}
} }
(states zip io.allocs).zipWithIndex.map { case ((s,a),i) => if (cParam.virtualChannelParams(i).traversable) {
when (a.alloc) {
s.occupied := true.B
s.flow := a.flow
}
} }
(io.credit_available zip states).zipWithIndex.map { case ((c,s),i) =>
c := s.c =/= 0.U //|| (io.out.credit_return.valid && io.out.credit_return.bits === i.U)
}
states.zipWithIndex.map { case (s,i) =>
val free = io.out.credit_return(i)
val alloc = io.credit_alloc(i).alloc
if (cParam.virtualChannelParams(i).traversable) {
s.c := s.c +& free - alloc
}
}
when (reset.asBool) {
states.foreach(_.occupied := false.B)
states.foreach(s => s.c := s.bufferSize.U)
}
}
|
module OutputUnit_5( // @[OutputUnit.scala:52:7]
input clock, // @[OutputUnit.scala:52:7]
input reset, // @[OutputUnit.scala:52:7]
input io_in_0_valid, // @[OutputUnit.scala:58:14]
input io_in_0_bits_head, // @[OutputUnit.scala:58:14]
input io_in_0_bits_tail, // @[OutputUnit.scala:58:14]
input [144:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14]
input [1:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14]
input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14]
input [1:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14]
input [1:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14]
output io_credit_available_1, // @[OutputUnit.scala:58:14]
output io_credit_available_2, // @[OutputUnit.scala:58:14]
output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14]
output io_channel_status_2_occupied, // @[OutputUnit.scala:58:14]
input io_allocs_1_alloc, // @[OutputUnit.scala:58:14]
input io_allocs_2_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14]
input io_credit_alloc_2_alloc, // @[OutputUnit.scala:58:14]
output io_out_flit_0_valid, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14]
output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14]
output [144:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14]
output [1:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14]
output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14]
output [2:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14]
output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14]
output [1:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14]
output [1:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14]
input [2:0] io_out_credit_return, // @[OutputUnit.scala:58:14]
input [2:0] io_out_vc_free // @[OutputUnit.scala:58:14]
);
reg states_2_occupied; // @[OutputUnit.scala:66:19]
reg [1:0] states_2_c; // @[OutputUnit.scala:66:19]
reg states_1_occupied; // @[OutputUnit.scala:66:19]
reg [1:0] states_1_c; // @[OutputUnit.scala:66:19]
|
Generate the Verilog code corresponding to the following Chisel files.
File rob.scala:
//******************************************************************************
// Copyright (c) 2013 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Re-order Buffer
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Bank the ROB, such that each "dispatch" group gets its own row of the ROB,
// and each instruction in the dispatch group goes to a different bank.
// We can compress out the PC by only saving the high-order bits!
//
// ASSUMPTIONS:
// - dispatch groups are aligned to the PC.
//
// NOTES:
// - Currently we do not compress out bubbles in the ROB.
// - Exceptions are only taken when at the head of the commit bundle --
// this helps deal with loads, stores, and refetch instructions.
package boom.v4.exu
import scala.math.ceil
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
import boom.v4.common._
import boom.v4.util._
/**
* IO bundle to interact with the ROB
*
* @param numWakeupPorts number of wakeup ports to the rob
* @param numFpuPorts number of fpu ports that will write back fflags
*/
class RobIo(
val numWakeupPorts: Int
)(implicit p: Parameters) extends BoomBundle
{
// Decode Stage
// (Allocate, write instruction to ROB).
val enq_valids = Input(Vec(coreWidth, Bool()))
val enq_uops = Input(Vec(coreWidth, new MicroOp()))
val enq_partial_stall= Input(Bool()) // we're dispatching only a partial packet,
// and stalling on the rest of it (don't
// advance the tail ptr)
val xcpt_fetch_pc = Input(UInt(vaddrBitsExtended.W))
val rob_tail_idx = Output(UInt(robAddrSz.W))
val rob_pnr_idx = Output(UInt(robAddrSz.W))
val rob_head_idx = Output(UInt(robAddrSz.W))
// Handle Branch Misspeculations
val brupdate = Input(new BrUpdateInfo())
// Write-back Stage
// (Update of ROB)
// Instruction is no longer busy and can be committed
val wb_resps = Flipped(Vec(numWakeupPorts, Valid(new ExeUnitResp(xLen max fLen+1))))
// Unbusying ports for stores.
val lsu_clr_bsy = Input(Vec(coreWidth, Valid(UInt(robAddrSz.W))))
// Port for unmarking loads/stores as speculation hazards..
val lsu_clr_unsafe = Input(Vec(lsuWidth, Valid(UInt(robAddrSz.W))))
val lxcpt = Flipped(new ValidIO(new Exception())) // LSU
val csr_replay = Input(Valid(new Exception()))
// Commit stage (free resources).
val commit = Output(new CommitSignals())
val rollback = Bool()
// tell the LSU that the head of the ROB is a load
// (some loads can only execute once they are at the head of the ROB).
val com_load_is_at_rob_head = Output(Bool())
// Communicate exceptions to the CSRFile
val com_xcpt = Valid(new CommitExceptionSignals())
// Let the CSRFile stall us (e.g., wfi).
val csr_stall = Input(Bool())
// Flush signals (including exceptions, pipeline replays, and memory ordering failures)
// to send to the frontend for redirection.
val flush = Valid(new CommitExceptionSignals)
// Stall Decode as appropriate
val empty = Output(Bool())
val ready = Output(Bool()) // ROB is busy unrolling rename state...
// Stall the frontend if we know we will redirect the PC
val flush_frontend = Output(Bool())
val debug_tsc = Input(UInt(xLen.W))
}
/**
* Bundle to send commit signals across processor
*/
class CommitSignals(implicit p: Parameters) extends BoomBundle
{
val valids = Vec(retireWidth, Bool()) // These instructions may not correspond to an architecturally executed insn
val arch_valids = Vec(retireWidth, Bool())
val uops = Vec(retireWidth, new MicroOp())
val fflags = Valid(UInt(5.W))
// These come a cycle later
val debug_insts = Vec(retireWidth, UInt(32.W))
val debug_wdata = Vec(retireWidth, UInt(xLen.W))
}
/**
* Bundle to communicate exceptions to CSRFile
*
* TODO combine FlushSignals and ExceptionSignals (currently timed to different cycles).
*/
class CommitExceptionSignals(implicit p: Parameters) extends BoomBundle
{
val ftq_idx = UInt(log2Ceil(ftqSz).W)
val edge_inst = Bool()
val is_rvc = Bool()
val pc_lob = UInt(log2Ceil(icBlockBytes).W)
val cause = UInt(xLen.W)
val badvaddr = UInt(xLen.W)
// The ROB needs to tell the FTQ if there's a pipeline flush (and what type)
// so the FTQ can drive the frontend with the correct redirected PC.
val flush_typ = FlushTypes()
}
/**
* Tell the frontend the type of flush so it can set up the next PC properly.
*/
object FlushTypes
{
def SZ = 3
def apply() = UInt(SZ.W)
def none = 0.U
def xcpt = 1.U // An exception occurred.
def eret = (2+1).U // Execute an environment return instruction.
def refetch = 2.U // Flush and refetch the head instruction.
def next = 4.U // Flush and fetch the next instruction.
def useCsrEvec(typ: UInt): Bool = typ(0) // typ === xcpt.U || typ === eret.U
def useSamePC(typ: UInt): Bool = typ === refetch
def usePCplus4(typ: UInt): Bool = typ === next
def getType(valid: Bool, i_xcpt: Bool, i_eret: Bool, i_refetch: Bool): UInt = {
val ret =
Mux(!valid, none,
Mux(i_eret, eret,
Mux(i_xcpt, xcpt,
Mux(i_refetch, refetch,
next))))
ret
}
}
/**
* Bundle of signals indicating that an exception occurred
*/
class Exception(implicit p: Parameters) extends BoomBundle
{
val uop = new MicroOp()
val cause = Bits(log2Ceil(freechips.rocketchip.rocket.Causes.all.max+2).W)
val badvaddr = UInt(coreMaxAddrBits.W)
}
/**
* Bundle for debug ROB signals
* These should not be synthesized!
*/
class DebugRobSignals(implicit p: Parameters) extends BoomBundle
{
val state = UInt()
val rob_head = UInt(robAddrSz.W)
val rob_pnr = UInt(robAddrSz.W)
val xcpt_val = Bool()
val xcpt_uop = new MicroOp()
val xcpt_badvaddr = UInt(xLen.W)
}
/**
* Reorder Buffer to keep track of dependencies and inflight instructions
*
* @param numWakeupPorts number of wakeup ports to the ROB
* @param numFpuPorts number of FPU units that will write back fflags
*/
class Rob(
val numWakeupPorts: Int,
val usingTrace: Boolean
)(implicit p: Parameters) extends BoomModule
{
val io = IO(new RobIo(numWakeupPorts))
// ROB Finite State Machine
val s_reset :: s_normal :: s_wait_till_empty :: s_rollback :: Nil = Enum(4)
val rob_state = RegInit(s_reset)
//commit entries at the head, and unwind exceptions from the tail
val rob_head = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_head_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W)) // TODO: Accurately track head LSB (currently always 0)
val rob_head_idx = if (coreWidth == 1) rob_head else Cat(rob_head, rob_head_lsb)
val rob_tail = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_tail_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))
val rob_tail_idx = if (coreWidth == 1) rob_tail else Cat(rob_tail, rob_tail_lsb)
val rob_pnr = RegInit(0.U(log2Ceil(numRobRows).W))
val rob_pnr_lsb = RegInit(0.U((1 max log2Ceil(coreWidth)).W))
val rob_pnr_idx = if (coreWidth == 1) rob_pnr else Cat(rob_pnr , rob_pnr_lsb)
val next_rob_head = WireInit(rob_head)
rob_head := next_rob_head
val full = Wire(Bool())
val empty = Wire(Bool())
val will_commit = Wire(Vec(coreWidth, Bool()))
val can_commit = Wire(Vec(coreWidth, Bool()))
val can_throw_exception = Wire(Vec(coreWidth, Bool()))
val rob_pnr_unsafe = Wire(Vec(coreWidth, Bool())) // are the instructions at the pnr unsafe?
val rob_head_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the head valid?
val rob_tail_vals = Wire(Vec(coreWidth, Bool())) // are the instructions at the tail valid? (to track partial row dispatches)
val rob_head_uses_stq = Wire(Vec(coreWidth, Bool()))
val rob_head_uses_ldq = Wire(Vec(coreWidth, Bool()))
val rob_head_fflags = Wire(Vec(coreWidth, Valid(UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))
val exception_thrown = Wire(Bool())
// exception info
// TODO compress xcpt cause size. Most bits in the middle are zero.
val r_xcpt_val = RegInit(false.B)
val r_xcpt_uop = Reg(new MicroOp())
val r_xcpt_badvaddr = Reg(UInt(coreMaxAddrBits.W))
io.flush_frontend := r_xcpt_val
//--------------------------------------------------
// Utility
def GetRowIdx(rob_idx: UInt): UInt = {
if (coreWidth == 1) return rob_idx
else return rob_idx >> log2Ceil(coreWidth).U
}
def GetBankIdx(rob_idx: UInt): UInt = {
if(coreWidth == 1) { return 0.U }
else { return rob_idx(log2Ceil(coreWidth)-1, 0).asUInt }
}
// **************************************************************************
// Debug
class DebugRobBundle extends BoomBundle
{
val valid = Bool()
val busy = Bool()
val unsafe = Bool()
val uop = new MicroOp()
val exception = Bool()
}
val debug_entry = Wire(Vec(numRobEntries, new DebugRobBundle))
debug_entry := DontCare // override in statements below
// **************************************************************************
// --------------------------------------------------------------------------
// **************************************************************************
// Contains all information the PNR needs to find the oldest instruction which can't be safely speculated past.
val rob_unsafe_masked = WireInit(VecInit(Seq.fill(numRobRows << log2Ceil(coreWidth)){false.B}))
val rob_debug_inst_rdata = Wire(Vec(coreWidth, UInt(32.W)))
val rob_debug_inst_wmask = WireInit(VecInit(0.U(coreWidth.W).asBools))
val rob_debug_inst_wdata = Wire(Vec(coreWidth, UInt(32.W)))
// Used for trace port, for debug purposes only
if (usingTrace) {
val rob_debug_inst_mem = SyncReadMem(numRobRows, Vec(coreWidth, UInt(32.W)))
rob_debug_inst_mem.write(rob_tail, rob_debug_inst_wdata, rob_debug_inst_wmask)
rob_debug_inst_rdata := rob_debug_inst_mem.read(rob_head, will_commit.reduce(_||_))
} else {
rob_debug_inst_rdata := DontCare
}
// Branch resolution
val brupdate_b2_rob_row = GetRowIdx(io.brupdate.b2.uop.rob_idx)
val brupdate_b2_rob_row_oh = UIntToOH(brupdate_b2_rob_row)
val brupdate_b2_rob_clr_oh = IsYoungerMask(brupdate_b2_rob_row, rob_head, numRobRows)
val brupdate_b2_rob_bank_idx = GetBankIdx(io.brupdate.b2.uop.rob_idx)
val brupdate_b2_rob_bank_clr_oh = ~MaskLower(UIntToOH(brupdate_b2_rob_bank_idx))
class RobCompactUop extends Bundle {
val is_fencei = Bool()
val ftq_idx = UInt(log2Ceil(ftqSz).W)
val uses_ldq = Bool()
val uses_stq = Bool()
val dst_rtype = UInt(2.W)
val ldst = UInt(lregSz.W)
val pdst = UInt(maxPregSz.W)
val stale_pdst = UInt(maxPregSz.W)
}
val compactUopWidth = 1 + log2Ceil(ftqSz) + 1 + 1 + 2 + lregSz + maxPregSz + maxPregSz
def compact_to_uop(compact: RobCompactUop, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.is_fencei := compact.is_fencei
out.ftq_idx := compact.ftq_idx
out.uses_ldq := compact.uses_ldq
out.uses_stq := compact.uses_stq
out.dst_rtype := compact.dst_rtype
out.ldst := compact.ldst
out.pdst := compact.pdst
out.stale_pdst := compact.stale_pdst
out
}
def uop_to_compact(uop: MicroOp): RobCompactUop = {
val out = Wire(new RobCompactUop)
out.is_fencei := uop.is_fencei
out.ftq_idx := uop.ftq_idx
out.uses_ldq := uop.uses_ldq
out.uses_stq := uop.uses_stq
out.dst_rtype := uop.dst_rtype
out.ldst := uop.ldst
out.pdst := uop.pdst
out.stale_pdst := uop.stale_pdst
out
}
// More efficient rob uop storage in 1R1W masked SRAM
val rob_compact_uop_mem = SyncReadMem(numRobRows, Vec(coreWidth, UInt(compactUopWidth.W)))
val rob_compact_uop_wdata = VecInit(io.enq_uops.map(u => uop_to_compact(u).asUInt))
rob_compact_uop_mem.write(rob_tail, rob_compact_uop_wdata, io.enq_valids)
val rob_compact_uop_rdata = rob_compact_uop_mem.read(next_rob_head)
val rob_compact_uop_might_bypass = rob_head === RegNext(rob_tail)
val rob_compact_uop_bypassed = (0 until coreWidth) map { w =>
Mux(rob_head === RegNext(rob_tail) && RegNext(io.enq_valids(w)),
RegNext(rob_compact_uop_wdata(w)),
Mux(rob_head === ShiftRegister(rob_tail, 2) && ShiftRegister(io.enq_valids(w), 2),
ShiftRegister(rob_compact_uop_wdata(w), 2),
rob_compact_uop_rdata(w)
)
).asTypeOf(new RobCompactUop)
}
val rob_fflags = Seq.fill(coreWidth)(Reg(Vec(numRobRows, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))
for (w <- 0 until coreWidth) {
def MatchBank(bank_idx: UInt): Bool = (bank_idx === w.U)
// one bank
val rob_val = RegInit(VecInit(Seq.fill(numRobRows){false.B}))
val rob_bsy = Reg(Vec(numRobRows, Bool()))
val rob_unsafe = Reg(Vec(numRobRows, Bool()))
val rob_uop = Reg(Vec(numRobRows, new MicroOp()))
val rob_exception = Reg(Vec(numRobRows, Bool()))
val rob_predicated = Reg(Vec(numRobRows, Bool())) // Was this instruction predicated out?
val rob_fflags = Reg(Vec(numRobRows, Valid(Bits(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W))))
val rob_debug_wdata = Mem(numRobRows, UInt(xLen.W))
//-----------------------------------------------
// Dispatch: Add Entry to ROB
rob_debug_inst_wmask(w) := io.enq_valids(w)
rob_debug_inst_wdata(w) := io.enq_uops(w).debug_inst
when (io.enq_valids(w)) {
rob_val(rob_tail) := true.B
rob_bsy(rob_tail) := io.enq_uops(w).starts_bsy
rob_unsafe(rob_tail) := io.enq_uops(w).starts_unsafe
rob_uop(rob_tail) := io.enq_uops(w)
rob_exception(rob_tail) := io.enq_uops(w).exception
rob_predicated(rob_tail) := false.B
rob_fflags(rob_tail).valid := false.B
rob_fflags(rob_tail).bits := 0.U
assert (rob_val(rob_tail) === false.B, "[rob] overwriting a valid entry.")
assert ((io.enq_uops(w).rob_idx >> log2Ceil(coreWidth)) === rob_tail)
} .elsewhen (io.enq_valids.reduce(_|_) && !rob_val(rob_tail)) {
}
//-----------------------------------------------
// Writeback
for (i <- 0 until numWakeupPorts) {
val wb_resp = io.wb_resps(i)
val wb_uop = wb_resp.bits.uop
val row_idx = GetRowIdx(wb_uop.rob_idx)
when (wb_resp.valid && MatchBank(GetBankIdx(wb_uop.rob_idx))) {
rob_bsy(row_idx) := false.B
rob_unsafe(row_idx) := false.B
rob_predicated(row_idx) := wb_resp.bits.predicated
when (wb_resp.bits.fflags.valid) {
assert(!rob_fflags(row_idx).valid)
rob_fflags(row_idx).valid := true.B
rob_fflags(row_idx).bits := wb_resp.bits.fflags.bits
}
}
}
// Stores have a separate method to clear busy bits
for (clr_rob_idx <- io.lsu_clr_bsy) {
when (clr_rob_idx.valid && MatchBank(GetBankIdx(clr_rob_idx.bits))) {
val cidx = GetRowIdx(clr_rob_idx.bits)
rob_bsy(cidx) := false.B
rob_unsafe(cidx) := false.B
assert (rob_val(cidx) === true.B, "[rob] store writing back to invalid entry.")
assert (rob_bsy(cidx) === true.B, "[rob] store writing back to a not-busy entry.")
}
}
for (clr <- io.lsu_clr_unsafe) {
when (clr.valid && MatchBank(GetBankIdx(clr.bits))) {
val cidx = GetRowIdx(clr.bits)
rob_unsafe(cidx) := false.B
}
}
//-----------------------------------------------------
// Exceptions
// (the cause bits are compressed and stored elsewhere)
when (io.lxcpt.valid && MatchBank(GetBankIdx(io.lxcpt.bits.uop.rob_idx))) {
rob_exception(GetRowIdx(io.lxcpt.bits.uop.rob_idx)) := true.B
when (io.lxcpt.bits.cause =/= MINI_EXCEPTION_MEM_ORDERING) {
// In the case of a mem-ordering failure, the failing load will have been marked safe already.
assert(rob_unsafe(GetRowIdx(io.lxcpt.bits.uop.rob_idx)),
"An instruction marked as safe is causing an exception")
}
}
when (io.csr_replay.valid && MatchBank(GetBankIdx(io.csr_replay.bits.uop.rob_idx))) {
rob_exception(GetRowIdx(io.csr_replay.bits.uop.rob_idx)) := true.B
}
can_throw_exception(w) := rob_val(rob_head) && rob_exception(rob_head)
//-----------------------------------------------
// Commit
// Can this instruction commit? (the check for exceptions/rob_state happens later).
// Block commit if there is mispredict
can_commit(w) := rob_val(rob_head) && !(rob_bsy(rob_head)) && !io.csr_stall && !io.brupdate.b2.mispredict
// use the same "com_uop" for both rollback AND commit
// Perform Commit
io.commit.valids(w) := will_commit(w)
io.commit.arch_valids(w) := will_commit(w) && !rob_predicated(rob_head)
io.commit.uops(w) := compact_to_uop(rob_compact_uop_bypassed(w), rob_uop(rob_head))
io.commit.debug_insts(w) := rob_debug_inst_rdata(w)
// We unbusy branches in b1, but its easier to mark the taken/provider src in b2,
// when the branch might be committing
when (io.brupdate.b2.mispredict &&
MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx)) &&
GetRowIdx(io.brupdate.b2.uop.rob_idx) === rob_head) {
io.commit.uops(w).debug_fsrc := BSRC_C
io.commit.uops(w).taken := io.brupdate.b2.taken
}
when (rob_state === s_rollback) {
for (i <- 0 until numRobRows) {
rob_val(i) := false.B
rob_bsy(i) := false.B
}
}
// -----------------------------------------------
// Kill speculated entries on branch mispredict
for (i <- 0 until numRobRows) {
val br_mask = rob_uop(i).br_mask
when (io.brupdate.b2.mispredict && (
brupdate_b2_rob_clr_oh(i) ||
(brupdate_b2_rob_row_oh(i) && brupdate_b2_rob_bank_clr_oh(w))
)) {
rob_val(i) := false.B
}
// //kill instruction if mispredict & br mask match
// when (IsKilledByBranch(io.brupdate, false.B, br_mask))
// {
// rob_val(i) := false.B
// } .elsewhen (rob_val(i)) {
// // clear speculation bit even on correct speculation
// rob_uop(i).br_mask := GetNewBrMask(io.brupdate, br_mask)
// }
}
// Debug signal to figure out which prediction structure
// or core resolved a branch correctly
when (io.brupdate.b2.mispredict &&
MatchBank(GetBankIdx(io.brupdate.b2.uop.rob_idx))) {
rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).debug_fsrc := BSRC_C
rob_uop(GetRowIdx(io.brupdate.b2.uop.rob_idx)).taken := io.brupdate.b2.taken
}
// -----------------------------------------------
// Commit
when (will_commit(w)) {
rob_val(rob_head) := false.B
}
// -----------------------------------------------
// Outputs
rob_head_vals(w) := rob_val(rob_head)
rob_tail_vals(w) := rob_val(rob_tail)
rob_head_fflags(w) := rob_fflags(rob_head)
rob_head_uses_stq(w) := io.commit.uops(w).uses_stq
rob_head_uses_ldq(w) := io.commit.uops(w).uses_ldq
//------------------------------------------------
// Invalid entries are safe; thrown exceptions are unsafe.
for (i <- 0 until numRobRows) {
rob_unsafe_masked((i << log2Ceil(coreWidth)) + w) := rob_val(i) && (rob_unsafe(i) || rob_exception(i))
}
// Read unsafe status of PNR row.
rob_pnr_unsafe(w) := rob_val(rob_pnr) && (rob_unsafe(rob_pnr) || rob_exception(rob_pnr))
//--------------------------------------------------
// Debug: for debug purposes, track side-effects to all register destinations
for (i <- 0 until numWakeupPorts) {
val rob_idx = io.wb_resps(i).bits.uop.rob_idx
when (io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx))) {
rob_debug_wdata(GetRowIdx(rob_idx)) := io.wb_resps(i).bits.data
}
val temp_uop = rob_uop(GetRowIdx(rob_idx))
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
!rob_val(GetRowIdx(rob_idx))),
"[rob] writeback (" + i + ") occurred to an invalid ROB entry.")
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
!rob_bsy(GetRowIdx(rob_idx))),
"[rob] writeback (" + i + ") occurred to a not-busy ROB entry.")
assert (!(io.wb_resps(i).valid && MatchBank(GetBankIdx(rob_idx)) &&
temp_uop.dst_rtype =/= RT_X && temp_uop.pdst =/= io.wb_resps(i).bits.uop.pdst),
"[rob] writeback (" + i + ") occurred to the wrong pdst.")
}
io.commit.debug_wdata(w) := rob_debug_wdata(rob_head)
} //for (w <- 0 until coreWidth)
// **************************************************************************
// --------------------------------------------------------------------------
// **************************************************************************
// -----------------------------------------------
// Commit Logic
// need to take a "can_commit" array, and let the first can_commits commit
// previous instructions may block the commit of younger instructions in the commit bundle
// e.g., exception, or (valid && busy).
// Finally, don't throw an exception if there are instructions in front of
// it that want to commit (only throw exception when head of the bundle).
var block_commit = (rob_state =/= s_normal) && (rob_state =/= s_wait_till_empty) || RegNext(exception_thrown) || RegNext(RegNext(exception_thrown))
var will_throw_exception = false.B
var block_xcpt = false.B
for (w <- 0 until coreWidth) {
will_throw_exception = (can_throw_exception(w) && !block_commit && !block_xcpt) || will_throw_exception
will_commit(w) := can_commit(w) && !can_throw_exception(w) && !block_commit
block_commit = (rob_head_vals(w) &&
(!can_commit(w) || can_throw_exception(w))) || block_commit
block_xcpt = will_commit(w)
}
// Note: exception must be in the commit bundle.
// Note: exception must be the first valid instruction in the commit bundle.
exception_thrown := will_throw_exception
val is_mini_exception = io.com_xcpt.bits.cause.isOneOf(MINI_EXCEPTION_MEM_ORDERING, MINI_EXCEPTION_CSR_REPLAY)
io.com_xcpt.valid := exception_thrown && !is_mini_exception
io.com_xcpt.bits := DontCare
io.com_xcpt.bits.cause := r_xcpt_uop.exc_cause
io.com_xcpt.bits.badvaddr := Sext(r_xcpt_badvaddr, xLen)
val insn_sys_pc2epc =
rob_head_vals.reduce(_|_) && PriorityMux(rob_head_vals, io.commit.uops.map{u => u.is_sys_pc2epc})
val refetch_inst = exception_thrown || insn_sys_pc2epc
val com_xcpt_uop = PriorityMux(rob_head_vals, io.commit.uops)
io.com_xcpt.bits.ftq_idx := com_xcpt_uop.ftq_idx
io.com_xcpt.bits.edge_inst := com_xcpt_uop.edge_inst
io.com_xcpt.bits.is_rvc := com_xcpt_uop.is_rvc
io.com_xcpt.bits.pc_lob := com_xcpt_uop.pc_lob
val flush_commit_mask = Range(0,coreWidth).map{i => io.commit.valids(i) && io.commit.uops(i).flush_on_commit}
val flush_commit = flush_commit_mask.reduce(_|_)
val flush_val = exception_thrown || flush_commit
assert(!(PopCount(flush_commit_mask) > 1.U),
"[rob] Can't commit multiple flush_on_commit instructions on one cycle")
val flush_uop = Mux(exception_thrown, com_xcpt_uop, Mux1H(flush_commit_mask, io.commit.uops))
// delay a cycle for critical path considerations
io.flush.valid := flush_val
io.flush.bits.badvaddr := DontCare
io.flush.bits.cause := DontCare
io.flush.bits.ftq_idx := flush_uop.ftq_idx
io.flush.bits.pc_lob := flush_uop.pc_lob
io.flush.bits.edge_inst := flush_uop.edge_inst
io.flush.bits.is_rvc := flush_uop.is_rvc
io.flush.bits.flush_typ := FlushTypes.getType(flush_val,
exception_thrown && !is_mini_exception,
flush_commit && flush_uop.is_eret,
refetch_inst)
io.rollback := rob_state === s_rollback
// -----------------------------------------------
// FP Exceptions
// send fflags bits to the CSRFile to accrue
val fflags_val = Wire(Vec(coreWidth, Bool()))
val fflags = Wire(Vec(coreWidth, UInt(freechips.rocketchip.tile.FPConstants.FLAGS_SZ.W)))
for (w <- 0 until coreWidth) {
fflags_val(w) := rob_head_fflags(w).valid && io.commit.valids(w)
fflags(w) := Mux(fflags_val(w), rob_head_fflags(w).bits, 0.U)
assert (!(io.commit.valids(w) &&
io.commit.uops(w).fp_val &&
!(io.commit.uops(w).uses_stq || io.commit.uops(w).uses_ldq) &&
!rob_head_fflags(w).valid),
"Committed FP instruction did not set fflag bits")
assert (!(io.commit.valids(w) &&
!io.commit.uops(w).fp_val &&
rob_head_fflags(w).valid),
"Committed non-FP instruction has non-zero fflag bits.")
assert (!(io.commit.valids(w) &&
io.commit.uops(w).fp_val &&
(io.commit.uops(w).uses_ldq || io.commit.uops(w).uses_stq) &&
(rob_head_fflags(w).bits =/= 0.U && rob_head_fflags(w).valid)),
"Committed FP load or store has non-zero fflag bits.")
}
io.commit.fflags.valid := fflags_val.reduce(_|_)
io.commit.fflags.bits := fflags.reduce(_|_)
// -----------------------------------------------
// Exception Tracking Logic
// only store the oldest exception, since only one can happen!
val next_xcpt_uop = Wire(new MicroOp())
next_xcpt_uop := r_xcpt_uop
val enq_xcpts = Wire(Vec(coreWidth, Bool()))
for (i <- 0 until coreWidth) {
enq_xcpts(i) := io.enq_valids(i) && io.enq_uops(i).exception
}
when (!(io.flush.valid || exception_thrown)) {
val new_xcpt_valid = io.lxcpt.valid || io.csr_replay.valid
val lxcpt_older = !io.csr_replay.valid || (IsOlder(io.lxcpt.bits.uop.rob_idx, io.csr_replay.bits.uop.rob_idx, rob_head_idx) && io.lxcpt.valid)
val new_xcpt = Mux(lxcpt_older, io.lxcpt.bits, io.csr_replay.bits)
when (new_xcpt_valid) {
when (!r_xcpt_val || IsOlder(new_xcpt.uop.rob_idx, r_xcpt_uop.rob_idx, rob_head_idx)) {
r_xcpt_val := true.B
next_xcpt_uop := new_xcpt.uop
next_xcpt_uop.exc_cause := new_xcpt.cause
r_xcpt_badvaddr := new_xcpt.badvaddr
}
} .elsewhen (!r_xcpt_val && enq_xcpts.reduce(_|_)) {
val idx = enq_xcpts.indexWhere{i: Bool => i}
// if no exception yet, dispatch exception wins
r_xcpt_val := true.B
next_xcpt_uop := io.enq_uops(idx)
r_xcpt_badvaddr := AlignPCToBoundary(io.xcpt_fetch_pc, icBlockBytes) | io.enq_uops(idx).pc_lob
}
}
r_xcpt_uop := next_xcpt_uop
r_xcpt_uop.br_mask := GetNewBrMask(io.brupdate, next_xcpt_uop)
when (IsKilledByBranch(io.brupdate, io.flush.valid, next_xcpt_uop)) {
r_xcpt_val := false.B
}
assert (!(exception_thrown && !r_xcpt_val),
"ROB trying to throw an exception, but it doesn't have a valid xcpt_cause")
assert (!(empty && r_xcpt_val),
"ROB is empty, but believes it has an outstanding exception.")
assert (!(will_throw_exception && (GetRowIdx(r_xcpt_uop.rob_idx) =/= rob_head)),
"ROB is throwing an exception, but the stored exception information's " +
"rob_idx does not match the rob_head")
// -----------------------------------------------
// ROB Head Logic
// remember if we're still waiting on the rest of the dispatch packet, and prevent
// the rob_head from advancing if it commits a partial parket before we
// dispatch the rest of it.
// update when committed ALL valid instructions in commit_bundle
val r_partial_row = RegInit(false.B)
val finished_committing_row =
(io.commit.valids.asUInt =/= 0.U) &&
((will_commit.asUInt ^ rob_head_vals.asUInt) === 0.U) &&
!(r_partial_row && rob_head === rob_tail && !io.brupdate.b2.mispredict)
when (finished_committing_row) {
next_rob_head := WrapInc(rob_head, numRobRows)
rob_head_lsb := 0.U
} .elsewhen (rob_state === s_rollback) {
rob_head_lsb := 0.U
} .otherwise {
rob_head_lsb := OHToUInt(PriorityEncoderOH(rob_head_vals.asUInt))
}
// -----------------------------------------------
// ROB Point-of-No-Return (PNR) Logic
// Acts as a second head, but only waits on busy instructions which might cause misspeculation.
// TODO is it worth it to add an extra 'parity' bit to all rob pointer logic?
// Makes 'older than' comparisons ~3x cheaper, in case we're going to use the PNR to do a large number of those.
// Also doesn't require the rob tail (or head) to be exported to whatever we want to compare with the PNR.
if (enableFastPNR) {
val unsafe_entry_in_rob = rob_unsafe_masked.reduce(_||_)
val next_rob_pnr_idx = Mux(unsafe_entry_in_rob,
AgePriorityEncoder(rob_unsafe_masked, rob_head_idx),
rob_tail << log2Ceil(coreWidth) | PriorityEncoder(~rob_tail_vals.asUInt))
rob_pnr := next_rob_pnr_idx >> log2Ceil(coreWidth)
if (coreWidth > 1)
rob_pnr_lsb := next_rob_pnr_idx(log2Ceil(coreWidth)-1, 0)
} else {
val safe_to_inc = rob_state === s_normal || rob_state === s_wait_till_empty
val do_inc_row = !rob_pnr_unsafe.reduce(_||_) && !(rob_pnr === rob_tail && !io.brupdate.b2.mispredict)
when (rob_state === s_rollback) {
assert(rob_pnr === rob_head)
rob_pnr_lsb := 0.U
} .elsewhen (empty && io.enq_valids.asUInt =/= 0.U) {
// Unforunately for us, the ROB does not use its entries in monotonically
// increasing order, even in the case of no exceptions. The edge case
// arises when partial rows are enqueued and committed, leaving an empty
// ROB.
rob_pnr := rob_head
rob_pnr_lsb := PriorityEncoder(io.enq_valids)
} .elsewhen (safe_to_inc && do_inc_row) {
rob_pnr := WrapInc(rob_pnr, numRobRows)
rob_pnr_lsb := 0.U
} .elsewhen (safe_to_inc && (rob_pnr =/= rob_tail)) {
rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe)
} .elsewhen (safe_to_inc && !full && !empty) {
rob_pnr_lsb := PriorityEncoder(rob_pnr_unsafe.asUInt | ~MaskLower(rob_tail_vals.asUInt))
}
}
// Head overrunning PNR likely means an entry hasn't been marked as safe when it should have been.
assert(!IsOlder(rob_pnr_idx, rob_head_idx, rob_tail_idx) || rob_pnr_idx === rob_tail_idx)
// PNR overrunning tail likely means an entry has been marked as safe when it shouldn't have been.
assert(!IsOlder(rob_tail_idx, rob_pnr_idx, rob_head_idx) || full)
// -----------------------------------------------
// ROB Tail Logic
when (io.brupdate.b2.mispredict) {
rob_tail := WrapInc(GetRowIdx(io.brupdate.b2.uop.rob_idx), numRobRows)
rob_tail_lsb := 0.U
r_partial_row := false.B
} .elsewhen (io.enq_valids.asUInt =/= 0.U && !io.enq_partial_stall) {
rob_tail := WrapInc(rob_tail, numRobRows)
rob_tail_lsb := 0.U
r_partial_row := false.B
} .elsewhen (io.enq_valids.asUInt =/= 0.U && io.enq_partial_stall) {
rob_tail_lsb := PriorityEncoder(~MaskLower(io.enq_valids.asUInt))
r_partial_row := true.B
}
// -----------------------------------------------
// Full/Empty Logic
full := WrapInc(rob_tail, numRobRows) === rob_head
empty := (rob_head === rob_tail) && (rob_head_vals.asUInt === 0.U)
io.rob_head_idx := rob_head_idx
io.rob_tail_idx := rob_tail_idx
io.rob_pnr_idx := rob_pnr_idx
io.empty := empty
io.ready := (rob_state === s_normal) && !full && !r_xcpt_val
//-----------------------------------------------
//-----------------------------------------------
//-----------------------------------------------
// ROB FSM
switch (rob_state) {
is (s_reset) {
rob_state := s_normal
}
is (s_normal) {
when (RegNext(RegNext(exception_thrown))) {
rob_state := s_rollback
} .otherwise {
for (w <- 0 until coreWidth) {
when (io.enq_valids(w) && io.enq_uops(w).is_unique) {
rob_state := s_wait_till_empty
}
}
}
}
is (s_rollback) {
rob_tail := rob_head
rob_tail_lsb := 0.U
rob_state := s_normal
}
is (s_wait_till_empty) {
when (RegNext(RegNext(exception_thrown))) {
rob_state := s_rollback
} .elsewhen (empty) {
rob_state := s_normal
}
}
}
// -----------------------------------------------
// Outputs
io.com_load_is_at_rob_head := RegNext(rob_head_uses_ldq(PriorityEncoder(rob_head_vals.asUInt)) &&
!will_commit.reduce(_||_))
override def toString: String = BoomCoreStringPrefix(
"==ROB==",
"Machine Width : " + coreWidth,
"Rob Entries : " + numRobEntries,
"Rob Rows : " + numRobRows,
"Rob Row size : " + log2Ceil(numRobRows),
"log2Ceil(coreWidth): " + log2Ceil(coreWidth))
}
|
module rob_debug_wdata_32x64( // @[rob.scala:366:30]
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [63:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [63:0] W0_data,
input [4:0] W1_addr,
input W1_en,
input W1_clk,
input [63:0] W1_data,
input [4:0] W2_addr,
input W2_en,
input W2_clk,
input [63:0] W2_data,
input [4:0] W3_addr,
input W3_en,
input W3_clk,
input [63:0] W3_data,
input [4:0] W4_addr,
input W4_en,
input W4_clk,
input [63:0] W4_data,
input [4:0] W5_addr,
input W5_en,
input W5_clk,
input [63:0] W5_data,
input [4:0] W6_addr,
input W6_en,
input W6_clk,
input [63:0] W6_data
);
reg [63:0] Memory[0:31]; // @[rob.scala:366:30]
always @(posedge W0_clk) begin // @[rob.scala:366:30]
if (W0_en & 1'h1) // @[rob.scala:366:30]
Memory[W0_addr] <= W0_data; // @[rob.scala:366:30]
if (W1_en & 1'h1) // @[rob.scala:366:30]
Memory[W1_addr] <= W1_data; // @[rob.scala:366:30]
if (W2_en & 1'h1) // @[rob.scala:366:30]
Memory[W2_addr] <= W2_data; // @[rob.scala:366:30]
if (W3_en & 1'h1) // @[rob.scala:366:30]
Memory[W3_addr] <= W3_data; // @[rob.scala:366:30]
if (W4_en & 1'h1) // @[rob.scala:366:30]
Memory[W4_addr] <= W4_data; // @[rob.scala:366:30]
if (W5_en & 1'h1) // @[rob.scala:366:30]
Memory[W5_addr] <= W5_data; // @[rob.scala:366:30]
if (W6_en & 1'h1) // @[rob.scala:366:30]
Memory[W6_addr] <= W6_data; // @[rob.scala:366:30]
always @(posedge)
assign R0_data = R0_en ? Memory[R0_addr] : 64'bx; // @[rob.scala:366:30]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File Monitor.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceLine
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy._
import freechips.rocketchip.diplomacy.EnableMonitors
import freechips.rocketchip.formal.{MonitorDirection, IfThen, Property, PropertyClass, TestplanTestType, TLMonitorStrictMode}
import freechips.rocketchip.util.PlusArg
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
val io = IO(new Bundle {
val in = Input(new TLBundle(args.edge.bundle))
})
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit
legalize(io.in, args.edge, reset)
}
object TLMonitor {
def apply(enable: Boolean, node: TLNode)(implicit p: Parameters): TLNode = {
if (enable) {
EnableMonitors { implicit p => node := TLEphemeralNode()(ValName("monitor")) }
} else { node }
}
}
class TLMonitor(args: TLMonitorArgs, monitorDir: MonitorDirection = MonitorDirection.Monitor) extends TLMonitorBase(args)
{
require (args.edge.params(TLMonitorStrictMode) || (! args.edge.params(TestplanTestType).formal))
val cover_prop_class = PropertyClass.Default
//Like assert but can flip to being an assumption for formal verification
def monAssert(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir, cond, message, PropertyClass.Default)
}
def assume(cond: Bool, message: String): Unit =
if (monitorDir == MonitorDirection.Monitor) {
assert(cond, message)
} else {
Property(monitorDir.flip, cond, message, PropertyClass.Default)
}
def extra = {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}
}
def visible(address: UInt, source: UInt, edge: TLEdge) =
edge.client.clients.map { c =>
!c.sourceId.contains(source) ||
c.visibility.map(_.contains(address)).reduce(_ || _)
}.reduce(_ && _)
def legalizeFormatA(bundle: TLBundleA, edge: TLEdge): Unit = {
//switch this flag to turn on diplomacy in error messages
def diplomacyInfo = if (true) "" else "\nThe diplomacy information for the edge is as follows:\n" + edge.formatEdge + "\n"
monAssert (TLMessages.isA(bundle.opcode), "'A' channel has invalid opcode" + extra)
// Reuse these subexpressions to save some firrtl lines
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'A' channel carries an address illegal for the specified bank visibility")
//The monitor doesn’t check for acquire T vs acquire B, it assumes that acquire B implies acquire T and only checks for acquire B
//TODO: check for acquireT?
when (bundle.opcode === TLMessages.AcquireBlock) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquireBlock from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquireBlock carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquireBlock smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquireBlock address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquireBlock carries invalid grow param" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquireBlock contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquireBlock is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AcquirePerm) {
monAssert (edge.master.emitsAcquireB(bundle.source, bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'A' channel carries AcquirePerm from a client which does not support Probe" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel AcquirePerm carries invalid source ID" + diplomacyInfo + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'A' channel AcquirePerm smaller than a beat" + extra)
monAssert (is_aligned, "'A' channel AcquirePerm address not aligned to size" + extra)
monAssert (TLPermissions.isGrow(bundle.param), "'A' channel AcquirePerm carries invalid grow param" + extra)
monAssert (bundle.param =/= TLPermissions.NtoB, "'A' channel AcquirePerm requests NtoB" + extra)
monAssert (~bundle.mask === 0.U, "'A' channel AcquirePerm contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel AcquirePerm is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.emitsGet(bundle.source, bundle.size), "'A' channel carries Get type which master claims it can't emit" + diplomacyInfo + extra)
monAssert (edge.slave.supportsGetSafe(edge.address(bundle), bundle.size, None), "'A' channel carries Get type which slave claims it can't support" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel Get carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.emitsPutFull(bundle.source, bundle.size) && edge.slave.supportsPutFullSafe(edge.address(bundle), bundle.size), "'A' channel carries PutFull type which is unexpected using diplomatic parameters" + diplomacyInfo + extra)
monAssert (source_ok, "'A' channel PutFull carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'A' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.emitsPutPartial(bundle.source, bundle.size) && edge.slave.supportsPutPartialSafe(edge.address(bundle), bundle.size), "'A' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel PutPartial carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'A' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'A' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.emitsArithmetic(bundle.source, bundle.size) && edge.slave.supportsArithmeticSafe(edge.address(bundle), bundle.size), "'A' channel carries Arithmetic type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Arithmetic carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'A' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.emitsLogical(bundle.source, bundle.size) && edge.slave.supportsLogicalSafe(edge.address(bundle), bundle.size), "'A' channel carries Logical type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Logical carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'A' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.emitsHint(bundle.source, bundle.size) && edge.slave.supportsHintSafe(edge.address(bundle), bundle.size), "'A' channel carries Hint type which is unexpected using diplomatic parameters" + extra)
monAssert (source_ok, "'A' channel Hint carries invalid source ID" + diplomacyInfo + extra)
monAssert (is_aligned, "'A' channel Hint address not aligned to size" + extra)
monAssert (TLHints.isHints(bundle.param), "'A' channel Hint carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'A' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'A' channel Hint is corrupt" + extra)
}
}
def legalizeFormatB(bundle: TLBundleB, edge: TLEdge): Unit = {
monAssert (TLMessages.isB(bundle.opcode), "'B' channel has invalid opcode" + extra)
monAssert (visible(edge.address(bundle), bundle.source, edge), "'B' channel carries an address illegal for the specified bank visibility")
// Reuse these subexpressions to save some firrtl lines
val address_ok = edge.manager.containsSafe(edge.address(bundle))
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val mask = edge.full_mask(bundle)
val legal_source = Mux1H(edge.client.find(bundle.source), edge.client.clients.map(c => c.sourceId.start.U)) === bundle.source
when (bundle.opcode === TLMessages.Probe) {
assume (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'B' channel carries Probe type which is unexpected using diplomatic parameters" + extra)
assume (address_ok, "'B' channel Probe carries unmanaged address" + extra)
assume (legal_source, "'B' channel Probe carries source that is not first source" + extra)
assume (is_aligned, "'B' channel Probe address not aligned to size" + extra)
assume (TLPermissions.isCap(bundle.param), "'B' channel Probe carries invalid cap param" + extra)
assume (bundle.mask === mask, "'B' channel Probe contains invalid mask" + extra)
assume (!bundle.corrupt, "'B' channel Probe is corrupt" + extra)
}
when (bundle.opcode === TLMessages.Get) {
monAssert (edge.master.supportsGet(edge.source(bundle), bundle.size) && edge.slave.emitsGetSafe(edge.address(bundle), bundle.size), "'B' channel carries Get type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel Get carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Get carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Get address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel Get carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel Get contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Get is corrupt" + extra)
}
when (bundle.opcode === TLMessages.PutFullData) {
monAssert (edge.master.supportsPutFull(edge.source(bundle), bundle.size) && edge.slave.emitsPutFullSafe(edge.address(bundle), bundle.size), "'B' channel carries PutFull type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutFull carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutFull carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutFull address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutFull carries invalid param" + extra)
monAssert (bundle.mask === mask, "'B' channel PutFull contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.PutPartialData) {
monAssert (edge.master.supportsPutPartial(edge.source(bundle), bundle.size) && edge.slave.emitsPutPartialSafe(edge.address(bundle), bundle.size), "'B' channel carries PutPartial type which is unexpected using diplomatic parameters" + extra)
monAssert (address_ok, "'B' channel PutPartial carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel PutPartial carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel PutPartial address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'B' channel PutPartial carries invalid param" + extra)
monAssert ((bundle.mask & ~mask) === 0.U, "'B' channel PutPartial contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.ArithmeticData) {
monAssert (edge.master.supportsArithmetic(edge.source(bundle), bundle.size) && edge.slave.emitsArithmeticSafe(edge.address(bundle), bundle.size), "'B' channel carries Arithmetic type unsupported by master" + extra)
monAssert (address_ok, "'B' channel Arithmetic carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Arithmetic carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Arithmetic address not aligned to size" + extra)
monAssert (TLAtomics.isArithmetic(bundle.param), "'B' channel Arithmetic carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Arithmetic contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.LogicalData) {
monAssert (edge.master.supportsLogical(edge.source(bundle), bundle.size) && edge.slave.emitsLogicalSafe(edge.address(bundle), bundle.size), "'B' channel carries Logical type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Logical carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Logical carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Logical address not aligned to size" + extra)
monAssert (TLAtomics.isLogical(bundle.param), "'B' channel Logical carries invalid opcode param" + extra)
monAssert (bundle.mask === mask, "'B' channel Logical contains invalid mask" + extra)
}
when (bundle.opcode === TLMessages.Hint) {
monAssert (edge.master.supportsHint(edge.source(bundle), bundle.size) && edge.slave.emitsHintSafe(edge.address(bundle), bundle.size), "'B' channel carries Hint type unsupported by client" + extra)
monAssert (address_ok, "'B' channel Hint carries unmanaged address" + extra)
monAssert (legal_source, "'B' channel Hint carries source that is not first source" + extra)
monAssert (is_aligned, "'B' channel Hint address not aligned to size" + extra)
monAssert (bundle.mask === mask, "'B' channel Hint contains invalid mask" + extra)
monAssert (!bundle.corrupt, "'B' channel Hint is corrupt" + extra)
}
}
def legalizeFormatC(bundle: TLBundleC, edge: TLEdge): Unit = {
monAssert (TLMessages.isC(bundle.opcode), "'C' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val is_aligned = edge.isAligned(bundle.address, bundle.size)
val address_ok = edge.manager.containsSafe(edge.address(bundle))
monAssert (visible(edge.address(bundle), bundle.source, edge), "'C' channel carries an address illegal for the specified bank visibility")
when (bundle.opcode === TLMessages.ProbeAck) {
monAssert (address_ok, "'C' channel ProbeAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAck carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAck smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAck address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAck carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel ProbeAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ProbeAckData) {
monAssert (address_ok, "'C' channel ProbeAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel ProbeAckData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ProbeAckData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ProbeAckData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ProbeAckData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.Release) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel Release carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel Release smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel Release address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel Release carries invalid report param" + extra)
monAssert (!bundle.corrupt, "'C' channel Release is corrupt" + extra)
}
when (bundle.opcode === TLMessages.ReleaseData) {
monAssert (edge.master.emitsAcquireB(edge.source(bundle), bundle.size) && edge.slave.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
monAssert (edge.master.supportsProbe(edge.source(bundle), bundle.size) && edge.slave.emitsProbeSafe(edge.address(bundle), bundle.size), "'C' channel carries Release from a client which does not support Probe" + extra)
monAssert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
monAssert (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'C' channel ReleaseData smaller than a beat" + extra)
monAssert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
monAssert (TLPermissions.isReport(bundle.param), "'C' channel ReleaseData carries invalid report param" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
monAssert (address_ok, "'C' channel AccessAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel AccessAck is corrupt" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
monAssert (address_ok, "'C' channel AccessAckData carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel AccessAckData carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel AccessAckData address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel AccessAckData carries invalid param" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
monAssert (address_ok, "'C' channel HintAck carries unmanaged address" + extra)
monAssert (source_ok, "'C' channel HintAck carries invalid source ID" + extra)
monAssert (is_aligned, "'C' channel HintAck address not aligned to size" + extra)
monAssert (bundle.param === 0.U, "'C' channel HintAck carries invalid param" + extra)
monAssert (!bundle.corrupt, "'C' channel HintAck is corrupt" + extra)
}
}
def legalizeFormatD(bundle: TLBundleD, edge: TLEdge): Unit = {
assume (TLMessages.isD(bundle.opcode), "'D' channel has invalid opcode" + extra)
val source_ok = edge.client.contains(bundle.source)
val sink_ok = bundle.sink < edge.manager.endSinkId.U
val deny_put_ok = edge.manager.mayDenyPut.B
val deny_get_ok = edge.manager.mayDenyGet.B
when (bundle.opcode === TLMessages.ReleaseAck) {
assume (source_ok, "'D' channel ReleaseAck carries invalid source ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel ReleaseAck smaller than a beat" + extra)
assume (bundle.param === 0.U, "'D' channel ReleaseeAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel ReleaseAck is corrupt" + extra)
assume (!bundle.denied, "'D' channel ReleaseAck is denied" + extra)
}
when (bundle.opcode === TLMessages.Grant) {
assume (source_ok, "'D' channel Grant carries invalid source ID" + extra)
assume (sink_ok, "'D' channel Grant carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel Grant smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel Grant carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel Grant carries toN param" + extra)
assume (!bundle.corrupt, "'D' channel Grant is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel Grant is denied" + extra)
}
when (bundle.opcode === TLMessages.GrantData) {
assume (source_ok, "'D' channel GrantData carries invalid source ID" + extra)
assume (sink_ok, "'D' channel GrantData carries invalid sink ID" + extra)
assume (bundle.size >= log2Ceil(edge.manager.beatBytes).U, "'D' channel GrantData smaller than a beat" + extra)
assume (TLPermissions.isCap(bundle.param), "'D' channel GrantData carries invalid cap param" + extra)
assume (bundle.param =/= TLPermissions.toN, "'D' channel GrantData carries toN param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel GrantData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel GrantData is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAck) {
assume (source_ok, "'D' channel AccessAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel AccessAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel AccessAck is denied" + extra)
}
when (bundle.opcode === TLMessages.AccessAckData) {
assume (source_ok, "'D' channel AccessAckData carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel AccessAckData carries invalid param" + extra)
assume (!bundle.denied || bundle.corrupt, "'D' channel AccessAckData is denied but not corrupt" + extra)
assume (deny_get_ok || !bundle.denied, "'D' channel AccessAckData is denied" + extra)
}
when (bundle.opcode === TLMessages.HintAck) {
assume (source_ok, "'D' channel HintAck carries invalid source ID" + extra)
// size is ignored
assume (bundle.param === 0.U, "'D' channel HintAck carries invalid param" + extra)
assume (!bundle.corrupt, "'D' channel HintAck is corrupt" + extra)
assume (deny_put_ok || !bundle.denied, "'D' channel HintAck is denied" + extra)
}
}
def legalizeFormatE(bundle: TLBundleE, edge: TLEdge): Unit = {
val sink_ok = bundle.sink < edge.manager.endSinkId.U
monAssert (sink_ok, "'E' channels carries invalid sink ID" + extra)
}
def legalizeFormat(bundle: TLBundle, edge: TLEdge) = {
when (bundle.a.valid) { legalizeFormatA(bundle.a.bits, edge) }
when (bundle.d.valid) { legalizeFormatD(bundle.d.bits, edge) }
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
when (bundle.b.valid) { legalizeFormatB(bundle.b.bits, edge) }
when (bundle.c.valid) { legalizeFormatC(bundle.c.bits, edge) }
when (bundle.e.valid) { legalizeFormatE(bundle.e.bits, edge) }
} else {
monAssert (!bundle.b.valid, "'B' channel valid and not TL-C" + extra)
monAssert (!bundle.c.valid, "'C' channel valid and not TL-C" + extra)
monAssert (!bundle.e.valid, "'E' channel valid and not TL-C" + extra)
}
}
def legalizeMultibeatA(a: DecoupledIO[TLBundleA], edge: TLEdge): Unit = {
val a_first = edge.first(a.bits, a.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (a.valid && !a_first) {
monAssert (a.bits.opcode === opcode, "'A' channel opcode changed within multibeat operation" + extra)
monAssert (a.bits.param === param, "'A' channel param changed within multibeat operation" + extra)
monAssert (a.bits.size === size, "'A' channel size changed within multibeat operation" + extra)
monAssert (a.bits.source === source, "'A' channel source changed within multibeat operation" + extra)
monAssert (a.bits.address=== address,"'A' channel address changed with multibeat operation" + extra)
}
when (a.fire && a_first) {
opcode := a.bits.opcode
param := a.bits.param
size := a.bits.size
source := a.bits.source
address := a.bits.address
}
}
def legalizeMultibeatB(b: DecoupledIO[TLBundleB], edge: TLEdge): Unit = {
val b_first = edge.first(b.bits, b.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (b.valid && !b_first) {
monAssert (b.bits.opcode === opcode, "'B' channel opcode changed within multibeat operation" + extra)
monAssert (b.bits.param === param, "'B' channel param changed within multibeat operation" + extra)
monAssert (b.bits.size === size, "'B' channel size changed within multibeat operation" + extra)
monAssert (b.bits.source === source, "'B' channel source changed within multibeat operation" + extra)
monAssert (b.bits.address=== address,"'B' channel addresss changed with multibeat operation" + extra)
}
when (b.fire && b_first) {
opcode := b.bits.opcode
param := b.bits.param
size := b.bits.size
source := b.bits.source
address := b.bits.address
}
}
def legalizeADSourceFormal(bundle: TLBundle, edge: TLEdge): Unit = {
// Symbolic variable
val sym_source = Wire(UInt(edge.client.endSourceId.W))
// TODO: Connect sym_source to a fixed value for simulation and to a
// free wire in formal
sym_source := 0.U
// Type casting Int to UInt
val maxSourceId = Wire(UInt(edge.client.endSourceId.W))
maxSourceId := edge.client.endSourceId.U
// Delayed verison of sym_source
val sym_source_d = Reg(UInt(edge.client.endSourceId.W))
sym_source_d := sym_source
// These will be constraints for FV setup
Property(
MonitorDirection.Monitor,
(sym_source === sym_source_d),
"sym_source should remain stable",
PropertyClass.Default)
Property(
MonitorDirection.Monitor,
(sym_source <= maxSourceId),
"sym_source should take legal value",
PropertyClass.Default)
val my_resp_pend = RegInit(false.B)
val my_opcode = Reg(UInt())
val my_size = Reg(UInt())
val a_first = bundle.a.valid && edge.first(bundle.a.bits, bundle.a.fire)
val d_first = bundle.d.valid && edge.first(bundle.d.bits, bundle.d.fire)
val my_a_first_beat = a_first && (bundle.a.bits.source === sym_source)
val my_d_first_beat = d_first && (bundle.d.bits.source === sym_source)
val my_clr_resp_pend = (bundle.d.fire && my_d_first_beat)
val my_set_resp_pend = (bundle.a.fire && my_a_first_beat && !my_clr_resp_pend)
when (my_set_resp_pend) {
my_resp_pend := true.B
} .elsewhen (my_clr_resp_pend) {
my_resp_pend := false.B
}
when (my_a_first_beat) {
my_opcode := bundle.a.bits.opcode
my_size := bundle.a.bits.size
}
val my_resp_size = Mux(my_a_first_beat, bundle.a.bits.size, my_size)
val my_resp_opcode = Mux(my_a_first_beat, bundle.a.bits.opcode, my_opcode)
val my_resp_opcode_legal = Wire(Bool())
when ((my_resp_opcode === TLMessages.Get) || (my_resp_opcode === TLMessages.ArithmeticData) ||
(my_resp_opcode === TLMessages.LogicalData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAckData)
} .elsewhen ((my_resp_opcode === TLMessages.PutFullData) || (my_resp_opcode === TLMessages.PutPartialData)) {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.AccessAck)
} .otherwise {
my_resp_opcode_legal := (bundle.d.bits.opcode === TLMessages.HintAck)
}
monAssert (IfThen(my_resp_pend, !my_a_first_beat),
"Request message should not be sent with a source ID, for which a response message" +
"is already pending (not received until current cycle) for a prior request message" +
"with the same source ID" + extra)
assume (IfThen(my_clr_resp_pend, (my_set_resp_pend || my_resp_pend)),
"Response message should be accepted with a source ID only if a request message with the" +
"same source ID has been accepted or is being accepted in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (my_a_first_beat || my_resp_pend)),
"Response message should be sent with a source ID only if a request message with the" +
"same source ID has been accepted or is being sent in the current cycle" + extra)
assume (IfThen(my_d_first_beat, (bundle.d.bits.size === my_resp_size)),
"If d_valid is 1, then d_size should be same as a_size of the corresponding request" +
"message" + extra)
assume (IfThen(my_d_first_beat, my_resp_opcode_legal),
"If d_valid is 1, then d_opcode should correspond with a_opcode of the corresponding" +
"request message" + extra)
}
def legalizeMultibeatC(c: DecoupledIO[TLBundleC], edge: TLEdge): Unit = {
val c_first = edge.first(c.bits, c.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val address = Reg(UInt())
when (c.valid && !c_first) {
monAssert (c.bits.opcode === opcode, "'C' channel opcode changed within multibeat operation" + extra)
monAssert (c.bits.param === param, "'C' channel param changed within multibeat operation" + extra)
monAssert (c.bits.size === size, "'C' channel size changed within multibeat operation" + extra)
monAssert (c.bits.source === source, "'C' channel source changed within multibeat operation" + extra)
monAssert (c.bits.address=== address,"'C' channel address changed with multibeat operation" + extra)
}
when (c.fire && c_first) {
opcode := c.bits.opcode
param := c.bits.param
size := c.bits.size
source := c.bits.source
address := c.bits.address
}
}
def legalizeMultibeatD(d: DecoupledIO[TLBundleD], edge: TLEdge): Unit = {
val d_first = edge.first(d.bits, d.fire)
val opcode = Reg(UInt())
val param = Reg(UInt())
val size = Reg(UInt())
val source = Reg(UInt())
val sink = Reg(UInt())
val denied = Reg(Bool())
when (d.valid && !d_first) {
assume (d.bits.opcode === opcode, "'D' channel opcode changed within multibeat operation" + extra)
assume (d.bits.param === param, "'D' channel param changed within multibeat operation" + extra)
assume (d.bits.size === size, "'D' channel size changed within multibeat operation" + extra)
assume (d.bits.source === source, "'D' channel source changed within multibeat operation" + extra)
assume (d.bits.sink === sink, "'D' channel sink changed with multibeat operation" + extra)
assume (d.bits.denied === denied, "'D' channel denied changed with multibeat operation" + extra)
}
when (d.fire && d_first) {
opcode := d.bits.opcode
param := d.bits.param
size := d.bits.size
source := d.bits.source
sink := d.bits.sink
denied := d.bits.denied
}
}
def legalizeMultibeat(bundle: TLBundle, edge: TLEdge): Unit = {
legalizeMultibeatA(bundle.a, edge)
legalizeMultibeatD(bundle.d, edge)
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
legalizeMultibeatB(bundle.b, edge)
legalizeMultibeatC(bundle.c, edge)
}
}
//This is left in for almond which doesn't adhere to the tilelink protocol
@deprecated("Use legalizeADSource instead if possible","")
def legalizeADSourceOld(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.client.endSourceId.W))
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val a_set = WireInit(0.U(edge.client.endSourceId.W))
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
assert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
assume((a_set | inflight)(bundle.d.bits.source), "'D' channel acknowledged for nothing inflight" + extra)
}
if (edge.manager.minLatency > 0) {
assume(a_set =/= d_clr || !a_set.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
assert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeADSource(bundle: TLBundle, edge: TLEdge): Unit = {
val a_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val a_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_a_opcode_bus_size = log2Ceil(a_opcode_bus_size)
val log_a_size_bus_size = log2Ceil(a_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W)) // size up to avoid width error
inflight.suggestName("inflight")
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
inflight_opcodes.suggestName("inflight_opcodes")
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
inflight_sizes.suggestName("inflight_sizes")
val a_first = edge.first(bundle.a.bits, bundle.a.fire)
a_first.suggestName("a_first")
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
d_first.suggestName("d_first")
val a_set = WireInit(0.U(edge.client.endSourceId.W))
val a_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
a_set.suggestName("a_set")
a_set_wo_ready.suggestName("a_set_wo_ready")
val a_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
a_opcodes_set.suggestName("a_opcodes_set")
val a_sizes_set = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
a_sizes_set.suggestName("a_sizes_set")
val a_opcode_lookup = WireInit(0.U((a_opcode_bus_size - 1).W))
a_opcode_lookup.suggestName("a_opcode_lookup")
a_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_a_opcode_bus_size.U) & size_to_numfullbits(1.U << log_a_opcode_bus_size.U)) >> 1.U
val a_size_lookup = WireInit(0.U((1 << log_a_size_bus_size).W))
a_size_lookup.suggestName("a_size_lookup")
a_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_a_size_bus_size.U) & size_to_numfullbits(1.U << log_a_size_bus_size.U)) >> 1.U
val responseMap = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.Grant, TLMessages.Grant))
val responseMapSecondOption = VecInit(Seq(TLMessages.AccessAck, TLMessages.AccessAck, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.AccessAckData, TLMessages.HintAck, TLMessages.GrantData, TLMessages.Grant))
val a_opcodes_set_interm = WireInit(0.U(a_opcode_bus_size.W))
a_opcodes_set_interm.suggestName("a_opcodes_set_interm")
val a_sizes_set_interm = WireInit(0.U(a_size_bus_size.W))
a_sizes_set_interm.suggestName("a_sizes_set_interm")
when (bundle.a.valid && a_first && edge.isRequest(bundle.a.bits)) {
a_set_wo_ready := UIntToOH(bundle.a.bits.source)
}
when (bundle.a.fire && a_first && edge.isRequest(bundle.a.bits)) {
a_set := UIntToOH(bundle.a.bits.source)
a_opcodes_set_interm := (bundle.a.bits.opcode << 1.U) | 1.U
a_sizes_set_interm := (bundle.a.bits.size << 1.U) | 1.U
a_opcodes_set := (a_opcodes_set_interm) << (bundle.a.bits.source << log_a_opcode_bus_size.U)
a_sizes_set := (a_sizes_set_interm) << (bundle.a.bits.source << log_a_size_bus_size.U)
monAssert(!inflight(bundle.a.bits.source), "'A' channel re-used a source ID" + extra)
}
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_a_opcode_bus_size).W))
d_opcodes_clr.suggestName("d_opcodes_clr")
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_a_size_bus_size).W))
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_a_opcode_bus_size.U) << (bundle.d.bits.source << log_a_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_a_size_bus_size.U) << (bundle.d.bits.source << log_a_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && !d_release_ack) {
val same_cycle_resp = bundle.a.valid && a_first && edge.isRequest(bundle.a.bits) && (bundle.a.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.opcode === responseMap(bundle.a.bits.opcode)) ||
(bundle.d.bits.opcode === responseMapSecondOption(bundle.a.bits.opcode)), "'D' channel contains improper opcode response" + extra)
assume((bundle.a.bits.size === bundle.d.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.opcode === responseMap(a_opcode_lookup)) ||
(bundle.d.bits.opcode === responseMapSecondOption(a_opcode_lookup)), "'D' channel contains improper opcode response" + extra)
assume((bundle.d.bits.size === a_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && a_first && bundle.a.valid && (bundle.a.bits.source === bundle.d.bits.source) && !d_release_ack) {
assume((!bundle.d.ready) || bundle.a.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
assume(a_set_wo_ready =/= d_clr_wo_ready || !a_set_wo_ready.orR, s"'A' and 'D' concurrent, despite minlatency > 0" + extra)
}
inflight := (inflight | a_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | a_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | a_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.a.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeCDSource(bundle: TLBundle, edge: TLEdge): Unit = {
val c_size_bus_size = edge.bundle.sizeBits + 1 //add one so that 0 is not mapped to anything (size 0 -> size 1 in map, size 0 in map means unset)
val c_opcode_bus_size = 3 + 1 //opcode size is 3, but add so that 0 is not mapped to anything
val log_c_opcode_bus_size = log2Ceil(c_opcode_bus_size)
val log_c_size_bus_size = log2Ceil(c_size_bus_size)
def size_to_numfullbits(x: UInt): UInt = (1.U << x) - 1.U //convert a number to that many full bits
val inflight = RegInit(0.U((2 max edge.client.endSourceId).W))
val inflight_opcodes = RegInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val inflight_sizes = RegInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
inflight.suggestName("inflight")
inflight_opcodes.suggestName("inflight_opcodes")
inflight_sizes.suggestName("inflight_sizes")
val c_first = edge.first(bundle.c.bits, bundle.c.fire)
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
c_first.suggestName("c_first")
d_first.suggestName("d_first")
val c_set = WireInit(0.U(edge.client.endSourceId.W))
val c_set_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val c_opcodes_set = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val c_sizes_set = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
c_set.suggestName("c_set")
c_set_wo_ready.suggestName("c_set_wo_ready")
c_opcodes_set.suggestName("c_opcodes_set")
c_sizes_set.suggestName("c_sizes_set")
val c_opcode_lookup = WireInit(0.U((1 << log_c_opcode_bus_size).W))
val c_size_lookup = WireInit(0.U((1 << log_c_size_bus_size).W))
c_opcode_lookup := ((inflight_opcodes) >> (bundle.d.bits.source << log_c_opcode_bus_size.U) & size_to_numfullbits(1.U << log_c_opcode_bus_size.U)) >> 1.U
c_size_lookup := ((inflight_sizes) >> (bundle.d.bits.source << log_c_size_bus_size.U) & size_to_numfullbits(1.U << log_c_size_bus_size.U)) >> 1.U
c_opcode_lookup.suggestName("c_opcode_lookup")
c_size_lookup.suggestName("c_size_lookup")
val c_opcodes_set_interm = WireInit(0.U(c_opcode_bus_size.W))
val c_sizes_set_interm = WireInit(0.U(c_size_bus_size.W))
c_opcodes_set_interm.suggestName("c_opcodes_set_interm")
c_sizes_set_interm.suggestName("c_sizes_set_interm")
when (bundle.c.valid && c_first && edge.isRequest(bundle.c.bits)) {
c_set_wo_ready := UIntToOH(bundle.c.bits.source)
}
when (bundle.c.fire && c_first && edge.isRequest(bundle.c.bits)) {
c_set := UIntToOH(bundle.c.bits.source)
c_opcodes_set_interm := (bundle.c.bits.opcode << 1.U) | 1.U
c_sizes_set_interm := (bundle.c.bits.size << 1.U) | 1.U
c_opcodes_set := (c_opcodes_set_interm) << (bundle.c.bits.source << log_c_opcode_bus_size.U)
c_sizes_set := (c_sizes_set_interm) << (bundle.c.bits.source << log_c_size_bus_size.U)
monAssert(!inflight(bundle.c.bits.source), "'C' channel re-used a source ID" + extra)
}
val c_probe_ack = bundle.c.bits.opcode === TLMessages.ProbeAck || bundle.c.bits.opcode === TLMessages.ProbeAckData
val d_clr = WireInit(0.U(edge.client.endSourceId.W))
val d_clr_wo_ready = WireInit(0.U(edge.client.endSourceId.W))
val d_opcodes_clr = WireInit(0.U((edge.client.endSourceId << log_c_opcode_bus_size).W))
val d_sizes_clr = WireInit(0.U((edge.client.endSourceId << log_c_size_bus_size).W))
d_clr.suggestName("d_clr")
d_clr_wo_ready.suggestName("d_clr_wo_ready")
d_opcodes_clr.suggestName("d_opcodes_clr")
d_sizes_clr.suggestName("d_sizes_clr")
val d_release_ack = bundle.d.bits.opcode === TLMessages.ReleaseAck
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr_wo_ready := UIntToOH(bundle.d.bits.source)
}
when (bundle.d.fire && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
d_clr := UIntToOH(bundle.d.bits.source)
d_opcodes_clr := size_to_numfullbits(1.U << log_c_opcode_bus_size.U) << (bundle.d.bits.source << log_c_opcode_bus_size.U)
d_sizes_clr := size_to_numfullbits(1.U << log_c_size_bus_size.U) << (bundle.d.bits.source << log_c_size_bus_size.U)
}
when (bundle.d.valid && d_first && edge.isResponse(bundle.d.bits) && d_release_ack) {
val same_cycle_resp = bundle.c.valid && c_first && edge.isRequest(bundle.c.bits) && (bundle.c.bits.source === bundle.d.bits.source)
assume(((inflight)(bundle.d.bits.source)) || same_cycle_resp, "'D' channel acknowledged for nothing inflight" + extra)
when (same_cycle_resp) {
assume((bundle.d.bits.size === bundle.c.bits.size), "'D' channel contains improper response size" + extra)
} .otherwise {
assume((bundle.d.bits.size === c_size_lookup), "'D' channel contains improper response size" + extra)
}
}
when(bundle.d.valid && d_first && c_first && bundle.c.valid && (bundle.c.bits.source === bundle.d.bits.source) && d_release_ack && !c_probe_ack) {
assume((!bundle.d.ready) || bundle.c.ready, "ready check")
}
if (edge.manager.minLatency > 0) {
when (c_set_wo_ready.orR) {
assume(c_set_wo_ready =/= d_clr_wo_ready, s"'C' and 'D' concurrent, despite minlatency > 0" + extra)
}
}
inflight := (inflight | c_set) & ~d_clr
inflight_opcodes := (inflight_opcodes | c_opcodes_set) & ~d_opcodes_clr
inflight_sizes := (inflight_sizes | c_sizes_set) & ~d_sizes_clr
val watchdog = RegInit(0.U(32.W))
val limit = PlusArg("tilelink_timeout",
docstring="Kill emulation after INT waiting TileLink cycles. Off if 0.")
monAssert (!inflight.orR || limit === 0.U || watchdog < limit, "TileLink timeout expired" + extra)
watchdog := watchdog + 1.U
when (bundle.c.fire || bundle.d.fire) { watchdog := 0.U }
}
def legalizeDESink(bundle: TLBundle, edge: TLEdge): Unit = {
val inflight = RegInit(0.U(edge.manager.endSinkId.W))
val d_first = edge.first(bundle.d.bits, bundle.d.fire)
val e_first = true.B
val d_set = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.d.fire && d_first && edge.isRequest(bundle.d.bits)) {
d_set := UIntToOH(bundle.d.bits.sink)
assume(!inflight(bundle.d.bits.sink), "'D' channel re-used a sink ID" + extra)
}
val e_clr = WireInit(0.U(edge.manager.endSinkId.W))
when (bundle.e.fire && e_first && edge.isResponse(bundle.e.bits)) {
e_clr := UIntToOH(bundle.e.bits.sink)
monAssert((d_set | inflight)(bundle.e.bits.sink), "'E' channel acknowledged for nothing inflight" + extra)
}
// edge.client.minLatency applies to BC, not DE
inflight := (inflight | d_set) & ~e_clr
}
def legalizeUnique(bundle: TLBundle, edge: TLEdge): Unit = {
val sourceBits = log2Ceil(edge.client.endSourceId)
val tooBig = 14 // >16kB worth of flight information gets to be too much
if (sourceBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with source bits (${sourceBits}) > ${tooBig}; A=>D transaction flight will not be checked")
} else {
if (args.edge.params(TestplanTestType).simulation) {
if (args.edge.params(TLMonitorStrictMode)) {
legalizeADSource(bundle, edge)
legalizeCDSource(bundle, edge)
} else {
legalizeADSourceOld(bundle, edge)
}
}
if (args.edge.params(TestplanTestType).formal) {
legalizeADSourceFormal(bundle, edge)
}
}
if (edge.client.anySupportProbe && edge.manager.anySupportAcquireB) {
// legalizeBCSourceAddress(bundle, edge) // too much state needed to synthesize...
val sinkBits = log2Ceil(edge.manager.endSinkId)
if (sinkBits > tooBig) {
println(s"WARNING: TLMonitor instantiated on a bus with sink bits (${sinkBits}) > ${tooBig}; D=>E transaction flight will not be checked")
} else {
legalizeDESink(bundle, edge)
}
}
}
def legalize(bundle: TLBundle, edge: TLEdge, reset: Reset): Unit = {
legalizeFormat (bundle, edge)
legalizeMultibeat (bundle, edge)
legalizeUnique (bundle, edge)
}
}
File Misc.scala:
// See LICENSE.Berkeley for license details.
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
import chisel3.util.random.LFSR
import org.chipsalliance.cde.config.Parameters
import scala.math._
class ParameterizedBundle(implicit p: Parameters) extends Bundle
trait Clocked extends Bundle {
val clock = Clock()
val reset = Bool()
}
object DecoupledHelper {
def apply(rvs: Bool*) = new DecoupledHelper(rvs)
}
class DecoupledHelper(val rvs: Seq[Bool]) {
def fire(exclude: Bool, includes: Bool*) = {
require(rvs.contains(exclude), "Excluded Bool not present in DecoupledHelper! Note that DecoupledHelper uses referential equality for exclusion! If you don't want to exclude anything, use fire()!")
(rvs.filter(_ ne exclude) ++ includes).reduce(_ && _)
}
def fire() = {
rvs.reduce(_ && _)
}
}
object MuxT {
def apply[T <: Data, U <: Data](cond: Bool, con: (T, U), alt: (T, U)): (T, U) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2))
def apply[T <: Data, U <: Data, W <: Data](cond: Bool, con: (T, U, W), alt: (T, U, W)): (T, U, W) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3))
def apply[T <: Data, U <: Data, W <: Data, X <: Data](cond: Bool, con: (T, U, W, X), alt: (T, U, W, X)): (T, U, W, X) =
(Mux(cond, con._1, alt._1), Mux(cond, con._2, alt._2), Mux(cond, con._3, alt._3), Mux(cond, con._4, alt._4))
}
/** Creates a cascade of n MuxTs to search for a key value. */
object MuxTLookup {
def apply[S <: UInt, T <: Data, U <: Data](key: S, default: (T, U), mapping: Seq[(S, (T, U))]): (T, U) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
def apply[S <: UInt, T <: Data, U <: Data, W <: Data](key: S, default: (T, U, W), mapping: Seq[(S, (T, U, W))]): (T, U, W) = {
var res = default
for ((k, v) <- mapping.reverse)
res = MuxT(k === key, v, res)
res
}
}
object ValidMux {
def apply[T <: Data](v1: ValidIO[T], v2: ValidIO[T]*): ValidIO[T] = {
apply(v1 +: v2.toSeq)
}
def apply[T <: Data](valids: Seq[ValidIO[T]]): ValidIO[T] = {
val out = Wire(Valid(valids.head.bits.cloneType))
out.valid := valids.map(_.valid).reduce(_ || _)
out.bits := MuxCase(valids.head.bits,
valids.map(v => (v.valid -> v.bits)))
out
}
}
object Str
{
def apply(s: String): UInt = {
var i = BigInt(0)
require(s.forall(validChar _))
for (c <- s)
i = (i << 8) | c
i.U((s.length*8).W)
}
def apply(x: Char): UInt = {
require(validChar(x))
x.U(8.W)
}
def apply(x: UInt): UInt = apply(x, 10)
def apply(x: UInt, radix: Int): UInt = {
val rad = radix.U
val w = x.getWidth
require(w > 0)
var q = x
var s = digit(q % rad)
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
s = Cat(Mux((radix == 10).B && q === 0.U, Str(' '), digit(q % rad)), s)
}
s
}
def apply(x: SInt): UInt = apply(x, 10)
def apply(x: SInt, radix: Int): UInt = {
val neg = x < 0.S
val abs = x.abs.asUInt
if (radix != 10) {
Cat(Mux(neg, Str('-'), Str(' ')), Str(abs, radix))
} else {
val rad = radix.U
val w = abs.getWidth
require(w > 0)
var q = abs
var s = digit(q % rad)
var needSign = neg
for (i <- 1 until ceil(log(2)/log(radix)*w).toInt) {
q = q / rad
val placeSpace = q === 0.U
val space = Mux(needSign, Str('-'), Str(' '))
needSign = needSign && !placeSpace
s = Cat(Mux(placeSpace, space, digit(q % rad)), s)
}
Cat(Mux(needSign, Str('-'), Str(' ')), s)
}
}
private def digit(d: UInt): UInt = Mux(d < 10.U, Str('0')+d, Str(('a'-10).toChar)+d)(7,0)
private def validChar(x: Char) = x == (x & 0xFF)
}
object Split
{
def apply(x: UInt, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
def apply(x: UInt, n2: Int, n1: Int, n0: Int) = {
val w = x.getWidth
(x.extract(w-1,n2), x.extract(n2-1,n1), x.extract(n1-1,n0), x.extract(n0-1,0))
}
}
object Random
{
def apply(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) random.extract(log2Ceil(mod)-1,0)
else PriorityEncoder(partition(apply(1 << log2Up(mod*8), random), mod))
}
def apply(mod: Int): UInt = apply(mod, randomizer)
def oneHot(mod: Int, random: UInt): UInt = {
if (isPow2(mod)) UIntToOH(random(log2Up(mod)-1,0))
else PriorityEncoderOH(partition(apply(1 << log2Up(mod*8), random), mod)).asUInt
}
def oneHot(mod: Int): UInt = oneHot(mod, randomizer)
private def randomizer = LFSR(16)
private def partition(value: UInt, slices: Int) =
Seq.tabulate(slices)(i => value < (((i + 1) << value.getWidth) / slices).U)
}
object Majority {
def apply(in: Set[Bool]): Bool = {
val n = (in.size >> 1) + 1
val clauses = in.subsets(n).map(_.reduce(_ && _))
clauses.reduce(_ || _)
}
def apply(in: Seq[Bool]): Bool = apply(in.toSet)
def apply(in: UInt): Bool = apply(in.asBools.toSet)
}
object PopCountAtLeast {
private def two(x: UInt): (Bool, Bool) = x.getWidth match {
case 1 => (x.asBool, false.B)
case n =>
val half = x.getWidth / 2
val (leftOne, leftTwo) = two(x(half - 1, 0))
val (rightOne, rightTwo) = two(x(x.getWidth - 1, half))
(leftOne || rightOne, leftTwo || rightTwo || (leftOne && rightOne))
}
def apply(x: UInt, n: Int): Bool = n match {
case 0 => true.B
case 1 => x.orR
case 2 => two(x)._2
case 3 => PopCount(x) >= n.U
}
}
// This gets used everywhere, so make the smallest circuit possible ...
// Given an address and size, create a mask of beatBytes size
// eg: (0x3, 0, 4) => 0001, (0x3, 1, 4) => 0011, (0x3, 2, 4) => 1111
// groupBy applies an interleaved OR reduction; groupBy=2 take 0010 => 01
object MaskGen {
def apply(addr_lo: UInt, lgSize: UInt, beatBytes: Int, groupBy: Int = 1): UInt = {
require (groupBy >= 1 && beatBytes >= groupBy)
require (isPow2(beatBytes) && isPow2(groupBy))
val lgBytes = log2Ceil(beatBytes)
val sizeOH = UIntToOH(lgSize | 0.U(log2Up(beatBytes).W), log2Up(beatBytes)) | (groupBy*2 - 1).U
def helper(i: Int): Seq[(Bool, Bool)] = {
if (i == 0) {
Seq((lgSize >= lgBytes.asUInt, true.B))
} else {
val sub = helper(i-1)
val size = sizeOH(lgBytes - i)
val bit = addr_lo(lgBytes - i)
val nbit = !bit
Seq.tabulate (1 << i) { j =>
val (sub_acc, sub_eq) = sub(j/2)
val eq = sub_eq && (if (j % 2 == 1) bit else nbit)
val acc = sub_acc || (size && eq)
(acc, eq)
}
}
}
if (groupBy == beatBytes) 1.U else
Cat(helper(lgBytes-log2Ceil(groupBy)).map(_._1).reverse)
}
}
File PlusArg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.experimental._
import chisel3.util.HasBlackBoxResource
@deprecated("This will be removed in Rocket Chip 2020.08", "Rocket Chip 2020.05")
case class PlusArgInfo(default: BigInt, docstring: String)
/** Case class for PlusArg information
*
* @tparam A scala type of the PlusArg value
* @param default optional default value
* @param docstring text to include in the help
* @param doctype description of the Verilog type of the PlusArg value (e.g. STRING, INT)
*/
private case class PlusArgContainer[A](default: Option[A], docstring: String, doctype: String)
/** Typeclass for converting a type to a doctype string
* @tparam A some type
*/
trait Doctypeable[A] {
/** Return the doctype string for some option */
def toDoctype(a: Option[A]): String
}
/** Object containing implementations of the Doctypeable typeclass */
object Doctypes {
/** Converts an Int => "INT" */
implicit val intToDoctype = new Doctypeable[Int] { def toDoctype(a: Option[Int]) = "INT" }
/** Converts a BigInt => "INT" */
implicit val bigIntToDoctype = new Doctypeable[BigInt] { def toDoctype(a: Option[BigInt]) = "INT" }
/** Converts a String => "STRING" */
implicit val stringToDoctype = new Doctypeable[String] { def toDoctype(a: Option[String]) = "STRING" }
}
class plusarg_reader(val format: String, val default: BigInt, val docstring: String, val width: Int) extends BlackBox(Map(
"FORMAT" -> StringParam(format),
"DEFAULT" -> IntParam(default),
"WIDTH" -> IntParam(width)
)) with HasBlackBoxResource {
val io = IO(new Bundle {
val out = Output(UInt(width.W))
})
addResource("/vsrc/plusarg_reader.v")
}
/* This wrapper class has no outputs, making it clear it is a simulation-only construct */
class PlusArgTimeout(val format: String, val default: BigInt, val docstring: String, val width: Int) extends Module {
val io = IO(new Bundle {
val count = Input(UInt(width.W))
})
val max = Module(new plusarg_reader(format, default, docstring, width)).io.out
when (max > 0.U) {
assert (io.count < max, s"Timeout exceeded: $docstring")
}
}
import Doctypes._
object PlusArg
{
/** PlusArg("foo") will return 42.U if the simulation is run with +foo=42
* Do not use this as an initial register value. The value is set in an
* initial block and thus accessing it from another initial is racey.
* Add a docstring to document the arg, which can be dumped in an elaboration
* pass.
*/
def apply(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32): UInt = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new plusarg_reader(name + "=%d", default, docstring, width)).io.out
}
/** PlusArg.timeout(name, default, docstring)(count) will use chisel.assert
* to kill the simulation when count exceeds the specified integer argument.
* Default 0 will never assert.
*/
def timeout(name: String, default: BigInt = 0, docstring: String = "", width: Int = 32)(count: UInt): Unit = {
PlusArgArtefacts.append(name, Some(default), docstring)
Module(new PlusArgTimeout(name + "=%d", default, docstring, width)).io.count := count
}
}
object PlusArgArtefacts {
private var artefacts: Map[String, PlusArgContainer[_]] = Map.empty
/* Add a new PlusArg */
@deprecated(
"Use `Some(BigInt)` to specify a `default` value. This will be removed in Rocket Chip 2020.08",
"Rocket Chip 2020.05"
)
def append(name: String, default: BigInt, docstring: String): Unit = append(name, Some(default), docstring)
/** Add a new PlusArg
*
* @tparam A scala type of the PlusArg value
* @param name name for the PlusArg
* @param default optional default value
* @param docstring text to include in the help
*/
def append[A : Doctypeable](name: String, default: Option[A], docstring: String): Unit =
artefacts = artefacts ++
Map(name -> PlusArgContainer(default, docstring, implicitly[Doctypeable[A]].toDoctype(default)))
/* From plus args, generate help text */
private def serializeHelp_cHeader(tab: String = ""): String = artefacts
.map{ case(arg, info) =>
s"""|$tab+$arg=${info.doctype}\\n\\
|$tab${" "*20}${info.docstring}\\n\\
|""".stripMargin ++ info.default.map{ case default =>
s"$tab${" "*22}(default=${default})\\n\\\n"}.getOrElse("")
}.toSeq.mkString("\\n\\\n") ++ "\""
/* From plus args, generate a char array of their names */
private def serializeArray_cHeader(tab: String = ""): String = {
val prettyTab = tab + " " * 44 // Length of 'static const ...'
s"${tab}static const char * verilog_plusargs [] = {\\\n" ++
artefacts
.map{ case(arg, _) => s"""$prettyTab"$arg",\\\n""" }
.mkString("")++
s"${prettyTab}0};"
}
/* Generate C code to be included in emulator.cc that helps with
* argument parsing based on available Verilog PlusArgs */
def serialize_cHeader(): String =
s"""|#define PLUSARG_USAGE_OPTIONS \"EMULATOR VERILOG PLUSARGS\\n\\
|${serializeHelp_cHeader(" "*7)}
|${serializeArray_cHeader()}
|""".stripMargin
}
File package.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip
import chisel3._
import chisel3.util._
import scala.math.min
import scala.collection.{immutable, mutable}
package object util {
implicit class UnzippableOption[S, T](val x: Option[(S, T)]) {
def unzip = (x.map(_._1), x.map(_._2))
}
implicit class UIntIsOneOf(private val x: UInt) extends AnyVal {
def isOneOf(s: Seq[UInt]): Bool = s.map(x === _).orR
def isOneOf(u1: UInt, u2: UInt*): Bool = isOneOf(u1 +: u2.toSeq)
}
implicit class VecToAugmentedVec[T <: Data](private val x: Vec[T]) extends AnyVal {
/** Like Vec.apply(idx), but tolerates indices of mismatched width */
def extract(idx: UInt): T = x((idx | 0.U(log2Ceil(x.size).W)).extract(log2Ceil(x.size) - 1, 0))
}
implicit class SeqToAugmentedSeq[T <: Data](private val x: Seq[T]) extends AnyVal {
def apply(idx: UInt): T = {
if (x.size <= 1) {
x.head
} else if (!isPow2(x.size)) {
// For non-power-of-2 seqs, reflect elements to simplify decoder
(x ++ x.takeRight(x.size & -x.size)).toSeq(idx)
} else {
// Ignore MSBs of idx
val truncIdx =
if (idx.isWidthKnown && idx.getWidth <= log2Ceil(x.size)) idx
else (idx | 0.U(log2Ceil(x.size).W))(log2Ceil(x.size)-1, 0)
x.zipWithIndex.tail.foldLeft(x.head) { case (prev, (cur, i)) => Mux(truncIdx === i.U, cur, prev) }
}
}
def extract(idx: UInt): T = VecInit(x).extract(idx)
def asUInt: UInt = Cat(x.map(_.asUInt).reverse)
def rotate(n: Int): Seq[T] = x.drop(n) ++ x.take(n)
def rotate(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotate(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
def rotateRight(n: Int): Seq[T] = x.takeRight(n) ++ x.dropRight(n)
def rotateRight(n: UInt): Seq[T] = {
if (x.size <= 1) {
x
} else {
require(isPow2(x.size))
val amt = n.padTo(log2Ceil(x.size))
(0 until log2Ceil(x.size)).foldLeft(x)((r, i) => (r.rotateRight(1 << i) zip r).map { case (s, a) => Mux(amt(i), s, a) })
}
}
}
// allow bitwise ops on Seq[Bool] just like UInt
implicit class SeqBoolBitwiseOps(private val x: Seq[Bool]) extends AnyVal {
def & (y: Seq[Bool]): Seq[Bool] = (x zip y).map { case (a, b) => a && b }
def | (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a || b }
def ^ (y: Seq[Bool]): Seq[Bool] = padZip(x, y).map { case (a, b) => a ^ b }
def << (n: Int): Seq[Bool] = Seq.fill(n)(false.B) ++ x
def >> (n: Int): Seq[Bool] = x drop n
def unary_~ : Seq[Bool] = x.map(!_)
def andR: Bool = if (x.isEmpty) true.B else x.reduce(_&&_)
def orR: Bool = if (x.isEmpty) false.B else x.reduce(_||_)
def xorR: Bool = if (x.isEmpty) false.B else x.reduce(_^_)
private def padZip(y: Seq[Bool], z: Seq[Bool]): Seq[(Bool, Bool)] = y.padTo(z.size, false.B) zip z.padTo(y.size, false.B)
}
implicit class DataToAugmentedData[T <: Data](private val x: T) extends AnyVal {
def holdUnless(enable: Bool): T = Mux(enable, x, RegEnable(x, enable))
def getElements: Seq[Element] = x match {
case e: Element => Seq(e)
case a: Aggregate => a.getElements.flatMap(_.getElements)
}
}
/** Any Data subtype that has a Bool member named valid. */
type DataCanBeValid = Data { val valid: Bool }
implicit class SeqMemToAugmentedSeqMem[T <: Data](private val x: SyncReadMem[T]) extends AnyVal {
def readAndHold(addr: UInt, enable: Bool): T = x.read(addr, enable) holdUnless RegNext(enable)
}
implicit class StringToAugmentedString(private val x: String) extends AnyVal {
/** converts from camel case to to underscores, also removing all spaces */
def underscore: String = x.tail.foldLeft(x.headOption.map(_.toLower + "") getOrElse "") {
case (acc, c) if c.isUpper => acc + "_" + c.toLower
case (acc, c) if c == ' ' => acc
case (acc, c) => acc + c
}
/** converts spaces or underscores to hyphens, also lowering case */
def kebab: String = x.toLowerCase map {
case ' ' => '-'
case '_' => '-'
case c => c
}
def named(name: Option[String]): String = {
x + name.map("_named_" + _ ).getOrElse("_with_no_name")
}
def named(name: String): String = named(Some(name))
}
implicit def uintToBitPat(x: UInt): BitPat = BitPat(x)
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(private val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(0.U((n - x.getWidth).W), x)
}
// shifts left by n if n >= 0, or right by -n if n < 0
def << (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << n(w-1, 0)
Mux(n(w), shifted >> (1 << w), shifted)
}
// shifts right by n if n >= 0, or left by -n if n < 0
def >> (n: SInt): UInt = {
val w = n.getWidth - 1
require(w <= 30)
val shifted = x << (1 << w) >> n(w-1, 0)
Mux(n(w), shifted, shifted >> (1 << w))
}
// Like UInt.apply(hi, lo), but returns 0.U for zero-width extracts
def extract(hi: Int, lo: Int): UInt = {
require(hi >= lo-1)
if (hi == lo-1) 0.U
else x(hi, lo)
}
// Like Some(UInt.apply(hi, lo)), but returns None for zero-width extracts
def extractOption(hi: Int, lo: Int): Option[UInt] = {
require(hi >= lo-1)
if (hi == lo-1) None
else Some(x(hi, lo))
}
// like x & ~y, but first truncate or zero-extend y to x's width
def andNot(y: UInt): UInt = x & ~(y | (x & 0.U))
def rotateRight(n: Int): UInt = if (n == 0) x else Cat(x(n-1, 0), x >> n)
def rotateRight(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateRight(1 << i), r))
}
}
def rotateLeft(n: Int): UInt = if (n == 0) x else Cat(x(x.getWidth-1-n,0), x(x.getWidth-1,x.getWidth-n))
def rotateLeft(n: UInt): UInt = {
if (x.getWidth <= 1) {
x
} else {
val amt = n.padTo(log2Ceil(x.getWidth))
(0 until log2Ceil(x.getWidth)).foldLeft(x)((r, i) => Mux(amt(i), r.rotateLeft(1 << i), r))
}
}
// compute (this + y) % n, given (this < n) and (y < n)
def addWrap(y: UInt, n: Int): UInt = {
val z = x +& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z >= n.U, z - n.U, z)(log2Ceil(n)-1, 0)
}
// compute (this - y) % n, given (this < n) and (y < n)
def subWrap(y: UInt, n: Int): UInt = {
val z = x -& y
if (isPow2(n)) z(n.log2-1, 0) else Mux(z(z.getWidth-1), z + n.U, z)(log2Ceil(n)-1, 0)
}
def grouped(width: Int): Seq[UInt] =
(0 until x.getWidth by width).map(base => x(base + width - 1, base))
def inRange(base: UInt, bounds: UInt) = x >= base && x < bounds
def ## (y: Option[UInt]): UInt = y.map(x ## _).getOrElse(x)
// Like >=, but prevents x-prop for ('x >= 0)
def >== (y: UInt): Bool = x >= y || y === 0.U
}
implicit class OptionUIntToAugmentedOptionUInt(private val x: Option[UInt]) extends AnyVal {
def ## (y: UInt): UInt = x.map(_ ## y).getOrElse(y)
def ## (y: Option[UInt]): Option[UInt] = x.map(_ ## y)
}
implicit class BooleanToAugmentedBoolean(private val x: Boolean) extends AnyVal {
def toInt: Int = if (x) 1 else 0
// this one's snagged from scalaz
def option[T](z: => T): Option[T] = if (x) Some(z) else None
}
implicit class IntToAugmentedInt(private val x: Int) extends AnyVal {
// exact log2
def log2: Int = {
require(isPow2(x))
log2Ceil(x)
}
}
def OH1ToOH(x: UInt): UInt = (x << 1 | 1.U) & ~Cat(0.U(1.W), x)
def OH1ToUInt(x: UInt): UInt = OHToUInt(OH1ToOH(x))
def UIntToOH1(x: UInt, width: Int): UInt = ~((-1).S(width.W).asUInt << x)(width-1, 0)
def UIntToOH1(x: UInt): UInt = UIntToOH1(x, (1 << x.getWidth) - 1)
def trailingZeros(x: Int): Option[Int] = if (x > 0) Some(log2Ceil(x & -x)) else None
// Fill 1s from low bits to high bits
def leftOR(x: UInt): UInt = leftOR(x, x.getWidth, x.getWidth)
def leftOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x << s)(width-1,0))
helper(1, x)(width-1, 0)
}
// Fill 1s form high bits to low bits
def rightOR(x: UInt): UInt = rightOR(x, x.getWidth, x.getWidth)
def rightOR(x: UInt, width: Integer, cap: Integer = 999999): UInt = {
val stop = min(width, cap)
def helper(s: Int, x: UInt): UInt =
if (s >= stop) x else helper(s+s, x | (x >> s))
helper(1, x)(width-1, 0)
}
def OptimizationBarrier[T <: Data](in: T): T = {
val barrier = Module(new Module {
val io = IO(new Bundle {
val x = Input(chiselTypeOf(in))
val y = Output(chiselTypeOf(in))
})
io.y := io.x
override def desiredName = s"OptimizationBarrier_${in.typeName}"
})
barrier.io.x := in
barrier.io.y
}
/** Similar to Seq.groupBy except this returns a Seq instead of a Map
* Useful for deterministic code generation
*/
def groupByIntoSeq[A, K](xs: Seq[A])(f: A => K): immutable.Seq[(K, immutable.Seq[A])] = {
val map = mutable.LinkedHashMap.empty[K, mutable.ListBuffer[A]]
for (x <- xs) {
val key = f(x)
val l = map.getOrElseUpdate(key, mutable.ListBuffer.empty[A])
l += x
}
map.view.map({ case (k, vs) => k -> vs.toList }).toList
}
def heterogeneousOrGlobalSetting[T](in: Seq[T], n: Int): Seq[T] = in.size match {
case 1 => List.fill(n)(in.head)
case x if x == n => in
case _ => throw new Exception(s"must provide exactly 1 or $n of some field, but got:\n$in")
}
// HeterogeneousBag moved to standalond diplomacy
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
def HeterogeneousBag[T <: Data](elts: Seq[T]) = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag[T](elts)
@deprecated("HeterogeneousBag has been absorbed into standalone diplomacy library", "rocketchip 2.0.0")
val HeterogeneousBag = _root_.org.chipsalliance.diplomacy.nodes.HeterogeneousBag
}
File Bundles.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import freechips.rocketchip.util._
import scala.collection.immutable.ListMap
import chisel3.util.Decoupled
import chisel3.util.DecoupledIO
import chisel3.reflect.DataMirror
abstract class TLBundleBase(val params: TLBundleParameters) extends Bundle
// common combos in lazy policy:
// Put + Acquire
// Release + AccessAck
object TLMessages
{
// A B C D E
def PutFullData = 0.U // . . => AccessAck
def PutPartialData = 1.U // . . => AccessAck
def ArithmeticData = 2.U // . . => AccessAckData
def LogicalData = 3.U // . . => AccessAckData
def Get = 4.U // . . => AccessAckData
def Hint = 5.U // . . => HintAck
def AcquireBlock = 6.U // . => Grant[Data]
def AcquirePerm = 7.U // . => Grant[Data]
def Probe = 6.U // . => ProbeAck[Data]
def AccessAck = 0.U // . .
def AccessAckData = 1.U // . .
def HintAck = 2.U // . .
def ProbeAck = 4.U // .
def ProbeAckData = 5.U // .
def Release = 6.U // . => ReleaseAck
def ReleaseData = 7.U // . => ReleaseAck
def Grant = 4.U // . => GrantAck
def GrantData = 5.U // . => GrantAck
def ReleaseAck = 6.U // .
def GrantAck = 0.U // .
def isA(x: UInt) = x <= AcquirePerm
def isB(x: UInt) = x <= Probe
def isC(x: UInt) = x <= ReleaseData
def isD(x: UInt) = x <= ReleaseAck
def adResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, Grant, Grant)
def bcResponse = VecInit(AccessAck, AccessAck, AccessAckData, AccessAckData, AccessAckData, HintAck, ProbeAck, ProbeAck)
def a = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("AcquireBlock",TLPermissions.PermMsgGrow),
("AcquirePerm",TLPermissions.PermMsgGrow))
def b = Seq( ("PutFullData",TLPermissions.PermMsgReserved),
("PutPartialData",TLPermissions.PermMsgReserved),
("ArithmeticData",TLAtomics.ArithMsg),
("LogicalData",TLAtomics.LogicMsg),
("Get",TLPermissions.PermMsgReserved),
("Hint",TLHints.HintsMsg),
("Probe",TLPermissions.PermMsgCap))
def c = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("ProbeAck",TLPermissions.PermMsgReport),
("ProbeAckData",TLPermissions.PermMsgReport),
("Release",TLPermissions.PermMsgReport),
("ReleaseData",TLPermissions.PermMsgReport))
def d = Seq( ("AccessAck",TLPermissions.PermMsgReserved),
("AccessAckData",TLPermissions.PermMsgReserved),
("HintAck",TLPermissions.PermMsgReserved),
("Invalid Opcode",TLPermissions.PermMsgReserved),
("Grant",TLPermissions.PermMsgCap),
("GrantData",TLPermissions.PermMsgCap),
("ReleaseAck",TLPermissions.PermMsgReserved))
}
/**
* The three primary TileLink permissions are:
* (T)runk: the agent is (or is on inwards path to) the global point of serialization.
* (B)ranch: the agent is on an outwards path to
* (N)one:
* These permissions are permuted by transfer operations in various ways.
* Operations can cap permissions, request for them to be grown or shrunk,
* or for a report on their current status.
*/
object TLPermissions
{
val aWidth = 2
val bdWidth = 2
val cWidth = 3
// Cap types (Grant = new permissions, Probe = permisions <= target)
def toT = 0.U(bdWidth.W)
def toB = 1.U(bdWidth.W)
def toN = 2.U(bdWidth.W)
def isCap(x: UInt) = x <= toN
// Grow types (Acquire = permissions >= target)
def NtoB = 0.U(aWidth.W)
def NtoT = 1.U(aWidth.W)
def BtoT = 2.U(aWidth.W)
def isGrow(x: UInt) = x <= BtoT
// Shrink types (ProbeAck, Release)
def TtoB = 0.U(cWidth.W)
def TtoN = 1.U(cWidth.W)
def BtoN = 2.U(cWidth.W)
def isShrink(x: UInt) = x <= BtoN
// Report types (ProbeAck, Release)
def TtoT = 3.U(cWidth.W)
def BtoB = 4.U(cWidth.W)
def NtoN = 5.U(cWidth.W)
def isReport(x: UInt) = x <= NtoN
def PermMsgGrow:Seq[String] = Seq("Grow NtoB", "Grow NtoT", "Grow BtoT")
def PermMsgCap:Seq[String] = Seq("Cap toT", "Cap toB", "Cap toN")
def PermMsgReport:Seq[String] = Seq("Shrink TtoB", "Shrink TtoN", "Shrink BtoN", "Report TotT", "Report BtoB", "Report NtoN")
def PermMsgReserved:Seq[String] = Seq("Reserved")
}
object TLAtomics
{
val width = 3
// Arithmetic types
def MIN = 0.U(width.W)
def MAX = 1.U(width.W)
def MINU = 2.U(width.W)
def MAXU = 3.U(width.W)
def ADD = 4.U(width.W)
def isArithmetic(x: UInt) = x <= ADD
// Logical types
def XOR = 0.U(width.W)
def OR = 1.U(width.W)
def AND = 2.U(width.W)
def SWAP = 3.U(width.W)
def isLogical(x: UInt) = x <= SWAP
def ArithMsg:Seq[String] = Seq("MIN", "MAX", "MINU", "MAXU", "ADD")
def LogicMsg:Seq[String] = Seq("XOR", "OR", "AND", "SWAP")
}
object TLHints
{
val width = 1
def PREFETCH_READ = 0.U(width.W)
def PREFETCH_WRITE = 1.U(width.W)
def isHints(x: UInt) = x <= PREFETCH_WRITE
def HintsMsg:Seq[String] = Seq("PrefetchRead", "PrefetchWrite")
}
sealed trait TLChannel extends TLBundleBase {
val channelName: String
}
sealed trait TLDataChannel extends TLChannel
sealed trait TLAddrChannel extends TLDataChannel
final class TLBundleA(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleA_${params.shortName}"
val channelName = "'A' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(List(TLAtomics.width, TLPermissions.aWidth, TLHints.width).max.W) // amo_opcode || grow perms || hint
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleB(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleB_${params.shortName}"
val channelName = "'B' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val address = UInt(params.addressBits.W) // from
// variable fields during multibeat:
val mask = UInt((params.dataBits/8).W)
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleC(params: TLBundleParameters)
extends TLBundleBase(params) with TLAddrChannel
{
override def typeName = s"TLBundleC_${params.shortName}"
val channelName = "'C' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.cWidth.W) // shrink or report perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // from
val address = UInt(params.addressBits.W) // to
val user = BundleMap(params.requestFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleD(params: TLBundleParameters)
extends TLBundleBase(params) with TLDataChannel
{
override def typeName = s"TLBundleD_${params.shortName}"
val channelName = "'D' channel"
// fixed fields during multibeat:
val opcode = UInt(3.W)
val param = UInt(TLPermissions.bdWidth.W) // cap perms
val size = UInt(params.sizeBits.W)
val source = UInt(params.sourceBits.W) // to
val sink = UInt(params.sinkBits.W) // from
val denied = Bool() // implies corrupt iff *Data
val user = BundleMap(params.responseFields)
val echo = BundleMap(params.echoFields)
// variable fields during multibeat:
val data = UInt(params.dataBits.W)
val corrupt = Bool() // only applies to *Data messages
}
final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel
{
override def typeName = s"TLBundleE_${params.shortName}"
val channelName = "'E' channel"
val sink = UInt(params.sinkBits.W) // to
}
class TLBundle(val params: TLBundleParameters) extends Record
{
// Emulate a Bundle with elements abcde or ad depending on params.hasBCE
private val optA = Some (Decoupled(new TLBundleA(params)))
private val optB = params.hasBCE.option(Flipped(Decoupled(new TLBundleB(params))))
private val optC = params.hasBCE.option(Decoupled(new TLBundleC(params)))
private val optD = Some (Flipped(Decoupled(new TLBundleD(params))))
private val optE = params.hasBCE.option(Decoupled(new TLBundleE(params)))
def a: DecoupledIO[TLBundleA] = optA.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleA(params)))))
def b: DecoupledIO[TLBundleB] = optB.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleB(params)))))
def c: DecoupledIO[TLBundleC] = optC.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleC(params)))))
def d: DecoupledIO[TLBundleD] = optD.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleD(params)))))
def e: DecoupledIO[TLBundleE] = optE.getOrElse(WireDefault(0.U.asTypeOf(Decoupled(new TLBundleE(params)))))
val elements =
if (params.hasBCE) ListMap("e" -> e, "d" -> d, "c" -> c, "b" -> b, "a" -> a)
else ListMap("d" -> d, "a" -> a)
def tieoff(): Unit = {
DataMirror.specifiedDirectionOf(a.ready) match {
case SpecifiedDirection.Input =>
a.ready := false.B
c.ready := false.B
e.ready := false.B
b.valid := false.B
d.valid := false.B
case SpecifiedDirection.Output =>
a.valid := false.B
c.valid := false.B
e.valid := false.B
b.ready := false.B
d.ready := false.B
case _ =>
}
}
}
object TLBundle
{
def apply(params: TLBundleParameters) = new TLBundle(params)
}
class TLAsyncBundleBase(val params: TLAsyncBundleParameters) extends Bundle
class TLAsyncBundle(params: TLAsyncBundleParameters) extends TLAsyncBundleBase(params)
{
val a = new AsyncBundle(new TLBundleA(params.base), params.async)
val b = Flipped(new AsyncBundle(new TLBundleB(params.base), params.async))
val c = new AsyncBundle(new TLBundleC(params.base), params.async)
val d = Flipped(new AsyncBundle(new TLBundleD(params.base), params.async))
val e = new AsyncBundle(new TLBundleE(params.base), params.async)
}
class TLRationalBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = RationalIO(new TLBundleA(params))
val b = Flipped(RationalIO(new TLBundleB(params)))
val c = RationalIO(new TLBundleC(params))
val d = Flipped(RationalIO(new TLBundleD(params)))
val e = RationalIO(new TLBundleE(params))
}
class TLCreditedBundle(params: TLBundleParameters) extends TLBundleBase(params)
{
val a = CreditedIO(new TLBundleA(params))
val b = Flipped(CreditedIO(new TLBundleB(params)))
val c = CreditedIO(new TLBundleC(params))
val d = Flipped(CreditedIO(new TLBundleD(params)))
val e = CreditedIO(new TLBundleE(params))
}
File Parameters.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config._
import org.chipsalliance.diplomacy.nodes._
import freechips.rocketchip.diplomacy.{
AddressDecoder, AddressSet, BufferParams, DirectedBuffers, IdMap, IdMapEntry,
IdRange, RegionType, TransferSizes
}
import freechips.rocketchip.resources.{Resource, ResourceAddress, ResourcePermissions}
import freechips.rocketchip.util.{
AsyncQueueParams, BundleField, BundleFieldBase, BundleKeyBase,
CreditedDelay, groupByIntoSeq, RationalDirection, SimpleProduct
}
import scala.math.max
//These transfer sizes describe requests issued from masters on the A channel that will be responded by slaves on the D channel
case class TLMasterToSlaveTransferSizes(
// Supports both Acquire+Release of the following two sizes:
acquireT: TransferSizes = TransferSizes.none,
acquireB: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none)
extends TLCommonTransferSizes {
def intersect(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .intersect(rhs.acquireT),
acquireB = acquireB .intersect(rhs.acquireB),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint))
def mincover(rhs: TLMasterToSlaveTransferSizes) = TLMasterToSlaveTransferSizes(
acquireT = acquireT .mincover(rhs.acquireT),
acquireB = acquireB .mincover(rhs.acquireB),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint))
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(acquireT, "T"),
str(acquireB, "B"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""acquireT = ${acquireT}
|acquireB = ${acquireB}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLMasterToSlaveTransferSizes {
def unknownEmits = TLMasterToSlaveTransferSizes(
acquireT = TransferSizes(1, 4096),
acquireB = TransferSizes(1, 4096),
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096))
def unknownSupports = TLMasterToSlaveTransferSizes()
}
//These transfer sizes describe requests issued from slaves on the B channel that will be responded by masters on the C channel
case class TLSlaveToMasterTransferSizes(
probe: TransferSizes = TransferSizes.none,
arithmetic: TransferSizes = TransferSizes.none,
logical: TransferSizes = TransferSizes.none,
get: TransferSizes = TransferSizes.none,
putFull: TransferSizes = TransferSizes.none,
putPartial: TransferSizes = TransferSizes.none,
hint: TransferSizes = TransferSizes.none
) extends TLCommonTransferSizes {
def intersect(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .intersect(rhs.probe),
arithmetic = arithmetic.intersect(rhs.arithmetic),
logical = logical .intersect(rhs.logical),
get = get .intersect(rhs.get),
putFull = putFull .intersect(rhs.putFull),
putPartial = putPartial.intersect(rhs.putPartial),
hint = hint .intersect(rhs.hint)
)
def mincover(rhs: TLSlaveToMasterTransferSizes) = TLSlaveToMasterTransferSizes(
probe = probe .mincover(rhs.probe),
arithmetic = arithmetic.mincover(rhs.arithmetic),
logical = logical .mincover(rhs.logical),
get = get .mincover(rhs.get),
putFull = putFull .mincover(rhs.putFull),
putPartial = putPartial.mincover(rhs.putPartial),
hint = hint .mincover(rhs.hint)
)
// Reduce rendering to a simple yes/no per field
override def toString = {
def str(x: TransferSizes, flag: String) = if (x.none) "" else flag
def flags = Vector(
str(probe, "P"),
str(arithmetic, "A"),
str(logical, "L"),
str(get, "G"),
str(putFull, "F"),
str(putPartial, "P"),
str(hint, "H"))
flags.mkString
}
// Prints out the actual information in a user readable way
def infoString = {
s"""probe = ${probe}
|arithmetic = ${arithmetic}
|logical = ${logical}
|get = ${get}
|putFull = ${putFull}
|putPartial = ${putPartial}
|hint = ${hint}
|
|""".stripMargin
}
}
object TLSlaveToMasterTransferSizes {
def unknownEmits = TLSlaveToMasterTransferSizes(
arithmetic = TransferSizes(1, 4096),
logical = TransferSizes(1, 4096),
get = TransferSizes(1, 4096),
putFull = TransferSizes(1, 4096),
putPartial = TransferSizes(1, 4096),
hint = TransferSizes(1, 4096),
probe = TransferSizes(1, 4096))
def unknownSupports = TLSlaveToMasterTransferSizes()
}
trait TLCommonTransferSizes {
def arithmetic: TransferSizes
def logical: TransferSizes
def get: TransferSizes
def putFull: TransferSizes
def putPartial: TransferSizes
def hint: TransferSizes
}
class TLSlaveParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
setName: Option[String],
val address: Seq[AddressSet],
val regionType: RegionType.T,
val executable: Boolean,
val fifoId: Option[Int],
val supports: TLMasterToSlaveTransferSizes,
val emits: TLSlaveToMasterTransferSizes,
// By default, slaves are forbidden from issuing 'denied' responses (it prevents Fragmentation)
val alwaysGrantsT: Boolean, // typically only true for CacheCork'd read-write devices; dual: neverReleaseData
// If fifoId=Some, all accesses sent to the same fifoId are executed and ACK'd in FIFO order
// Note: you can only rely on this FIFO behaviour if your TLMasterParameters include requestFifo
val mayDenyGet: Boolean, // applies to: AccessAckData, GrantData
val mayDenyPut: Boolean) // applies to: AccessAck, Grant, HintAck
// ReleaseAck may NEVER be denied
extends SimpleProduct
{
def sortedAddress = address.sorted
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlaveParameters]
override def productPrefix = "TLSlaveParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 11
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => address
case 2 => resources
case 3 => regionType
case 4 => executable
case 5 => fifoId
case 6 => supports
case 7 => emits
case 8 => alwaysGrantsT
case 9 => mayDenyGet
case 10 => mayDenyPut
case _ => throw new IndexOutOfBoundsException(n.toString)
}
def supportsAcquireT: TransferSizes = supports.acquireT
def supportsAcquireB: TransferSizes = supports.acquireB
def supportsArithmetic: TransferSizes = supports.arithmetic
def supportsLogical: TransferSizes = supports.logical
def supportsGet: TransferSizes = supports.get
def supportsPutFull: TransferSizes = supports.putFull
def supportsPutPartial: TransferSizes = supports.putPartial
def supportsHint: TransferSizes = supports.hint
require (!address.isEmpty, "Address cannot be empty")
address.foreach { a => require (a.finite, "Address must be finite") }
address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
require (supportsPutFull.contains(supportsPutPartial), s"PutFull($supportsPutFull) < PutPartial($supportsPutPartial)")
require (supportsPutFull.contains(supportsArithmetic), s"PutFull($supportsPutFull) < Arithmetic($supportsArithmetic)")
require (supportsPutFull.contains(supportsLogical), s"PutFull($supportsPutFull) < Logical($supportsLogical)")
require (supportsGet.contains(supportsArithmetic), s"Get($supportsGet) < Arithmetic($supportsArithmetic)")
require (supportsGet.contains(supportsLogical), s"Get($supportsGet) < Logical($supportsLogical)")
require (supportsAcquireB.contains(supportsAcquireT), s"AcquireB($supportsAcquireB) < AcquireT($supportsAcquireT)")
require (!alwaysGrantsT || supportsAcquireT, s"Must supportAcquireT if promising to always grantT")
// Make sure that the regionType agrees with the capabilities
require (!supportsAcquireB || regionType >= RegionType.UNCACHED) // acquire -> uncached, tracked, cached
require (regionType <= RegionType.UNCACHED || supportsAcquireB) // tracked, cached -> acquire
require (regionType != RegionType.UNCACHED || supportsGet) // uncached -> supportsGet
val name = setName.orElse(nodePath.lastOption.map(_.lazyModule.name)).getOrElse("disconnected")
val maxTransfer = List( // Largest supported transfer of all types
supportsAcquireT.max,
supportsAcquireB.max,
supportsArithmetic.max,
supportsLogical.max,
supportsGet.max,
supportsPutFull.max,
supportsPutPartial.max).max
val maxAddress = address.map(_.max).max
val minAlignment = address.map(_.alignment).min
// The device had better not support a transfer larger than its alignment
require (minAlignment >= maxTransfer, s"Bad $address: minAlignment ($minAlignment) must be >= maxTransfer ($maxTransfer)")
def toResource: ResourceAddress = {
ResourceAddress(address, ResourcePermissions(
r = supportsAcquireB || supportsGet,
w = supportsAcquireT || supportsPutFull,
x = executable,
c = supportsAcquireB,
a = supportsArithmetic && supportsLogical))
}
def findTreeViolation() = nodePath.find {
case _: MixedAdapterNode[_, _, _, _, _, _, _, _] => false
case _: SinkNode[_, _, _, _, _] => false
case node => node.inputs.size != 1
}
def isTree = findTreeViolation() == None
def infoString = {
s"""Slave Name = ${name}
|Slave Address = ${address}
|supports = ${supports.infoString}
|
|""".stripMargin
}
def v1copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
new TLSlaveParameters(
setName = setName,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = emits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: Option[String] = setName,
address: Seq[AddressSet] = address,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
fifoId: Option[Int] = fifoId,
supports: TLMasterToSlaveTransferSizes = supports,
emits: TLSlaveToMasterTransferSizes = emits,
alwaysGrantsT: Boolean = alwaysGrantsT,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
@deprecated("Use v1copy instead of copy","")
def copy(
address: Seq[AddressSet] = address,
resources: Seq[Resource] = resources,
regionType: RegionType.T = regionType,
executable: Boolean = executable,
nodePath: Seq[BaseNode] = nodePath,
supportsAcquireT: TransferSizes = supports.acquireT,
supportsAcquireB: TransferSizes = supports.acquireB,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint,
mayDenyGet: Boolean = mayDenyGet,
mayDenyPut: Boolean = mayDenyPut,
alwaysGrantsT: Boolean = alwaysGrantsT,
fifoId: Option[Int] = fifoId) =
{
v1copy(
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supportsAcquireT = supportsAcquireT,
supportsAcquireB = supportsAcquireB,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
}
object TLSlaveParameters {
def v1(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
{
new TLSlaveParameters(
setName = None,
address = address,
resources = resources,
regionType = regionType,
executable = executable,
nodePath = nodePath,
supports = TLMasterToSlaveTransferSizes(
acquireT = supportsAcquireT,
acquireB = supportsAcquireB,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLSlaveToMasterTransferSizes.unknownEmits,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut,
alwaysGrantsT = alwaysGrantsT,
fifoId = fifoId)
}
def v2(
address: Seq[AddressSet],
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Seq(),
name: Option[String] = None,
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
fifoId: Option[Int] = None,
supports: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownSupports,
emits: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownEmits,
alwaysGrantsT: Boolean = false,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false) =
{
new TLSlaveParameters(
nodePath = nodePath,
resources = resources,
setName = name,
address = address,
regionType = regionType,
executable = executable,
fifoId = fifoId,
supports = supports,
emits = emits,
alwaysGrantsT = alwaysGrantsT,
mayDenyGet = mayDenyGet,
mayDenyPut = mayDenyPut)
}
}
object TLManagerParameters {
@deprecated("Use TLSlaveParameters.v1 instead of TLManagerParameters","")
def apply(
address: Seq[AddressSet],
resources: Seq[Resource] = Seq(),
regionType: RegionType.T = RegionType.GET_EFFECTS,
executable: Boolean = false,
nodePath: Seq[BaseNode] = Seq(),
supportsAcquireT: TransferSizes = TransferSizes.none,
supportsAcquireB: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none,
mayDenyGet: Boolean = false,
mayDenyPut: Boolean = false,
alwaysGrantsT: Boolean = false,
fifoId: Option[Int] = None) =
TLSlaveParameters.v1(
address,
resources,
regionType,
executable,
nodePath,
supportsAcquireT,
supportsAcquireB,
supportsArithmetic,
supportsLogical,
supportsGet,
supportsPutFull,
supportsPutPartial,
supportsHint,
mayDenyGet,
mayDenyPut,
alwaysGrantsT,
fifoId,
)
}
case class TLChannelBeatBytes(a: Option[Int], b: Option[Int], c: Option[Int], d: Option[Int])
{
def members = Seq(a, b, c, d)
members.collect { case Some(beatBytes) =>
require (isPow2(beatBytes), "Data channel width must be a power of 2")
}
}
object TLChannelBeatBytes{
def apply(beatBytes: Int): TLChannelBeatBytes = TLChannelBeatBytes(
Some(beatBytes),
Some(beatBytes),
Some(beatBytes),
Some(beatBytes))
def apply(): TLChannelBeatBytes = TLChannelBeatBytes(
None,
None,
None,
None)
}
class TLSlavePortParameters private(
val slaves: Seq[TLSlaveParameters],
val channelBytes: TLChannelBeatBytes,
val endSinkId: Int,
val minLatency: Int,
val responseFields: Seq[BundleFieldBase],
val requestKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
def sortedSlaves = slaves.sortBy(_.sortedAddress.head)
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLSlavePortParameters]
override def productPrefix = "TLSlavePortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => slaves
case 1 => channelBytes
case 2 => endSinkId
case 3 => minLatency
case 4 => responseFields
case 5 => requestKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!slaves.isEmpty, "Slave ports must have slaves")
require (endSinkId >= 0, "Sink ids cannot be negative")
require (minLatency >= 0, "Minimum required latency cannot be negative")
// Using this API implies you cannot handle mixed-width busses
def beatBytes = {
channelBytes.members.foreach { width =>
require (width.isDefined && width == channelBytes.a)
}
channelBytes.a.get
}
// TODO this should be deprecated
def managers = slaves
def requireFifo(policy: TLFIFOFixer.Policy = TLFIFOFixer.allFIFO) = {
val relevant = slaves.filter(m => policy(m))
relevant.foreach { m =>
require(m.fifoId == relevant.head.fifoId, s"${m.name} had fifoId ${m.fifoId}, which was not homogeneous (${slaves.map(s => (s.name, s.fifoId))}) ")
}
}
// Bounds on required sizes
def maxAddress = slaves.map(_.maxAddress).max
def maxTransfer = slaves.map(_.maxTransfer).max
def mayDenyGet = slaves.exists(_.mayDenyGet)
def mayDenyPut = slaves.exists(_.mayDenyPut)
// Diplomatically determined operation sizes emitted by all outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = slaves.map(_.emits).reduce( _ intersect _)
// Operation Emitted by at least one outward Slaves
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = slaves.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportClaims = slaves.map(_.supports).reduce( _ intersect _)
val allSupportAcquireT = allSupportClaims.acquireT
val allSupportAcquireB = allSupportClaims.acquireB
val allSupportArithmetic = allSupportClaims.arithmetic
val allSupportLogical = allSupportClaims.logical
val allSupportGet = allSupportClaims.get
val allSupportPutFull = allSupportClaims.putFull
val allSupportPutPartial = allSupportClaims.putPartial
val allSupportHint = allSupportClaims.hint
// Operation supported by at least one outward Slaves
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportClaims = slaves.map(_.supports).reduce(_ mincover _)
val anySupportAcquireT = !anySupportClaims.acquireT.none
val anySupportAcquireB = !anySupportClaims.acquireB.none
val anySupportArithmetic = !anySupportClaims.arithmetic.none
val anySupportLogical = !anySupportClaims.logical.none
val anySupportGet = !anySupportClaims.get.none
val anySupportPutFull = !anySupportClaims.putFull.none
val anySupportPutPartial = !anySupportClaims.putPartial.none
val anySupportHint = !anySupportClaims.hint.none
// Supporting Acquire means being routable for GrantAck
require ((endSinkId == 0) == !anySupportAcquireB)
// These return Option[TLSlaveParameters] for your convenience
def find(address: BigInt) = slaves.find(_.address.exists(_.contains(address)))
// The safe version will check the entire address
def findSafe(address: UInt) = VecInit(sortedSlaves.map(_.address.map(_.contains(address)).reduce(_ || _)))
// The fast version assumes the address is valid (you probably want fastProperty instead of this function)
def findFast(address: UInt) = {
val routingMask = AddressDecoder(slaves.map(_.address))
VecInit(sortedSlaves.map(_.address.map(_.widen(~routingMask)).distinct.map(_.contains(address)).reduce(_ || _)))
}
// Compute the simplest AddressSets that decide a key
def fastPropertyGroup[K](p: TLSlaveParameters => K): Seq[(K, Seq[AddressSet])] = {
val groups = groupByIntoSeq(sortedSlaves.map(m => (p(m), m.address)))( _._1).map { case (k, vs) =>
k -> vs.flatMap(_._2)
}
val reductionMask = AddressDecoder(groups.map(_._2))
groups.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~reductionMask)).distinct) }
}
// Select a property
def fastProperty[K, D <: Data](address: UInt, p: TLSlaveParameters => K, d: K => D): D =
Mux1H(fastPropertyGroup(p).map { case (v, a) => (a.map(_.contains(address)).reduce(_||_), d(v)) })
// Note: returns the actual fifoId + 1 or 0 if None
def findFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.map(_+1).getOrElse(0), (i:Int) => i.U)
def hasFifoIdFast(address: UInt) = fastProperty(address, _.fifoId.isDefined, (b:Boolean) => b.B)
// Does this Port manage this ID/address?
def containsSafe(address: UInt) = findSafe(address).reduce(_ || _)
private def addressHelper(
// setting safe to false indicates that all addresses are expected to be legal, which might reduce circuit complexity
safe: Boolean,
// member filters out the sizes being checked based on the opcode being emitted or supported
member: TLSlaveParameters => TransferSizes,
address: UInt,
lgSize: UInt,
// range provides a limit on the sizes that are expected to be evaluated, which might reduce circuit complexity
range: Option[TransferSizes]): Bool = {
// trim reduces circuit complexity by intersecting checked sizes with the range argument
def trim(x: TransferSizes) = range.map(_.intersect(x)).getOrElse(x)
// groupBy returns an unordered map, convert back to Seq and sort the result for determinism
// groupByIntoSeq is turning slaves into trimmed membership sizes
// We are grouping all the slaves by their transfer size where
// if they support the trimmed size then
// member is the type of transfer that you are looking for (What you are trying to filter on)
// When you consider membership, you are trimming the sizes to only the ones that you care about
// you are filtering the slaves based on both whether they support a particular opcode and the size
// Grouping the slaves based on the actual transfer size range they support
// intersecting the range and checking their membership
// FOR SUPPORTCASES instead of returning the list of slaves,
// you are returning a map from transfer size to the set of
// address sets that are supported for that transfer size
// find all the slaves that support a certain type of operation and then group their addresses by the supported size
// for every size there could be multiple address ranges
// safety is a trade off between checking between all possible addresses vs only the addresses
// that are known to have supported sizes
// the trade off is 'checking all addresses is a more expensive circuit but will always give you
// the right answer even if you give it an illegal address'
// the not safe version is a cheaper circuit but if you give it an illegal address then it might produce the wrong answer
// fast presumes address legality
// This groupByIntoSeq deterministically groups all address sets for which a given `member` transfer size applies.
// In the resulting Map of cases, the keys are transfer sizes and the values are all address sets which emit or support that size.
val supportCases = groupByIntoSeq(slaves)(m => trim(member(m))).map { case (k: TransferSizes, vs: Seq[TLSlaveParameters]) =>
k -> vs.flatMap(_.address)
}
// safe produces a circuit that compares against all possible addresses,
// whereas fast presumes that the address is legal but uses an efficient address decoder
val mask = if (safe) ~BigInt(0) else AddressDecoder(supportCases.map(_._2))
// Simplified creates the most concise possible representation of each cases' address sets based on the mask.
val simplified = supportCases.map { case (k, seq) => k -> AddressSet.unify(seq.map(_.widen(~mask)).distinct) }
simplified.map { case (s, a) =>
// s is a size, you are checking for this size either the size of the operation is in s
// We return an or-reduction of all the cases, checking whether any contains both the dynamic size and dynamic address on the wire.
((Some(s) == range).B || s.containsLg(lgSize)) &&
a.map(_.contains(address)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
def supportsAcquireTSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.logical, address, lgSize, range)
def supportsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.get, address, lgSize, range)
def supportsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putFull, address, lgSize, range)
def supportsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.putPartial, address, lgSize, range)
def supportsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.supports.hint, address, lgSize, range)
def supportsAcquireTFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireT, address, lgSize, range)
def supportsAcquireBFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.acquireB, address, lgSize, range)
def supportsArithmeticFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.arithmetic, address, lgSize, range)
def supportsLogicalFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.logical, address, lgSize, range)
def supportsGetFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.get, address, lgSize, range)
def supportsPutFullFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putFull, address, lgSize, range)
def supportsPutPartialFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.putPartial, address, lgSize, range)
def supportsHintFast (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(false, _.supports.hint, address, lgSize, range)
def emitsProbeSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.probe, address, lgSize, range)
def emitsArithmeticSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.arithmetic, address, lgSize, range)
def emitsLogicalSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.logical, address, lgSize, range)
def emitsGetSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.get, address, lgSize, range)
def emitsPutFullSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putFull, address, lgSize, range)
def emitsPutPartialSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.putPartial, address, lgSize, range)
def emitsHintSafe (address: UInt, lgSize: UInt, range: Option[TransferSizes] = None) = addressHelper(true, _.emits.hint, address, lgSize, range)
def findTreeViolation() = slaves.flatMap(_.findTreeViolation()).headOption
def isTree = !slaves.exists(!_.isTree)
def infoString = "Slave Port Beatbytes = " + beatBytes + "\n" + "Slave Port MinLatency = " + minLatency + "\n\n" + slaves.map(_.infoString).mkString
def v1copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = if (beatBytes != -1) TLChannelBeatBytes(beatBytes) else channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
def v2copy(
slaves: Seq[TLSlaveParameters] = slaves,
channelBytes: TLChannelBeatBytes = channelBytes,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
new TLSlavePortParameters(
slaves = slaves,
channelBytes = channelBytes,
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
managers: Seq[TLSlaveParameters] = slaves,
beatBytes: Int = -1,
endSinkId: Int = endSinkId,
minLatency: Int = minLatency,
responseFields: Seq[BundleFieldBase] = responseFields,
requestKeys: Seq[BundleKeyBase] = requestKeys) =
{
v1copy(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
object TLSlavePortParameters {
def v1(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
new TLSlavePortParameters(
slaves = managers,
channelBytes = TLChannelBeatBytes(beatBytes),
endSinkId = endSinkId,
minLatency = minLatency,
responseFields = responseFields,
requestKeys = requestKeys)
}
}
object TLManagerPortParameters {
@deprecated("Use TLSlavePortParameters.v1 instead of TLManagerPortParameters","")
def apply(
managers: Seq[TLSlaveParameters],
beatBytes: Int,
endSinkId: Int = 0,
minLatency: Int = 0,
responseFields: Seq[BundleFieldBase] = Nil,
requestKeys: Seq[BundleKeyBase] = Nil) =
{
TLSlavePortParameters.v1(
managers,
beatBytes,
endSinkId,
minLatency,
responseFields,
requestKeys)
}
}
class TLMasterParameters private(
val nodePath: Seq[BaseNode],
val resources: Seq[Resource],
val name: String,
val visibility: Seq[AddressSet],
val unusedRegionTypes: Set[RegionType.T],
val executesOnly: Boolean,
val requestFifo: Boolean, // only a request, not a requirement. applies to A, not C.
val supports: TLSlaveToMasterTransferSizes,
val emits: TLMasterToSlaveTransferSizes,
val neverReleasesData: Boolean,
val sourceId: IdRange) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterParameters]
override def productPrefix = "TLMasterParameters"
// We intentionally omit nodePath for equality testing / formatting
def productArity: Int = 10
def productElement(n: Int): Any = n match {
case 0 => name
case 1 => sourceId
case 2 => resources
case 3 => visibility
case 4 => unusedRegionTypes
case 5 => executesOnly
case 6 => requestFifo
case 7 => supports
case 8 => emits
case 9 => neverReleasesData
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!sourceId.isEmpty)
require (!visibility.isEmpty)
require (supports.putFull.contains(supports.putPartial))
// We only support these operations if we support Probe (ie: we're a cache)
require (supports.probe.contains(supports.arithmetic))
require (supports.probe.contains(supports.logical))
require (supports.probe.contains(supports.get))
require (supports.probe.contains(supports.putFull))
require (supports.probe.contains(supports.putPartial))
require (supports.probe.contains(supports.hint))
visibility.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y), s"$x and $y overlap.") }
val maxTransfer = List(
supports.probe.max,
supports.arithmetic.max,
supports.logical.max,
supports.get.max,
supports.putFull.max,
supports.putPartial.max).max
def infoString = {
s"""Master Name = ${name}
|visibility = ${visibility}
|emits = ${emits.infoString}
|sourceId = ${sourceId}
|
|""".stripMargin
}
def v1copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = this.resources,
name = name,
visibility = visibility,
unusedRegionTypes = this.unusedRegionTypes,
executesOnly = this.executesOnly,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = this.emits,
neverReleasesData = this.neverReleasesData,
sourceId = sourceId)
}
def v2copy(
nodePath: Seq[BaseNode] = nodePath,
resources: Seq[Resource] = resources,
name: String = name,
visibility: Seq[AddressSet] = visibility,
unusedRegionTypes: Set[RegionType.T] = unusedRegionTypes,
executesOnly: Boolean = executesOnly,
requestFifo: Boolean = requestFifo,
supports: TLSlaveToMasterTransferSizes = supports,
emits: TLMasterToSlaveTransferSizes = emits,
neverReleasesData: Boolean = neverReleasesData,
sourceId: IdRange = sourceId) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
@deprecated("Use v1copy instead of copy","")
def copy(
name: String = name,
sourceId: IdRange = sourceId,
nodePath: Seq[BaseNode] = nodePath,
requestFifo: Boolean = requestFifo,
visibility: Seq[AddressSet] = visibility,
supportsProbe: TransferSizes = supports.probe,
supportsArithmetic: TransferSizes = supports.arithmetic,
supportsLogical: TransferSizes = supports.logical,
supportsGet: TransferSizes = supports.get,
supportsPutFull: TransferSizes = supports.putFull,
supportsPutPartial: TransferSizes = supports.putPartial,
supportsHint: TransferSizes = supports.hint) =
{
v1copy(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
object TLMasterParameters {
def v1(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = Nil,
name = name,
visibility = visibility,
unusedRegionTypes = Set(),
executesOnly = false,
requestFifo = requestFifo,
supports = TLSlaveToMasterTransferSizes(
probe = supportsProbe,
arithmetic = supportsArithmetic,
logical = supportsLogical,
get = supportsGet,
putFull = supportsPutFull,
putPartial = supportsPutPartial,
hint = supportsHint),
emits = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData = false,
sourceId = sourceId)
}
def v2(
nodePath: Seq[BaseNode] = Seq(),
resources: Seq[Resource] = Nil,
name: String,
visibility: Seq[AddressSet] = Seq(AddressSet(0, ~0)),
unusedRegionTypes: Set[RegionType.T] = Set(),
executesOnly: Boolean = false,
requestFifo: Boolean = false,
supports: TLSlaveToMasterTransferSizes = TLSlaveToMasterTransferSizes.unknownSupports,
emits: TLMasterToSlaveTransferSizes = TLMasterToSlaveTransferSizes.unknownEmits,
neverReleasesData: Boolean = false,
sourceId: IdRange = IdRange(0,1)) =
{
new TLMasterParameters(
nodePath = nodePath,
resources = resources,
name = name,
visibility = visibility,
unusedRegionTypes = unusedRegionTypes,
executesOnly = executesOnly,
requestFifo = requestFifo,
supports = supports,
emits = emits,
neverReleasesData = neverReleasesData,
sourceId = sourceId)
}
}
object TLClientParameters {
@deprecated("Use TLMasterParameters.v1 instead of TLClientParameters","")
def apply(
name: String,
sourceId: IdRange = IdRange(0,1),
nodePath: Seq[BaseNode] = Seq(),
requestFifo: Boolean = false,
visibility: Seq[AddressSet] = Seq(AddressSet.everything),
supportsProbe: TransferSizes = TransferSizes.none,
supportsArithmetic: TransferSizes = TransferSizes.none,
supportsLogical: TransferSizes = TransferSizes.none,
supportsGet: TransferSizes = TransferSizes.none,
supportsPutFull: TransferSizes = TransferSizes.none,
supportsPutPartial: TransferSizes = TransferSizes.none,
supportsHint: TransferSizes = TransferSizes.none) =
{
TLMasterParameters.v1(
name = name,
sourceId = sourceId,
nodePath = nodePath,
requestFifo = requestFifo,
visibility = visibility,
supportsProbe = supportsProbe,
supportsArithmetic = supportsArithmetic,
supportsLogical = supportsLogical,
supportsGet = supportsGet,
supportsPutFull = supportsPutFull,
supportsPutPartial = supportsPutPartial,
supportsHint = supportsHint)
}
}
class TLMasterPortParameters private(
val masters: Seq[TLMasterParameters],
val channelBytes: TLChannelBeatBytes,
val minLatency: Int,
val echoFields: Seq[BundleFieldBase],
val requestFields: Seq[BundleFieldBase],
val responseKeys: Seq[BundleKeyBase]) extends SimpleProduct
{
override def canEqual(that: Any): Boolean = that.isInstanceOf[TLMasterPortParameters]
override def productPrefix = "TLMasterPortParameters"
def productArity: Int = 6
def productElement(n: Int): Any = n match {
case 0 => masters
case 1 => channelBytes
case 2 => minLatency
case 3 => echoFields
case 4 => requestFields
case 5 => responseKeys
case _ => throw new IndexOutOfBoundsException(n.toString)
}
require (!masters.isEmpty)
require (minLatency >= 0)
def clients = masters
// Require disjoint ranges for Ids
IdRange.overlaps(masters.map(_.sourceId)).foreach { case (x, y) =>
require (!x.overlaps(y), s"TLClientParameters.sourceId ${x} overlaps ${y}")
}
// Bounds on required sizes
def endSourceId = masters.map(_.sourceId.end).max
def maxTransfer = masters.map(_.maxTransfer).max
// The unused sources < endSourceId
def unusedSources: Seq[Int] = {
val usedSources = masters.map(_.sourceId).sortBy(_.start)
((Seq(0) ++ usedSources.map(_.end)) zip usedSources.map(_.start)) flatMap { case (end, start) =>
end until start
}
}
// Diplomatically determined operation sizes emitted by all inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val allEmitClaims = masters.map(_.emits).reduce( _ intersect _)
// Diplomatically determined operation sizes Emitted by at least one inward Masters
// as opposed to emits* which generate circuitry to check which specific addresses
val anyEmitClaims = masters.map(_.emits).reduce(_ mincover _)
// Diplomatically determined operation sizes supported by all inward Masters
// as opposed to supports* which generate circuitry to check which specific addresses
val allSupportProbe = masters.map(_.supports.probe) .reduce(_ intersect _)
val allSupportArithmetic = masters.map(_.supports.arithmetic).reduce(_ intersect _)
val allSupportLogical = masters.map(_.supports.logical) .reduce(_ intersect _)
val allSupportGet = masters.map(_.supports.get) .reduce(_ intersect _)
val allSupportPutFull = masters.map(_.supports.putFull) .reduce(_ intersect _)
val allSupportPutPartial = masters.map(_.supports.putPartial).reduce(_ intersect _)
val allSupportHint = masters.map(_.supports.hint) .reduce(_ intersect _)
// Diplomatically determined operation sizes supported by at least one master
// as opposed to supports* which generate circuitry to check which specific addresses
val anySupportProbe = masters.map(!_.supports.probe.none) .reduce(_ || _)
val anySupportArithmetic = masters.map(!_.supports.arithmetic.none).reduce(_ || _)
val anySupportLogical = masters.map(!_.supports.logical.none) .reduce(_ || _)
val anySupportGet = masters.map(!_.supports.get.none) .reduce(_ || _)
val anySupportPutFull = masters.map(!_.supports.putFull.none) .reduce(_ || _)
val anySupportPutPartial = masters.map(!_.supports.putPartial.none).reduce(_ || _)
val anySupportHint = masters.map(!_.supports.hint.none) .reduce(_ || _)
// These return Option[TLMasterParameters] for your convenience
def find(id: Int) = masters.find(_.sourceId.contains(id))
// Synthesizable lookup methods
def find(id: UInt) = VecInit(masters.map(_.sourceId.contains(id)))
def contains(id: UInt) = find(id).reduce(_ || _)
def requestFifo(id: UInt) = Mux1H(find(id), masters.map(c => c.requestFifo.B))
// Available during RTL runtime, checks to see if (id, size) is supported by the master's (client's) diplomatic parameters
private def sourceIdHelper(member: TLMasterParameters => TransferSizes)(id: UInt, lgSize: UInt) = {
val allSame = masters.map(member(_) == member(masters(0))).reduce(_ && _)
// this if statement is a coarse generalization of the groupBy in the sourceIdHelper2 version;
// the case where there is only one group.
if (allSame) member(masters(0)).containsLg(lgSize) else {
// Find the master associated with ID and returns whether that particular master is able to receive transaction of lgSize
Mux1H(find(id), masters.map(member(_).containsLg(lgSize)))
}
}
// Check for support of a given operation at a specific id
val supportsProbe = sourceIdHelper(_.supports.probe) _
val supportsArithmetic = sourceIdHelper(_.supports.arithmetic) _
val supportsLogical = sourceIdHelper(_.supports.logical) _
val supportsGet = sourceIdHelper(_.supports.get) _
val supportsPutFull = sourceIdHelper(_.supports.putFull) _
val supportsPutPartial = sourceIdHelper(_.supports.putPartial) _
val supportsHint = sourceIdHelper(_.supports.hint) _
// TODO: Merge sourceIdHelper2 with sourceIdHelper
private def sourceIdHelper2(
member: TLMasterParameters => TransferSizes,
sourceId: UInt,
lgSize: UInt): Bool = {
// Because sourceIds are uniquely owned by each master, we use them to group the
// cases that have to be checked.
val emitCases = groupByIntoSeq(masters)(m => member(m)).map { case (k, vs) =>
k -> vs.map(_.sourceId)
}
emitCases.map { case (s, a) =>
(s.containsLg(lgSize)) &&
a.map(_.contains(sourceId)).reduce(_||_)
}.foldLeft(false.B)(_||_)
}
// Check for emit of a given operation at a specific id
def emitsAcquireT (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireT, sourceId, lgSize)
def emitsAcquireB (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.acquireB, sourceId, lgSize)
def emitsArithmetic(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.arithmetic, sourceId, lgSize)
def emitsLogical (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.logical, sourceId, lgSize)
def emitsGet (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.get, sourceId, lgSize)
def emitsPutFull (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putFull, sourceId, lgSize)
def emitsPutPartial(sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.putPartial, sourceId, lgSize)
def emitsHint (sourceId: UInt, lgSize: UInt) = sourceIdHelper2(_.emits.hint, sourceId, lgSize)
def infoString = masters.map(_.infoString).mkString
def v1copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2copy(
masters: Seq[TLMasterParameters] = masters,
channelBytes: TLChannelBeatBytes = channelBytes,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
@deprecated("Use v1copy instead of copy","")
def copy(
clients: Seq[TLMasterParameters] = masters,
minLatency: Int = minLatency,
echoFields: Seq[BundleFieldBase] = echoFields,
requestFields: Seq[BundleFieldBase] = requestFields,
responseKeys: Seq[BundleKeyBase] = responseKeys) =
{
v1copy(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLClientPortParameters {
@deprecated("Use TLMasterPortParameters.v1 instead of TLClientPortParameters","")
def apply(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
TLMasterPortParameters.v1(
clients,
minLatency,
echoFields,
requestFields,
responseKeys)
}
}
object TLMasterPortParameters {
def v1(
clients: Seq[TLMasterParameters],
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = clients,
channelBytes = TLChannelBeatBytes(),
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
def v2(
masters: Seq[TLMasterParameters],
channelBytes: TLChannelBeatBytes = TLChannelBeatBytes(),
minLatency: Int = 0,
echoFields: Seq[BundleFieldBase] = Nil,
requestFields: Seq[BundleFieldBase] = Nil,
responseKeys: Seq[BundleKeyBase] = Nil) =
{
new TLMasterPortParameters(
masters = masters,
channelBytes = channelBytes,
minLatency = minLatency,
echoFields = echoFields,
requestFields = requestFields,
responseKeys = responseKeys)
}
}
case class TLBundleParameters(
addressBits: Int,
dataBits: Int,
sourceBits: Int,
sinkBits: Int,
sizeBits: Int,
echoFields: Seq[BundleFieldBase],
requestFields: Seq[BundleFieldBase],
responseFields: Seq[BundleFieldBase],
hasBCE: Boolean)
{
// Chisel has issues with 0-width wires
require (addressBits >= 1)
require (dataBits >= 8)
require (sourceBits >= 1)
require (sinkBits >= 1)
require (sizeBits >= 1)
require (isPow2(dataBits))
echoFields.foreach { f => require (f.key.isControl, s"${f} is not a legal echo field") }
val addrLoBits = log2Up(dataBits/8)
// Used to uniquify bus IP names
def shortName = s"a${addressBits}d${dataBits}s${sourceBits}k${sinkBits}z${sizeBits}" + (if (hasBCE) "c" else "u")
def union(x: TLBundleParameters) =
TLBundleParameters(
max(addressBits, x.addressBits),
max(dataBits, x.dataBits),
max(sourceBits, x.sourceBits),
max(sinkBits, x.sinkBits),
max(sizeBits, x.sizeBits),
echoFields = BundleField.union(echoFields ++ x.echoFields),
requestFields = BundleField.union(requestFields ++ x.requestFields),
responseFields = BundleField.union(responseFields ++ x.responseFields),
hasBCE || x.hasBCE)
}
object TLBundleParameters
{
val emptyBundleParams = TLBundleParameters(
addressBits = 1,
dataBits = 8,
sourceBits = 1,
sinkBits = 1,
sizeBits = 1,
echoFields = Nil,
requestFields = Nil,
responseFields = Nil,
hasBCE = false)
def union(x: Seq[TLBundleParameters]) = x.foldLeft(emptyBundleParams)((x,y) => x.union(y))
def apply(master: TLMasterPortParameters, slave: TLSlavePortParameters) =
new TLBundleParameters(
addressBits = log2Up(slave.maxAddress + 1),
dataBits = slave.beatBytes * 8,
sourceBits = log2Up(master.endSourceId),
sinkBits = log2Up(slave.endSinkId),
sizeBits = log2Up(log2Ceil(max(master.maxTransfer, slave.maxTransfer))+1),
echoFields = master.echoFields,
requestFields = BundleField.accept(master.requestFields, slave.requestKeys),
responseFields = BundleField.accept(slave.responseFields, master.responseKeys),
hasBCE = master.anySupportProbe && slave.anySupportAcquireB)
}
case class TLEdgeParameters(
master: TLMasterPortParameters,
slave: TLSlavePortParameters,
params: Parameters,
sourceInfo: SourceInfo) extends FormatEdge
{
// legacy names:
def manager = slave
def client = master
val maxTransfer = max(master.maxTransfer, slave.maxTransfer)
val maxLgSize = log2Ceil(maxTransfer)
// Sanity check the link...
require (maxTransfer >= slave.beatBytes, s"Link's max transfer (${maxTransfer}) < ${slave.slaves.map(_.name)}'s beatBytes (${slave.beatBytes})")
def diplomaticClaimsMasterToSlave = master.anyEmitClaims.intersect(slave.anySupportClaims)
val bundle = TLBundleParameters(master, slave)
def formatEdge = master.infoString + "\n" + slave.infoString
}
case class TLCreditedDelay(
a: CreditedDelay,
b: CreditedDelay,
c: CreditedDelay,
d: CreditedDelay,
e: CreditedDelay)
{
def + (that: TLCreditedDelay): TLCreditedDelay = TLCreditedDelay(
a = a + that.a,
b = b + that.b,
c = c + that.c,
d = d + that.d,
e = e + that.e)
override def toString = s"(${a}, ${b}, ${c}, ${d}, ${e})"
}
object TLCreditedDelay {
def apply(delay: CreditedDelay): TLCreditedDelay = apply(delay, delay.flip, delay, delay.flip, delay)
}
case class TLCreditedManagerPortParameters(delay: TLCreditedDelay, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLCreditedClientPortParameters(delay: TLCreditedDelay, base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLCreditedEdgeParameters(client: TLCreditedClientPortParameters, manager: TLCreditedManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val delay = client.delay + manager.delay
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLAsyncManagerPortParameters(async: AsyncQueueParams, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLAsyncClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLAsyncBundleParameters(async: AsyncQueueParams, base: TLBundleParameters)
case class TLAsyncEdgeParameters(client: TLAsyncClientPortParameters, manager: TLAsyncManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLAsyncBundleParameters(manager.async, TLBundleParameters(client.base, manager.base))
def formatEdge = client.infoString + "\n" + manager.infoString
}
case class TLRationalManagerPortParameters(direction: RationalDirection, base: TLSlavePortParameters) {def infoString = base.infoString}
case class TLRationalClientPortParameters(base: TLMasterPortParameters) {def infoString = base.infoString}
case class TLRationalEdgeParameters(client: TLRationalClientPortParameters, manager: TLRationalManagerPortParameters, params: Parameters, sourceInfo: SourceInfo) extends FormatEdge
{
val bundle = TLBundleParameters(client.base, manager.base)
def formatEdge = client.infoString + "\n" + manager.infoString
}
// To be unified, devices must agree on all of these terms
case class ManagerUnificationKey(
resources: Seq[Resource],
regionType: RegionType.T,
executable: Boolean,
supportsAcquireT: TransferSizes,
supportsAcquireB: TransferSizes,
supportsArithmetic: TransferSizes,
supportsLogical: TransferSizes,
supportsGet: TransferSizes,
supportsPutFull: TransferSizes,
supportsPutPartial: TransferSizes,
supportsHint: TransferSizes)
object ManagerUnificationKey
{
def apply(x: TLSlaveParameters): ManagerUnificationKey = ManagerUnificationKey(
resources = x.resources,
regionType = x.regionType,
executable = x.executable,
supportsAcquireT = x.supportsAcquireT,
supportsAcquireB = x.supportsAcquireB,
supportsArithmetic = x.supportsArithmetic,
supportsLogical = x.supportsLogical,
supportsGet = x.supportsGet,
supportsPutFull = x.supportsPutFull,
supportsPutPartial = x.supportsPutPartial,
supportsHint = x.supportsHint)
}
object ManagerUnification
{
def apply(slaves: Seq[TLSlaveParameters]): List[TLSlaveParameters] = {
slaves.groupBy(ManagerUnificationKey.apply).values.map { seq =>
val agree = seq.forall(_.fifoId == seq.head.fifoId)
seq(0).v1copy(
address = AddressSet.unify(seq.flatMap(_.address)),
fifoId = if (agree) seq(0).fifoId else None)
}.toList
}
}
case class TLBufferParams(
a: BufferParams = BufferParams.none,
b: BufferParams = BufferParams.none,
c: BufferParams = BufferParams.none,
d: BufferParams = BufferParams.none,
e: BufferParams = BufferParams.none
) extends DirectedBuffers[TLBufferParams] {
def copyIn(x: BufferParams) = this.copy(b = x, d = x)
def copyOut(x: BufferParams) = this.copy(a = x, c = x, e = x)
def copyInOut(x: BufferParams) = this.copyIn(x).copyOut(x)
}
/** Pretty printing of TL source id maps */
class TLSourceIdMap(tl: TLMasterPortParameters) extends IdMap[TLSourceIdMapEntry] {
private val tlDigits = String.valueOf(tl.endSourceId-1).length()
protected val fmt = s"\t[%${tlDigits}d, %${tlDigits}d) %s%s%s"
private val sorted = tl.masters.sortBy(_.sourceId)
val mapping: Seq[TLSourceIdMapEntry] = sorted.map { case c =>
TLSourceIdMapEntry(c.sourceId, c.name, c.supports.probe, c.requestFifo)
}
}
case class TLSourceIdMapEntry(tlId: IdRange, name: String, isCache: Boolean, requestFifo: Boolean)
extends IdMapEntry
{
val from = tlId
val to = tlId
val maxTransactionsInFlight = Some(tlId.size)
}
File Edges.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.tilelink
import chisel3._
import chisel3.util._
import chisel3.experimental.SourceInfo
import org.chipsalliance.cde.config.Parameters
import freechips.rocketchip.util._
class TLEdge(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdgeParameters(client, manager, params, sourceInfo)
{
def isAligned(address: UInt, lgSize: UInt): Bool = {
if (maxLgSize == 0) true.B else {
val mask = UIntToOH1(lgSize, maxLgSize)
(address & mask) === 0.U
}
}
def mask(address: UInt, lgSize: UInt): UInt =
MaskGen(address, lgSize, manager.beatBytes)
def staticHasData(bundle: TLChannel): Option[Boolean] = {
bundle match {
case _:TLBundleA => {
// Do there exist A messages with Data?
val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
// Do there exist A messages without Data?
val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
// Statically optimize the case where hasData is a constant
if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
}
case _:TLBundleB => {
// Do there exist B messages with Data?
val bDataYes = client.anySupportArithmetic || client.anySupportLogical || client.anySupportPutFull || client.anySupportPutPartial
// Do there exist B messages without Data?
val bDataNo = client.anySupportProbe || client.anySupportGet || client.anySupportHint
// Statically optimize the case where hasData is a constant
if (!bDataYes) Some(false) else if (!bDataNo) Some(true) else None
}
case _:TLBundleC => {
// Do there eixst C messages with Data?
val cDataYes = client.anySupportGet || client.anySupportArithmetic || client.anySupportLogical || client.anySupportProbe
// Do there exist C messages without Data?
val cDataNo = client.anySupportPutFull || client.anySupportPutPartial || client.anySupportHint || client.anySupportProbe
if (!cDataYes) Some(false) else if (!cDataNo) Some(true) else None
}
case _:TLBundleD => {
// Do there eixst D messages with Data?
val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
// Do there exist D messages without Data?
val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
}
case _:TLBundleE => Some(false)
}
}
def isRequest(x: TLChannel): Bool = {
x match {
case a: TLBundleA => true.B
case b: TLBundleB => true.B
case c: TLBundleC => c.opcode(2) && c.opcode(1)
// opcode === TLMessages.Release ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(2) && !d.opcode(1)
// opcode === TLMessages.Grant ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
}
def isResponse(x: TLChannel): Bool = {
x match {
case a: TLBundleA => false.B
case b: TLBundleB => false.B
case c: TLBundleC => !c.opcode(2) || !c.opcode(1)
// opcode =/= TLMessages.Release &&
// opcode =/= TLMessages.ReleaseData
case d: TLBundleD => true.B // Grant isResponse + isRequest
case e: TLBundleE => true.B
}
}
def hasData(x: TLChannel): Bool = {
val opdata = x match {
case a: TLBundleA => !a.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case b: TLBundleB => !b.opcode(2)
// opcode === TLMessages.PutFullData ||
// opcode === TLMessages.PutPartialData ||
// opcode === TLMessages.ArithmeticData ||
// opcode === TLMessages.LogicalData
case c: TLBundleC => c.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.ProbeAckData ||
// opcode === TLMessages.ReleaseData
case d: TLBundleD => d.opcode(0)
// opcode === TLMessages.AccessAckData ||
// opcode === TLMessages.GrantData
case e: TLBundleE => false.B
}
staticHasData(x).map(_.B).getOrElse(opdata)
}
def opcode(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.opcode
case b: TLBundleB => b.opcode
case c: TLBundleC => c.opcode
case d: TLBundleD => d.opcode
}
}
def param(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.param
case b: TLBundleB => b.param
case c: TLBundleC => c.param
case d: TLBundleD => d.param
}
}
def size(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.size
case b: TLBundleB => b.size
case c: TLBundleC => c.size
case d: TLBundleD => d.size
}
}
def data(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.data
case b: TLBundleB => b.data
case c: TLBundleC => c.data
case d: TLBundleD => d.data
}
}
def corrupt(x: TLDataChannel): Bool = {
x match {
case a: TLBundleA => a.corrupt
case b: TLBundleB => b.corrupt
case c: TLBundleC => c.corrupt
case d: TLBundleD => d.corrupt
}
}
def mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.mask
case b: TLBundleB => b.mask
case c: TLBundleC => mask(c.address, c.size)
}
}
def full_mask(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => mask(a.address, a.size)
case b: TLBundleB => mask(b.address, b.size)
case c: TLBundleC => mask(c.address, c.size)
}
}
def address(x: TLAddrChannel): UInt = {
x match {
case a: TLBundleA => a.address
case b: TLBundleB => b.address
case c: TLBundleC => c.address
}
}
def source(x: TLDataChannel): UInt = {
x match {
case a: TLBundleA => a.source
case b: TLBundleB => b.source
case c: TLBundleC => c.source
case d: TLBundleD => d.source
}
}
def addr_hi(x: UInt): UInt = x >> log2Ceil(manager.beatBytes)
def addr_lo(x: UInt): UInt =
if (manager.beatBytes == 1) 0.U else x(log2Ceil(manager.beatBytes)-1, 0)
def addr_hi(x: TLAddrChannel): UInt = addr_hi(address(x))
def addr_lo(x: TLAddrChannel): UInt = addr_lo(address(x))
def numBeats(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 1.U
case bundle: TLDataChannel => {
val hasData = this.hasData(bundle)
val size = this.size(bundle)
val cutoff = log2Ceil(manager.beatBytes)
val small = if (manager.maxTransfer <= manager.beatBytes) true.B else size <= (cutoff).U
val decode = UIntToOH(size, maxLgSize+1) >> cutoff
Mux(hasData, decode | small.asUInt, 1.U)
}
}
}
def numBeats1(x: TLChannel): UInt = {
x match {
case _: TLBundleE => 0.U
case bundle: TLDataChannel => {
if (maxLgSize == 0) {
0.U
} else {
val decode = UIntToOH1(size(bundle), maxLgSize) >> log2Ceil(manager.beatBytes)
Mux(hasData(bundle), decode, 0.U)
}
}
}
}
def firstlastHelper(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val beats1 = numBeats1(bits)
val counter = RegInit(0.U(log2Up(maxTransfer / manager.beatBytes).W))
val counter1 = counter - 1.U
val first = counter === 0.U
val last = counter === 1.U || beats1 === 0.U
val done = last && fire
val count = (beats1 & ~counter1)
when (fire) {
counter := Mux(first, beats1, counter1)
}
(first, last, done, count)
}
def first(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._1
def first(x: DecoupledIO[TLChannel]): Bool = first(x.bits, x.fire)
def first(x: ValidIO[TLChannel]): Bool = first(x.bits, x.valid)
def last(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._2
def last(x: DecoupledIO[TLChannel]): Bool = last(x.bits, x.fire)
def last(x: ValidIO[TLChannel]): Bool = last(x.bits, x.valid)
def done(bits: TLChannel, fire: Bool): Bool = firstlastHelper(bits, fire)._3
def done(x: DecoupledIO[TLChannel]): Bool = done(x.bits, x.fire)
def done(x: ValidIO[TLChannel]): Bool = done(x.bits, x.valid)
def firstlast(bits: TLChannel, fire: Bool): (Bool, Bool, Bool) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3)
}
def firstlast(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.fire)
def firstlast(x: ValidIO[TLChannel]): (Bool, Bool, Bool) = firstlast(x.bits, x.valid)
def count(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4)
}
def count(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.fire)
def count(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = count(x.bits, x.valid)
def addr_inc(bits: TLChannel, fire: Bool): (Bool, Bool, Bool, UInt) = {
val r = firstlastHelper(bits, fire)
(r._1, r._2, r._3, r._4 << log2Ceil(manager.beatBytes))
}
def addr_inc(x: DecoupledIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.fire)
def addr_inc(x: ValidIO[TLChannel]): (Bool, Bool, Bool, UInt) = addr_inc(x.bits, x.valid)
// Does the request need T permissions to be executed?
def needT(a: TLBundleA): Bool = {
val acq_needT = MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLPermissions.NtoB -> false.B,
TLPermissions.NtoT -> true.B,
TLPermissions.BtoT -> true.B))
MuxLookup(a.opcode, WireDefault(Bool(), DontCare))(Array(
TLMessages.PutFullData -> true.B,
TLMessages.PutPartialData -> true.B,
TLMessages.ArithmeticData -> true.B,
TLMessages.LogicalData -> true.B,
TLMessages.Get -> false.B,
TLMessages.Hint -> MuxLookup(a.param, WireDefault(Bool(), DontCare))(Array(
TLHints.PREFETCH_READ -> false.B,
TLHints.PREFETCH_WRITE -> true.B)),
TLMessages.AcquireBlock -> acq_needT,
TLMessages.AcquirePerm -> acq_needT))
}
// This is a very expensive circuit; use only if you really mean it!
def inFlight(x: TLBundle): (UInt, UInt) = {
val flight = RegInit(0.U(log2Ceil(3*client.endSourceId+1).W))
val bce = manager.anySupportAcquireB && client.anySupportProbe
val (a_first, a_last, _) = firstlast(x.a)
val (b_first, b_last, _) = firstlast(x.b)
val (c_first, c_last, _) = firstlast(x.c)
val (d_first, d_last, _) = firstlast(x.d)
val (e_first, e_last, _) = firstlast(x.e)
val (a_request, a_response) = (isRequest(x.a.bits), isResponse(x.a.bits))
val (b_request, b_response) = (isRequest(x.b.bits), isResponse(x.b.bits))
val (c_request, c_response) = (isRequest(x.c.bits), isResponse(x.c.bits))
val (d_request, d_response) = (isRequest(x.d.bits), isResponse(x.d.bits))
val (e_request, e_response) = (isRequest(x.e.bits), isResponse(x.e.bits))
val a_inc = x.a.fire && a_first && a_request
val b_inc = x.b.fire && b_first && b_request
val c_inc = x.c.fire && c_first && c_request
val d_inc = x.d.fire && d_first && d_request
val e_inc = x.e.fire && e_first && e_request
val inc = Cat(Seq(a_inc, d_inc) ++ (if (bce) Seq(b_inc, c_inc, e_inc) else Nil))
val a_dec = x.a.fire && a_last && a_response
val b_dec = x.b.fire && b_last && b_response
val c_dec = x.c.fire && c_last && c_response
val d_dec = x.d.fire && d_last && d_response
val e_dec = x.e.fire && e_last && e_response
val dec = Cat(Seq(a_dec, d_dec) ++ (if (bce) Seq(b_dec, c_dec, e_dec) else Nil))
val next_flight = flight + PopCount(inc) - PopCount(dec)
flight := next_flight
(flight, next_flight)
}
def prettySourceMapping(context: String): String = {
s"TL-Source mapping for $context:\n${(new TLSourceIdMap(client)).pretty}\n"
}
}
class TLEdgeOut(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
// Transfers
def AcquireBlock(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquireBlock
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AcquirePerm(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.AcquirePerm
a.param := growPermissions
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.Release
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleC) = {
require (manager.anySupportAcquireB, s"TileLink: No managers visible from this edge support Acquires, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsAcquireBFast(toAddress, lgSize)
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ReleaseData
c.param := shrinkPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
(legal, c)
}
def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt): (Bool, TLBundleC) =
Release(fromSource, toAddress, lgSize, shrinkPermissions, data, false.B)
def ProbeAck(b: TLBundleB, reportPermissions: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAck
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def ProbeAck(b: TLBundleB, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(b.source, b.address, b.size, reportPermissions, data)
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt, corrupt: Bool): TLBundleC = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.ProbeAckData
c.param := reportPermissions
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def ProbeAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, reportPermissions: UInt, data: UInt): TLBundleC =
ProbeAck(fromSource, toAddress, lgSize, reportPermissions, data, false.B)
def GrantAck(d: TLBundleD): TLBundleE = GrantAck(d.sink)
def GrantAck(toSink: UInt): TLBundleE = {
val e = Wire(new TLBundleE(bundle))
e.sink := toSink
e
}
// Accesses
def Get(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
require (manager.anySupportGet, s"TileLink: No managers visible from this edge support Gets, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsGetFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Get
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutFull, s"TileLink: No managers visible from this edge support Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutFullFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutFullData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleA) =
Put(fromSource, toAddress, lgSize, data, mask, false.B)
def Put(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleA) = {
require (manager.anySupportPutPartial, s"TileLink: No managers visible from this edge support masked Puts, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsPutPartialFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.PutPartialData
a.param := 0.U
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Arithmetic(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B): (Bool, TLBundleA) = {
require (manager.anySupportArithmetic, s"TileLink: No managers visible from this edge support arithmetic AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsArithmeticFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.ArithmeticData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Logical(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (manager.anySupportLogical, s"TileLink: No managers visible from this edge support logical AMOs, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsLogicalFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.LogicalData
a.param := atomic
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := data
a.corrupt := corrupt
(legal, a)
}
def Hint(fromSource: UInt, toAddress: UInt, lgSize: UInt, param: UInt) = {
require (manager.anySupportHint, s"TileLink: No managers visible from this edge support Hints, but one of these clients would try to request one: ${client.clients}")
val legal = manager.supportsHintFast(toAddress, lgSize)
val a = Wire(new TLBundleA(bundle))
a.opcode := TLMessages.Hint
a.param := param
a.size := lgSize
a.source := fromSource
a.address := toAddress
a.user := DontCare
a.echo := DontCare
a.mask := mask(toAddress, lgSize)
a.data := DontCare
a.corrupt := false.B
(legal, a)
}
def AccessAck(b: TLBundleB): TLBundleC = AccessAck(b.source, address(b), b.size)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
def AccessAck(b: TLBundleB, data: UInt): TLBundleC = AccessAck(b.source, address(b), b.size, data)
def AccessAck(b: TLBundleB, data: UInt, corrupt: Bool): TLBundleC = AccessAck(b.source, address(b), b.size, data, corrupt)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt): TLBundleC = AccessAck(fromSource, toAddress, lgSize, data, false.B)
def AccessAck(fromSource: UInt, toAddress: UInt, lgSize: UInt, data: UInt, corrupt: Bool) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.AccessAckData
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := data
c.corrupt := corrupt
c
}
def HintAck(b: TLBundleB): TLBundleC = HintAck(b.source, address(b), b.size)
def HintAck(fromSource: UInt, toAddress: UInt, lgSize: UInt) = {
val c = Wire(new TLBundleC(bundle))
c.opcode := TLMessages.HintAck
c.param := 0.U
c.size := lgSize
c.source := fromSource
c.address := toAddress
c.user := DontCare
c.echo := DontCare
c.data := DontCare
c.corrupt := false.B
c
}
}
class TLEdgeIn(
client: TLClientPortParameters,
manager: TLManagerPortParameters,
params: Parameters,
sourceInfo: SourceInfo)
extends TLEdge(client, manager, params, sourceInfo)
{
private def myTranspose[T](x: Seq[Seq[T]]): Seq[Seq[T]] = {
val todo = x.filter(!_.isEmpty)
val heads = todo.map(_.head)
val tails = todo.map(_.tail)
if (todo.isEmpty) Nil else { heads +: myTranspose(tails) }
}
// Transfers
def Probe(fromAddress: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt) = {
require (client.anySupportProbe, s"TileLink: No clients visible from this edge support probes, but one of these managers tried to issue one: ${manager.managers}")
val legal = client.supportsProbe(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Probe
b.param := capPermissions
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.Grant
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt): TLBundleD = Grant(fromSink, toSource, lgSize, capPermissions, data, false.B, false.B)
def Grant(fromSink: UInt, toSource: UInt, lgSize: UInt, capPermissions: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.GrantData
d.param := capPermissions
d.size := lgSize
d.source := toSource
d.sink := fromSink
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def ReleaseAck(c: TLBundleC): TLBundleD = ReleaseAck(c.source, c.size, false.B)
def ReleaseAck(toSource: UInt, lgSize: UInt, denied: Bool): TLBundleD = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.ReleaseAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
// Accesses
def Get(fromAddress: UInt, toSource: UInt, lgSize: UInt) = {
require (client.anySupportGet, s"TileLink: No clients visible from this edge support Gets, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsGet(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Get
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutFull, s"TileLink: No clients visible from this edge support Puts, but one of these managers would try to issue one: ${manager.managers}")
val legal = client.supportsPutFull(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutFullData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt): (Bool, TLBundleB) =
Put(fromAddress, toSource, lgSize, data, mask, false.B)
def Put(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, mask: UInt, corrupt: Bool): (Bool, TLBundleB) = {
require (client.anySupportPutPartial, s"TileLink: No clients visible from this edge support masked Puts, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsPutPartial(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.PutPartialData
b.param := 0.U
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Arithmetic(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportArithmetic, s"TileLink: No clients visible from this edge support arithmetic AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsArithmetic(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.ArithmeticData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Logical(fromAddress: UInt, toSource: UInt, lgSize: UInt, data: UInt, atomic: UInt, corrupt: Bool = false.B) = {
require (client.anySupportLogical, s"TileLink: No clients visible from this edge support logical AMOs, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsLogical(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.LogicalData
b.param := atomic
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := data
b.corrupt := corrupt
(legal, b)
}
def Hint(fromAddress: UInt, toSource: UInt, lgSize: UInt, param: UInt) = {
require (client.anySupportHint, s"TileLink: No clients visible from this edge support Hints, but one of these managers would try to request one: ${manager.managers}")
val legal = client.supportsHint(toSource, lgSize)
val b = Wire(new TLBundleB(bundle))
b.opcode := TLMessages.Hint
b.param := param
b.size := lgSize
b.source := toSource
b.address := fromAddress
b.mask := mask(fromAddress, lgSize)
b.data := DontCare
b.corrupt := false.B
(legal, b)
}
def AccessAck(a: TLBundleA): TLBundleD = AccessAck(a.source, a.size)
def AccessAck(a: TLBundleA, denied: Bool): TLBundleD = AccessAck(a.source, a.size, denied)
def AccessAck(toSource: UInt, lgSize: UInt): TLBundleD = AccessAck(toSource, lgSize, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
def AccessAck(a: TLBundleA, data: UInt): TLBundleD = AccessAck(a.source, a.size, data)
def AccessAck(a: TLBundleA, data: UInt, denied: Bool, corrupt: Bool): TLBundleD = AccessAck(a.source, a.size, data, denied, corrupt)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt): TLBundleD = AccessAck(toSource, lgSize, data, false.B, false.B)
def AccessAck(toSource: UInt, lgSize: UInt, data: UInt, denied: Bool, corrupt: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.AccessAckData
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := data
d.corrupt := corrupt
d
}
def HintAck(a: TLBundleA): TLBundleD = HintAck(a, false.B)
def HintAck(a: TLBundleA, denied: Bool): TLBundleD = HintAck(a.source, a.size, denied)
def HintAck(toSource: UInt, lgSize: UInt): TLBundleD = HintAck(toSource, lgSize, false.B)
def HintAck(toSource: UInt, lgSize: UInt, denied: Bool) = {
val d = Wire(new TLBundleD(bundle))
d.opcode := TLMessages.HintAck
d.param := 0.U
d.size := lgSize
d.source := toSource
d.sink := 0.U
d.denied := denied
d.user := DontCare
d.echo := DontCare
d.data := DontCare
d.corrupt := false.B
d
}
}
|
module TLMonitor_89( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:48]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34]
wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34]
wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40]
wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51]
wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57]
wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57]
wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57]
wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57]
wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51]
wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52]
wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79]
wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77]
wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54]
wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35]
wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35]
wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34]
wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34]
wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117]
wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48]
wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119]
wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [4:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [4:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [4:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [4:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _T_1257 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1257; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1257; // @[Decoupled.scala:51:35]
wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg [4:0] source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
wire _T_1330 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1330; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1330; // @[Decoupled.scala:51:35]
wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg [4:0] source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [31:0] inflight; // @[Monitor.scala:614:27]
reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [255:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [31:0] a_set; // @[Monitor.scala:626:34]
wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [255:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [7:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65]
wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65]
wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99]
wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67]
wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99]
wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}]
wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35]
wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35]
wire [31:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1183 = _T_1257 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1183 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1183 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1183 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1183 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77]
wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1183 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [31:0] d_clr; // @[Monitor.scala:664:34]
wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46]
wire _T_1229 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35]
wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35]
wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1229 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35]
wire _T_1198 = _T_1330 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1198 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1198 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1198 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [31:0] inflight_1; // @[Monitor.scala:726:35]
wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46]
wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [7:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}]
wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [31:0] d_clr_1; // @[Monitor.scala:774:34]
wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1301 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1301 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire _T_1283 = _T_1330 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1283 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35]
wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1283 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1283 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113]
wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File ShiftReg.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
// Similar to the Chisel ShiftRegister but allows the user to suggest a
// name to the registers that get instantiated, and
// to provide a reset value.
object ShiftRegInit {
def apply[T <: Data](in: T, n: Int, init: T, name: Option[String] = None): T =
(0 until n).foldRight(in) {
case (i, next) => {
val r = RegNext(next, init)
name.foreach { na => r.suggestName(s"${na}_${i}") }
r
}
}
}
/** These wrap behavioral
* shift registers into specific modules to allow for
* backend flows to replace or constrain
* them properly when used for CDC synchronization,
* rather than buffering.
*
* The different types vary in their reset behavior:
* AsyncResetShiftReg -- Asynchronously reset register array
* A W(width) x D(depth) sized array is constructed from D instantiations of a
* W-wide register vector. Functionally identical to AsyncResetSyncrhonizerShiftReg,
* but only used for timing applications
*/
abstract class AbstractPipelineReg(w: Int = 1) extends Module {
val io = IO(new Bundle {
val d = Input(UInt(w.W))
val q = Output(UInt(w.W))
}
)
}
object AbstractPipelineReg {
def apply [T <: Data](gen: => AbstractPipelineReg, in: T, name: Option[String] = None): T = {
val chain = Module(gen)
name.foreach{ chain.suggestName(_) }
chain.io.d := in.asUInt
chain.io.q.asTypeOf(in)
}
}
class AsyncResetShiftReg(w: Int = 1, depth: Int = 1, init: Int = 0, name: String = "pipe") extends AbstractPipelineReg(w) {
require(depth > 0, "Depth must be greater than 0.")
override def desiredName = s"AsyncResetShiftReg_w${w}_d${depth}_i${init}"
val chain = List.tabulate(depth) { i =>
Module (new AsyncResetRegVec(w, init)).suggestName(s"${name}_${i}")
}
chain.last.io.d := io.d
chain.last.io.en := true.B
(chain.init zip chain.tail).foreach { case (sink, source) =>
sink.io.d := source.io.q
sink.io.en := true.B
}
io.q := chain.head.io.q
}
object AsyncResetShiftReg {
def apply [T <: Data](in: T, depth: Int, init: Int = 0, name: Option[String] = None): T =
AbstractPipelineReg(new AsyncResetShiftReg(in.getWidth, depth, init), in, name)
def apply [T <: Data](in: T, depth: Int, name: Option[String]): T =
apply(in, depth, 0, name)
def apply [T <: Data](in: T, depth: Int, init: T, name: Option[String]): T =
apply(in, depth, init.litValue.toInt, name)
def apply [T <: Data](in: T, depth: Int, init: T): T =
apply (in, depth, init.litValue.toInt, None)
}
File AsyncQueue.scala:
// See LICENSE.SiFive for license details.
package freechips.rocketchip.util
import chisel3._
import chisel3.util._
case class AsyncQueueParams(
depth: Int = 8,
sync: Int = 3,
safe: Boolean = true,
// If safe is true, then effort is made to resynchronize the crossing indices when either side is reset.
// This makes it safe/possible to reset one side of the crossing (but not the other) when the queue is empty.
narrow: Boolean = false)
// If narrow is true then the read mux is moved to the source side of the crossing.
// This reduces the number of level shifters in the case where the clock crossing is also a voltage crossing,
// at the expense of a combinational path from the sink to the source and back to the sink.
{
require (depth > 0 && isPow2(depth))
require (sync >= 2)
val bits = log2Ceil(depth)
val wires = if (narrow) 1 else depth
}
object AsyncQueueParams {
// When there is only one entry, we don't need narrow.
def singleton(sync: Int = 3, safe: Boolean = true) = AsyncQueueParams(1, sync, safe, false)
}
class AsyncBundleSafety extends Bundle {
val ridx_valid = Input (Bool())
val widx_valid = Output(Bool())
val source_reset_n = Output(Bool())
val sink_reset_n = Input (Bool())
}
class AsyncBundle[T <: Data](private val gen: T, val params: AsyncQueueParams = AsyncQueueParams()) extends Bundle {
// Data-path synchronization
val mem = Output(Vec(params.wires, gen))
val ridx = Input (UInt((params.bits+1).W))
val widx = Output(UInt((params.bits+1).W))
val index = params.narrow.option(Input(UInt(params.bits.W)))
// Signals used to self-stabilize a safe AsyncQueue
val safe = params.safe.option(new AsyncBundleSafety)
}
object GrayCounter {
def apply(bits: Int, increment: Bool = true.B, clear: Bool = false.B, name: String = "binary"): UInt = {
val incremented = Wire(UInt(bits.W))
val binary = RegNext(next=incremented, init=0.U).suggestName(name)
incremented := Mux(clear, 0.U, binary + increment.asUInt)
incremented ^ (incremented >> 1)
}
}
class AsyncValidSync(sync: Int, desc: String) extends RawModule {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
val clock = IO(Input(Clock()))
val reset = IO(Input(AsyncReset()))
withClockAndReset(clock, reset){
io.out := AsyncResetSynchronizerShiftReg(io.in, sync, Some(desc))
}
}
class AsyncQueueSource[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSource_${gen.typeName}"
val io = IO(new Bundle {
// These come from the source domain
val enq = Flipped(Decoupled(gen))
// These cross to the sink clock domain
val async = new AsyncBundle(gen, params)
})
val bits = params.bits
val sink_ready = WireInit(true.B)
val mem = Reg(Vec(params.depth, gen)) // This does NOT need to be reset at all.
val widx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.enq.fire, !sink_ready, "widx_bin"))
val ridx = AsyncResetSynchronizerShiftReg(io.async.ridx, params.sync, Some("ridx_gray"))
val ready = sink_ready && widx =/= (ridx ^ (params.depth | params.depth >> 1).U)
val index = if (bits == 0) 0.U else io.async.widx(bits-1, 0) ^ (io.async.widx(bits, bits) << (bits-1))
when (io.enq.fire) { mem(index) := io.enq.bits }
val ready_reg = withReset(reset.asAsyncReset)(RegNext(next=ready, init=false.B).suggestName("ready_reg"))
io.enq.ready := ready_reg && sink_ready
val widx_reg = withReset(reset.asAsyncReset)(RegNext(next=widx, init=0.U).suggestName("widx_gray"))
io.async.widx := widx_reg
io.async.index match {
case Some(index) => io.async.mem(0) := mem(index)
case None => io.async.mem := mem
}
io.async.safe.foreach { sio =>
val source_valid_0 = Module(new AsyncValidSync(params.sync, "source_valid_0"))
val source_valid_1 = Module(new AsyncValidSync(params.sync, "source_valid_1"))
val sink_extend = Module(new AsyncValidSync(params.sync, "sink_extend"))
val sink_valid = Module(new AsyncValidSync(params.sync, "sink_valid"))
source_valid_0.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
source_valid_1.reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_extend .reset := (reset.asBool || !sio.sink_reset_n).asAsyncReset
sink_valid .reset := reset.asAsyncReset
source_valid_0.clock := clock
source_valid_1.clock := clock
sink_extend .clock := clock
sink_valid .clock := clock
source_valid_0.io.in := true.B
source_valid_1.io.in := source_valid_0.io.out
sio.widx_valid := source_valid_1.io.out
sink_extend.io.in := sio.ridx_valid
sink_valid.io.in := sink_extend.io.out
sink_ready := sink_valid.io.out
sio.source_reset_n := !reset.asBool
// Assert that if there is stuff in the queue, then reset cannot happen
// Impossible to write because dequeue can occur on the receiving side,
// then reset allowed to happen, but write side cannot know that dequeue
// occurred.
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
// assert (!(reset || !sio.sink_reset_n) || !io.enq.valid, "Enqueue while sink is reset and AsyncQueueSource is unprotected")
// assert (!reset_rise || prev_idx_match.asBool, "Sink reset while AsyncQueueSource not empty")
}
}
class AsyncQueueSink[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Module {
override def desiredName = s"AsyncQueueSink_${gen.typeName}"
val io = IO(new Bundle {
// These come from the sink domain
val deq = Decoupled(gen)
// These cross to the source clock domain
val async = Flipped(new AsyncBundle(gen, params))
})
val bits = params.bits
val source_ready = WireInit(true.B)
val ridx = withReset(reset.asAsyncReset)(GrayCounter(bits+1, io.deq.fire, !source_ready, "ridx_bin"))
val widx = AsyncResetSynchronizerShiftReg(io.async.widx, params.sync, Some("widx_gray"))
val valid = source_ready && ridx =/= widx
// The mux is safe because timing analysis ensures ridx has reached the register
// On an ASIC, changes to the unread location cannot affect the selected value
// On an FPGA, only one input changes at a time => mem updates don't cause glitches
// The register only latches when the selected valued is not being written
val index = if (bits == 0) 0.U else ridx(bits-1, 0) ^ (ridx(bits, bits) << (bits-1))
io.async.index.foreach { _ := index }
// This register does not NEED to be reset, as its contents will not
// be considered unless the asynchronously reset deq valid register is set.
// It is possible that bits latches when the source domain is reset / has power cut
// This is safe, because isolation gates brought mem low before the zeroed widx reached us
val deq_bits_nxt = io.async.mem(if (params.narrow) 0.U else index)
io.deq.bits := ClockCrossingReg(deq_bits_nxt, en = valid, doInit = false, name = Some("deq_bits_reg"))
val valid_reg = withReset(reset.asAsyncReset)(RegNext(next=valid, init=false.B).suggestName("valid_reg"))
io.deq.valid := valid_reg && source_ready
val ridx_reg = withReset(reset.asAsyncReset)(RegNext(next=ridx, init=0.U).suggestName("ridx_gray"))
io.async.ridx := ridx_reg
io.async.safe.foreach { sio =>
val sink_valid_0 = Module(new AsyncValidSync(params.sync, "sink_valid_0"))
val sink_valid_1 = Module(new AsyncValidSync(params.sync, "sink_valid_1"))
val source_extend = Module(new AsyncValidSync(params.sync, "source_extend"))
val source_valid = Module(new AsyncValidSync(params.sync, "source_valid"))
sink_valid_0 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
sink_valid_1 .reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_extend.reset := (reset.asBool || !sio.source_reset_n).asAsyncReset
source_valid .reset := reset.asAsyncReset
sink_valid_0 .clock := clock
sink_valid_1 .clock := clock
source_extend.clock := clock
source_valid .clock := clock
sink_valid_0.io.in := true.B
sink_valid_1.io.in := sink_valid_0.io.out
sio.ridx_valid := sink_valid_1.io.out
source_extend.io.in := sio.widx_valid
source_valid.io.in := source_extend.io.out
source_ready := source_valid.io.out
sio.sink_reset_n := !reset.asBool
// TODO: write some sort of sanity check assertion for users
// that denote don't reset when there is activity
//
// val reset_and_extend = !source_ready || !sio.source_reset_n || reset.asBool
// val reset_and_extend_prev = RegNext(reset_and_extend, true.B)
// val reset_rise = !reset_and_extend_prev && reset_and_extend
// val prev_idx_match = AsyncResetReg(updateData=(io.async.widx===io.async.ridx), resetData=0)
// assert (!reset_rise || prev_idx_match.asBool, "Source reset while AsyncQueueSink not empty")
}
}
object FromAsyncBundle
{
// Sometimes it makes sense for the sink to have different sync than the source
def apply[T <: Data](x: AsyncBundle[T]): DecoupledIO[T] = apply(x, x.params.sync)
def apply[T <: Data](x: AsyncBundle[T], sync: Int): DecoupledIO[T] = {
val sink = Module(new AsyncQueueSink(chiselTypeOf(x.mem(0)), x.params.copy(sync = sync)))
sink.io.async <> x
sink.io.deq
}
}
object ToAsyncBundle
{
def apply[T <: Data](x: ReadyValidIO[T], params: AsyncQueueParams = AsyncQueueParams()): AsyncBundle[T] = {
val source = Module(new AsyncQueueSource(chiselTypeOf(x.bits), params))
source.io.enq <> x
source.io.async
}
}
class AsyncQueue[T <: Data](gen: T, params: AsyncQueueParams = AsyncQueueParams()) extends Crossing[T] {
val io = IO(new CrossingIO(gen))
val source = withClockAndReset(io.enq_clock, io.enq_reset) { Module(new AsyncQueueSource(gen, params)) }
val sink = withClockAndReset(io.deq_clock, io.deq_reset) { Module(new AsyncQueueSink (gen, params)) }
source.io.enq <> io.enq
io.deq <> sink.io.deq
sink.io.async <> source.io.async
}
|
module AsyncValidSync_55( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_72 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule
|
Generate the Verilog code corresponding to the following Chisel files.
File EgressUnit.scala:
package constellation.router
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.util._
import constellation.channel._
import constellation.routing.{FlowRoutingBundle}
class EgressUnit(coupleSAVA: Boolean, combineSAST: Boolean, inParams: Seq[ChannelParams], ingressParams: Seq[IngressChannelParams], cParam: EgressChannelParams)
(implicit p: Parameters) extends AbstractOutputUnit(inParams, ingressParams, cParam)(p) {
class EgressUnitIO extends AbstractOutputUnitIO(inParams, ingressParams, cParam) {
val out = Decoupled(new EgressFlit(cParam.payloadBits))
}
val io = IO(new EgressUnitIO)
val channel_empty = RegInit(true.B)
val flow = Reg(new FlowRoutingBundle)
val q = Module(new Queue(new EgressFlit(cParam.payloadBits), 3 - (if (combineSAST) 1 else 0), flow=true))
q.io.enq.valid := io.in(0).valid
q.io.enq.bits.head := io.in(0).bits.head
q.io.enq.bits.tail := io.in(0).bits.tail
val flows = cParam.possibleFlows.toSeq
if (flows.size == 0) {
q.io.enq.bits.ingress_id := 0.U(1.W)
} else {
q.io.enq.bits.ingress_id := Mux1H(
flows.map(f => (f.ingressNode.U === io.in(0).bits.flow.ingress_node &&
f.ingressNodeId.U === io.in(0).bits.flow.ingress_node_id)),
flows.map(f => f.ingressId.U(ingressIdBits.W))
)
}
q.io.enq.bits.payload := io.in(0).bits.payload
io.out <> q.io.deq
assert(!(q.io.enq.valid && !q.io.enq.ready))
io.credit_available(0) := q.io.count === 0.U
io.channel_status(0).occupied := !channel_empty
io.channel_status(0).flow := flow
when (io.credit_alloc(0).alloc && io.credit_alloc(0).tail) {
channel_empty := true.B
if (coupleSAVA) io.channel_status(0).occupied := false.B
}
when (io.allocs(0).alloc) {
channel_empty := false.B
flow := io.allocs(0).flow
}
}
|
module EgressUnit_13( // @[EgressUnit.scala:12:7]
input clock, // @[EgressUnit.scala:12:7]
input reset, // @[EgressUnit.scala:12:7]
input io_in_0_valid, // @[EgressUnit.scala:18:14]
input io_in_0_bits_head, // @[EgressUnit.scala:18:14]
input io_in_0_bits_tail, // @[EgressUnit.scala:18:14]
input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14]
input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14]
input [2:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14]
output io_credit_available_0, // @[EgressUnit.scala:18:14]
output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14]
input io_allocs_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14]
input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14]
input io_out_ready, // @[EgressUnit.scala:18:14]
output io_out_valid, // @[EgressUnit.scala:18:14]
output io_out_bits_head, // @[EgressUnit.scala:18:14]
output io_out_bits_tail, // @[EgressUnit.scala:18:14]
output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14]
);
wire _q_io_enq_ready; // @[EgressUnit.scala:22:17]
wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17]
reg channel_empty; // @[EgressUnit.scala:20:30]
wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 3'h0; // @[EgressUnit.scala:32:27]
|
Generate the Verilog code corresponding to the following Chisel files.
File util.scala:
//******************************************************************************
// Copyright (c) 2015 - 2019, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Utility Functions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
package boom.v4.util
import chisel3._
import chisel3.util._
import freechips.rocketchip.rocket.Instructions._
import freechips.rocketchip.rocket._
import freechips.rocketchip.util.{Str}
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tile.{TileKey}
import boom.v4.common.{MicroOp}
import boom.v4.exu.{BrUpdateInfo}
/**
* Object to XOR fold a input register of fullLength into a compressedLength.
*/
object Fold
{
def apply(input: UInt, compressedLength: Int, fullLength: Int): UInt = {
val clen = compressedLength
val hlen = fullLength
if (hlen <= clen) {
input
} else {
var res = 0.U(clen.W)
var remaining = input.asUInt
for (i <- 0 to hlen-1 by clen) {
val len = if (i + clen > hlen ) (hlen - i) else clen
require(len > 0)
res = res(clen-1,0) ^ remaining(len-1,0)
remaining = remaining >> len.U
}
res
}
}
}
/**
* Object to check if MicroOp was killed due to a branch mispredict.
* Uses "Fast" branch masks
*/
object IsKilledByBranch
{
def apply(brupdate: BrUpdateInfo, flush: Bool, uop: MicroOp): Bool = {
return apply(brupdate, flush, uop.br_mask)
}
def apply(brupdate: BrUpdateInfo, flush: Bool, uop_mask: UInt): Bool = {
return maskMatch(brupdate.b1.mispredict_mask, uop_mask) || flush
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: T): Bool = {
return apply(brupdate, flush, bundle.uop)
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Bool = {
return apply(brupdate, flush, bundle.bits)
}
}
/**
* Object to return new MicroOp with a new BR mask given a MicroOp mask
* and old BR mask.
*/
object GetNewUopAndBrMask
{
def apply(uop: MicroOp, brupdate: BrUpdateInfo)
(implicit p: Parameters): MicroOp = {
val newuop = WireInit(uop)
newuop.br_mask := uop.br_mask & ~brupdate.b1.resolve_mask
newuop
}
}
/**
* Object to return a BR mask given a MicroOp mask and old BR mask.
*/
object GetNewBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): UInt = {
return uop.br_mask & ~brupdate.b1.resolve_mask
}
def apply(brupdate: BrUpdateInfo, br_mask: UInt): UInt = {
return br_mask & ~brupdate.b1.resolve_mask
}
}
object UpdateBrMask
{
def apply(brupdate: BrUpdateInfo, uop: MicroOp): MicroOp = {
val out = WireInit(uop)
out.br_mask := GetNewBrMask(brupdate, uop)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, bundle: T): T = {
val out = WireInit(bundle)
out.uop.br_mask := GetNewBrMask(brupdate, bundle.uop.br_mask)
out
}
def apply[T <: boom.v4.common.HasBoomUOP](brupdate: BrUpdateInfo, flush: Bool, bundle: Valid[T]): Valid[T] = {
val out = WireInit(bundle)
out.bits.uop.br_mask := GetNewBrMask(brupdate, bundle.bits.uop.br_mask)
out.valid := bundle.valid && !IsKilledByBranch(brupdate, flush, bundle.bits.uop.br_mask)
out
}
}
/**
* Object to check if at least 1 bit matches in two masks
*/
object maskMatch
{
def apply(msk1: UInt, msk2: UInt): Bool = (msk1 & msk2) =/= 0.U
}
/**
* Object to clear one bit in a mask given an index
*/
object clearMaskBit
{
def apply(msk: UInt, idx: UInt): UInt = (msk & ~(1.U << idx))(msk.getWidth-1, 0)
}
/**
* Object to shift a register over by one bit and concat a new one
*/
object PerformShiftRegister
{
def apply(reg_val: UInt, new_bit: Bool): UInt = {
reg_val := Cat(reg_val(reg_val.getWidth-1, 0).asUInt, new_bit.asUInt).asUInt
reg_val
}
}
/**
* Object to shift a register over by one bit, wrapping the top bit around to the bottom
* (XOR'ed with a new-bit), and evicting a bit at index HLEN.
* This is used to simulate a longer HLEN-width shift register that is folded
* down to a compressed CLEN.
*/
object PerformCircularShiftRegister
{
def apply(csr: UInt, new_bit: Bool, evict_bit: Bool, hlen: Int, clen: Int): UInt = {
val carry = csr(clen-1)
val newval = Cat(csr, new_bit ^ carry) ^ (evict_bit << (hlen % clen).U)
newval
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapAdd
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, amt: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + amt)(log2Ceil(n)-1,0)
} else {
val sum = Cat(0.U(1.W), value) + Cat(0.U(1.W), amt)
Mux(sum >= n.U,
sum - n.U,
sum)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapSub
{
// "n" is the number of increments, so we wrap to n-1.
def apply(value: UInt, amt: Int, n: Int): UInt = {
if (isPow2(n)) {
(value - amt.U)(log2Ceil(n)-1,0)
} else {
val v = Cat(0.U(1.W), value)
val b = Cat(0.U(1.W), amt.U)
Mux(value >= amt.U,
value - amt.U,
n.U - amt.U + value)
}
}
}
/**
* Object to increment an input value, wrapping it if
* necessary.
*/
object WrapInc
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value + 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === (n-1).U)
Mux(wrap, 0.U, value + 1.U)
}
}
}
/**
* Object to decrement an input value, wrapping it if
* necessary.
*/
object WrapDec
{
// "n" is the number of increments, so we wrap at n-1.
def apply(value: UInt, n: Int): UInt = {
if (isPow2(n)) {
(value - 1.U)(log2Ceil(n)-1,0)
} else {
val wrap = (value === 0.U)
Mux(wrap, (n-1).U, value - 1.U)
}
}
}
/**
* Object to mask off lower bits of a PC to align to a "b"
* Byte boundary.
*/
object AlignPCToBoundary
{
def apply(pc: UInt, b: Int): UInt = {
// Invert for scenario where pc longer than b
// (which would clear all bits above size(b)).
~(~pc | (b-1).U)
}
}
/**
* Object to rotate a signal left by one
*/
object RotateL1
{
def apply(signal: UInt): UInt = {
val w = signal.getWidth
val out = Cat(signal(w-2,0), signal(w-1))
return out
}
}
/**
* Object to sext a value to a particular length.
*/
object Sext
{
def apply(x: UInt, length: Int): UInt = {
if (x.getWidth == length) return x
else return Cat(Fill(length-x.getWidth, x(x.getWidth-1)), x)
}
}
/**
* Object to translate from BOOM's special "packed immediate" to a 32b signed immediate
* Asking for U-type gives it shifted up 12 bits.
*/
object ImmGen
{
import boom.v4.common.{LONGEST_IMM_SZ, IS_B, IS_I, IS_J, IS_S, IS_U, IS_N}
def apply(i: UInt, isel: UInt): UInt = {
val ip = Mux(isel === IS_N, 0.U(LONGEST_IMM_SZ.W), i)
val sign = ip(LONGEST_IMM_SZ-1).asSInt
val i30_20 = Mux(isel === IS_U, ip(18,8).asSInt, sign)
val i19_12 = Mux(isel === IS_U || isel === IS_J, ip(7,0).asSInt, sign)
val i11 = Mux(isel === IS_U, 0.S,
Mux(isel === IS_J || isel === IS_B, ip(8).asSInt, sign))
val i10_5 = Mux(isel === IS_U, 0.S, ip(18,14).asSInt)
val i4_1 = Mux(isel === IS_U, 0.S, ip(13,9).asSInt)
val i0 = Mux(isel === IS_S || isel === IS_I, ip(8).asSInt, 0.S)
return Cat(sign, i30_20, i19_12, i11, i10_5, i4_1, i0)
}
}
/**
* Object to see if an instruction is a JALR.
*/
object DebugIsJALR
{
def apply(inst: UInt): Bool = {
// TODO Chisel not sure why this won't compile
// val is_jalr = rocket.DecodeLogic(inst, List(Bool(false)),
// Array(
// JALR -> Bool(true)))
inst(6,0) === "b1100111".U
}
}
/**
* Object to take an instruction and output its branch or jal target. Only used
* for a debug assert (no where else would we jump straight from instruction
* bits to a target).
*/
object DebugGetBJImm
{
def apply(inst: UInt): UInt = {
// TODO Chisel not sure why this won't compile
//val csignals =
//rocket.DecodeLogic(inst,
// List(Bool(false), Bool(false)),
// Array(
// BEQ -> List(Bool(true ), Bool(false)),
// BNE -> List(Bool(true ), Bool(false)),
// BGE -> List(Bool(true ), Bool(false)),
// BGEU -> List(Bool(true ), Bool(false)),
// BLT -> List(Bool(true ), Bool(false)),
// BLTU -> List(Bool(true ), Bool(false))
// ))
//val is_br :: nothing :: Nil = csignals
val is_br = (inst(6,0) === "b1100011".U)
val br_targ = Cat(Fill(12, inst(31)), Fill(8,inst(31)), inst(7), inst(30,25), inst(11,8), 0.U(1.W))
val jal_targ= Cat(Fill(12, inst(31)), inst(19,12), inst(20), inst(30,25), inst(24,21), 0.U(1.W))
Mux(is_br, br_targ, jal_targ)
}
}
/**
* Object to return the lowest bit position after the head.
*/
object AgePriorityEncoder
{
def apply(in: Seq[Bool], head: UInt): UInt = {
val n = in.size
val width = log2Ceil(in.size)
val n_padded = 1 << width
val temp_vec = (0 until n_padded).map(i => if (i < n) in(i) && i.U >= head else false.B) ++ in
val idx = PriorityEncoder(temp_vec)
idx(width-1, 0) //discard msb
}
}
/**
* Object to determine whether queue
* index i0 is older than index i1.
*/
object IsOlder
{
def apply(i0: UInt, i1: UInt, head: UInt) = ((i0 < i1) ^ (i0 < head) ^ (i1 < head))
}
object IsYoungerMask
{
def apply(i: UInt, head: UInt, n: Integer): UInt = {
val hi_mask = ~MaskLower(UIntToOH(i)(n-1,0))
val lo_mask = ~MaskUpper(UIntToOH(head)(n-1,0))
Mux(i < head, hi_mask & lo_mask, hi_mask | lo_mask)(n-1,0)
}
}
/**
* Set all bits at or below the highest order '1'.
*/
object MaskLower
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => in >> i.U).reduce(_|_)
}
}
/**
* Set all bits at or above the lowest order '1'.
*/
object MaskUpper
{
def apply(in: UInt) = {
val n = in.getWidth
(0 until n).map(i => (in << i.U)(n-1,0)).reduce(_|_)
}
}
/**
* Transpose a matrix of Chisel Vecs.
*/
object Transpose
{
def apply[T <: chisel3.Data](in: Vec[Vec[T]]) = {
val n = in(0).size
VecInit((0 until n).map(i => VecInit(in.map(row => row(i)))))
}
}
/**
* N-wide one-hot priority encoder.
*/
object SelectFirstN
{
def apply(in: UInt, n: Int) = {
val sels = Wire(Vec(n, UInt(in.getWidth.W)))
var mask = in
for (i <- 0 until n) {
sels(i) := PriorityEncoderOH(mask)
mask = mask & ~sels(i)
}
sels
}
}
/**
* Connect the first k of n valid input interfaces to k output interfaces.
*/
class Compactor[T <: chisel3.Data](n: Int, k: Int, gen: T) extends Module
{
require(n >= k)
val io = IO(new Bundle {
val in = Vec(n, Flipped(DecoupledIO(gen)))
val out = Vec(k, DecoupledIO(gen))
})
if (n == k) {
io.out <> io.in
} else {
val counts = io.in.map(_.valid).scanLeft(1.U(k.W)) ((c,e) => Mux(e, (c<<1)(k-1,0), c))
val sels = Transpose(VecInit(counts map (c => VecInit(c.asBools)))) map (col =>
(col zip io.in.map(_.valid)) map {case (c,v) => c && v})
val in_readys = counts map (row => (row.asBools zip io.out.map(_.ready)) map {case (c,r) => c && r} reduce (_||_))
val out_valids = sels map (col => col.reduce(_||_))
val out_data = sels map (s => Mux1H(s, io.in.map(_.bits)))
in_readys zip io.in foreach {case (r,i) => i.ready := r}
out_valids zip out_data zip io.out foreach {case ((v,d),o) => o.valid := v; o.bits := d}
}
}
/**
* Create a queue that can be killed with a branch kill signal.
* Assumption: enq.valid only high if not killed by branch (so don't check IsKilled on io.enq).
*/
class BranchKillableQueue[T <: boom.v4.common.HasBoomUOP](gen: T, entries: Int, flush_fn: boom.v4.common.MicroOp => Bool = u => true.B, fastDeq: Boolean = false)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val enq = Flipped(Decoupled(gen))
val deq = Decoupled(gen)
val brupdate = Input(new BrUpdateInfo())
val flush = Input(Bool())
val empty = Output(Bool())
val count = Output(UInt(log2Ceil(entries).W))
})
if (fastDeq && entries > 1) {
// Pipeline dequeue selection so the mux gets an entire cycle
val main = Module(new BranchKillableQueue(gen, entries-1, flush_fn, false))
val out_reg = Reg(gen)
val out_valid = RegInit(false.B)
val out_uop = Reg(new MicroOp)
main.io.enq <> io.enq
main.io.brupdate := io.brupdate
main.io.flush := io.flush
io.empty := main.io.empty && !out_valid
io.count := main.io.count + out_valid
io.deq.valid := out_valid
io.deq.bits := out_reg
io.deq.bits.uop := out_uop
out_uop := UpdateBrMask(io.brupdate, out_uop)
out_valid := out_valid && !IsKilledByBranch(io.brupdate, false.B, out_uop) && !(io.flush && flush_fn(out_uop))
main.io.deq.ready := false.B
when (io.deq.fire || !out_valid) {
out_valid := main.io.deq.valid && !IsKilledByBranch(io.brupdate, false.B, main.io.deq.bits.uop) && !(io.flush && flush_fn(main.io.deq.bits.uop))
out_reg := main.io.deq.bits
out_uop := UpdateBrMask(io.brupdate, main.io.deq.bits.uop)
main.io.deq.ready := true.B
}
} else {
val ram = Mem(entries, gen)
val valids = RegInit(VecInit(Seq.fill(entries) {false.B}))
val uops = Reg(Vec(entries, new MicroOp))
val enq_ptr = Counter(entries)
val deq_ptr = Counter(entries)
val maybe_full = RegInit(false.B)
val ptr_match = enq_ptr.value === deq_ptr.value
io.empty := ptr_match && !maybe_full
val full = ptr_match && maybe_full
val do_enq = WireInit(io.enq.fire && !IsKilledByBranch(io.brupdate, false.B, io.enq.bits.uop) && !(io.flush && flush_fn(io.enq.bits.uop)))
val do_deq = WireInit((io.deq.ready || !valids(deq_ptr.value)) && !io.empty)
for (i <- 0 until entries) {
val mask = uops(i).br_mask
val uop = uops(i)
valids(i) := valids(i) && !IsKilledByBranch(io.brupdate, false.B, mask) && !(io.flush && flush_fn(uop))
when (valids(i)) {
uops(i).br_mask := GetNewBrMask(io.brupdate, mask)
}
}
when (do_enq) {
ram(enq_ptr.value) := io.enq.bits
valids(enq_ptr.value) := true.B
uops(enq_ptr.value) := io.enq.bits.uop
uops(enq_ptr.value).br_mask := GetNewBrMask(io.brupdate, io.enq.bits.uop)
enq_ptr.inc()
}
when (do_deq) {
valids(deq_ptr.value) := false.B
deq_ptr.inc()
}
when (do_enq =/= do_deq) {
maybe_full := do_enq
}
io.enq.ready := !full
val out = Wire(gen)
out := ram(deq_ptr.value)
out.uop := uops(deq_ptr.value)
io.deq.valid := !io.empty && valids(deq_ptr.value)
io.deq.bits := out
val ptr_diff = enq_ptr.value - deq_ptr.value
if (isPow2(entries)) {
io.count := Cat(maybe_full && ptr_match, ptr_diff)
}
else {
io.count := Mux(ptr_match,
Mux(maybe_full,
entries.asUInt, 0.U),
Mux(deq_ptr.value > enq_ptr.value,
entries.asUInt + ptr_diff, ptr_diff))
}
}
}
// ------------------------------------------
// Printf helper functions
// ------------------------------------------
object BoolToChar
{
/**
* Take in a Chisel Bool and convert it into a Str
* based on the Chars given
*
* @param c_bool Chisel Bool
* @param trueChar Scala Char if bool is true
* @param falseChar Scala Char if bool is false
* @return UInt ASCII Char for "trueChar" or "falseChar"
*/
def apply(c_bool: Bool, trueChar: Char, falseChar: Char = '-'): UInt = {
Mux(c_bool, Str(trueChar), Str(falseChar))
}
}
object CfiTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param cfi_type specific cfi type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(cfi_type: UInt) = {
val strings = Seq("----", "BR ", "JAL ", "JALR")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(cfi_type)
}
}
object BpdTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param bpd_type specific bpd type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(bpd_type: UInt) = {
val strings = Seq("BR ", "JUMP", "----", "RET ", "----", "CALL", "----", "----")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(bpd_type)
}
}
object RobTypeToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param rob_type specific rob type
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(rob_type: UInt) = {
val strings = Seq("RST", "NML", "RBK", " WT")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(rob_type)
}
}
object XRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param xreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(xreg: UInt) = {
val strings = Seq(" x0", " ra", " sp", " gp",
" tp", " t0", " t1", " t2",
" s0", " s1", " a0", " a1",
" a2", " a3", " a4", " a5",
" a6", " a7", " s2", " s3",
" s4", " s5", " s6", " s7",
" s8", " s9", "s10", "s11",
" t3", " t4", " t5", " t6")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(xreg)
}
}
object FPRegToChars
{
/**
* Get a Vec of Strs that can be used for printing
*
* @param fpreg specific register number
* @return Vec of Strs (must be indexed to get specific char)
*/
def apply(fpreg: UInt) = {
val strings = Seq(" ft0", " ft1", " ft2", " ft3",
" ft4", " ft5", " ft6", " ft7",
" fs0", " fs1", " fa0", " fa1",
" fa2", " fa3", " fa4", " fa5",
" fa6", " fa7", " fs2", " fs3",
" fs4", " fs5", " fs6", " fs7",
" fs8", " fs9", "fs10", "fs11",
" ft8", " ft9", "ft10", "ft11")
val multiVec = VecInit(for(string <- strings) yield { VecInit(for (c <- string) yield { Str(c) }) })
multiVec(fpreg)
}
}
object BoomCoreStringPrefix
{
/**
* Add prefix to BOOM strings (currently only adds the hartId)
*
* @param strs list of strings
* @return String combining the list with the prefix per line
*/
def apply(strs: String*)(implicit p: Parameters) = {
val prefix = "[C" + s"${p(TileKey).tileId}" + "] "
strs.map(str => prefix + str + "\n").mkString("")
}
}
class BranchKillablePipeline[T <: boom.v4.common.HasBoomUOP](gen: T, stages: Int)
(implicit p: org.chipsalliance.cde.config.Parameters)
extends boom.v4.common.BoomModule()(p)
with boom.v4.common.HasBoomCoreParameters
{
val io = IO(new Bundle {
val req = Input(Valid(gen))
val flush = Input(Bool())
val brupdate = Input(new BrUpdateInfo)
val resp = Output(Vec(stages, Valid(gen)))
})
require(stages > 0)
val uops = Reg(Vec(stages, Valid(gen)))
uops(0).valid := io.req.valid && !IsKilledByBranch(io.brupdate, io.flush, io.req.bits)
uops(0).bits := UpdateBrMask(io.brupdate, io.req.bits)
for (i <- 1 until stages) {
uops(i).valid := uops(i-1).valid && !IsKilledByBranch(io.brupdate, io.flush, uops(i-1).bits)
uops(i).bits := UpdateBrMask(io.brupdate, uops(i-1).bits)
}
for (i <- 0 until stages) { when (reset.asBool) { uops(i).valid := false.B } }
io.resp := uops
}
File issue-slot.scala:
//******************************************************************************
// Copyright (c) 2015 - 2018, The Regents of the University of California (Regents).
// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// RISCV Processor Issue Slot Logic
//--------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
// Note: stores (and AMOs) are "broken down" into 2 uops, but stored within a single issue-slot.
// TODO XXX make a separate issueSlot for MemoryIssueSlots, and only they break apart stores.
// TODO Disable ldspec for FP queue.
package boom.v4.exu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.Parameters
import boom.v4.common._
import boom.v4.util._
class IssueSlotIO(val numWakeupPorts: Int)(implicit p: Parameters) extends BoomBundle
{
val valid = Output(Bool())
val will_be_valid = Output(Bool()) // TODO code review, do we need this signal so explicitely?
val request = Output(Bool())
val grant = Input(Bool())
val iss_uop = Output(new MicroOp())
val in_uop = Input(Valid(new MicroOp())) // if valid, this WILL overwrite an entry!
val out_uop = Output(new MicroOp())
val brupdate = Input(new BrUpdateInfo())
val kill = Input(Bool()) // pipeline flush
val clear = Input(Bool()) // entry being moved elsewhere (not mutually exclusive with grant)
val squash_grant = Input(Bool())
val wakeup_ports = Flipped(Vec(numWakeupPorts, Valid(new Wakeup)))
val pred_wakeup_port = Flipped(Valid(UInt(log2Ceil(ftqSz).W)))
val child_rebusys = Input(UInt(aluWidth.W))
}
class IssueSlot(val numWakeupPorts: Int, val isMem: Boolean, val isFp: Boolean)(implicit p: Parameters)
extends BoomModule
{
val io = IO(new IssueSlotIO(numWakeupPorts))
val slot_valid = RegInit(false.B)
val slot_uop = Reg(new MicroOp())
val next_valid = WireInit(slot_valid)
val next_uop = WireInit(UpdateBrMask(io.brupdate, slot_uop))
val killed = IsKilledByBranch(io.brupdate, io.kill, slot_uop)
io.valid := slot_valid
io.out_uop := next_uop
io.will_be_valid := next_valid && !killed
when (io.kill) {
slot_valid := false.B
} .elsewhen (io.in_uop.valid) {
slot_valid := true.B
} .elsewhen (io.clear) {
slot_valid := false.B
} .otherwise {
slot_valid := next_valid && !killed
}
when (io.in_uop.valid) {
slot_uop := io.in_uop.bits
assert (!slot_valid || io.clear || io.kill)
} .otherwise {
slot_uop := next_uop
}
// Wakeups
next_uop.iw_p1_bypass_hint := false.B
next_uop.iw_p2_bypass_hint := false.B
next_uop.iw_p3_bypass_hint := false.B
next_uop.iw_p1_speculative_child := 0.U
next_uop.iw_p2_speculative_child := 0.U
val rebusied_prs1 = WireInit(false.B)
val rebusied_prs2 = WireInit(false.B)
val rebusied = rebusied_prs1 || rebusied_prs2
val prs1_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs1 }
val prs2_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs2 }
val prs3_matches = io.wakeup_ports.map { w => w.bits.uop.pdst === slot_uop.prs3 }
val prs1_wakeups = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.valid && m }
val prs2_wakeups = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.valid && m }
val prs3_wakeups = (io.wakeup_ports zip prs3_matches).map { case (w,m) => w.valid && m }
val prs1_rebusys = (io.wakeup_ports zip prs1_matches).map { case (w,m) => w.bits.rebusy && m }
val prs2_rebusys = (io.wakeup_ports zip prs2_matches).map { case (w,m) => w.bits.rebusy && m }
val bypassables = io.wakeup_ports.map { w => w.bits.bypassable }
val speculative_masks = io.wakeup_ports.map { w => w.bits.speculative_mask }
when (prs1_wakeups.reduce(_||_)) {
next_uop.prs1_busy := false.B
next_uop.iw_p1_speculative_child := Mux1H(prs1_wakeups, speculative_masks)
next_uop.iw_p1_bypass_hint := Mux1H(prs1_wakeups, bypassables)
}
when ((prs1_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p1_speculative_child) =/= 0.U)) &&
slot_uop.lrs1_rtype === RT_FIX) {
next_uop.prs1_busy := true.B
rebusied_prs1 := true.B
}
when (prs2_wakeups.reduce(_||_)) {
next_uop.prs2_busy := false.B
next_uop.iw_p2_speculative_child := Mux1H(prs2_wakeups, speculative_masks)
next_uop.iw_p2_bypass_hint := Mux1H(prs2_wakeups, bypassables)
}
when ((prs2_rebusys.reduce(_||_) || ((io.child_rebusys & slot_uop.iw_p2_speculative_child) =/= 0.U)) &&
slot_uop.lrs2_rtype === RT_FIX) {
next_uop.prs2_busy := true.B
rebusied_prs2 := true.B
}
when (prs3_wakeups.reduce(_||_)) {
next_uop.prs3_busy := false.B
next_uop.iw_p3_bypass_hint := Mux1H(prs3_wakeups, bypassables)
}
when (io.pred_wakeup_port.valid && io.pred_wakeup_port.bits === slot_uop.ppred) {
next_uop.ppred_busy := false.B
}
val iss_ready = !slot_uop.prs1_busy && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && !(slot_uop.prs3_busy && isFp.B)
val agen_ready = (slot_uop.fu_code(FC_AGEN) && !slot_uop.prs1_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
val dgen_ready = (slot_uop.fu_code(FC_DGEN) && !slot_uop.prs2_busy && !(slot_uop.ppred_busy && enableSFBOpt.B) && isMem.B)
io.request := slot_valid && !slot_uop.iw_issued && (
iss_ready || agen_ready || dgen_ready
)
io.iss_uop := slot_uop
// Update state for current micro-op based on grant
next_uop.iw_issued := false.B
next_uop.iw_issued_partial_agen := false.B
next_uop.iw_issued_partial_dgen := false.B
when (io.grant && !io.squash_grant) {
next_uop.iw_issued := true.B
}
if (isMem) {
when (slot_uop.fu_code(FC_AGEN) && slot_uop.fu_code(FC_DGEN)) {
when (agen_ready) {
// Issue the AGEN, next slot entry is a DGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_agen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := true.B
io.iss_uop.fu_code(FC_DGEN) := false.B
} .otherwise {
// Issue the DGEN, next slot entry is the AGEN
when (io.grant && !io.squash_grant) {
next_uop.iw_issued_partial_dgen := true.B
}
io.iss_uop.fu_code(FC_AGEN) := false.B
io.iss_uop.fu_code(FC_DGEN) := true.B
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
} .elsewhen (slot_uop.fu_code(FC_DGEN)) {
io.iss_uop.imm_sel := IS_N
io.iss_uop.prs1 := slot_uop.prs2
io.iss_uop.lrs1_rtype := slot_uop.lrs2_rtype
io.iss_uop.iw_p1_bypass_hint := slot_uop.iw_p2_bypass_hint
}
io.iss_uop.lrs2_rtype := RT_X
io.iss_uop.prs2 := io.iss_uop.prs1 // helps with DCE
}
when (slot_valid && slot_uop.iw_issued) {
next_valid := rebusied
if (isMem) {
when (slot_uop.iw_issued_partial_agen) {
next_valid := true.B
when (!rebusied_prs1) {
next_uop.fu_code(FC_AGEN) := false.B
next_uop.fu_code(FC_DGEN) := true.B
}
} .elsewhen (slot_uop.iw_issued_partial_dgen) {
next_valid := true.B
when (!rebusied_prs2) {
next_uop.fu_code(FC_AGEN) := true.B
next_uop.fu_code(FC_DGEN) := false.B
}
}
}
}
}
|
module IssueSlot_10( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_issued, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_0 = io_in_uop_bits_iw_issued; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31]
wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31]
wire rebusied = 1'h0; // @[issue-slot.scala:94:32]
wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [1:0] io_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] next_uop_iw_p1_speculative_child = 2'h0; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child = 2'h0; // @[issue-slot.scala:59:28]
wire [1:0] _next_uop_iw_p1_speculative_child_T = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p1_speculative_child_T_2 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p1_speculative_child_WIRE = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_2 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_WIRE = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}]
|
Generate the Verilog code corresponding to the following Chisel files.
File btb.scala:
package boom.v4.ifu
import chisel3._
import chisel3.util._
import org.chipsalliance.cde.config.{Field, Parameters}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import boom.v4.common._
import boom.v4.util.{BoomCoreStringPrefix}
import scala.math.min
case class BoomBTBParams(
nSets: Int = 128,
nWays: Int = 2,
offsetSz: Int = 13,
extendedNSets: Int = 128,
useFlops: Boolean = false
)
class BTBBranchPredictorBank(params: BoomBTBParams = BoomBTBParams())(implicit p: Parameters) extends BranchPredictorBank()(p)
{
override val nSets = params.nSets
override val nWays = params.nWays
val tagSz = vaddrBitsExtended - log2Ceil(nSets) - log2Ceil(fetchWidth) - 1
val offsetSz = params.offsetSz
val extendedNSets = params.extendedNSets
require(isPow2(nSets))
require(isPow2(extendedNSets) || extendedNSets == 0)
require(extendedNSets <= nSets)
require(extendedNSets >= 1)
class BTBEntry extends Bundle {
val offset = SInt(offsetSz.W)
val extended = Bool()
}
val btbEntrySz = offsetSz + 1
class BTBMeta extends Bundle {
val is_br = Bool()
val tag = UInt(tagSz.W)
}
val btbMetaSz = tagSz + 1
class BTBPredictMeta extends Bundle {
val write_way = UInt(log2Ceil(nWays).W)
}
val s1_meta = Wire(new BTBPredictMeta)
val f3_meta = RegNext(RegNext(s1_meta))
io.f3_meta := f3_meta.asUInt
override val metaSz = s1_meta.asUInt.getWidth
val doing_reset = RegInit(true.B)
val reset_idx = RegInit(0.U(log2Ceil(nSets).W))
reset_idx := reset_idx + doing_reset
when (reset_idx === (nSets-1).U) { doing_reset := false.B }
val mems = (((0 until nWays) map ({w:Int => Seq(
(f"btb_meta_way$w", nSets, bankWidth * btbMetaSz),
(f"btb_data_way$w", nSets, bankWidth * btbEntrySz))})).flatten ++ Seq(("ebtb", extendedNSets, vaddrBitsExtended)))
val s1_req_rmeta = Wire(Vec(nWays, Vec(bankWidth, new BTBMeta)))
val s1_req_rbtb = Wire(Vec(nWays, Vec(bankWidth, new BTBEntry)))
val s1_req_rebtb = Wire(UInt(vaddrBitsExtended.W))
val s1_req_tag = s1_idx >> log2Ceil(nSets)
val s1_resp = Wire(Vec(bankWidth, Valid(UInt(vaddrBitsExtended.W))))
val s1_is_br = Wire(Vec(bankWidth, Bool()))
val s1_is_jal = Wire(Vec(bankWidth, Bool()))
val s1_hit_ohs = VecInit((0 until bankWidth) map { i =>
VecInit((0 until nWays) map { w =>
s1_req_rmeta(w)(i).tag === s1_req_tag(tagSz-1,0)
})
})
val s1_hits = s1_hit_ohs.map { oh => oh.reduce(_||_) }
val s1_hit_ways = s1_hit_ohs.map { oh => PriorityEncoder(oh) }
val s1_targs = Wire(Vec(nWays, Vec(bankWidth, UInt(vaddrBitsExtended.W))))
for (w <- 0 until bankWidth) {
for (b <- 0 until nWays) {
val entry_btb = WireInit(s1_req_rbtb(b)(w))
s1_targs(b)(w) := Mux(entry_btb.extended,
s1_req_rebtb,
(s1_pc.asSInt + (w << 1).S + entry_btb.offset).asUInt)
}
val entry_meta = s1_req_rmeta(s1_hit_ways(w))(w)
s1_resp(w).valid := !doing_reset && s1_valid && s1_hits(w)
s1_resp(w).bits := s1_targs(s1_hit_ways(w))(w)
s1_is_br(w) := !doing_reset && s1_resp(w).valid && entry_meta.is_br
s1_is_jal(w) := !doing_reset && s1_resp(w).valid && !entry_meta.is_br
io.resp.f1(w) := io.resp_in(0).f1(w)
io.resp.f2(w) := io.resp_in(0).f2(w)
io.resp.f3(w) := io.resp_in(0).f3(w)
when (RegNext(s1_hits(w))) {
io.resp.f2(w).predicted_pc := RegNext(s1_resp(w))
io.resp.f2(w).is_br := RegNext(s1_is_br(w))
io.resp.f2(w).is_jal := RegNext(s1_is_jal(w))
when (RegNext(s1_is_jal(w))) {
io.resp.f2(w).taken := true.B
}
}
when (RegNext(RegNext(s1_hits(w)))) {
io.resp.f3(w).predicted_pc := RegNext(io.resp.f2(w).predicted_pc)
io.resp.f3(w).is_br := RegNext(io.resp.f2(w).is_br)
io.resp.f3(w).is_jal := RegNext(io.resp.f2(w).is_jal)
when (RegNext(RegNext(s1_is_jal(w)))) {
io.resp.f3(w).taken := true.B
}
}
}
val alloc_way = if (nWays > 1) {
val r_metas = Cat(VecInit(s1_req_rmeta.map { w => VecInit(w.map(_.tag)) }).asUInt, s1_req_tag(tagSz-1,0))
val l = log2Ceil(nWays)
val nChunks = (r_metas.getWidth + l - 1) / l
val chunks = (0 until nChunks) map { i =>
r_metas(min((i+1)*l, r_metas.getWidth)-1, i*l)
}
chunks.reduce(_^_)
} else {
0.U
}
s1_meta.write_way := Mux(s1_hits.reduce(_||_),
PriorityEncoder(s1_hit_ohs.map(_.asUInt).reduce(_|_)),
alloc_way)
val s1_update_cfi_idx = s1_update.bits.cfi_idx.bits
val s1_update_meta = s1_update.bits.meta.asTypeOf(new BTBPredictMeta)
val max_offset_value = Cat(0.B, ~(0.U((offsetSz-1).W))).asSInt
val min_offset_value = Cat(1.B, (0.U((offsetSz-1).W))).asSInt
val new_offset_value = (s1_update.bits.target.asSInt -
(s1_update.bits.pc + (s1_update.bits.cfi_idx.bits << 1)).asSInt)
val offset_is_extended = (new_offset_value > max_offset_value ||
new_offset_value < min_offset_value)
val s1_update_wbtb_data = Wire(new BTBEntry)
s1_update_wbtb_data.extended := offset_is_extended
s1_update_wbtb_data.offset := new_offset_value
val s1_update_wbtb_mask = (UIntToOH(s1_update_cfi_idx) &
Fill(bankWidth, s1_update.bits.cfi_idx.valid && s1_update.valid && s1_update.bits.cfi_taken && s1_update.bits.is_commit_update))
val s1_update_wmeta_mask = ((s1_update_wbtb_mask | s1_update.bits.br_mask) &
(Fill(bankWidth, s1_update.valid && s1_update.bits.is_commit_update) |
(Fill(bankWidth, s1_update.valid) & s1_update.bits.btb_mispredicts)
)
)
val s1_update_wmeta_data = Wire(Vec(bankWidth, new BTBMeta))
for (w <- 0 until bankWidth) {
s1_update_wmeta_data(w).tag := Mux(s1_update.bits.btb_mispredicts(w), 0.U, s1_update_idx >> log2Ceil(nSets))
s1_update_wmeta_data(w).is_br := s1_update.bits.br_mask(w)
}
if (params.useFlops) {
for (w <- 0 until nWays) {
val meta = Reg(Vec(nSets, Vec(bankWidth, new BTBMeta)))
val btb = Reg(Vec(nSets, Vec(bankWidth, new BTBEntry)))
s1_req_rmeta(w) := meta(s1_idx)
s1_req_rbtb(w) := btb(s1_idx)
for (i <- 0 until bankWidth) {
when (doing_reset || s1_update_meta.write_way === w.U || (nWays == 1).B) {
when (doing_reset || s1_update_wbtb_mask(i)) {
btb(Mux(doing_reset, reset_idx, s1_update_idx))(i) := Mux(doing_reset,
0.U.asTypeOf(new BTBEntry), s1_update_wbtb_data)
}
when (doing_reset || s1_update_wmeta_mask(i)) {
meta(Mux(doing_reset, reset_idx, s1_update_idx))(i) := Mux(doing_reset,
0.U.asTypeOf(new BTBMeta), s1_update_wmeta_data(i))
}
}
}
}
val ebtb = Reg(Vec(extendedNSets, UInt(vaddrBitsExtended.W)))
s1_req_rebtb := ebtb(s1_idx)
} else {
for (w <- 0 until nWays) {
val meta = SyncReadMem(nSets, Vec(bankWidth, UInt(btbMetaSz.W)))
val btb = SyncReadMem(nSets, Vec(bankWidth, UInt(btbEntrySz.W)))
meta.suggestName(s"btb_meta_way_${w}")
btb.suggestName(s"btb_data_way_${w}")
s1_req_rmeta(w) := VecInit(meta.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBMeta)))
s1_req_rbtb(w) := VecInit(btb.read(s0_idx, s0_valid).map(_.asTypeOf(new BTBEntry)))
when (doing_reset || s1_update_meta.write_way === w.U || (nWays == 1).B) {
btb.write(
Mux(doing_reset, reset_idx, s1_update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbEntrySz.W) }),
VecInit(Seq.fill(bankWidth) { s1_update_wbtb_data.asUInt })),
Mux(doing_reset, ~(0.U(bankWidth.W)), s1_update_wbtb_mask).asBools
)
meta.write(
Mux(doing_reset, reset_idx, s1_update_idx),
Mux(doing_reset, VecInit(Seq.fill(bankWidth) { 0.U(btbMetaSz.W) }),
VecInit(s1_update_wmeta_data.map(_.asUInt))),
Mux(doing_reset, ~(0.U(bankWidth.W)), s1_update_wmeta_mask).asBools
)
}
}
val ebtb = SyncReadMem(extendedNSets, UInt(vaddrBitsExtended.W))
ebtb.suggestName(s"btb_ebtb")
s1_req_rebtb := ebtb.read(s0_idx, s0_valid)
when (s1_update_wbtb_mask =/= 0.U && offset_is_extended) {
ebtb.write(s1_update_idx, s1_update.bits.target)
}
}
}
|
module btb_ebtb_0( // @[btb.scala:213:27]
input [6:0] R0_addr,
input R0_en,
input R0_clk,
output [39:0] R0_data,
input [6:0] W0_addr,
input W0_en,
input W0_clk,
input [39:0] W0_data
);
btb_ebtb_ext btb_ebtb_ext ( // @[btb.scala:213:27]
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data)
); // @[btb.scala:213:27]
endmodule
|
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